Method for producing a multilayer structure and multilayer structure

Abstract

The invention relates to a method for producing a multilayer structure, comprising the following steps: - providing a carrier substrate that is formed of a first material and comprises a first face, a second face opposite the first face, and a lateral surface connecting the first and second faces; - depositing an amorphous silicon carbide support layer on the carrier substrate, the first material being different from the amorphous silicon carbide, the support layer being deposited at least on the first face of the carrier substrate; - transferring a useful layer of a semiconductor material onto the portion of the support layer deposited on the first face of the carrier substrate; - heat treatment of the support layer so as to crystallize the initially amorphous silicon carbide.

Description

DESCRIPTION TITLE: METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE AND MULTILAYER STRUCTURE TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of semiconductor materials for microelectronic components. More particularly, the invention relates to a method for manufacturing a multilayer structure used as a support for the fabrication of electronic components. The invention also relates to an intermediate multilayer structure obtained during the manufacturing process. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] It is common to use thin film transfer solutions to fabricate multilayer structures comprising a high crystalline quality semiconductor useful layer on a lower crystalline quality semiconductor support substrate, the useful layer then being used to form electronic components.

[0003] A well-known thin-film transfer solution is the Smart Cut™ process, based on light ion implantation and direct bonding. In addition to the economic advantages of streamlining the use of high-quality material for the active layer, the multilayer structure can also provide beneficial properties, such as those related to thermal conductivity, electrical conductivity, or the mechanical compatibility of the substrate.

[0004] The Smart Cut™ process makes it possible to manufacture a multilayer structure comprising a thin layer of single-crystal semiconductor material such as single-crystal silicon carbide (SiC) (mono-SiC) or single-crystal gallium nitride (GaN) (mono-GaN), taken from a mono-SiC or mono-GaN donor substrate, in direct contact with a polycrystalline SiC (poly-SiC) support substrate.

[0005] Such a multilayer structure based on mono-SiC allows in particular vertical electrical conduction, thus enabling the manufacture of vertical power electronic components.

[0006] Interest in SiC has increased considerably in recent years, as power electronics components and integrated power systems based on monocrystalline SiC can handle much higher power density than their silicon counterparts, and with smaller active area dimensions.

[0007] The substrate, which must be thick enough to support the component formation, is ultimately thinned to obtain the complete set of electronic components ready for integration. Even if the substrate is of lower quality, the thinning steps and material loss remain cost contributors that are desirable to eliminate.

[0008] French patent FR3120736B1 describes a solution to this problem, proposing a manufacturing process for a multilayer mono-SiC structure on poly-SiC, comprising: the supply of a temporary graphite substrate; the deposition of a poly-SiC support layer on one or both main faces of the temporary substrate, but also on its lateral surface; the transfer of a useful mono-SiC layer onto the support layer, this transfer implementing molecular adhesion bonding; the formation of an active layer of doped mono-SiC on the useful layer; and the removal of the temporary graphite substrate and the poly-SiC layer from the lateral surface.

[0009] The temporary graphite substrate, a material much less expensive than poly-SiC and with a coefficient of expansion close to that of poly-SiC, allows only the desired thickness of poly-SiC to be deposited (and therefore avoids loss of poly-SiC by thinning) and has a reduced vertical resistivity while maintaining overall rigidity without risk of deformation during handling of the substrate.

[0010] The solution below, however, has the disadvantage of remaining relatively expensive and requiring relatively high poly-SiC deposition temperatures as well as surface treatment and / or grinding steps of the poly-SiC before the transfer of the mono-SiC layer, while poly-SiC is a material with relatively high hardness. SUMMARY OF THE INVENTION

[0011] The invention relates to a method for manufacturing a semiconductor structure which reduces manufacturing costs associated with the use of a polycrystalline SiC layer and limits the problems of grinding and polishing this same polycrystalline SiC layer, while retaining the advantages of manufacturing by transfer of a multilayer structure comprising a thin layer of single-crystal semiconductor material.

[0012] To this end, the invention relates in particular to a method for manufacturing a multilayer structure comprising the following steps: provide a load-bearing substrate made of a first material and comprising a first face, a second face opposite the first face and a lateral surface connecting the first and second faces; deposit on the carrier substrate a support layer of amorphous silicon carbide, said first material being different from amorphous silicon carbide, the support layer being deposited at least on the first face of the carrier substrate; transfer a useful layer of a semiconductor material onto the portion of the support layer deposited on the first face of the carrier substrate; heat treatment of the support layer so as to crystallize the initially amorphous silicon carbide.

[0013] The invention takes advantage of the use of amorphous silicon carbide, which serves as the base for transferring the useful layer. The advantage of amorphous silicon carbide, particularly compared to poly-SiC, is that it can be deposited at lower temperatures, very homogeneously, and particularly quickly. Furthermore, this material is softer than poly-SiC, thus facilitating polishing and / or grinding steps and therefore any necessary surface preparation prior to transferring the useful layer.

[0014] It should also be noted that the crystallization of amorphous silicon carbide can be obtained by a thermal annealing step which can take place at different times in the process according to the invention, this heat treatment being able to be carried out by different techniques.

[0015] In addition to the characteristics mentioned in the preceding paragraphs, the manufacturing process according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: the transfer is a transfer by gluing; the heat treatment step of the support layer also ensures heat treatment of the useful layer; The transfer by bonding is carried out according to the following steps: provision of a donor substrate comprising at least one area of ​​the semiconductor material of the useful layer on the upper part of the donor substrate; formation, by ion implantation, of a localized embrittlement plane in the area of ​​the semiconductor material of the donor substrate and separating the useful layer of semiconductor material from the rest of the donor substrate; The donor substrate is bonded to the portion of the support layer deposited on the first face of the carrier substrate; the donor substrate is then detached along the weakening plane to transfer the useful layer to the portion of the support layer deposited on the first face of the carrier substrate. The heat treatment step of the support layer is carried out after the bonding step and further ensures the detachment of the donor substrate along the weakening plane. the first material is graphite; the semiconductor material of the useful layer is a single-crystal material such as single-crystal silicon carbide or single-crystal gallium nitride; the thickness of the amorphous silicon carbide support layer is between 5 microns and 200 microns and preferably between 10 microns and 100 microns; the deposition of the amorphous silicon carbide support layer is also carried out on the second face and on the lateral surface of the carrier substrate; According to one embodiment, the heat treatment step of the support layer is carried out by means of laser annealing; the laser annealing step is carried out through the carrier substrate or through the useful layer; the process according to the invention includes a step of removing the carrier substrate after the transfer of the useful layer; the laser annealing step is carried out through the face of the amorphous silicon carbide support layer opposite the face onto which the useful layer is transferred; amorphous silicon carbide is doped, with the activation of the dopants being achieved during the heat treatment of the support layer.

[0016] The present invention also relates to a multilayer structure comprising: a load-bearing substrate formed of a first material and comprising a first face, a second face opposite the first face and a lateral surface connecting the first and second faces; a support layer of amorphous silicon carbide, said first material being different from amorphous silicon carbide, the support layer being deposited at least on the first face of the carrier substrate; a useful layer of a semiconductor material disposed on the portion of the support layer deposited on the first face of the carrier substrate.

[0017] The multilayer structure according to the invention may include one or more complementary features defined with reference to the process according to the invention, considered individually or according to all technically possible combinations. BRIEF DESCRIPTION OF THE FIGURES

[0018] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which Figures [Fig. 1], [Fig. 2], and [Fig. 3] illustrate an example of an embodiment of the process for manufacturing a multilayer structure according to the invention. Figure [Fig. 3] also illustrates an example of an intermediate multilayer structure according to the invention.

[0019] For clarity, identical or similar elements are identified by identical reference symbols across all figures. DETAILED DESCRIPTION

[0020] Figures 1 to 3 illustrate an example of an embodiment of the manufacturing process for a multilayer structure according to the invention.

[0021] As illustrated in Figure 1, the manufacturing process of the multilayer structure according to the invention includes a first step 100 of supplying a carrier substrate 1 formed of a first material.

[0022] The supporting substrate 1 comprises: a first face 1a, referred to interchangeably as the front face, a second face 1b, referred to interchangeably as the back face, opposite the first face 1a and a lateral surface 1c connecting the first and second faces 1a and 1b.

[0023] Advantageously, the coefficient of thermal expansion of the first material is matched to the coefficient of thermal expansion of a-SiC, which limits mechanical stresses in the structure during high-temperature operations or treatments.

[0024] The first material could be, for example, polycrystalline graphite or aluminum nitride (AIN).

[0025] According to a preferred embodiment, the first material is graphite. Graphite may, in particular, have a grain size between 4 µm and 35 µm, a porosity between 6% and 17%, and a coefficient of thermal expansion between 4 x 10⁻¹⁰⁸⁻¹⁰ ... 6 / °C and 5.10' 6 / °C.

[0026] The carrier substrate 1 may be in the form of a circular plate. The first and second faces 1a and 1b of the carrier substrate 1 are preferably flat and parallel to each other. The lateral surface 1c of the carrier substrate 1 connects the first and second faces 1a and 1b at their periphery.

[0027] The supporting substrate 1 advantageously has a thickness e greater than 100 pm. The thickness of the temporary substrate is measured along a direction perpendicular to the plane of the first and second faces 1a and 1b.

[0028] As illustrated in Figure 2, the manufacturing process of the multilayer structure according to the invention continues with a step 101 of deposition of a layer 2 of amorphous SiC support.

[0029] The support layer 2 comprises at least a first portion 2a deposited on the first face 1a of the carrier substrate 1. According to the embodiment illustrated in Figure 2, and optionally and advantageously, the support layer 2 here comprises a second portion 2b deposited on the lateral surface 1c and a third portion 2c deposited on the second face 1b of the carrier substrate 1.

[0030] Prior to the deposition of the a-SiC support layer 2, cleaning operations may be applied to the carrier substrate 1 to remove all or part of particulate, metallic or organic contaminants potentially present on its first and second faces 1a and 1b as well as on its lateral surface 1c.

[0031] The deposition can be carried out using any known technique, notably chemical vapor deposition (CVD) at low temperatures, for example, at a temperature of around 150°C to 850°C in the case of amorphous SiC. It should be noted that this temperature is much lower than that used for the deposition of polycrystalline SiC, which is generally between 850°C and 1650°C.

[0032] Examples of thermal CVD techniques include atmospheric pressure CVD (APCVD) and low pressure CVD (LPCVD). Plasma-enhanced CVD (PECVD) can also be used.

[0033] It should be noted that if support layer 2 is to ensure vertical electrical conduction, it must have low resistivity after the heat treatment described later. To guarantee this electrical conductivity property (low resistivity), necessary for example for vertical power components, support layer 2 can be doped with n-type or p-type doping as required. This might be the case, for example, when the subsequently transferred useful layer is made of single-crystal silicon carbide for vertically conductive components.

[0034] Alternatively, support layer 2 can be semi-insulating (resistivity between 10 2 Q.cm and 10 4 Q.cm), or even highly resistive (resistivity between 10 4 Q.cm and 10 8Q.cm), particularly in the case of side-conducting power components or radio frequency (RF) components. This can be the case, for example, when the subsequently transferred useful layer is made of single-crystal gallium nitride for side-conducting components.

[0035] The first portion 2a of the amorphous SiC support layer 2 preferably has a thickness e1 between 50 pm and 200 pm and preferably between 10 pm and 100 pm.

[0036] Advantageously, the growth rate of the support layer 2 is the same vertically and laterally so that the thickness e3 of the third portion and the thickness e2 of the second portion 2b of the support layer 2 are equal to the thickness e1 of the first portion 2a of the support layer 2.

[0037]

[0038] In general, the thickness of a deposited layer is measured along a direction perpendicular to the surface on which it is deposited.

[0039] According to an advantageous but non-limiting embodiment, surface treatment can be performed on the first and second portions 2a and 2b, and optionally on the third portion 2c. Specifically, the second portion 2b deposited on the lateral surface 1c can be ground to correct the thickness e2. This surface treatment aims to improve the surface roughness of the first portion 2a made of a-SiC. Conventional chemical etching and / or mechanical grinding and / or chemical polishing techniques can thus be implemented to achieve the desired surface roughness. Thanks to the invention, this grinding step is easier to perform with amorphous SiC than with poly-SiC, which is a harder material and therefore more difficult to surface treat.

[0040] The manufacturing process according to the invention then proceeds with a step of transferring a useful layer 3 onto the first portion 2a of the amorphous silicon carbide support layer 2. More precisely, the transfer of the useful layer 3 takes place on the free surface of the first portion 2a of the a-SiC support layer.

[0041] The useful layer 3 is made of a semiconductor material, preferably a single-crystal material. This single-crystal material is, for example, silicon carbide, an III-V semiconductor material (such as GaN), or an II-VI semiconductor material. Furthermore, it can be intrinsic or doped, of type n or type p (depending on the requirement).

[0042] The thickness of the useful layer 3 can be between 100 nm and 1500 nm.

[0043] The transfer of the useful layer 3 can be achieved by any known layer transfer technique. However, transfer techniques employing molecular adhesion, and therefore a bonding interface, are preferred.

[0044] Molecular adhesion bonding does not require an adhesive; bonds are formed at the atomic level between the surfaces being joined. Several types of molecular adhesion bonding exist, differing primarily in terms of temperature, pressure, atmosphere, or pretreatments before the surfaces are brought into contact. Examples include room-temperature bonding with or without prior plasma activation of the surfaces to be joined, atomic diffusion bonding (ADB), and surface-activated bonding (SAB).

[0045] The useful layer 3 can be transferred directly onto the free surface of the first portion 2a of the a-SiC support layer 2 or via an intermediate layer. The intermediate layer can be formed on the side of the useful layer 3 and / or on the side of the first portion 2a, to promote bonding, in particular by smoothing out residual roughness or surface defects present on the faces to be joined.

[0046] When the intermediate layer is metallic (e.g., tungsten) or made of a semiconductor material, such as a doped semiconductor (e.g., silicon), it can further promote vertical electrical conduction. Alternatively, the intermediate layer can be a metalloid layer, an electrically insulating layer (e.g., silicon oxide, silicon nitride), or an intrinsically conductive semiconductor material for applications not requiring vertical electrical conduction.

[0047] At the end of this step 102, we therefore obtain an intermediate multilayer structure 5 comprising: the supporting substrate 1 formed from the first material and comprising the first face 1a, the second face 1b opposite the first face 1a and the lateral surface 1c connecting the first and second faces; the support layer 2 made of amorphous silicon carbide, the first material, for example graphite, being different from amorphous silicon carbide, the support layer 2 being deposited at least on the first face 1a of the carrier substrate 1 (in this case, the a-SiC support layer 2 is deposited over the entire surface of the carrier substrate 1, and therefore on the first and second faces 1a and 1b as well as on the lateral surface 1c); the useful layer 3 of a semiconductor material disposed on the portion of the support layer deposited on the first face of the carrier substrate

[0048] The manufacturing process according to the invention further comprises a heat treatment step, variously referred to as "thermal annealing." As will be seen below, this heat treatment can occur at different points in the process according to the invention and aims to crystallize the support layer 2 in amorphous silicon carbide (it should be noted that according to the invention, it is not necessary to crystallize the entire support layer 2 but only the first portion 2a onto which the useful layer 3 is transferred). The temperature to be reached for the crystallization of the amorphous silicon carbide depends on the deposition techniques used and the composition (particularly the carbon percentage) but can reach temperatures exceeding 1000°C.

[0049] Advantageously, and as is known in reference to the Smart Cut™ process, transfer step 102 comprises the following successive substeps: the introduction of light species (typically hydrogen ions and / or helium ions), preferably by ion implantation, into a donor substrate to form a buried brittle plane, the buried brittle plane defining, together with the front face of the donor substrate, the useful layer 3; the assembly of the front face of the donor substrate onto the free surface of the first portion 2a of the α-SiC layer 2, directly or via an intermediate layer, by molecular adhesion bonding, along a bonding interface; and the separation along the buried fragile plane to transfer the useful layer 3 onto the free surface of the first portion 2a of the a-SiC support layer.

[0050] The separation is achieved, for example, by applying a heat treatment at a temperature that may be higher than the crystallization temperature of layer 2 in α-SiC, for example, above 1000°C, on the order of 1100°C. Thus, according to this first embodiment, the process according to the invention includes a heat treatment step that not only crystallizes layer 2 of amorphous silicon carbide but also ensures separation along the buried brittle plane to transfer the useful layer 3 onto layer 2 in α-SiC. It should also be noted that this thermal annealing step can, in the case of a doped α-SiC layer, activate the dopants present in the α-SiC.

[0051] The assembly sub-step may include, prior to bringing the faces to be assembled into contact, cleaning, surface activation or other surface preparation operations, which may promote the quality of the bonding interface (low defect, high adhesion energy).

[0052] In a known manner, the process according to the invention may then include a step of forming an active layer on the useful layer 3. The active layer may be deposited by epitaxial growth. The manufacturing process according to the invention may further include a step of fabricating one or more electronic components on and / or within the active layer. The electronic components may be, for example, transistors or other high-voltage and / or high-frequency components. It should be noted that these steps may be carried out at high temperatures (i.e., greater than or equal to 1600°C), particularly due to the presence of heat treatments. Thus, according to a second embodiment, even if the temperature reached during the heat treatment step carried out during the separation step is not sufficient to crystallize the amorphous silicon carbide of the support layer 2, the latter will crystallize during subsequent heat treatments.

[0053] It should also be noted that the graphite that can be used for the carrier substrate 1 is likely to cause contamination at such temperatures. The fact that the carrier substrate 1 is completely surrounded by layer 2 (via portions 2a, 2b, and 2c) prevents this risk of contamination.

[0054] According to a third embodiment, the heat treatment for crystallizing amorphous silicon carbide can be carried out by laser annealing, for example, using a laser with a beam wavelength in the ultraviolet. This laser annealing can be in the form of one or more pulses of a duration chosen to achieve crystallization. The advantage of laser annealing is that it allows for localized and rapid treatment. The laser treatment can be performed through the useful layer 3 after its transfer onto the support layer 2 and the portion 2a of the support layer 2 to be crystallized. The laser treatment can also be performed through the active layer deposited on the useful layer, the useful layer 3, and the portion 2a of the support layer 2 to be crystallized. It is also possible to perform this laser treatment via the back face 1b of the carrier substrate 1 (with or without removal of the portion 2c of the support layer 2).

[0055] According to a fourth embodiment, it is also possible to cut and remove the lower part of the multilayer structure 5 formed by portion 2c of the support layer 2, so as to retain the assembly comprising the first portion 2a onto which the useful layer 3 is transferred and a portion of the second portion 2b and the carrier substrate 1. According to this fifth embodiment, the remaining carrier substrate present in this assembly can then be removed. Once this removal has been carried out, the laser treatment can be performed directly through the back face of portion 2a of the support layer 2. The cutting step can, for example, be carried out using a laser, and the step of removing the material from the carrier substrate 1 can, for example, be carried out by an abrasive blasting or burning step.

[0056] The laser processing step according to this fourth embodiment can advantageously be carried out by attaching a handle to the upper face of the useful layer 3 or the active layer (on which the components are formed) to ensure the mechanical strength of the assembly.

Claims

DEMANDS

1. A method for manufacturing a multilayer structure comprising the following steps: • provide a load-bearing substrate made of a first material and comprising a first face, a second face opposite the first face and a lateral surface connecting the first and second faces; • deposit on the carrier substrate a support layer of amorphous silicon carbide, said first material being different from amorphous silicon carbide, the support layer being deposited at least on the first face of the carrier substrate; • surface treatment of the support layer to improve the surface roughness of said support layer • transfer a useful layer of a single-crystal semiconductor material onto the portion of the support layer deposited on the first face of the carrier substrate; • heat treatment of the support layer so as to crystallize the initially amorphous silicon carbide.

2. A method according to the preceding claim in which the transfer is a transfer by gluing.

3. A method according to any one of the preceding claims wherein the heat treatment step of the support layer further provides heat treatment of the useful layer.

4. A method according to any one of the preceding claims, characterized in that the transfer by gluing is carried out according to the following steps: - provision of a donor substrate comprising at least one area of ​​the semiconductor material of the useful layer on the upper part of the donor substrate; - formation, by ion implantation, of a localized weakening plane in the area of ​​the semiconductor material of the donor substrate and separating the useful layer of semiconductor material from the rest of the donor substrate; - bonding of the donor substrate to the portion of the support layer deposited on the first face of the carrier substrate; - detachment of the donor substrate along the weakening plane in order to transfer the useful layer onto the portion of the support layer deposited on the first face of the carrier substrate.

5. A method according to the preceding claim wherein the heat treatment step of the support layer is carried out after the bonding step and further ensures the detachment of the donor substrate along the embrittlement plane.

6. A method according to any one of the preceding claims wherein the first material is graphite.

7. A method according to any one of the preceding claims wherein the useful layer is made of single-crystal silicon carbide or single-crystal gallium nitride.

8. A method according to any one of the preceding claims wherein the thickness of the amorphous silicon carbide support layer is between 5 microns and 200 microns and preferably between 10 microns and 100 microns.

9. A method according to any one of the preceding claims wherein the deposition of the amorphous silicon carbide support layer is also carried out on the second face and on the lateral surface of the carrier substrate.

10. A method according to any one of the preceding claims wherein the heat treatment step of the support layer is carried out by means of laser annealing.

11. A method according to the preceding claim in which the laser annealing step is carried out through the carrier substrate or through the useful layer.

12. A method according to any one of the preceding claims comprising a step of removing the carrier substrate after the transfer of the useful layer.

13. A method according to claims 10 and 12, wherein the laser annealing step is carried out through the face of the amorphous silicon carbide support layer opposite the face onto which the useful layer is transferred.

14. A method according to any one of the preceding claims, wherein the amorphous silicon carbide is doped, the activation of the dopants being achieved during the heat treatment of the support layer.

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