Image sensor assembly with charge pump circuit for pixel driver circuits

Abstract

An image sensor assembly includes a main capacitor with a working electrode and a reference electrode electrically connected to a global reference potential GND. A charge pump circuit connects a flying capacitor between a positive supply voltage VDD and the global reference potential GND in first phases and between a controllable node and the working electrode of the main capacitor in second phases. A protection circuit reduces a voltage across the flying capacitor when a burn-in protection signal VBP is active. A constant voltage source outputs a constant voltage VOUT referenced to a local reference potential VRL of the working electrode of the main capacitor. A pixel driver circuit outputs a pixel control signal referenced to the constant voltage VOUT.

Description

[0001] 73952

[0002] 1

[0003] IMAGE SENSOR ASSEMBLY WITH CHARGE PUMP CIRCUIT FOR PIXEL DRIVER CIRCUITS

[0004] The present disclosure relates to an image sensor assembly with pixel circuits and with a charge pump circuit for generating reference potentials for pixel driver circuits that control the pixel transistors in the pixel circuits.

[0005] BACKGROUND

[0006] Active pixel sensors (APS) convert radiation into analog voltage signals. For each image point, the active pixel sensor includes a pixel circuit with a photoelectric conversion element and three, four, or more pixel transistors. The photoelectric conversion element transforms incident radiation into a photocurrent. The transistors control reset, exposure time, pixel readout and possibly pixel sensitivity. Internal reference potentials of the pixel circuits and the gate voltages of the pixel transistors are precisely adjusted to the circuit design. Pixel driver circuits providing the gate voltages and pixel reference voltages require a sufficiently low local reference potential for providing the sufficiently low gate voltage levels.

[0007] SUMMARY

[0008] Typically, an external power supply circuit supplies an image sensor with various positive supply voltages that are referenced to a global reference potential GND. The image sensor receives the positive supply voltages. From one of the positive supply voltages, internal charge pump circuits generate local supply and / or reference potentials which are negative with reference to the global reference voltage GND. Each charge pump circuit uses a comparatively large output capacitance which is typically a comparatively large discrete capacitor. The capacitors and the image sensor are mounted next to each other on a printed circuit board.

[0009] The present disclosure addresses deficiencies in image sensor assemblies with charge pump circuits for pixel driver circuits. To this end, an image sensor assembly includes a main capacitor with a working electrode, and a reference electrode electrically connected to a global reference potential GND. A charge pump circuit connects a flying capacitor between a positive supply voltage VDD and the global reference potential GND in first phases and between a controllable node and the working electrode of the main capacitor in second phases. A protection circuit reduces a voltage across the flying capacitor when a bumin protection signal VBP is active. A constant voltage source outputs a constant voltage VOUT referenced to a local reference potential VRL of the working electrode of the main capacitor. A pixel driver circuit outputs a pixel control signal referenced to the constant voltage VOUT.

[0010] The constant voltage source decouples the pixel drivers and the pixel circuits controlled by the pixel drivers from the noise that passes through and / or is generated the charge pump circuit. The protection circuit reduces the voltage stress on the flying capacitor, especially in a boost mode when the main capacitor is fully charged for the first time after the image sensor assembly wakes up from a stand-by operating mode.

[0011] BRIEF DESCRIPTION OF THE DRAWINGS2

[0012] A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0013] FIG. 1 is a simplified block diagram of an image sensor assembly with a charge pump circuit and a protection circuit, in accordance with an embodiment.

[0014] FIG. 2 is a simplified block diagram of a portion of an image sensor assembly with a charge pump circuit, a protection circuit, a constant voltage source and a pixel driver circuit, in accordance with an embodiment.

[0015] FIG. 3 is a circuit diagram of pixel circuit with four pixel transistors, suitable for an image sensor assembly according to the embodiments.

[0016] FIG. 4 is a circuit diagram of pixel circuit with six pixel transistors, suitable for an image sensor assembly according to the embodiment.

[0017] FIG. 5 is a simplified block diagram of a portion of an image sensor assembly with a charge pump circuit, a protection circuit, a plurality of constant voltage sources and a pixel driver circuit, in accordance with an embodiment.

[0018] FIG. 6A is a circuit diagram of a comparator circuit in combination with a charge pump circuit and a protection circuit connected to VDD, in accordance with an embodiment.

[0019] FIG. 6B is a simplified timing diagram for control signals controlling the charge pump circuit of FIG. 6A.

[0020] FIG. 6C is a timing diagram for a local reference potential at the working electrode of the main capacitor for the charge pump circuit of FIG. 6A.

[0021] FIG. 6D is a circuit diagram of a comparator circuit in combination with a charge pump circuit and a protection circuit connected to GND, in accordance with an embodiment.

[0022] FIG. 7A and 7B are block diagrams of protection circuits for the flying capacitor of the charge pump circuit of a row driver assembly, in accordance with embodiments.

[0023] FIG. 8 A and 8B are circuit diagrams of protection circuits for the flying capacitor of the charge pump circuit of a row driver assembly, according to embodiments providing a single diode.

[0024] FIG. 9A and 9B are circuit diagrams of protection circuits for the flying capacitor of the charge pump circuit of a row driver assembly, according to embodiments providing two diodes electrically connected in series.3

[0025] FIG. 10A and 10B are circuit diagrams of protection circuits for the flying capacitor of the charge pump circuit of a row driver assembly, according to embodiments providing a diode-connected transistor.

[0026] FIG. 11 is a circuit diagram of a comparator circuit in combination with a charge pump circuit and a protection circuit, in accordance with another embodiment.

[0027] FIG. 12 is a circuit diagram of a constant voltage source based on a linear regulator and suitable for an image sensor assembly according to the embodiments.

[0028] FIG. 13A is a circuit diagram of a constant voltage source based on a resistor ladder and a class AB amplifier and suitable for an image sensor assembly according to the embodiments.

[0029] FIG. 13B schematically shows noise amplitudes in a constant voltage source without noise reduction circuit between resistor ladder and class AB amplifier for discussing effects of embodiments.

[0030] FIG. 13C schematically shows noise amplitudes in a constant voltage source including an RC filter between resistor ladder and class AB amplifier for discussing effects of embodiments.

[0031] FIG. 13D schematically shows noise amplitudes in a constant voltage source including a SH element between resistor ladder and class AB amplifier for discussing effects of embodiments.

[0032] FIG. 14 is a simplified block diagram of a portion of an image sensor assembly with a charge pump circuit, a protection circuit, and a constant voltage source with an input connected to a global reference potential GND, in accordance with an embodiment.

[0033] FIG. 15 is a simplified block diagram of a portion of an image sensor assembly with a charge pump circuit, a protection circuit, and a constant voltage source with an input connected via a shared terminal to an output of a power management integrated circuit, in accordance with an embodiment.

[0034] FIG. 16 is a simplified block diagram of a portion of an image sensor assembly with a charge pump circuit, a protection circuit, and a constant voltage source having an input connected via a dedicated terminal to an output of a power management integrated circuit, in accordance with an embodiment.

[0035] FIG. 17 is a schematic diagram illustrating an embodiment in which an image sensor has a two-layer structure in a stacked CIS configuration.

[0036] FIG. 18 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0037] FIG. 19 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG. 18.

[0038] DETAILED DESCRIPTION4

[0039] Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various features in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

[0040] The terms “electrically connected”, “signal-connected”, and “operatively connected” may include a direct connection or a connection through other electronic elements provided and suitable for permanent and / or temporary signal transmission and / or transmission of energy. Electronic elements can be electrically connected, signal-connected and operatively connected via resistors, capacitors, electronic switches such as field effect transistors, or transistor circuits such as transmission gates. At least one electrical signal in a second electrical circuit that is in signal-connection or operational connection with a first electrical circuit responds in a predictable, intended manner to a change of an electrical signal in the first electrical circuit. Directly electrically connected electronic elements are connected through a permanent low-resistive wiring, an ohmic contact and / or a unipolar semiconductor junction.

[0041] The load path of a transistor is the controlled current path through a transistor. A voltage applied to the gate of a field effect transistor controls the current flow through the load path (controlled path) between source and drain of the transistor by field effect. When transistors are electrically connected in series, the load paths of the transistors are electrically connected in series. When transistors are electrically connected in parallel, the load paths of the transistors are electrically connected in parallel.

[0042] A digital signal alternates between at least one active level and at least one inactive level. A digital signal having an active level is active. A digital signal having an inactive level is inactive. For each signal separately, the active level can be a digital high level and the inactive level a digital low level, or the active level can be the digital low level and the inactive level the digital high level. Digital signals include binary signals alternating between one active level and one inactive level.

[0043] FIG. 1 illustrates a configuration example of an image sensor assembly 90 with an image sensor 70, a signal processing unit 80 and a main capacitor 250.

[0044] The image sensor 70 includes a pixel array 10, a row driver assembly 20, a row decoder 21, a column signal unit 30 with integrated readout circuit, and a sensor controller 50.

[0045] The pixel array 10 includes a plurality of pixel circuits 100. Each pixel circuit 100 includes a photoelectric conversion element and pixel transistors for controlling the signal output by the photoelectric conversion element. The pixel circuits 100 may be any active pixel sensors adapted for intensity readout. The pixel transistors may be field effect transistors (FETs), e.g. metal oxide semiconductor field effect transistors (MOSFETs).5

[0046] The pixel array 10 may be a two-dimensional array, wherein the photoelectric conversion elements of the pixel circuits 100 may be arranged along straight or meandering rows and along straight or meandering columns in a horizontal plane of a pixel substrate.

[0047] The pixel circuits 100 may be connected along columns and along rows. A subset of pixel circuits 100 assigned to the same row form a pixel row. The pixel circuits 100 of the same pixel row may share common pixel control lines and may be addressed synchronously. A subset of pixel circuits 100 assigned to the same column form a pixel column. The pixel circuits 100 of the same pixel column share at least one common data signal line (vertical signal line). The pixel output signals of the pixel circuits 100 of the same pixel column are successively passed to the same data signal line in a time division multiplexing scheme.

[0048] The row decoder 21 and the row driver assembly 20 control driving of each pixel circuit 100 of the pixel array 10. In particular, the row decoder 21 may supply one or more control signals for designating the pixel circuit 100 or the pixel row to be controlled to the row driver assembly 20 according to an address signal and / or a driver timing signal supplied from the sensor controller 50.

[0049] The row driver assembly 20 includes the main capacitor 250 and a charge pump circuit 230 with a flying capacitor 235. By sequentially charging the flying capacitor 235 from a positive supply voltage VDD in first phases and connecting the flying capacitor 235 to a working electrode of the external main capacitor 250 in second phases, the charge pump circuit 230 charges the main capacitor 250 to a predefined local reference potential VRL in a boost mode after waking up from a stand-by operating mode. The predefined local reference potential VRL can be negative with regard to the global reference potential GND. The charge pump circuit 230 keeps the local reference potential VRL approximately constant in a continuous operation mode following the boost mode. A protection circuit 240 reduces a voltage effective across the flying capacitor 235 when a bum-in protection signal VBP is active. The local reference potential VRL is passed to one or more constant voltage sources 260. Each constant voltage source 260 outputs a constant voltage VOUT referenced to the local reference potential VRL. The output signals VOUT of the constant voltage sources 260 have reduced noise compared to the local reference potential VRL. Using a positive supply voltage VDD as high buffer supply voltage and the constant voltage VOUT as low buffer supply voltage, pixel driver circuits 270 drive pixel control signals for the pixel circuits 100 in the pixel array 10 according to output signals of the row decoder 21.

[0050] The output signals of the pixel circuits 100 (pixel signals) are passed through data signal lines to the column signal unit 30. The column signal unit 30 may include one or more identical column signal circuits, wherein each column signal circuit receives pixel signals via one or more of the data signal lines. The column signal unit 30 may include as much column signal circuits as the pixel array unit 10 includes data signal lines or pixel columns. Alternatively, the number of column signal circuits may be lower than the number of pixel columns, wherein each column signal circuit may be multiplexed between two or more of the data signal lines. Each column signal circuit includes an analog-to-digital converter (ADC) performing an analog-to-digital conversion on the pixel output signals successively read out from the respective pixel column. Each ADC may include a comparator, a digital-to-analog converter (DAC) and a counter to convert each pixel output signal into digital pixel data DPXS.6

[0051] The column signal unit 30 further includes a horizontal driving circuit that controls the elements of the column signal circuits to pass the pixel data DPXS of the pixel columns through a data interface to the signal processing unit 80.

[0052] The sensor controller 50 controls the other components of the image sensor 70. For example, the sensor controller 50 may supply a timing signal for addressing the selected pixel row to the row decoder 21. The sensor controller 50 may supply one or more control signals for controlling the column signal unit 30, e.g., the horizontal driving circuit and the ADCs, the protection circuit 240, the charge pump circuit 240 and / or the constant voltage source 260.

[0053] FIG. 2 shows a part of the row driver assembly 21 of the image sensor assembly 70 of FIG. 1. A main capacitor 250 includes a reference electrode 251 electrically connected to a global reference potential GND, and a working electrode 252. A charge pump circuit 230 is configured to connect a flying capacitor 235 between a positive supply voltage VDD and the global reference potential GND in first phases and between a controllable node 229 and the working electrode 252 of the main capacitor 250 in second phases. A protection circuit 240 is configured to reduce a voltage across the flying capacitor 235 when a bum-in protection signal VBP is active. A constant voltage source 260 is configured to output a constant voltage VOUT referenced to a local reference potential VRL of the working electrode 252 of the main capacitor 250. A pixel driver circuit 270 is configured to output a pixel control signal CTR_B referenced to the constant voltage VOUT.

[0054] In the illustrated example, the main capacitor 250 is a discrete capacitor. The main capacitor 250 and the image sensor 70 are placed next to each other on an assembly surface of a substrate 300, e.g., a printed circuit board (PCB). The reference electrode 251 of the main capacitor 250 is electrically connected to a ground line distributing the global reference potential GND on the substrate 300. A conductor track connects the working electrode 252 of the main capacitor 250 with a VRL terminal of the image sensor 70. A VRL conductor line directly electrically connects the VRL terminal with an output of the charge pump circuit 230 and with reference accesses of the constant voltage sources 260, and distributes the local reference potential VRL in the image sensor 70.

[0055] The charge pump circuit 230 includes the flying capacitor 235 and a set of semiconductor switches. The set of semiconductor switches can assume at least two different switching states. In a first switching state, the set of semiconductor switches connects the flying capacitor 235 between a positive supply voltage VDD and the global reference potential GND, wherein the flying capacitor 235 is charged through the positive supply voltage VDD. In a second switching state, the set of semiconductor switches connects the flying capacitor 235 between a potential lower than the positive supply voltage VDD and the working electrode 252 of the main capacitor 250, wherein the voltage at the working electrode 252 of the main capacitor 250 is reduced by an amount resulting from the charge of the flying capacitor 235.

[0056] The protection circuit 240 for reducing a maximum voltage across the flying capacitor 235 may be placed between a supply line for the positive supply voltage VDD and the flying capacitor 235 and / or between the7

[0057] flying capacitor 235 and the global reference potential GND. The flying capacitor 235 is a comparatively small device with a capacitance several orders of magnitudes smaller than the capacitance of the main capacitance 250, and may be susceptible to voltage breakdown. The statistical probability for a voltage breakdown of the capacitor dielectric increases with increasing voltage stress induced by the charging current. The protection circuit 240 allows connecting the charge pump circuit 230 to a voltage supply line conveying a comparatively high supply voltage VDD and at the same time significantly reduces the mean time between failures (MTBF) of the charge pump circuit 230.

[0058] The constant voltage source 260 may include any electronic circuits capable of supplying a constant output voltage VOUT despite of load changes within a predefined load window. The constant voltage sources may be or include line regulators e.g. low-dropout (LDO) regulators with or without boosting function, or flipped-voltage-follower (FVF) regulators. Another type of constant voltage source is based on an amplifier stage buffering an input voltage which may be tapped from a resistor ladder.

[0059] The pixel driver circuit 270 may include an active amplifier circuit supplied with a high positive supply voltage VDDH as high buffer supply voltage, and the constant output voltage VOUT of the constant voltage source 260 as low buffer supply voltage. The image sensor 70 may receive the high positive supply voltage VDDH from an external power supply circuit through a VDDH supply terminal. The high positive supply voltage VDDH is a positive voltage with reference to the global reference potential GND. The constant output voltage VOUT serving as the low buffer supply voltage may be a negative voltage with reference to the global reference potential GND.

[0060] The pixel driver circuit 270 may receive a digital pixel control signal CTR alternating between a buffer input low level and a buffer input high level and outputs a buffered pixel control signal CTR B alternating between a buffer output low level and a buffer output high level. The pixel driver circuit 270 may be effective as level-shifter. In particular, the buffer input low level and the buffer output low level differ from each other and / or the buffer input high level and the buffer output high level differ from each other. The pixel driver circuit 270 may have a comparatively high input impedance with respect to the pixel control signal CTR and may have a comparatively low output impedance with respect to the buffered pixel control signal CTR B.

[0061] The buffered and / or level-shifted pixel control signal CTR B may be passed to one single pixel circuit 100, to the pixel circuits 100 of one or more pixel rows, to a portion of a pixel row, or to all pixel circuits 100 of the image sensor 70. Each pixel circuit 100 may include a photoelectric conversion element and several pixel transistors, e.g. field effect transistors (FETs). The pixel transistors may include a transfer transistor for temporarily connecting the photoelectric conversion element with a floating diffusion region, a reset transistor for presetting the floating diffusion to a pre-defined potential and a selection transistor for selectively connecting a pixel output node of a pixel circuit to a data signal line.

[0062] The image sensor assembly 90 further includes a pixel circuit 100 configured to output a pixel voltage signal with a voltage being a function of intensity of incident radiation, the pixel circuit 100 including a pixel transistor controllable by the pixel control signal.8

[0063] FIG. 3 shows one of the examples of a pixel circuit 100 that can be used in the image sensor 70 of FIG. 1 or FIG. 2. The pixel circuit 100 includes a photodetector 101, a transfer transistor 102, a sense region 111, and a pixel readout circuit with a reset transistor 103, an amplifier transistor 109, and a select transistor 110.

[0064] The photodetector 101 includes a photoelectric conversion element that photoelectrically converts incident electromagnetic radiation into electric charges. The amount of electric charge generated in the photodetector 101 corresponds to the intensity of incident electromagnetic radiation. The photodetector 101 may include or consist of a photodiode which converts electromagnetic radiation incident on a detection surface into a detector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation and / or ultraviolet radiation. The amplitude of the detector current is a function of the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the detector current may increase approximately linearly with increasing intensity of the detected electromagnetic radiation.

[0065] The sense region 111 can include a floating diffusion region and / or a capacitor electrode. In a reset phase, a potential of the sense region 111 is a function of the pixel dark current representing the noise. In a data phase, the potential of the sense region 111 is a function of the integrated detector current.

[0066] A load path of the transfer transistor 102 may electrically connect a cathode of the photodetector 101 and the sense region 111. The transfer transistor 102 serves as transfer element for transferring charge from the photodetector 101 to the sense region 111 in or after an integration period. A transfer signal TRG is supplied to the gate (transfer gate) of the transfer transistor 102 through a transfer signal line. The transfer signal TRG changes between an active signal level (“active transfer signal”) and an inactive signal level (“inactive transfer signal”). In response to an active transfer signal TRG, the transfer transistor 102 may transfer electrons photoelectrically converted by the photodetector 101 to the sense region 111. In the illustrated example, the active signal level is the high level.

[0067] A reset signal RST is supplied to a gate of the reset transistor 103 through a reset control line. The reset signal RST changes between an active signal level (“active reset signal”) and an inactive signal level (“inactive reset signal”). In response to an active reset signal RST, the reset transistor 103 may connect the sense region 111 to a reset potential, which may be the positive supply potential VDD. In the illustrated embodiment, the active signal level is the high level.

[0068] A controlled load path of the amplifier transistor 109 is electrically connected between the positive supply potential VDD and a data signal line 190. The sense region 111 is connected to the gate of the amplifier transistor 109. A potential at the gate of the amplifier transistor 109 is equal to the potential of the sense region 111. When the pixel circuit 100 is selected, the amplifier transistor 109 may be in a source follower configuration with a constant current source electrically connected to the data signal line 190.

[0069] In particular, the load path of the amplifier transistor 109 and a load path of the select transistor 110 may be electrically connected in series between the positive supply potential VDD and the data signal line 190.9

[0070] A row select signal SEL is supplied to the gate of the select transistor 110 through a select signal line. The select signal SEL changes between an active signal level (“active select signal”) and an inactive signal level (“inactive select signal”). In the illustrated example, the select transistor 110 is an nFET (n channel field effect transistor) and the active signal level is the high level. The active select signal turns on the select transistor 110.

[0071] The transfer signal TRG, the reset signal RST and the select signal SEL are examples for the buffered pixel control signal CTR_B of FIG. 2. Each of the transfer transistor 102, the reset transistor 103, and the select transistor 110 can benefit from a buffered control signal output by a pixel driver circuit 270 using the low-noise constant voltage VOUT output by the constant voltage source 260 as low buffer supply voltage. With the negative low buffer supply voltages, the pixel driver circuits can output low gate voltages which may in turn allow very low leakage currents through the respective pixel transistor in the off-state.

[0072] FIG. 4 shows a pixel circuit 100 with an additional photodetector 105, an additional floating diffusion transistor 104 and an additional floating capacitance transistor 106. The load path of the reset transistor 103 is electrically connected between the positive supply potential VDD and a storage region 112.

[0073] The photodetector 101 and the additional photodetector 105 may have different sensitivities. A load path of the floating capacitance transistor 106 is electrically connected between a cathode of the additional photodetector 105 and the storage region 112. The floating capacitance transistor 106 serves as transfer element for transferring charge from the additional photodetector 105 to the storage region 112 in or after an integration period. A floating capacitor signal FCG is supplied to the gate of the floating capacitance transistor 106 through a floating capacitor signal line. The floating capacitor signal FCG changes between an active signal level (“active transfer signal”) and an inactive signal level (“inactive transfer signal”). In response to an active floating capacitor signal FCG, the floating capacitance transistor 106 may transfer electrons photoelectrically converted by the additional photodetector 105 to the storage region 112. In the illustrated example, the active signal level is the high level.

[0074] A load path of a floating diffusion transistor 104 is electrically connected between the storage region 112 and the sense region 111. The floating diffusion transistor 104 may transfer charge between the storage region 112 to the sense region 111 in or after an integration period and / or in the reset period. A floating diffusion signal FDG is supplied to the gate of the floating diffusion transistor 104 through a floating diffusion signal line. The floating diffusion signal FDG changes between an active signal level (“active transfer signal”) and an inactive signal level (“inactive transfer signal”). In response to an active floating diffusion signal FDG, the floating diffusion transistor 104 may transfer charges between the storage region 112 and the sense region 111. In the illustrated example, the active signal level is the high level.

[0075] A first auxiliary capacitance 107 may be effective between the storage region 112 and a first auxiliary potential VEC. A second auxiliary capacitance 108 may be effective between the cathode of the additional photodetector 105 and a second auxiliary potential FCVDD.10

[0076] Each of the transfer signal TRG, the reset signal RST, the select signal SEL, the floating diffusion signal FDG, the floating capacitor signal FCG, the first auxiliary potential VEC, and the second auxiliary potential FCVDD are examples for the buffered pixel control signal CTR B of FIG. 2. Each of the transfer transistor 102, the reset transistor 103, the floating diffusion transistor 104, the floating capacitance transistor 106, and the select transistor 110 can benefit from a buffered control signal output by a pixel driver circuit 270, which uses the low-noise constant voltage VOUT output by the constant voltage source 260 as described with reference to FIG. 2 as low buffer supply voltage.

[0077] In FIG. 5, the image sensor assembly 70 includes a plurality of constant voltage sources 260-1, 260-2, ... , each constant voltage source circuit 260-1, 260-2, ..., being configured to output a constant voltage VOUT1, VOUT2, VOUT3 referenced to the local reference potential VRL.

[0078] In the illustrated example, each constant voltage source 260-1, 260-2, ... receives a positive supply voltage VDD at an input. The positive supply voltage VDD may be a low positive supply voltage VDDL of 0.8V or less, a medium positive supply voltage VDDM higher than the low positive supply voltage VDDL or a high positive supply voltage VDDH higher than the medium positive supply voltage VDDM. For example, the medium positive supply voltage VDDM may be about 1.8V or less and the high positive supply voltage VDDH may be about 3.3V or less. According to another example, the global reference potential GND may be supplied to the input of at least one of the constant voltage sources 260-1, 260-2, ... . Each constant voltage source 260-1, 260-2, ... may receive the same voltage at the input. According to another example, the constant voltage sources 260-1, 260-2, ... may receive at least two different voltages at the inputs.

[0079] Each constant voltage source 260-1, 260-2, ... is connected to the local reference potential VRL and outputs a constant voltage VOUT1, VOUT2, ... with reference the local reference potential VRL. Each constant voltage source 260-1, 260-2, ... may output the same constant voltage or different constant voltages.

[0080] The constant voltages sources 260-1, 260-2, ... may be assigned to groups of voltage sources, wherein each group provides the low buffer supply voltages for all pixel driver circuits 270 of one or more pixel rows.

[0081] In the illustrated example, the image sensor assembly 70 further includes a comparator circuit 220 configured to change a potential of the controllable node 229 depending on a voltage difference between the local reference potential VRL and the global reference potential GND.

[0082] In particular, the comparator circuit 220 may be configured to supply a first voltage to the controlled node 229 when a voltage difference between the local reference potential VRL and the global reference potential GND is less than a predetermined threshold, and a second voltage higher than the first voltage otherwise.

[0083] FIG. 6A shows a charge pump circuit 230 for charging a working electrode of a main capacitor 250 to a negative voltage with respect to a global reference potential GND from a supply voltage VDD which is positive with respect to the global reference potential GND.73952

[0084] 11

[0085] The charge pump circuit 230 includes a flying capacitor 235, a first set of switches 232, 233 for connecting the flying capacitor 235 between a positive supply voltage VDD and the global reference potential GND in first phases and a second set of switches 231, 234 for connecting the flying capacitor 235 between a controllable node 229 and the working electrode of the main capacitor 250 in second phases. The potential at the working electrode of the main capacitor 250 provides the local reference potential VRL.

[0086] In the illustrated example, the first set of switches 232, 233 includes p-channel FETs and the second set of switches 231, 234 include n-channel FETs. A first control signal PHI controls a first switch 231 with a controlled path between the controlled node 226 and a first electrode of the flying capacitor 235, and a second switch 232 with a controlled path between the positive supply potential VDD and the first electrode of the flying capacitor 235. A second control signal PH2 controls a fourth switch 234 with a controlled path between the second electrode of the flying capacitor 235 and the working electrode of the main capacitor 250.

[0087] A third control signal PH3 controls a third switch 233 with a controlled path between the second electrode of the flying capacitor 235 and the global reference potential GND. A digital high level of the first control signal PHI turns on the first switch 231 and turns off the second switch 232. A digital low level of the first control signal PHI turns off the first switch 231 and turns on the second switch 232. A digital high level of the second control signal PH2 turns on the fourth switch 234, and a digital low level of the second control signal PH2 turns off the fourth switch 234. A digital high level of the third control signal PH3 turns off the third switch 233, and a digital low level of the third control signal PH3 turns on the third switch 234. The sensor controller 50 of FIG. 1 or another circuit of the image sensor assembly generates the first, second and third control signals PHI, PH2, PH3 for the charge pump circuit 230.

[0088] A comparator circuit 230 includes a first constant current source 221 and a first resistive load 222 electrically connected in series in this order between a positive supply voltage VDD and the global reference potential GND. A second constant current source 226 and a second resistive load 227 are electrically connected in series in this order between the positive supply voltage VDD and the working electrode of the main capacitor 250. The comparator circuit 230 further includes an amplifier circuit 225.

[0089] A comparator reference voltage VRF at the node between the first constant current source 221 and the first resistive load 222 is passed to the non-inverting input of the amplifier circuit 225. A sense voltage VSN at the node between the second constant current source 226 and the second resistive load 227 is passed to the inverting input of the amplifier circuit 225. The sense voltage VSN is the lower, the more negative the local reference voltage VLR is with respect to the global reference voltage GND.

[0090] In a stand-by operating mode of an image sensor assembly, the first, second and third control signals PHI, PH2, PH3 may set the charge pump circuit into an idle state. The local reference voltage VRL is equal to the global reference voltage GND, e.g. OV The sense voltage VSN at the inverting input of the amplifier circuit 225 is higher than the comparator reference voltage VRF. The amplifier circuit 225 sets the controlled node 226 to a low voltage of about 0V.73952

[0091] 12

[0092] When at tl the image sensor wakes up from the stand-by operating mode, the first, second, and third control signals PHI, PH2, PH3 begin to alternate between the digital high level and the digital low level at the same clock rate.

[0093] As illustrated in FIG. 6B, rising and falling edges of the second and third control signals PH2, PH3 may be at least approximately synchronous with the corresponding rising and falling edges of the first control signal PHI. In the illustrated example, small offsets between the falling edges of the control signals PHI, PH2, PH3 provide a successive biasing of the concerned nodes and avoid a high dynamic current. According to another example, at least the second switch 232 and the third switch 233 may be turned off and on simultaneously, and / or the first switch 231 and the fourth switch 234 may be turned off and on simultaneously.

[0094] In first phases, the first to third control signals PHI, PH2, PH3 have the digital low level, the second and third switches 232, 233 are “on” and the first and fourth switches 231, 234 are “off’. The flying capacitor 235 is charged to the positive supply potential VDD.

[0095] In second phases, the first to third control signals PHI, PH2, PH3 have the digital high level, the second and third switches 232, 233 are “off’ and the first and fourth switches 231, 234 are “on”. The potential at the first electrode of the flying capacitor 235 is forced to about 0V. The potential at the second electrode of the flying capacitor 235 is forced to a voltage depending on the voltage drop across the flying capacitor 235 in the preceding first phase and the capacitance ratio between flying capacitor 235 and the main capacitor. A portion of the charge of the flying capacitor 235 is discharged to the working electrode of the main capacitor 250.

[0096] With each cycle including a first phase and a second phase, the local reference voltage VRL gets more negative by an amount given by the positive supply voltage VDD and the ratio between the capacitance of the flying capacitor 235 and the capacitance of the main capacitor 250. The ratio between the capacitance of the flying capacitor 235 and the capacitance of the main capacitor 250 is less than 0.001. FIG. 6C shows the local reference potential VRL gradually becoming more negative in the boost mode (boosting period) after tl.

[0097] With decreasing local reference potential VRL, the sense voltage VSN at the inverting input of the amplifier circuit 225 decreases. At t2, the sense voltage VSN falls below the comparator reference voltage VRF and the amplifier circuit 225 sets the controlled node 226 to a high voltage of approximately the positive supply voltage VDD. When changing from the first phase to the second phase, the voltage at the first electrode of the flying capacitor 235 remains the same. The charge and the local reference potential VRL remains unchanged. FIG. 6C shows the transition of the charge pump circuit 230 from the boost mode after tl to a saturation mode after t2. In the saturation mode, local reference potential VRL changes only within a small voltage window.

[0098] Only when the main capacitor 250 discharges to a degree that the sense voltage VSN exceeds the comparator reference voltage VRF, the charge pump circuit 230 returns to the boost mode until the sense73952

[0099] 13

[0100] voltage VSN again falls below the comparator reference voltage VRF. As illustrated in FIG. 6C, the local reference potential VRL is essentially constant in the saturation mode after t2 (saturated period).

[0101] The protection circuit 240 reduces the voltage effective across the flying capacitor in the first and second phases. In the example illustrated in FIG. 6A, the protection circuit 240 reduces the positive supply voltage VDD to a voltage RVDD which is lower than the positive supply voltage VDD. In the example illustrated in FIG. 6D, the protection circuit 240 generates a local reference potential RGND which is above the global reference potential GND.

[0102] FIG. 7A shows a protection circuit 240 that includes a diode circuit 241 electrically connected between the positive supply voltage VDD and the flying capacitor 235. The protection circuit 240 in FIG. 7B includes a diode circuit 241 electrically connected between the flying capacitor 235 and the global reference potential GND. The diode circuit 241 may include one or more elements including one or more pn junctions which are forward biased in the first phases of the charge mode pump 230.

[0103] More particular, the diode circuit 241 may be electrically connected between the positive supply voltage VDD and the second switch 232 or between the third switch 233 and the global reference potential GND. The protection circuits 240 of FIG. 7A and FIG. 7B may be combined with each other.

[0104] The protection circuit 240 may further include a semiconductor switch 245 electrically connected in parallel with the diode circuit 241, wherein the semiconductor switch 245 is configured to be turned off when the bum-in protection signal VBP is active.

[0105] The sensor controller 50 of FIG. 5 or another component inside or outside the image sensor assembly may generate the bum-in protection signal VBP When the semiconductor switch 245 is “on”, the diode circuit 241 is by-passed. The protection circuit 240 allows the use of the high positive supply voltage VDDH for the charge pump circuit 230 such that the mean positive supply voltage VDDM and the low positive supply voltage VSSL remain to a high degree unaffected by the operation of the charge pump circuit 230, and at the same time keeps the voltage stress for the flying capacitor 235 low.

[0106] The semiconductor switch 245 may include a field effect transistor 246. In the example illustrated in FIG. 8A, the field effect transistor 246 is a p-channel field effect transistor for a protection circuit 240 in the configuration of FIG. 6A. In the example illustrated in FIG. 8B, the field effect transistor 246 is an n-channel field effect transistor for a protection circuit 240 in the configuration of FIG. 6C.

[0107] The illustrated diode circuit 241 includes one single diode element 242 with an anode orientated towards the positive supply voltage VDD. In the example illustrated in FIG. 8 A, the anode of the diode element 242 is directly connected to the positive supply voltage VDD. In the example illustrated in FIG. 8B, the cathode of the diode element 242 is directly connected to the global reference potential GND. The protection circuit 240 reduces the voltage across the flying capacitor 235 by the forward voltage of the diode element 242.73952

[0108] 14

[0109] In FIG. 9A and FIG. 9B, the diode circuit 241 includes at least two diode elements 242, 243 electrically connected in series. The anodes of the diode elements 242, 243 are orientated to the positive supply voltage VDD. The at least two diode elements 242, 243 may have the same target parameters. The protection circuit 240 reduces the high positive supply voltage VDDH by at least two-times the forward voltage of a diode element 242, 243.

[0110] In FIG. 10A and FIG. 10B, the diode circuit 241 includes at least one diode-connected field effect transistor 244. Two or more diode-connected field effect transistor 244 may be electrically connected in parallel and / or in series. In the illustrated embodiments, the protection circuit 240 reduces the high positive supply voltage VDDH by at least the threshold voltage of the diode-connected field effect transistor 244.

[0111] FIG. 11 shows the charge pump circuit 230 of FIG. 6A combined with the protection circuit 240 illustrated in FIG. 10. The protection circuit 240 reduces the voltage switched by the second switch 232 by the threshold voltage VTH of the diode-connected field effect transistor 244.

[0112] FIG. 12 shows an example of a constant voltage source 260 based on a line regulator. The constant voltage source 260 includes a first LDO constant current source 261 and a LDO resistive load 262 electrically connected in series in this order between a positive supply voltage VDD and the local reference potential VRL. A second LDO constant current source 264 and a load path of an LDO n-channel FET 265 are electrically connected in series in this order between the positive supply voltage VDD and the local reference potential VRL. An inverting input of an LDO amplifier circuit 263 receives a voltage tapped from the node between the LDO constant current source 261 and the LDO resistive load 262. The output of the LDO amplifier circuit 263 controls the gate of the LDO n-channel FET 265. An output voltage VOUT tapped from the drain of the LDO amplifier circuit 263 is fed back to the non-inverting input of the LDO amplifier circuit 263. An LDO output capacitance 266 is electrically connected between the output of the line regulator and the local reference potential VRL. The constant voltage source 260 outputs a constant voltage VOUT at the output.

[0113] In the example illustrated in FIG. 13 A, the constant voltage source 260 includes a string of resistors 362 and a current source 361 electrically connected in series between a positive supply potential VDD and the local reference voltage VRL, a multiplexer 363 with data inputs electrically connected to nodes of the string of resistors 362, and an amplifier stage 364 configured to buffer an output signal of the multiplexer 363.

[0114] The current source 361 may be an active current source that decouples the generation of the target voltage from noise on the local reference potential VRL.

[0115] The positive supply potential VDD may be a temperature-regulated voltage. The sensor controller 50 of FIG. 1 or another component outside or integrated in the image sensor assembly generates control signal 10, ... , In, which are passed to control inputs of the multiplexer 363. Alternatively, the control inputs may be permanently programmed in a testing environment. Depending on the control signals 10, ... , In, the multiplexer 363 passes the voltage at a matching one of the data inputs to the amplifier stage 364.73952

[0116] 15

[0117] The constant voltage source 260 may further include a noise reduction circuit 367 that receives the voltage signal from the multiplexer 363 and passes a noise-fdtered version of the voltage signal to the amplifier stage 364. The amplifier stage 364 may include a class AB amplifier providing a high power supply rejection ratio (PSRR) and good driving capabilities for both positive and negative voltages. The amplifier stage 364 may be powered by the same positive supply potential VDD as the resistor ladder. In the illustrated embodiment, a second supply potential VDDB powers the amplifier stage 364, wherein the second supply potential is independent from the positive supply potential VDD and therefore noise interference can be reduced.

[0118] A load path of a p-channel FET 365 may be electrically connected between the second supply potential VDDB and the output of the amplifier stage 364. A first control signal CTR1 may switch the p-channel FET 365 on or off. The sensor controller 50 of FIG. 1 or another component outside or integrated in the image sensor assembly may generate the first control signal CTR1. Alternatively, the first control signal CTR1 is permanently set to a high potential.

[0119] A load path of an n-channel FET 366 may be electrically connected between the output of the amplifier stage 364 and the local reference potential VRL. A second control signal CTR2 may switch the n-channel FET 366 on or off. The sensor controller 50 of FIG. 1 or another component outside or integrated in the image sensor assembly may generate the second control signal CTR2. Alternatively, the second control signal CTR2 is permanently set to a high potential.

[0120] When the target voltage for the output voltage VOUT is between VDD and VRL, the multiplexer 363 is active and controlled to output the voltage from the selected node of the resistor ladder. Both the p-channel FET 365 and the n-channel FET 366 are off. Due to the limited output range of the amplifier stage 364, the output signal of the amplifier stage 364 can only approach VDD and VRL up to approximately 100~200mV. When the target voltage for the output voltage VOUT is VDD, the p-channel FET 365 is turned on and the n-channel FET 366 is turned off. The resistor ladder, the multiplexer 363, and the amplifier stage 364 can be switched off. When the target voltage for the output voltage VOUT is VRL, the p-channel FET 365 is turned off and the n-channel FET 366 is turned on. The resistor ladder, the multiplexer 363, and the amplifier stage 364 can be switched off. In addition, when the pixel operation is decided, the target voltage will not be changed during the operation and the same output voltage is kept.

[0121] FIG. 13B schematically shows the propagation of a noise signal originating from the resistor ladder through the multiplexer 363 and the amplifier stage 364 in case the output of the multiplexer is directly connected to the input of the amplifier stage 364. The output voltage VOUT contains a strong noise signal propagated through the multiplexer 364 and a low noise signal generated in the amplifier stage 364.

[0122] In FIG. 13C and FIG. 13D, a noise reduction circuit 376 is electrically connected between the output of the multiplexer 363 and the input of the amplifier stage 364. In FIG. 13C, the noise reduction circuit 376 is an RC filter with a serial resistor between the output of the multiplexer 363 and the input of the amplifier stage 364 and with a capacitor between the input of the amplifier stage 364 and the global reference potential GND. In FIG. 13D, the noise reduction circuit 376 is a sample-and-hold circuit with a switch between the73952

[0123] 16

[0124] output of the multiplexer 363 and the input of the amplifier stage 364 and with a capacitor between the input of the amplifier stage 364 and the global reference potential GND. In the output voltage VOUT, the noise portion originating from the resistor ladder is reduced.

[0125] According to FIG. 14, the image sensor assembly 90 includes a substrate 300, wherein the main capacitor 250 and an image sensor 70 that includes the charge pump circuit 230 are mounted on the substrate 300.

[0126] The substrate 300 may be a PCB. The main capacitor 250 and the image sensor 70 may be mounted on the same side of the substrate 300 or on different sides of the substrate 300. A conductor track on the substrate 300 connects a VRL terminal of the image sensor 70 and a pad on which the working electrode of the main capacitor may be soldered.

[0127] The input of the constant voltage source 260 is electrically connected to the global reference potential GND. A conductor track formed in the image sensor 70 directly connects a GND terminal of the image sensor 70 with the input IN of the constant voltage source 260. The local reference potential VRL is supplied to a VSS input of the constant voltage source 260. The constant voltage source 260 outputs the output voltage VOUT at an output OUT. Operating the constant voltage source 260 with the global reference potential GND supplied to the input may reduce noise.

[0128] In FIG. 15 and FIG. 16, the image sensor assembly 90 includes a power management integrated circuit 390 configured to generate a positive supply voltage VDD, wherein the power management integrated circuit 390 is mounted on the substrate 300, and wherein the positive supply voltage VDD is supplied to an input of the constant voltage source 260 via a single terminal as in FIG. 15 or via a plurality of terminals of the image sensor 70 as in FIG. 16.

[0129] Operating the constant voltage source 260 and / or the charge pump circuit 230 with one of the positive supply voltages VDDL, VDDM, VDDH received via a shared terminal of the image sensor 70 improves the overall voltage margin.

[0130] Operating the constant voltage source 260 with one of the positive supply voltages VDDL, VDDM, VDDH received via a dedicated terminal of the image sensor 70 reduces the noise interference from / to other components of the image sensor 70.

[0131] FIG. 17 is a diagram illustrating an example in which the image sensor 70 of FIG. 1 includes a CIS (stacked contact image sensor) having a two-layer structure with a radiation receiving chip 910 and a processing chip 920. The radiation receiving chip 910 includes at least the photoelectric conversion element, e.g., only the photoelectric conversion element, the photoelectric conversion element and the complete pixel circuit or the photoelectric conversion element and some components of the pixel circuits. The processing chip 920 includes the further elements of the pixel circuits 100. As illustrated on the right side of FIG. 17, the image sensor 70 is formed as one sensor by bonding the radiation receiving chip 910 and the processing chip 920 while electrically bringing contact pads on the radiation receiving chip 910 in contact with corresponding contact pads on the processing chip 920.73952

[0132] 17

[0133] FIG. 18 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied.

[0134] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 18, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehiclemounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0135] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0136] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0137] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. The outside-vehicle information detecting unit 12030 can be connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image. Based on the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0138] The imaging section 12031 may be or may include an image sensor assembly according to the embodiments of the present disclosure. The light received by the imaging section 12031 may contain visible light and / or invisible light such as infrared rays or the like.73952

[0139] 18

[0140] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include an image sensor assembly according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the image sensor assembly according to the embodiments and that is focused on the driver. Based on detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing.

[0141] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0142] In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0143] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle which information is obtained by the outsidevehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0144] The sound / image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 18, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display.

[0145] FIG. 19 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12104, and 12105.

[0146] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on73952

[0147] 19

[0148] an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0149] Incidentally, FIG. 19 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0150] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including an image sensor assembly according to the embodiments of the present disclosure.

[0151] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100 on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

[0152] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk73952

[0153] 20

[0154] of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0155] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0156] The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying an image sensor assembly according to the embodiments of the present disclosure, the system can be improved. In particular, the failure rate can be reduced.

[0157] Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

[0158] The image sensor assembly according to the present disclosure may be any device used for analyzing and / or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, an image sensor assembly according to the embodiments may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

[0159] Specifically, in the field of image reproduction, the image sensor assembly according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, a solid-state imaging device including an image sensor assembly according to the embodiments may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.73952

[0160] 21

[0161] In the field of home appliances, a solid-state imaging device with an image sensor assembly according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly, the solid-state imaging device with an image sensor assembly according to the embodiments may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and / or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the solid-state imaging device with an image sensor assembly according to the embodiments may be integrated in any type of sensor, e.g., a camera device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

[0162] In the field of security, the solid-state imaging device with an image sensor assembly according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, a solid-state imaging device with an image sensor assembly according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, a solid-state imaging device with an image sensor assembly according to the embodiments can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the solid-state imaging device with an image sensor assembly according to the embodiments can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

[0163] The present technology can also be configured as described below: [1] An image sensor assembly (900) that includes: a main capacitor (250) including a reference electrode electrically connected to a global reference potential GND and a working electrode; a charge pump circuit (230) configured to connect a flying capacitor (235) between a positive supply voltage VDD and the global reference potential GND in first phases and between a controllable node (229) and the working electrode of the main capacitor (250) in second phases; a protection circuit (240) configured to reduce a voltage across the flying capacitor (235) when a bum-in protection signal VBP is active; a constant voltage source (260) configured to output a constant voltage VOUT referenced to a local reference potential VRL of the working electrode of the main capacitor (250); and a pixel driver circuit (270) configured to output a pixel control signal referenced to the constant voltage VOUT.

[0164] [2] The image sensor assembly according to [1], further including: a pixel circuit (100) configured to output a pixel voltage signal with a voltage being a function of intensity of incident radiation, the pixel circuit (100) including a pixel transistor controllable by the pixel control signal.

[0165] [3] The image sensor assembly according to any of [1] to [2], including: a plurality of constant voltage source circuits (260,1 260-2, ...), each constant voltage source (260-1, 260-2, ...) being configured to output a constant voltage VOUT1, VOUT2, VOUT3 referenced to the local reference potential VRL.73952

[0166] 22

[0167] [4] The image sensor assembly according to any of [1] to [3], further including: a comparator circuit (220) configured to change a potential of the controllable node (229) depending on a voltage difference between the local reference potential VRL and the global reference potential GND..

[0168] [5] The image sensor assembly according to [4], wherein the comparator circuit (220) is configured to supply a first voltage to the controlled node (229) when a voltage difference between the local reference potential VRL and the global reference potential GND is less than a predetermined threshold, and a second voltage higher than the first voltage otherwise.

[0169] [6] The image sensor assembly according to any of [1] to [5], wherein the protection circuit (240) includes a diode circuit (241) electrically connected between the positive supply voltage VDD and the flying capacitor (235) and / or between the flying capacitor (235) and the global reference potential GND.

[0170] [7] The image sensor assembly according to [6], wherein the protection circuit (240) includes a semiconductor switch (245) electrically connected in parallel with the diode circuit (241), and wherein the semiconductor switch (245) is configured to be turned off when the bum-in protection signal VBP is active.

[0171] [8] The image sensor assembly according to [7], wherein the semiconductor switch (245) includes a field effect transistor (246).

[0172] [9] The image sensor assembly according to any of [6] to [8], wherein the diode circuit (241) includes one diode element (242) with an anode orientated towards the positive supply voltage VDD.

[0173]

[0010] The image sensor assembly according to any of [6] to [8], wherein the diode circuit (241) includes at least two diode elements (242, 243) electrically connected in series.

[0174]

[0011] The image sensor assembly according to any of [6] to

[0010] , wherein the diode circuit (241) includes at least one diode-connected field effect transistor (244).

[0175]

[0012] The image sensor assembly according to any of [1] to

[0011] , wherein the constant voltage source (260) includes a string of resistors (362) and a current source (361) electrically connected in series between a positive supply potential VDD and the local reference voltage VRL, a multiplexer (363) with data inputs electrically connected to nodes of the string of resistors (362), and an amplifier stage (364) configured to buffer an output signal of the multiplexer (363).

[0176]

[0013] The image sensor assembly according to any of [1] to

[0012] , further including:

[0177] a substrate (300), wherein the main capacitor (250) and an image sensor (70) including the charge pump circuit (230) are mounted on the substrate (300).

[0178]

[0014] The image sensor assembly according to

[0013] , wherein an input of the constant voltage source (260) is electrically connected to the global reference potential GND.73952

[0179] 23

[0180]

[0015] The image sensor assembly according to any of

[0013] to

[0015] , further including: a power management integrated circuit (390) configured to generate a positive supply voltage VDD, wherein the power management integrated circuit (390) is mounted on the substrate (300), and wherein the positive supply voltage VDD is supplied to an input of the constant voltage source (260) via a single terminal or via a plurality of terminals of the image sensor (70).

Claims

7395224CLAIMS1. An image sensor assembly, comprising:a main capacitor comprising a reference electrode electrically connected to a global reference potential GND and a working electrode;a charge pump circuit configured to connect a flying capacitor between a positive supply voltage VDD and the global reference potential GND in first phases and between a controllable node and the working electrode of the main capacitor in second phases;a protection circuit configured to reduce a voltage across the flying capacitor when a bum-in protection signal VBP is active;a constant voltage source configured to output a constant voltage VOUT referenced to a local reference potential VRL of the working electrode of the main capacitor; anda pixel driver circuit configured to output a pixel control signal referenced to the constant voltage VOUT.

2. The image sensor assembly according to claim 1, further comprising:a pixel circuit configured to output a pixel voltage signal with a voltage being a function of intensity of incident radiation, the pixel circuit comprising a pixel transistor controllable by the pixel control signal.

3. The image sensor assembly according to claim 1, comprising:a plurality of constant voltage source circuits, each constant voltage source being configured to output a constant voltage VOUT1, VOUT2, VOUT3 referenced to the local reference potential VRL.

4. The image sensor assembly according to claim 1, further comprising:a comparator circuit configured to change a potential of the controllable node depending on a voltage difference between the local reference potential VRL and the global reference potential GND.

5. The image sensor assembly according to claim 4,wherein the comparator circuit is configured to supply a first voltage to the controlled node when a voltage difference between the local reference potential VRL and the global reference potential GND is less than a predetermined threshold, and a second voltage higher than the first voltage otherwise.

6. The image sensor assembly according to claim 1,wherein the protection circuit comprises a diode circuit electrically connected between the positive supply voltage VDD and the flying capacitor and / or between the flying capacitor and the global reference potential GND.

7. The image sensor assembly according to claim 6,wherein the protection circuit comprises a semiconductor switch electrically connected in parallel with the diode circuit, and wherein the semiconductor switch is configured to be turned off when the bum-in protection signal VBP is active.

8. The image sensor assembly according to claim 7,wherein the semiconductor switch comprises a field effect transistor.

9. The image sensor assembly according to claim 6,wherein the diode circuit comprises one diode element with an anode orientated towards the positive supply voltage VDD.

10. The image sensor assembly according to claim 6,wherein the diode circuit comprises at least two diode elements electrically connected in series.

11. The image sensor assembly according to claim 6,wherein the diode circuit comprises at least one diode-connected field effect transistor.

12. The image sensor assembly according to claim 1,wherein the constant voltage source comprises a string of resistors and a current source electrically connected in series between a positive supply potential VDD and the local reference voltage VRL, a multiplexer with data inputs electrically connected to nodes of the string of resistors, and an amplifier stage configured to buffer an output signal of the multiplexer.

13. The image sensor assembly according to claim 1, further comprising:a substrate, wherein the main capacitor and an image sensor comprising the charge pump circuit are mounted on the substrate.

14. The image sensor assembly according to claim 13,wherein an input of the constant voltage source is electrically connected to the global reference potential GND.

15. The image sensor assembly according to claim 13, further comprising:a power management integrated circuit configured to generate a positive supply voltage VDD, wherein the power management integrated circuit is mounted on the substrate, and wherein the positive supply voltage VDD is supplied to an input of the constant voltage source via a single terminal or via a plurality of terminals of the image sensor.

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