Common gate amplifier circuit, analog-to-digital converter circuit and image sensor assembly

Abstract

A common gate amplifier circuit includes a field effect transistor that receives an input signal at a source. A feedback circuit feeds back a portion of an output voltage VOUT from an amplifier output to a gate of the field effect transistor. A drain capacitor is electrically connected between a drain of the field effect transistor and a reference potential. A noise reduction circuit connects the drain of the field effect transistor to the amplifier output via a capacitive path for low-noise phases, and via a resistive path outside the low-noise phases.

Description

[0001] 73953

[0002] 1

[0003] COMMON GATE AMPLIFIER CIRCUIT, ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND IMAGE SENSOR ASSEMBLY

[0004] The present disclosure relates to a common gate amplifier circuit and an analog-to-digital converter circuit that includes a common gate amplifier circuit. The present disclosure further relates to an image sensor assembly having an analog-to-digital converter circuit to convert analog pixel signals into digital pixel values.

[0005] BACKGROUND

[0006] In common gate amplifiers, the source of a field effect transistor serves as the input and the drain is the output. A constant bias voltage is applied to the gate. When the common gate amplifier operates in a feedback loop, the parameters of the feedback loop define a voltage amplification of the common gate amplifier circuit. The output current is a function of the input voltage, the gate bias voltage, the threshold voltage of the field effect transistor and the transconductance of the field effect transistor. When a further electronic circuit receives a signal from the common gate amplifier, the input capacitance of the further electronic circuit, the voltage amplification and the transconductance of the field effect transistor determine the bandwidth of the circuit. Some circuits like analog-to-digital converters (ADCs) have a comparatively high input capacitance. ADCs are used inter alia in active pixel sensors (APS) that convert radiation into analog voltage signals (pixel signals). ADCs convert the pixel signals into digital pixel values.

[0007] SUMMARY

[0008] In a field effect transistor, Brownian motion of electrons generate random currents effective as thermal noise. When an electronic circuit receives the output signal of a field effect transistor in common gate amplifier configuration, the input capacitance of the electronic circuit accumulates noise, wherein the noise density of the thermal noise is integrated over all frequencies within the transmission bandwidth of the common gate amplifier. Some of the unwanted charge can be accumulated at a drain capacitor connected between the drain of the field effect transistor and a reference potential instead of at the input capacitance of the electronic circuit.

[0009] The present disclosure addresses deficiencies in common gate amplifiers. To this end, a common gate amplifier circuit includes a field effect transistor that receives an input signal at a source. A feedback circuit feeds back a portion of an output voltage VOUT from an amplifier output to a gate of the field effect transistor. A drain capacitor is electrically connected between a drain of the field effect transistor and a reference potential. A noise reduction circuit connects the drain of the field effect transistor to the amplifier output via a capacitive path for low-noise phases, and via a resistive path outside the low-noise phases.

[0010] Outside the low-noise phases, the drain of the common gate amplifier circuit is directly connected to the amplifier output and the common gate amplifier operates like a conventional common gate amplifier. In73953

[0011] 2

[0012] the low-noise phases, the feedback circuit is still connected between the amplifier output and the gate of the field effect transistor, so that the voltage transfer function given by the ratio between the output voltage VOUT and the voltage of the input signal remains the same. But with the capacitive path of the noise reduction circuit electrically connected in series with the input capacitance of an electronic circuit connected to the amplifier output, the voltage across that input capacitance is lower than the voltage across the drain capacitor. As a result, an effective bandwidth of the common gate amplifier as regards the input capacitance of the electronic circuit that receives the output signal VOUT can be significantly reduced, which in turns results in less noise being transferred to the input capacitance of the electronic circuit that receives the output signal VOUT.

[0013] Another aspect of the present disclosure is related to an analog-to-digital converter interfacing amplifier circuit. The analog-to-digital converter interfacing amplifier circuit (“analog-to-digital converter circuit” in the following) includes a field effect transistor configured to receive an input signal at a source; a feedback circuit configured to feed back a portion of an output voltage VOUT from an amplifier output to a gate of the field effect transistor; a drain capacitor electrically connected between a drain of the field effect transistor and a reference potential; a noise reduction circuit configured to connect the drain of the field effect transistor to the amplifier output via a capacitive path for low-noise phases, and via a resistive path outside the low-noise phases; and an analog-to-digital converter configured to convert the output voltage VOUT into a digital value.

[0014] A further aspect of the present disclosure is related to an image sensor assembly. The image sensor assembly includes a pixel circuit configured to output a pixel signal, wherein a voltage of the pixel signal is a function of an intensity of incoming radiation; a field effect transistor configured to receive the pixel signal at a source; a feedback circuit configured to feed back a portion of an output voltage VOUT from an amplifier output to a gate of the field effect transistor; a drain capacitor electrically connected between a drain of the field effect transistor and a reference potential; a noise reduction circuit configured to connect the drain of the field effect transistor to the amplifier output via a capacitive path for low-noise phases, and via a resistive path outside the low-noise phases; and an analog-to-digital converter configured to convert the output voltage VOUT into a digital value.

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016] A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0017] FIG. 1 is a simplified circuit diagram of a common gate amplifier circuit with a noise reduction circuit, in accordance with an embodiment.

[0018] FIG. 2 is a circuit diagram of a common gate amplifier circuit with a noise reduction circuit and a feedback circuit in a first configuration, in accordance with an embodiment.3

[0019] FIG. 3 is a simplified circuit diagram of a common gate amplifier circuit based on a pFET and with a noise reduction circuit, in accordance with an embodiment.

[0020] FIG. 4 is a circuit diagram of a common gate amplifier circuit based on a pFET and with a noise reduction circuit including an auxiliary capacitor and a preset switch, in accordance with an embodiment.

[0021] FIG. 5A is a simplified circuit diagram of an analog-to-digital converter circuit that includes a common gate amplifier circuit based on a pFET, in accordance with an embodiment.

[0022] FIG. 5B is a simplified time diagram for control signals, the drain voltage, and the output voltage of the analog-to-digital converter circuit of FIG. 5 A, in accordance with an embodiment.

[0023] FIG. 6 is a time diagram showing the output signal VOUT of a common gate amplifier circuit before and during a low-noise phase, in accordance with an embodiment.

[0024] FIG. 7 is a circuit diagram showing pixel circuits connected to an analog-to-digital converter circuit of an image sensor assembly in accordance with an embodiment.

[0025] FIG. 8 is a simplified block diagram of an image sensor assembly with analog-to-digital converters in accordance with an embodiment.

[0026] FIG. 9 is a circuit diagram of a pixel circuit with four pixel transistors, suitable for an image sensor assembly according to the embodiments.

[0027] FIG. 10A is a circuit diagram showing a pixel circuit connected to an analog-to-digital converter circuit of an image sensor assembly in accordance with an embodiment.

[0028] FIG. 1 OB is a simplified time diagram for control signals for the pixel circuit and the analog-to-digital converter circuit of FIG. 10A, in accordance with an embodiment.

[0029] FIG. 11 is a schematic diagram illustrating an embodiment in which an image sensor has a two-layer structure in a stacked CIS configuration.

[0030] FIG. 12 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0031] FIG. 13 is a diagram of assistance in explaining an example of installation positions of an outsidevehicle information detecting section and an imaging section of the vehicle control system of FIG. 12.

[0032] DETAILED DESCRIPTION4

[0033] Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various features in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

[0034] The terms “electrically connected”, “signal-connected”, and “operatively connected” may include a direct connection or a connection through other electronic elements provided and suitable for permanent and / or temporary signal transmission and / or transmission of energy. Electronic elements can be electrically connected, signal-connected and operatively connected via resistors, capacitors, electronic switches such as field effect transistors, or transistor circuits such as transmission gates. At least one electrical signal in a second electrical circuit that is in signal-connection or operational connection with a first electrical circuit responds in a predictable, intended manner to a change of an electrical signal in the first electrical circuit. Directly electrically connected electronic elements are connected through a permanent low-resistive wiring, an ohmic contact and / or a unipolar semiconductor junction.

[0035] The load path of a transistor is the controlled current path through a transistor. A voltage applied to the gate of a field effect transistor (FET) controls the current flow through the load path (controlled path) between source and drain of the transistor by field effect. When transistors are electrically connected in series, the load paths of the transistors are electrically connected in series. When transistors are electrically connected in parallel, the load paths of the transistors are electrically connected in parallel.

[0036] A digital signal alternates between at least one active level and at least one inactive level. A digital signal having an active level is active. A digital signal having an inactive level is inactive. For each signal separately, the active level can be a digital high level and the inactive level a digital low level, or the active level can be the digital low level and the inactive level the digital high level. Digital signals include binary signals alternating between one active level and one inactive level.

[0037] FIG. 1 shows a common gate amplifier circuit 261 that includes a field effect transistor 205 receiving an input signal VIN at a source. A feedback circuit 220 feeds back a portion of an output voltage VOUT from an amplifier output 209 to a gate of the field effect transistor 205. A drain capacitor 230 is electrically connected between a drain of the field effect transistor 205 and a reference potential VSS. A noise reduction circuit 240 connects the drain of the field effect transistor 205 to the amplifier output 209 via a capacitive path for low-noise phases and via a resistive path outside the low-noise phases.

[0038] In the illustrated example, the field effect transistor 205 is an n-channel FET in common gate amplifier configuration. An input voltage source 210 providing the input signal VIN is electrically connected between the source of the field effect transistor 205 and the reference potential VSS. The drain of the field effect transistor 205 may be connected to a positive supply potential VDD through a load 250. The feedback circuit 220 taps the output voltage VOUT of the common gate amplifier circuit 261 from the amplifier output 209 and supplies a predefined portion of the output voltage VOUT to the gate of the field effect transistor 205. With the feedback circuit 220, the common gate amplifier circuit 261 operates5

[0039] at closed loop with negative feedback. The configuration of the feedback circuit 220 gives the small signal voltage gain (voltage transfer ratio) A between the output voltage VOUT and the voltage of the input signal VIN according to equation # 1 :

[0040] #1: A = -V^

[0041] VIN

[0042] The drain capacitor 230 may be an exclusively intrinsic drain capacitance of the field effect transistor 205, a capacitive element provided in addition to the field effect transistor 205, or a combination of both. The drain capacitor 230 accumulates some of the charge generated by noise in the field effect transistor 205 and reduces to some degree the noise voltage across a load capacitor 271 that is typically effective when an electronic circuit is connected to the amplifier output 209 of the common gate amplifier circuit 261. The load capacitor 271 may be or may include the input capacitance of an electronic circuit receiving and processing the output voltage VOUT of the common gate amplifier circuit 261.

[0043] The noise reduction circuit 240 forms a resistive path between the drain of the field effect transistor 205 and the amplifier output 209 in settling phases preceding the low-noise phases. The resistive path may include conductor tracks, the semiconductor channel of a switched-on field effect transistor or the semiconductor channels of more than one switched-on field effect transistors. In the settling phases, the common gate amplifier circuit 261 amplifies the voltage of the input signal VIN with the voltage transfer ratio A defined by the feedback circuit 220.

[0044] In the low-noise phases, the noise reduction circuit 240 provides a capacitive path between the drain of the field effect transistor 205 and the amplifier output 209, wherein the coupling between the drain of the field effect transistor 205 and the amplifier output 209 is purely capacitive with no conducting bypass between the drain of the field effect transistor 205 and the amplifier output 209. The capacitive path includes at least one capacitor electrically connected in series between an input of the noise reduction circuit 240 connected to the drain of the field effect transistor 205 and an output of the noise reduction circuit 240 connected to the amplifier output 209. The capacitive path may include further capacitors electrically connected in series or in parallel, the semiconductor channel of a switched-on or switched-off field effect transistor or the semiconductor channels of more than one field effect transistor, and / or one or more pn junctions.

[0045] In the low-noise phases, the feedback circuit 220 remains connected between the amplifier output 209 and the gate of the field effect transistor 205, so that the voltage transfer ratio A remains the same as in the settling phases. Since the capacitive path of the noise reduction circuit 220 is electrically connected in series with the load capacitor 271, the voltage across the load capacitor 271 is lower than the voltage across the drain capacitor 230. As a result, the effective bandwidth of the common gate amplifier circuit 261 for the load capacitor 271 can be significantly lower in the low-noise phases than in the settling phases. Less noise is transferred to the load capacitor 271. Any electronic circuit that receives and processes the output voltage VOUT can process, e.g., sample the output voltage VOUT during the low-6

[0046] noise phases to benefit from a temporarily better signal -to-noise ratio. The electronic circuit receiving the output voltage VOUT may be a switched capacitor filter or an ADC, by way of example.

[0047] After a low-noise phase and after sampling of the output voltage VOUT, the noise reduction circuit 240 returns to the resistive connection between the drain of the field effect transistor 205 and the amplifier output 209. The drain voltage VDR adapts to the output voltage VOUT and the bandwidth is again increased to allow a fast tracking of the voltage of the input signal VIN by the output voltage VOUT. The noise reduction circuit 240 may filter excess noise shorty prior to sampling on the load capacitor, e.g., prior to ADC sampling.

[0048] FIG. 2 shows a common gate amplifier circuit 261 including an active load 252 electrically connected in series with the field effect transistor 205 at a drain side of the field effect transistor 205 and configured to supply a constant current.

[0049] By providing a constant current, the active load 252 may decouple the voltage transfer ratio A from fluctuating load conditions and / or may improve the open loop gain. The active load 252 may include a field effect transistor biased to be in saturation mode.

[0050] The feedback circuit 220 is configured to connect the drain and the gate of the field effect transistor 205 via a resistive path in initialization phases and via a capacitive path outside the initialization phases.

[0051] The controllable feedback circuit 220 effects an initialization of the bias at the gate of the field effect transistor 205. In operation phases outside the initialization phases, the feedback circuit defines the voltage transfer ratio A. The initialization may be repeated periodically.

[0052] In the illustrated example, the feedback circuit 220 includes a first capacitor 221 electrically connected between the gate of the field effect transistor 205 and the reference potential VSS, a second capacitor 222 electrically connected between the amplifier output 209 and the gate of the field effect transistor 205, and an initialization switch 225 that short-circuits the second capacitor 222 for initialization phases.

[0053] In the illustrated example, the initialization switch 225 is directly connected between the drain and the gate of the field effect transistor 205 at any time and is directly connected between the two electrodes of the second capacitor 222 only outside the low-noise phases. An initialization control signal S2 controls the initialization switch 225. An active initialization control signal S2 turns on the initialization switch 225 for the initialization phases. For example, the initialization switch 225 is a FET or a circuit including FETs and the initialization control signal S2 is supplied to the gate of the FET(s). Depending on the voltage range of the input signal VIN, the initialization switch 225 may be an nFET (n-channel field effect transistor, “NMOS”), a pFET (p-channel field effect transistor, “PMOS”), or a full transmission gate with the load paths of an nFET and a pFET electrically connected in parallel and with the nFET and the pFET simultaneously turned on and off.7

[0054] When the initialization switch 225 is switched on in settling phases outside the low-noise phases, the output voltage VOUT results from the sum of the voltage of the input signal VIN and the threshold voltage Vth of the field effect transistor 205:

[0055] #2: VOUT = VIN + Vth

[0056] When the initialization switch 225 is off in settling phases, the voltage transfer ratio A results from the capacitive voltage divider formed by the second capacitor 222 with capacitance C2 and the first capacitor 221 with capacitance Cl according to equation #3:

[0057] ci

[0058] #3: A = 1 + - C2

[0059] With VGS as the gate voltage of the field effect transistor 205 at the end of an initialization phase and VINO as the voltage of the input signal VIN at the end of the initialization phase, the output voltage VOUT of the common gate amplifier circuit 261 is obtained from equation #4:

[0060] #4: VO UT = VINO + VGS + A * VIN - VINO

[0061] The time needed to fully charge the load capacitor 271 defines an upper cutoff frequency or bandwidth BW up to which the common gate amplifier circuit 261 and an electronic circuit processing the output voltage of the common gate amplifier circuit 261 can be regularly operated.

[0062] The charging rate for the load capacitor 271 and the bandwidth BW increase with the output current IOUT and decrease with increasing charge AQOUT to be transferred to the load capacitor 271 within a given time according to equation #5 :

[0063] I OUT

[0064] #5: BW

[0065]

[0066] AQOUT

[0067] With AQOUT defined by the product of the capacitance CU of the load capacitor 271 and the change of the output voltage AVOUT, with the change of the output voltage AVOUT defined by the product of the change of the voltage of the input signal AVIN and the voltage transfer ratio A, and with the output current IOUT defined by the product of the change of the voltage of the input signal AVIN and the transconductance gm of the field effect transistor 205, equation #5 transforms in equation #6:

[0068] #6: BW «

[0069]

[0070] CL*A

[0071] In the illustrated example, the noise reduction circuit 240 includes an auxiliary capacitor 244 electrically connected between the drain of the field effect transistor 205 and the amplifier output 209, and a preset8

[0072] switch 245 configured to short-circuit the auxiliary capacitance 244 for settling phases outside the low-noise phases.

[0073] In the illustrated example, the preset switch 245 is directly connected between the drain of the field effect transistor 205 and the amplifier output 209. A noise control signal SI controls the preset switch 245. An active noise control signal SI turns off the preset switch 245 for the low-noise phase. For example, the preset switch 245 is a FET and the noise control signal SI is supplied to the gate of the FET. Depending on the range of the output voltage VOUT, the preset switch 245 may be an nFET or a pFET. If the preset switch 245 is an nFET, the active level of the noise control signal SI is the low level. If the preset switch 245 is a pFET, the active level of the noise control signal SI is the high level. When the range of the output voltage VOUT is comparatively large, the preset switch 245 may be or may include a transmission gate with the load paths of an nFET and a pFET electrically connected in parallel and with the nFET and the pFET simultaneously turned on and off.

[0074] When the preset switch 245 is on, the output voltage VOUT is equal to the drain voltage VDR of the field effect transistor 205. The common gate amplifier circuit 261 can charge the load capacitor 271 up to the upper cutoff frequency following from equation #6. The output voltage VOUT and the drain voltage VDR across the drain capacitor 230 are equal.

[0075] When the preset switch 245 is switched off, the auxiliary capacitor 244 separates the amplifier output 209 from the drain of the field effect transistor 205. The ratio between the output voltage VOUT and the drain voltage VDR adjust to a ratio given by the capacitive voltage divider formed by the auxiliary capacitor 244 with the capacitance C4 and the load capacitor 271 with the capacitance CL according to equation #7 :

[0076] #7:= 1 +£

[0077] VOUT C4

[0078] Since the feedback circuit 220 remains connected to the amplifier output 209, the voltage transfer ratio A as regards the output voltage VOUT remains unaffected. The load capacitor 271 accumulates the same amount of charge as in the settling phases. But the voltage transfer ratio between the drain voltage VDR and the voltage of the input signal VIN according to equation #8 is greater than the voltage transfer ratio A between the voltage of the input signal VIN and the output voltage VOUT by (1 + CL / C4):

[0079] #8: — = A * (1 + -)

[0080]

[0081] VINvC4y

[0082] The output current IOUT given by the product of the transconductance gm and the voltage of the input signal VIN charges both the drain capacitance 230 and the load capacitor 271. Since the output voltage VOUT remains the same, the load capacitor 271 accumulates the same amount of charge as in the settling phases. Since the voltage across the drain capacitor 230 is increased, the drain capacitor 230 accumulates more charge. As a result, the amplifier bandwidth BW can be significantly reduced, and9

[0083] the noise transfer is reduced accordingly. When the electronic circuit receiving and processing the output voltage VOUT processes or takes over the output voltage VOUT at points in time within the low-noise phases, the processing in the electronic circuit can benefit from a higher signal -to-noise ratio.

[0084] In each of FIG. 1 to 2, the field effect transistor 205 of the common gate amplifier circuit 261 is an n-channel FET that switches on in response to a gate voltage exceeding a positive gate threshold voltage.

[0085] FIG. 3 illustrates a common gate amplifier circuit 261, wherein the field effect transistor 205 is configured as p-channel field effect transistor (pFET).

[0086] The p-channel FET switches on in response to a gate voltage falling below a positive gate threshold voltage. The field effect transistor 205 receives an input signal VIN at a source. A feedback circuit 220 feeds back a portion of an output voltage VOUT from an amplifier output 209 to a gate of the field effect transistor 205. A drain capacitor 230 is electrically connected between a drain of the field effect transistor 205 and a reference potential VSS. A noise reduction circuit 240 connects the drain of the field effect transistor 205 to the amplifier output 209 via a capacitive path for low-noise phases and via a resistive path outside the low-noise phases.

[0087] An input voltage source 210 providing the input signal VIN is electrically connected between a positive supply potential VDD and the source of the field effect transistor 205. The source of the field effect transistor 205 may be connected to the reference potential VSS through a load, e.g., an active load 252. The feedback circuit 220 taps the output voltage VOUT of the common gate amplifier circuit 261 from the amplifier output 209 and supplies a predefined portion of the output voltage VOUT to the gate of the field effect transistor 205 so that the common gate amplifier circuit 261 operates at closed loop with negative feedback in settling phases.

[0088] The noise reduction circuit 240 forms a resistive path between the drain of the field effect transistor 205 and the amplifier output 209 in settling phases preceding the low-noise phases. In the settling phases, the common gate amplifier circuit 261 amplifies the voltage of the input signal VIN with the voltage transfer ratio A defined by the feedback circuit 220. In the low-noise phases, the noise reduction circuit 240 provides a capacitive path between the drain of the field effect transistor 205 and the amplifier output 209, wherein the coupling between the drain of the field effect transistor 205 and the amplifier output 209 is purely capacitive with no conducting bypass between the drain of the field effect transistor 205 and the amplifier output 209.

[0089] In FIG. 4, the feedback circuit 220 includes a first capacitor 221 electrically connected between the gate of the field effect transistor 205 and the reference potential VSS, a second capacitor 222 electrically connected between the amplifier output 209 and the gate of the field effect transistor 205, and an initialization switch 225 that short-circuits the second capacitor 222 for initialization phases.

[0090] In the illustrated example, the initialization switch 225 is directly connected between the drain and the gate of the field effect transistor 205 at any time and is connected between the two electrodes of the10

[0091] second capacitor 222 in the settling phases. An active initialization control signal S2 turns on the initialization switch 225 for the initialization phases. For example, the initialization switch 225 is a FET and the initialization control signal S2 is supplied to the gate of the FET. For typical voltage ranges of the input signal VIN, the initialization switch 225 may be a pFET. Alternatively, the initialization switch 225 may be an nFET or may be or include a full transmission gate.

[0092] The noise reduction circuit 240 includes an auxiliary capacitor 244 electrically connected between the drain of the field effect transistor 205 and the amplifier output 209, and a preset switch 245 configured to short-circuit the auxiliary capacitance 244 for settling phases outside the low-noise phases.

[0093] In the illustrated example, the preset switch 245 is directly connected between the drain of the field effect transistor 205 and the amplifier output 209. An active noise control signal SI turns off the preset switch 245 for the low-noise phases. For example, the preset switch 245 is a FET and the noise control signal SI is supplied to the gate of the FET. For wide ranges of the output voltage VOUT, the preset switch 245 may be or may include a transmission gate. Alternatively, the preset switch 245 may be an nFET or a pFET.

[0094] FIG. 5 A shows an analog -to-digital converter circuit 270 that includes a field effect transistor 205 configured to receive an input signal at a source. A feedback circuit 220 feeds back a portion of an output voltage VOUT from an amplifier output 209 to a gate of the field effect transistor 205. A drain capacitor 230 is electrically connected between a drain of the field effect transistor 205 and a reference potential. A noise reduction circuit 240 connects the drain of the field effect transistor 205 to the amplifier output 209 via a capacitive path for low-noise phases, and via a resistive path outside the low-noise phases. An analog -to-digital converter 262 is configured to convert the output voltage VOUT into a digital value.

[0095] The field effect transistor 205, the feedback circuit 220, the drain capacitor 230 and the noise reduction circuit 240 may be components of a common gate amplifier circuit 261 as described with reference to FIG. 1 to FIG. 4.

[0096] The analog -to-digital converter 262 includes an input capacitance. The input capacitance is effective as load capacitor 271 for the common gate amplifier circuit 261.

[0097] The analog -to-digital converter 262 samples the output voltage VOUT at a defined temporal relationship with the low-noise phases.

[0098] An active sample signal SMPL may control the analog-to-digital converter 262 to sample the output voltage VOUT during the time the sample signal SMPL is active, or in response to a rising or falling edge of the sample signal SMPL. For example, the sample signal SMPL may become active simultaneously with the noise control signal S 1 or with some delay with respect to a change of the noise signal from inactive to active, or shortly before the noise control signal SI becomes inactive.73953

[0099] 11

[0100] According to an example, the analog-to-digital converter 262 may be configured to sample the output voltage VOUT in the low-noise phases.

[0101] FIG. 5B shows time diagrams for the control signals SI, S2, SMPL, the input signal VIN, and the output voltage VOUT for the analog-to-digital converter circuit 270 with the common gate amplifier circuit illustrated in FIG. 6A. The active level of the initialization control signal S2 and the sample control signal SMPL is the high level. The active level of the noise control signal SI is the low level, corresponding to an example providing the preset switch 245 as nFET.

[0102] The initialization control signal S2 is active in an initialization phase tinit between tO and tl. The active initialization control signal S2 turns on the initialization switch 225. At the end of the initialization phase tinit at tl, the common gate amplifier circuit changes into an operating phase. The operating phase includes a settling phase tstl beginning at tl and ending at t2. In the settling phase, the output voltage VOUT tracks the voltage of the input signal VIN according to the voltage transfer ratio A defined by the feedback circuit 220. The operating phase further includes a low-noise phase tins beginning at t2 and ending at t5. In the operating phase, an active noise control signal SI switches off the preset switch 245 to reduce the bandwidth of the common gate amplifier circuit 261 as regards the output voltage VOUT, wherein the noise on the input capacitance of the analog-to-digital converter 262 is reduced.

[0103] The sample control signal SMPL may become active after a certain delay with respect to the noise control signal SL A minimum delay may be in the range of a few ten or hundred nanoseconds. The sample control signal SMPL may return to the inactive level within the low-noise phase, i.e., before the noise control signal SI becomes inactive to switch on the preset switch 245.

[0104] In the illustrated example, the first half of the low-noise phase tins expires at t3. At t4 after t3 , the sample control signal SMPL becomes active and effects a sampling of the output voltage VOUT by the internal circuitry of the analog-to-digital converter 262. Instead of after the first half, the sample control signal SMPL may become active after a fifth, after a tenth or after 1 / 100 of the low-noise phase.

[0105] In FIG. 6, the active level of the noise control signals for switching off the preset switch 245 is the low level. A ratio between the capacitance CL of the load capacitor 271 and the capacitance C4 of the auxiliary capacitor 244 is about 1 / 10. The capacitances C3 of the drain capacitor 230 and the capacitance CL of the load capacitor 271 are approx. lOOfF, the capacitance C4 of the auxiliary capacitor 244 is approx. lOfF, the transconductance gm about 40 pS and the voltage transfer ratio A is equal 8. The drain voltage VDR and the output voltage VOUT are differently scaled. Before t2, the drain voltage VDR and the output voltage VOUT are directly connected and essentially the same with the same noise. Starting at t2, the output voltage VOUT is driven through the auxiliary capacitor 244. The drain capacitor accumulates a greater portion of the charge so that the amplitude of noise in the drain voltage VDR is significantly increased. On the other hand, the effective bandwidth is reduced for the output voltage VOUT. The upper cutoff frequency for the noise signal is lowered resulting in slower noise signals and in a reduced noise amplitude.73953

[0106] 12

[0107] FIG. 7 refers to an image sensor assembly, that includes a pixel circuit 100 configured to output a pixel signal, wherein a voltage of the pixel signal is a function of an intensity of incoming radiation. A field effect transistor 205 is configured to receive the pixel signal at a source. A feedback circuit 220 is configured to feed back a portion of an output voltage VOUT from an amplifier output 209 to a gate of the field effect transistor 205. A drain capacitor 230 is electrically connected between a drain of the field effect transistor 205 and a reference potential. A noise reduction circuit 240 is configured to connect the drain of the field effect transistor 205 to the amplifier output 209 via a capacitive path for low-noise phases, and via a resistive path outside the low-noise phases. An analog -to-digital converter 262 is configured to convert the output voltage VOUT into a digital value.

[0108] In particular, FIG. 7 shows the output portions of two pixel circuits 100-1, 100-n of n pixel circuits electrically connected to the same data signal line f. The output portions include an amplifier transistor 108 and a select transistor 109 electrically connected in series between a positive supply potential VDD and the data signal line 19. Receiving portions of the pixel circuits 100 convert incoming radiation into a charge which is transferred to the gate of the amplifier transistor 108 of the respective pixel circuit 100, wherein the amount of accumulated charge is a function of the intensity of the radiation received during an exposure period. An active select signal SEL applied to the gate of the select transistor 109 connects the amplifier transistor 108 of the selected pixel circuit 100 to the data signal line 19, which is electrically connected to the source of the field effect transistor 205 of a common gate amplifier circuit 261 as described with respect to any of FIG. 3, FIG.4 and FIG. 5 A.

[0109] The load paths of the amplifier transistor 108 of the selected pixel circuit 100 and the field effect transistor 205 of the common gate amplifier circuit 261 are electrically connected in series, wherein the amplifier transistor 108 is in a source follower configuration with the source signal following the gate voltage.

[0110] The pixel circuits 100 are formed on a radiation receiving chip 910. An analog -to-digital converter circuit 270 including the common gate amplifier circuit 261 and an analog -to-digital converter 262 as described with reference to FIG. 6A is formed on a processing chip 920. One single through contact via 915 per pixel circuit 100 passes the pixel signal transmitted via the data signal line 19 from the radiation receiving chip 910 to the processing chip 920. According to other examples, some components of the analog-to-digital converter circuit 270 may be formed on the processing chip 920.

[0111] FIG. 8 illustrates a configuration example of a solid-state imaging device 90 in accordance with embodiments of the present technology. The solid-state imaging device 90 includes an image sensor assembly 70 and a signal processing unit 80. The image sensor assembly 70 includes a row decoder / driver 30, a pixel array 10, a column signal processing unit 20 that includes a plurality of column signal processing circuits 200, a digital readout unit 40, and a sensor controller 50.

[0112] The pixel array 10 includes a plurality of identical pixel circuits 100. The pixel circuits 100 may be any active pixel sensors (APS) for intensity readout with one or two photoelectric conversion elements and three, four or more pixel transistors. The pixel circuits 100 convert incident radiation into a pixel internal73953

[0113] 13

[0114] voltage that is a monotonic function of the intensity of incident radiation detected by the pixel circuit 100 in an exposure period. When a pixel circuit 100 is selected in a row readout period, the selected pixel circuit 100 outputs a pixel signal with a voltage controlled by the pixel internal voltage to one of the data signal lines 19.

[0115] The pixel circuits 100 may be arranged matrix-like in columns and rows. A subset of pixel circuits 100 assigned to the same column form a pixel column. A subset of pixel circuits 100 assigned to the same row form a pixel row.

[0116] The row decoder / driver 30 controls the pixel circuits 100 by generating pixel control signals for operating and selecting groups of pixel circuits 100. The pixel control signals control reset, exposure time, internal temporal storage of the illumination information, and the readout of the pixel circuits 100. The row decoder / driver 30 outputs the pixel control signals on pixel control lines 13 according to driver timing signals supplied from the sensor controller 50.

[0117] The row decoder / driver 30 controls all pixel circuits 100 of a selected group of pixel circuits 100 synchronously. The selected group of pixel circuits 100 may include some pixel circuits 100 of one pixel row, all pixel circuits 100 of one pixel row, or some or all pixel circuits 100 of more than one pixel row. The following part of the description refers to “pixel rows” as examples for “groups of pixel circuits” for simplicity.

[0118] The pixel circuits 100 of a pixel output group sequentially pass information about the pixel internal voltage, which depends on an illumination intensity detected by the pixel circuits 100 in an exposure period, to at least one data signal line (vertical signal line) 19. Each pixel output group may include some pixel circuits 100 of one pixel column, all pixel circuits 100 of one pixel column, or some or all pixel circuits 100 of more than one pixel column. The following part of the description refers to “pixel columns” as examples for “pixel output groups” for simplicity.

[0119] Each pixel circuit 100 includes an amplifier transistor 108 in a source follower configuration with a component of the group signal processing unit 20. A load path of the amplifier transistor 108 is electrically connected between a positive supply potential and the voltage signal line 19. Each voltage signal line 19 sequentially conveys the pixel voltages from the pixel circuits 100 of one of the pixel columns to the column signal processing unit 20.

[0120] The column signal processing unit 20 includes one column signal processing circuit 200 for each data signal line 19, at least one voltage ramp generator 27 and at least one counter circuit 28. The column signal processing circuit 200 converts the voltage of the pixel signals into digital pixel values, may preprocess the digital pixel values and outputs the digital pixel values or the preprocessed digital pixel values to the digital readout unit 40.

[0121] To this end, each column signal processing circuit 200 includes a common gate amplifier circuit 261 as described above, a comparator circuit 263, and a digital counting circuit 264, wherein the comparator73953

[0122] 14

[0123] circuit 263 and the digital counting circuit 264 form parts of the analog-to-digital converter 262 described above. The output voltage of the common gate amplifier circuit 261 is supplied to a first input of the comparator circuit 263.

[0124] The column signal processing unit 20 may include one voltage ramp generator 27 for each column signal processing circuit 200. In the illustrated example, one single global voltage ramp generator 27 supplies a voltage ramp signal VRMP to all column signal processing circuits 200, in response to an active ramp enable signal REN. The voltage ramp signal VRMP falls from a high voltage level to a low voltage level continuously or in small steps. The voltage ramp signal VRMP is applied to the second inputs of the comparator circuits 263 in row readout periods. Each comparator circuit 263 outputs an active comparator output signal when the voltage level of the voltage ramp signal VRMP falls below the voltage level of the pixel signal applied to the first input of the comparator circuit 263.

[0125] The column signal processing unit 20 may include one counter circuit 26 for each column signal processing circuit 200. In the illustrated example, one global counter circuit 28 supplies the same count signal to all column signal processing circuits 200.

[0126] The counter circuit 28 may output a digital count value of a digital counter on a digital bus to data inputs of the digital counting circuits 264 in response to an active count enable signal CEN. The active count enable signal CEN and the active ramp enable signal REN have a predetermined temporal relationship to each other and to the beginning of the row readout period. The digital counting circuits 264 latch the current count values applied to the data inputs with a transition from an inactive comparator output signal to the active comparator output signal. The latched count value represents the digital pixel value of the voltage of the pixel signal obtained from the pixel circuit 100 in the row readout period. The digital readout unit 40 may store digital values obtained in data phases and preset phases for correlated double sampling (CDS) and / or digital double sampling (DDS).

[0127] The sensor controller 50 generates the driver timing signal and outputs the driver timing signals to the row decoder / driver 30. The sensor controller 50 generates the ramp enable signal REN and the count enable signal CEN for controlling the voltage ramp generator 27 and the counter circuit 28 and may generate a readout control signal that controls the readout of the digital values from the readout digital readout unit 40 to the signal processing unit 80 and / or to a digital interface.

[0128] The sensor controller 50 may be configured to control the low-noise phases of the noise reduction circuit 240 and to control the analog-to-digital converter 262 to sample the output voltage VOUT of the common gate amplifier circuit 262 at a defined temporal relationship with the low-noise phases.

[0129] In addition, the low-noise phases may have a predetermined relationship with other control signals concerning the analog-to-digital conversion. The predetermined relationship may concern signal levels and / or timings. For example, the beginning of the low-noise phases may have a predetermined temporal relationship with the start of a ramp in a voltage ramp signal used for the analog-to-digital conversion.73953

[0130] 15

[0131] In particular, the sensor controller 50 may be configured to control the analog -to-digital converter 262 to sample the output voltage VOUT in the low-noise phases.

[0132] For example, the sensor controller 50 may be configured to output a noise control signal SI and a sample signal SMPL, wherein an active noise control signal SI controls the noise reduction circuit 240 to connect the drain of the field effect transistor 205 of the common gate amplifier circuit 261 to the amplifier output 209 via the capacitive path for the low-noise phases, and wherein an active sample signal SMPL controls the analog -to-digital converter 262 to sample the output voltage VOUT in the low-noise phases.

[0133] FIG. 9 shows one of the examples of a pixel circuit 100 that can be used in the image sensor 70 of FIG. 8. The pixel circuit 100 includes a photodetector 101, a transfer transistor 102, a sense region 111, and a pixel readout circuit with a reset transistor 103, an amplifier transistor 108, and a select transistor 109.

[0134] The photodetector 101 includes a photoelectric conversion element that photoelectrically converts incident electromagnetic radiation into electric charges. The amount of electric charge generated in the photodetector 101 corresponds to the intensity of incident electromagnetic radiation. The photodetector 101 may include or consist of a photodiode which converts electromagnetic radiation incident on a detection surface into a detector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation and / or ultraviolet radiation. The amplitude of the detector current is a function of the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the detector current may increase approximately linearly with increasing intensity of the detected electromagnetic radiation.

[0135] The sense region 111 can include a floating diffusion region and / or a capacitor electrode. In reset phases, a potential of the sense region 111 is a function of the pixel dark current representing the noise. In data phases, the potential of the sense region 111 is a function of the integrated detector current.

[0136] A load path of the transfer transistor 102 may electrically connect a cathode of the photodetector 101 and the sense region 111. The transfer transistor 102 serves as transfer element for transferring charge from the photodetector 101 to the sense region 111 in or after an integration period. A transfer signal TRG is supplied to the gate (transfer gate) of the transfer transistor 102 through a transfer signal line. The transfer signal TRG changes between an active signal level (“active transfer signal”) and an inactive signal level (“inactive transfer signal”). In response to an active transfer signal TRG, the transfer transistor 102 may transfer electrons photoelectrically converted by the photodetector 101 to the sense region 111. In the illustrated example, the active signal level is the high level.

[0137] A reset signal RST is supplied to a gate of the reset transistor 103 through a reset control line. The reset signal RST changes between an active signal level (“active reset signal”) and an inactive signal level (“inactive reset signal”). In response to an active reset signal RST, the reset transistor 103 may connect73953

[0138] 16

[0139] the sense region 111 to a reset potential, which may be the positive supply potential VDD. In the illustrated embodiment, the active signal level is the high level.

[0140] A controlled load path of the amplifier transistor 108 is electrically connected between the positive supply potential VDD and a data signal line 19. The sense region 111 is connected to the gate of the amplifier transistor 108. A potential at the gate of the amplifier transistor 108 is equal to the potential of the sense region 111. When the pixel circuit 100 is selected, the amplifier transistor 108 may be in a source follower configuration with a constant current source electrically connected to the data signal line 19, for example, in a sort of cascode configuration with the field effect transistor 205 and the active load 252 of any of the common gate amplifier circuits 261 as described with reference to FIG. 3, FIG. 4 and FIG. 5A.

[0141] In particular, the load path of the amplifier transistor 108 and a load path of the select transistor 109 may be electrically connected in series between the positive supply potential VDD and the data signal line 19. A row select signal SEL is supplied to the gate of the select transistor 109 through a select signal line. The select signal SEL changes between an active signal level (“active select signal”) and an inactive signal level (“inactive select signal”). In the illustrated example, the select transistor 109 is an nFET (n channel field effect transistor) and the active signal level is the high level. The active select signal turns on the select transistor 109.

[0142] The transfer signal TRG, the reset signal RST and the select signal SEL are examples for pixel control signals transmitted via the pixel control lines 13 in FIG. 8.

[0143] In FIG. 10A, the pixel signal which is output by a pixel circuit 100-i of the type described with reference to FIG. 9 is the input signal VIN of an analog-to-digital converter circuit 270 that includes a common gate amplifier circuit 261 as described with reference to FIG. 4. The pixel signal is transmitted via a data signal line 19 that is connected to the source of the select transistor 109 of the pixel circuit 100-i and the source of the field effect transistor 205 of the common gate amplifier circuit 261. The data signal line 19 transmits the pixel signal from the pixel circuit 100-i to the common gate amplifier circuit 261.

[0144] FIG. 10B shows the timing of the pixel control signals SEL, TRG, and RST and the control signals SI, S2, SMPL for the analog-to-digital converter circuit 270 for a correlated-double-sampling (CDS) readout of the pixel circuit 100-i. The noise control signal SI has the low level as active level. All other control signals have the high level as active level.

[0145] The pixel circuit 100-i is selected for the entire period between tO and t6, in which the select signal SEL is active. Within the initial period tinit between tO and tl, an active reset signal RST sets the pixel floating diffusion region to a potential representing the thermal noise of the pixel circuit 100-1 and an active initialization control signal S2 initializes the feedback loop of the common gate amplifier circuit 261. When both the reset signal RST and the initialization control signal S2 are inactive at tl, the P-phase of the CDS cycle begins. In the P-phase, the analog-to-digital converter circuit 270 compares the output voltage VOUT with a falling ramp signal. In a first part of the P-phase between tl and t2, the73953

[0146] 17

[0147] common gate amplifier circuit 261 is in a settling phase tstlP of the P-phase. In a second part of the P-phase between t2 and t3, an active noise control signal SI sets the common gate amplifier circuit 261 into a low-noise phase tlwbP of the P-phase. The active noise control signal SI may be triggered by a timing condition, e.g., the beginning of the falling ramp in the ramp signal and / or a signal level condition concerning the output voltage VOUT and / or the ramp signal. At the end of the low-noise phase tlwbP, an active sample signal SMPL may control a sample-and-hold of the output voltage for the analog-to-digital conversion of the P-phase signal.

[0148] Between t3 and t4 an active transfer signal TRG discharges the floating diffusion regions by an amount of charge accumulated during the exposure. When the transfer signal TRG changes to inactive at t4, the D-phase of the CDS cycle begins. In the D-phase, the voltage of the pixel signal is a function of the received light intensity. In a first part of the D-phase between t4 and t5, the common gate amplifier circuit 261 is in a settling phase tstlD of the D-phase. In a second part of the D-phase between t5 and t6, an active noise control signal S 1 sets the common gate amplifier circuit 261 into a low-noise phase tlbwD of the D-phase. Again, the active noise control signal SI may be triggered by a timing condition, e.g., the beginning of the falling ramp in the ramp signal and / or a signal level condition concerning the output voltage VOUT and / or the ramp signal. At the end of the low-noise phase tlwbD, an active sample signal SMPL may control a sample-and-hold of the output voltage for the analog-to-digital conversion of the D-phase signal.

[0149] FIG. 11 is a diagram illustrating an example in which the image sensor 70 of FIG. 8 includes a CIS (stacked contact image sensor) having a two-layer structure with a radiation receiving chip 910 and a processing chip 920. The radiation receiving chip 910 includes at least the photoelectric conversion element, e.g., only the photoelectric conversion element, the photoelectric conversion element and the complete pixel circuit or the photoelectric conversion element and some components of the pixel circuits. The processing chip 920 includes the further elements of the pixel circuits 100. As illustrated on the right side of FIG. 11, the image sensor 70 is formed as one sensor by bonding the radiation receiving chip 910 and the processing chip 920 while electrically bringing contact pads on the radiation receiving chip 910 in contact with corresponding contact pads on the processing chip 920.

[0150] FIG. 12 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied.

[0151] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 12, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outsidevehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.73953

[0152] 18

[0153] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0154] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0155] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. The outside-vehicle information detecting unit 12030 can be connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image. Based on the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0156] The imaging section 12031 may be or may include an image sensor assembly according to the embodiments of the present disclosure. The light received by the imaging section 12031 may contain visible light and / or invisible light such as infrared rays or the like.

[0157] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include an image sensor assembly according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the image sensor assembly according to the embodiments and that is focused on the driver. Based on detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing.

[0158] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040 and output a control command to the driving system control73953

[0159] 19

[0160] unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0161] In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0162] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0163] The sound / image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 12, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display.

[0164] FIG. 13 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12104, and 12105.

[0165] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.73953

[0166] 20

[0167] Incidentally, FIG. 13 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0168] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including an image sensor assembly according to the embodiments of the present disclosure.

[0169] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100 on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

[0170] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a largesized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0171] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there73953

[0172] 21

[0173] is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0174] The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying an image sensor assembly according to the embodiments of the present disclosure, the system can be improved. In particular, the signal -to-noise ratio can be improved for the analog -to-digital conversion of the pixel signals.

[0175] Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

[0176] The image sensor assembly according to the present disclosure may be any device used for analyzing and / or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, an image sensor assembly according to the embodiments may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

[0177] Specifically, in the field of image reproduction, the image sensor assembly according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, a solid-state imaging device including an image sensor assembly according to the embodiments may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

[0178] In the field of home appliances, a solid-state imaging device with an image sensor assembly according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly, the solid-state imaging device with an image sensor assembly according to the embodiments may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and / or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the solid-state imaging device with an73953

[0179] 22

[0180] image sensor assembly according to the embodiments may be integrated in any type of sensor, e.g., a camera device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

[0181] In the field of security, the solid-state imaging device with an image sensor assembly according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, a solid-state imaging device with an image sensor assembly according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, a solid-state imaging device with an image sensor assembly according to the embodiments can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the solid-state imaging device with an image sensor assembly according to the embodiments can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

[0182] The present technology can also be configured as described below: [1] A common gate amplifier circuit (261), including: a field effect transistor (205) configured to receive an input signal at a source; a feedback circuit (220) configured to feed back a portion of an output voltage VOUT from an amplifier output (209) to a gate of the field effect transistor (205); a drain capacitor (230) electrically connected between a drain of the field effect transistor (205) and a reference potential; and a noise reduction circuit (240) configured to connect the drain of the field effect transistor (205) to the amplifier output (209) via a capacitive path for low-noise phases, and via a resistive path outside the low-noise phases.

[0183] [2] The common gate amplifier circuit according to [1], further including: an active load (252) electrically connected in series with the field effect transistor (205) at a drain side of the field effect transistor (205) and configured to supply a constant current.

[0184] [3] The common gate amplifier circuit according to any of [1] and [2], wherein the feedback circuit (220) is configured to connect the drain and the gate of the field effect transistor (205) via a resistive path in initialization phases and via a capacitive path outside the initialization phases.

[0185] [4] The common gate amplifier circuit according to any of [1] to [3], wherein the feedback circuit (220) includes a first capacitor (221) electrically connected between the gate of the field effect transistor (205) and the reference potential, a second capacitor (222) electrically connected between the amplifier output (209) and the gate of the field effect transistor (205), and an initialization switch (225) configured to short-circuit the second capacitor (222) for initialization phases (245).

[0186] [5] The common gate amplifier circuit according to any of [1] to [4], wherein the noise reduction circuit (240) includes an auxiliary capacitor (244) electrically connected between the drain of the field effect transistor (205) and the amplifier output (209), and a preset switch (245) configured to short-circuit the auxiliary capacitance (244) for settling phases outside the low-noise phases.73953

[0187] 23

[0188] [6] The common gate amplifier circuit according to any of [1] to [5], wherein the field effect transistor (205) is configured as p-channel field effect transistor.

[0189] [7] An analog -to-digital converter circuit (270), including: the common gate amplifier circuit (261) according to any of [1] to [6]; and an analog -to-digital converter (262) configured to convert the output voltage VOUT into a digital value.

[0190] [8] The analog -to-digital converter circuit according to [7], wherein the analog -to-digital converter (262) includes an input capacitance.

[0191] [9] The analog -to-digital converter circuit according to any of [7] and [8], wherein the analog -to-digital converter (262) is configured to sample the output voltage VOUT at a defined temporal relationship with the low-noise phases.

[0192]

[0010] The analog -to-digital converter circuit according to any of [7] to [9], wherein the analog -to-digital converter (262) is configured to sample the output voltage VOUT in the low-noise phases.

[0193]

[0011] An image sensor assembly (70), including: a pixel circuit (100) configured to output a pixel signal, wherein a voltage of the pixel signal is a function of an intensity of incoming radiation; the common gate amplifier circuit (261) according to any of [1] to [6], wherein the field effect transistor (205) is configured to receive the pixel signal at a source as the input signal; and an analog-to-digital converter (262) configured to convert the output voltage VOUT of the common gate amplifier circuit (261) into a digital value.

[0194]

[0012] The image sensor assembly according to

[0011] , further including: a sensor controller (50) configured to control the low-noise phases of the noise reduction circuit (240) and to control the analog-to-digital converter (262) to sample the output voltage VOUT at a defined temporal relationship with the low-noise phases.

[0195]

[0013] The image sensor assembly according to

[0012] , wherein the sensor controller (50) is configured to control the analog-to-digital converter (262) to sample the output voltage VOUT in the low-noise phases.

[0196]

[0014] The image sensor assembly according to any of

[0012] and

[0013] , wherein the sensor controller (50) is configured to output a noise control signal S 1 and a sample signal SMPU, wherein an active noise control signal S 1 controls the noise reduction circuit (240) to connect the drain of the field effect transistor (205) to the amplifier output (209) via the capacitive path for the low-noise phases, and wherein an active sample signal SMPU controls the analog-to-digital converter (262) to sample the output voltage VOUT in the low-noise phases.

Claims

7395324CLAIMS1. A common gate amplifier circuit, comprising:a field effect transistor configured to receive an input signal at a source;a feedback circuit configured to feed back a portion of an output voltage VOUT from an amplifier output to a gate of the field effect transistor;a drain capacitor electrically connected between a drain of the field effect transistor and a reference potential; anda noise reduction circuit configured to connect the drain of the field effect transistor to the amplifier output via a capacitive path for low-noise phases, and via a resistive path outside the low-noise phases.

2. The common gate amplifier circuit according to claim 1, further comprising:an active load electrically connected in series with the field effect transistor at a drain side of the field effect transistor and configured to supply a constant current.

3. The common gate amplifier circuit according to claim 1,wherein the feedback circuit is configured to connect the drain and the gate of the field effect transistor via a resistive path in initialization phases and via a capacitive path outside the initialization phases.

4. The common gate amplifier circuit according to claim 1,wherein the feedback circuit comprises a first capacitor electrically connected between the gate of the field effect transistor and the reference potential, a second capacitor electrically connected between the amplifier output and the gate of the field effect transistor, and an initialization switch configured to short-circuit the second capacitor for initialization phases.

5. The common gate amplifier circuit according to claim 1,wherein the noise reduction circuit comprises an auxiliary capacitor electrically connected between the drain of the field effect transistor and the amplifier output, and a preset switch configured to short-circuit the auxiliary capacitance for settling phases outside the low- noise phases.

6. The common gate amplifier circuit according to claim 1,wherein the field effect transistor is configured as p-channel field effect transistor.

7. An analog -to-digital converter circuit, comprising:the common gate amplifier circuit according to claim 1 ; andan analog -to-digital converter configured to convert the output voltage VOUT into a digital value.

8. The analog -to-digital converter circuit according to claim 7,7395325wherein the analog -to-digital converter comprises an input capacitance.

9. The analog -to-digital converter circuit according to claim 7,wherein the analog -to-digital converter is configured to sample the output voltage VOUT at a defined temporal relationship with the low-noise phases.

10. The analog -to-digital converter circuit according to claim 7,wherein the analog -to-digital converter is configured to sample the output voltage VOUT in the low-noise phases.

11. An image sensor assembly, comprising:a pixel circuit configured to output a pixel signal, wherein a voltage of the pixel signal is a function of an intensity of incoming radiation;the common gate amplifier circuit according to claim 1, wherein the field effect transistor is configured to receive the pixel signal at a source as the input signal; andan analog -to-digital converter configured to convert the output voltage VOUT of the common gate amplifier circuit into a digital value.

12. The image sensor assembly according to claim 11, further comprising:a sensor controller configured to control the low-noise phases of the noise reduction circuit and to control the analog -to-digital converter to sample the output voltage VOUT at a defined temporal relationship with the low-noise phases.

13. The image sensor assembly according to claim 12,wherein the sensor controller is configured to control the analog-to-digital converter to sample the output voltage VOUT in the low-noise phases.

14. The image sensor assembly according to claim 12,wherein the sensor controller is configured to output a noise control signal S 1 and a sample signal SMPU, wherein an active noise control signal S 1 controls the noise reduction circuit to connect the drain of the field effect transistor to the amplifier output via the capacitive path for the low-noise phases, and wherein an active sample signal SMPU controls the analog- to-digital converter to sample the output voltage VOUT in the low-noise phases.

Images