Potential-separating DC / DC converter for high voltages and frequencies
Patent Information
- Application Number
- PCT/EP2026/058523
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-26
- Filing Date
- 2026-03-25
- Publication Date
- 2026-10-01
Smart Images
Figure EP2026058523_01102026_PF_FP_ABST
Abstract
Description
[0001] Potentially isolating DC / DC converter for high voltages and frequencies
[0002] Many future applications of electrical power engineering require the connection of the respective load to medium and high voltage networks as well as the control and regulation of the energy flow by means of converters.
[0003] Such requirements arise, for example, when connecting charging stations for electric vehicles, battery storage systems, or large computing systems. Typical power outputs range from 1 to over 10 megawatts, necessitating connection to high voltages. A further requirement is the implementation of safe galvanic isolation between the high mains voltage and the output side of the converter. In this power range, this can only be effectively achieved using transformers. To minimize their size, these transformers should be operated at the highest possible frequencies.
[0004] In principle, a large number of DC / DC converters are already known that meet these requirements. Among others, a circuit called a "Dual Active Bridge" is known, which is frequently used for galvanically isolated DC / DC converters; see Figure 1 in DE 102018210807 A1, Figure 2 in CN 118889833 A1, and Figures 1 and 2 in US 10361624 B2.
[0005] The use of these circuits for high voltages is made possible by connecting a large number of such converters in series on the DC side. This is possible primarily because each converter incorporates a potential-isolating transformer. The resulting circuit thus consists of a large number of identical low-voltage converters, each feeding transformers with a low operating voltage. However, the insulation voltage requirement for the transformers is very high, as they must be dimensioned according to the (high) total voltage. An excessively high ratio of insulation voltage to operating voltage is detrimental to the transformer design. Furthermore, connecting a very large number of isolation gaps in parallel is also unfavorable with regard to the reliability of the insulation.
[0006] Another concept involves the use of so-called modular multilevel converters (MLCs). These can directly feed a transformer with a high operating voltage, thus avoiding the need for a large number of transformers, each with a lower operating voltage and power rating. Such a solution is known, among other places, from US 7269037 B2. Figure 1 of that patent shows a direct converter that feeds a transformer directly with a high operating voltage. MLCs are therefore a proven standard for medium- and high-voltage applications. Scaling to higher voltages and power ratings also presents few difficulties. However, a disadvantage of this solution is the high number of power semiconductors required, which in turn leads to greater complexity in terms of control.Despite the aforementioned technical advantages, the effort required to implement the relatively simple function of a DC / DC converter therefore appears too high.
[0007] The first concept, which requires connecting a large number of low-voltage DC / DC converters and a large number of transformers in series, is also disadvantageous in terms of effort and complexity. Further problems arise when scaling to higher voltages and power levels. One of these disadvantages is the high cost of the transformers due to their large number and their unfavorable sizing when high insulation requirements are needed.
[0008] Figure 1 shows the basic functional blocks of a potential-isolated DC / DC converter. A first DC / AC converter 100 is supplied with the input voltage U1 and converts it into an AC voltage U3, which is present at its output. The AC voltage U3 represents the input to the transformer block 300, which contains a transformer 30. The converted AC voltage at the output of block 300 is supplied to a further AC / DC converter 200, which again generates a DC voltage U2. The present invention is based on such a setup for realizing a DC / DC conversion.
[0009] Typical values for the voltages and currents shown in Figure 1 are assumed as examples below in order to illustrate the increasing technical problems when scaling up to high voltages and power levels.
[0010] The DC voltage U1 is applied to the DC-side terminals P1, N1 of the first converter 100. This voltage will be the larger of the two voltages U1, U2. Since the converters and the transformer fundamentally allow energy flow in both directions, the terms input and output are actually inappropriate. For example, let the voltage U1, typically 10 to 20 kV, be U1 = 18 kV. The first converter 100 generates the AC voltage U3 with the operating frequency f1 for the transformer 300 functional unit from this voltage. In Figure 1, this unit contains, for example, only a single-phase transformer 30. However, it is also possible for it to contain a multi-phase transformer or several single- or multi-phase transformers. If the converter generates a three-phase voltage system, a significant advantage is that it avoids three divisible harmonics in the transformer current.The second converter 200 enables the controllable energy flow between the secondary side of transformer 30 and the DC side with voltage U2 at terminals P2,N2. The DC voltage U2, with typical values below 1 kV, is U2 = 800 V in this example. A variety of suitable circuits and embodiments for the second converter 200 are known according to the prior art. Several types – especially two-point and three-point circuits – are already available as industrial series products in technically and economically optimized form. Furthermore, the industrial series production of SiC terminals has also made the desired operating frequencies of the transformers up to approximately f1 = 50 kHz possible. However, the first converter 100, which must perform its function at the high voltage U1, is particularly in need of improvement.
[0011] The object of the present invention is therefore to reduce the effort required with regard to power semiconductors and the complexity, while simultaneously reducing electromagnetic interference and increasing efficiency.
[0012] This problem is solved by the subject matter of the independent patent claims. Advantageous embodiments are the subject matter of the dependent claims.
[0013] Preferred configurations are explained in more detail below, also taking the drawings into account. These show:
[0014] Fig. 1: a schematic representation of the three-component DC / DC converter made possible by the present invention;
[0015] Fig. 2: an embodiment of the DC / AC converter for the circuit according to Figure 1;
[0016] Fig. 3: Diagrams illustrating the achievable improvement in the stress profiles in the embodiment according to Fig. 2, and
[0017] Fig. 4: an alternative embodiment of the DC / AC converter.
[0018] The present invention builds on the understanding that the solutions known from the prior art each exhibit a multitude of disadvantages. This is due, firstly, to the fact that these solutions were developed and technically implemented for significantly lower voltages and power levels. When these concepts are scaled up by more than an order of magnitude, the relevance of many technical problems increases considerably. For example, it is known to those skilled in the art that power electronic converters, due to their switching operation, are affected by parasitic capacitances in the load loop, such as the winding capacitances of transformers. The primary problem here is the pulsed currents caused by the high voltage transient of the switching operations of the power semiconductors. These currents lead, among other things, to electromagnetic interference, which is undesirable with regard to EMC (electromagnetic compatibility).Less well known is the energy loss caused by the periodic recharging of parasitic capacitances. This loss is inherent in the laws of physics and increases proportionally to the energy content of the capacitances. The energy content, in turn, increases quadratically with the switching voltage, so that in periodic switching operation, the resulting power loss increases proportionally with the switching frequency and quadratically with the voltage. In reality, this power loss is distributed across the power semiconductors, parasitic resistances, and other components. Since power electronic converters are designed for low power loss, the recharging of parasitic capacitances generally occurs as a weakly damped, high-frequency oscillation, even though this is not the intended behavior. The disruptive effect of these high-frequency oscillations on electromagnetic compatibility (EMC) usually receives more attention than the resulting energy losses.This can be understood by the fact that the development and technical implementation of converters has so far focused primarily on low voltages. In this context, "low voltage" refers to the technically and industrially advanced state of the art of converters with DC voltages up to approximately 1 to 2 kV, with a particular emphasis on voltages below 1 kV.
[0019] The present invention aims to provide a suitable solution for voltages that are ten times higher.
[0020] From CN 118889833 A1 a circuit of the Dual Active Bridge (DAB) is known, which is intended to further explain the basic technical problems and the considerations relevant to the invention.
[0021] A full bridge circuit consisting of four transistors Q1, Q2, Q3, and Q4 is connected to the input voltage V1. This circuit is controlled such that, via a series inductor L, the primary winding of a transformer can be supplied with an alternating voltage of the desired frequency f1. A similar circuit is present on the secondary side of the transformer and is connected to the output voltage V2. Capacitors 2 are connected in parallel with each transistor. Under certain limiting conditions, these capacitors significantly reduce the switching power losses of the transistors. If it can be ensured that the transistors switch on at a transistor voltage of approximately 0 volts, the switching energy losses during the transistor switch-off process can also be considerably reduced. This desirable operating mode is known in the literature as "Zero Voltage Switching" (ZVS).The necessary constraints for this operating mode are also known and are essentially: operation of the transformer with a sufficiently high phase angle.
[0022]
[0023] in the inductive range and with a sufficiently large load current. To also cover the partial load range, i.e., smaller load currents, as much as possible, the following measures are known.
[0024] a.) The increase in the phase angle <t>.
[0025] b.) Inserting a series choke L before the transformer.
[0026] c.) Reducing the capacitance of the parallel capacitors 2 to possibly 0.
[0027] d.) The insertion of an additional, active auxiliary circuit for recharging the capacitors.
[0028] Measures a) and b) are disadvantageous because they impair efficiency. Regarding measure b), the disadvantage is that the phase angle increases with increasing power. This means that, especially at higher power levels, the phase angle...
[0029]
[0030] unfavorable. Measure c) is disadvantageous because it impairs the desired reduction in switching-off energy loss. Measure d) on the other hand leads to a significantly higher circuit complexity.
[0031] These aspects are explained in detail in DE102018210807 A1. According to the present invention, the parallel capacitors 2 can be dimensioned so that the duration of the charging processes per period of the operating frequency is up to approximately 60 degrees. This means that with a period T1 = 1 / f1, the duration of the 2 charging processes is therefore approximately T1 / 6. The frequency f1 at which the converter is operated can, for example, be 25 kHz. This results in the following advantages:
[0032] - The voltage gradient of the converter's AC voltage is significantly reduced, thereby reducing disruptive currents in parasitic capacitances and EMC interference.
[0033] - The harmonics of the converter's AC voltage are significantly reduced.
[0034] - The switch-off energy loss of the transistors is reduced significantly better compared to smaller parallel capacitors.
[0035] A direct series connection of the transistors is made possible in the simplest way by the good dynamic voltage distribution. However, the technical implementation of a suitable and cost-effective converter for high voltages is hampered by another problem: unavoidable parasitic inductances in the power section of the "Dual Active Bridge" (DAB) lead to disruptive, high-frequency oscillations with every transistor switch-off process, which impair the desired commutation process and cause electromagnetic interference. This detrimental effect also increases disproportionately with higher voltage and power, so that it does not yet reach a disruptive level at lower voltages and power levels.
[0036] In the following reference closed loops, this high-frequency oscillation occurs in principle during every switch-off process; compare Figure 2 of CN 11889833 A1:
[0037] A: via the transistors Q1, Q2 and the DC voltage V1 or via the parallel capacitors of these components.
[0038] B: via the transistors Q3, Q4 and the DC voltage V1 or via the parallel capacitors of these components.
[0039] C: via the transistors Q1, Q2, Q3, Q4 or via the parallel capacitors of these components.
[0040] This problem arises from the fact that all loops of the DAB circuit contain unavoidable parasitic inductances, the magnitude of which increases considerably with the nominal voltage of the actual design. While each of these loops can still be implemented with a minimum loop inductance of LS = 50 nH in a converter with a nominal voltage of, for example, U1 = 1 kV, a value of LS = 500 nH will result for a converter with U1 = 10 kV. This effect is essentially due to the increased spatial extent of the circuit and the air gaps required for insulation, which hinder a low-inductance design. This problem when scaling up the voltage cannot be significantly reduced by arbitrarily repositioning the components. For example, a capacitor for twice the nominal voltage will have approximately twice the distance between its two terminals.Replacing it with two capacitors, each with half the rated voltage, will exhibit approximately the same disruptive leakage inductance. Therefore, connecting several components with lower rated voltages in series is considered indifferent with regard to this problem. Since it is not inherently disadvantageous, it is often used to employ readily available, mass-produced components. To illustrate the problem quantitatively, let's assume a converter with a voltage of U1 = 6 kV. The parasitic inductances in the loops are as follows:
[0041] Mesh A: LA = 300 nH
[0042] Mesh B: LB = 300 nH
[0043] Mesh C: LC= 400 nH
[0044] The parallel capacitors 2 are dimensioned with CP = 55 nF. The dimensioning is explained below using the converter according to the invention. A possible series connection of the transistors and capacitors is not considered initially, as it is irrelevant to the present problem. The following values therefore result for the resonant frequencies of the three different loops, since the capacitance in parallel with V1 is large compared to CP.
[0045] Stitch A: f A = — 2 n yCp - / 2 L A = 1.75 MHz
[0046] Stitch B: f B = f A = 1.75 MH Z
[0047] The resonant frequency of loop C is of a similar order of magnitude. However, its exact value depends on the precise distribution of leakage inductances in all branches. The resonant frequencies occur during the charging and discharging processes of the parallel capacitors. When a charging and discharging process is complete, one of the parallel semiconductors conducts. In loop A, this is either Q1 or Q2. Even in this state, the desired commutation is impaired by a high-frequency oscillation. The fact that the resonant frequency decreases slightly and the damping due to the resistance of the conducting conductor increases slightly is negligible. During the charging and discharging process, a symmetrical distribution of the load current between the two branches containing Q1 and Q2 is desired, according to the intended function of the DAB circuit.Due to the practically undamped resonance, the current in branch Q1 oscillates at frequency fA between 0% and 100% of the load current, and the same occurs in branch Q2, but out of phase, so that the sum of both currents always equals the load current. The desired current distribution for the function would be achieved if both branches carried 50% of the load current each. As already explained, further high-frequency oscillations occur even after the charging processes have ended. These will not be discussed in detail below, as they do not fundamentally change or mitigate the problem at hand.
[0048] The advantages of the circuit, including the intended ZVS (Zero-Voltage Sequence) operating mode, would be largely negated if damping resistors were connected in series with each of the two parallel capacitors. While such a measure would be effective from a conservative standpoint and is known as an RC circuit, it leads to unacceptably high energy losses in the present application due to the high frequency. This method of vibration damping is known to have originated in mains frequency applications. Furthermore, the resulting high power losses preclude the insertion of damping resistors into all branches that carry the load current at certain times.
[0049] According to the present invention, it is possible to insert a suitable damping circuit into the branches of the DC capacitors, which is technically feasible. In this regard, an important objective of the invention is to enable damping using very simple, robust components and with low energy losses. It can be achieved to keep the energy losses small compared to those of the transistors, so that the efficiency of the converter is not significantly reduced. It is also noteworthy that no suitable measures are known for damping loop C, since all the branches involved carry the load current. Therefore, according to the invention, the converter circuit is designed in such a way that such loops are avoided.
[0050] As explained, the present invention improves the converter 100 from Figure 1 in order to address the problems for DC / DC converters at high voltages and high powers discussed in connection with the prior art.
[0051] Figure 2 shows a preferred embodiment of the DC / AC converter according to the present invention. The converter block 10 shown has terminals Y1 and Y2, with the positive terminal of the high DC voltage U1 being connected to terminal Y2 and the negative terminal to terminal Y1. The generated AC voltage with frequency f1 is connected to terminal L.
[0052] Between terminal Y2 and output L is a series connection of several transistor modules 11, with three of these modules shown as an example in Figure 2, but there can also be up to 50 or more. Likewise, a corresponding number of series-connected transistor modules 11 are connected between output L and input terminal Y1. Each module consists of a transistor 1, preferably field-effect transistors using SiC technology. In addition to the transistor 1, each module preferably has a capacitor 2 connected in parallel and optionally a resistor 3 also connected in parallel, so that a transistor module 11 consists of a resistor, a capacitor, and a transistor connected in parallel.
[0053] The number of modules is even, but in principle arbitrary. The transistor modules 11 have the aforementioned structure and preferably no further components, which makes them simple and inexpensive. In particular, no bridge circuits consisting of multiple transistors are required.
[0054] Parallel to the branch of transistor modules, terminals Y2 and Y1 are each connected to an attenuator 4, preferably via a decoupling capacitor 7 and 8, respectively. The attenuator optionally consists of two series-connected high-frequency chokes (inductors) 5 connected in parallel to an optional resistor 6. The center of the high-frequency chokes 5 is connected directly or optionally via an additional inductor 4 to terminal L.
[0055] It is also possible to work with only a high-frequency choke 5, whereby the resulting voltage offset can then be compensated by means of another capacitor between the center of the transistor modules (L) and the damping element 9.
[0056] The two high-frequency chokes can also be combined into one choke if the resulting slight asymmetry is acceptable.
[0057] It is also possible to work with two such DC / AC converters 10 from Figure 2 and to connect the load between these two DC / AC converters (whereby the DC / AC converters must be operated in opposite phases in order not to compensate for each other in terms of voltage).
[0058] Figure 2 shows the connection for the load L without a second connection, although it is clear to those skilled in the art that there are several possibilities. For example, Y1 could form the second connection, but this would result in a DC voltage offset. Likewise, Y2 could be used as the second connection point, with a correspondingly reversed voltage offset. However, the voltage offset can be eliminated by means of additional connected capacitors, for example, by a capacitor between connection point L and the connected load.
[0059] Because of the attenuator, the use of relatively large transistors 2 in the transistor modules 11 is possible. These can be dimensioned up to two orders of magnitude larger than the parasitic capacitances of the transistors 1 (which are approximately 0.5-1 nF) and thus compensate for their tolerances.
[0060] Large loops with many transistor modules 11 are thus possible to achieve correspondingly high voltages. Furthermore, very large transistors can be used, up to a factor of 10 larger than in comparable prior art solutions. The additional inductance 4 is dimensioned such that an inductive reactive current iz flows, which is small compared to the load current iL. Since both currents are approximately sinusoidal, the dimensioning can be formulated as the quotient of the peak currents. Thus, a preferred dimension is iz = 1 / 4 iL. Of course, other quotients are possible, but the overall aim is to ensure that the charging times of the parallel capacitors 2 are preferably between T1 / 6 and T1 / 9 across the entire operating range (no load to rated power).
[0061] As indicated, iz should not be too large to avoid unnecessary losses due to reactive power. However, the presence of the reactive current iz is generally advantageous to enable the charging and discharging of the capacitors 2 of the transistor modules 11. This is ensured by the use of the additional inductor or choke coil 4.
[0062] The reactive power iz can optionally also be supplied by the transformers in transformer block 300, so that the additional choke 4 can be omitted in limiting cases. This option requires transformers with a relatively high magnetizing current due to their design. Without the damping element, strong high-frequency oscillations in the MHz range would occur, which would impair the function of the circuit.
[0063] The AC-side power factor, or cosine <t>This results in very high values at high power levels, typically >= 0.95. The attenuator 9 is inserted in the branch of the DC-side capacitors 7, 8. The high-frequency chokes 5 carry approximately only the current components of frequencies f1 and 2*f1, which originate from the auxiliary current IZ and the load current IL, respectively. The high-frequency chokes can optionally be replaced by short conductor segments and / or cables, which can exhibit the same impedance as the high-frequency chokes at high frequencies. The resistor 6 carries approximately only high-frequency current pulses that were excited by the switching of the transistors 1. This distribution of the currents according to their frequency spectrum is achieved by the very high quotient fA / f1 and a corresponding dimensioning of elements 5 and 6. The transistors 1 are preferably implemented as field-effect transistors using SiC technology.The number of transistors 1 connected in series is shown as 3 in Figure 2, for example, but is basically freely selectable.
[0064] Figure 3 illustrates the significance of the capacitors 2 in the transistor modules 11 of Figure 2. Since CP > 0 with these capacitors, the edges of the output voltage are smoother, with the slope preferably being approximately T1 / 6 - T1 / 9, where f1 represents the generated output frequency and UAC the output voltage. The diagram above, however, indicates the sharp rise and fall that would occur without capacitors at CP = 0. The smooth edges have a positive effect on EMC and the resulting harmonics, especially when large capacitors 2 are chosen. However, the capacitors 2 must be recharged, for which the additional inductor or choke 4 is advantageous.
[0065] Figure 4 shows an alternative embodiment of the high-voltage-side converter 100, which can generate a three-phase AC voltage system at terminals L1, L2, and L3. The invention thus enables a series connection of three such converter cells on the DC side, thereby minimizing the number of transistors 1 required at high voltages of U1. In this case, the DC component of the converter voltages must be isolated by additional capacitors 12. This is not necessary for the middle converter, as it does not have a DC component in the first place.
[0066] Such a measure is generally known and requires little effort. Figure 4 shows, by way of example, the functional block 300 with the transformers, which here are formed by three single-phase transformers 13. The star / delta connection shown in the figure is advantageous, but not strictly necessary.
[0067] The control system for the Converter 100 can be implemented in the same way as for a VSC converter on a 3-phase network:
[0068] The converter generates the mains voltage 100
[0069] A low-voltage converter 200 is connected via the transformer(s) of transformer block 300. Its control is synchronized to the specified mains voltage. The converter 200 can now...
[0070] a) specified power (or mains current) and
[0071] b) a given phase angle (or reactive power)
[0072] The settings are similar to a conventional converter connected to a specified mains voltage via a mains transformer. However, the "mains frequency" is higher here, and the specified "mains voltage" is generated by the Converter 100.
[0073] The frequency fi can be variably controllable. In particular, it can be advantageous to increase the frequency as the power decreases. This measure can reduce the reactive current iz and consequently the power loss of the converter at no load and partial load.< / t> < / t>
Claims
P154574 12 Claims 1. DC / DC Converter with: a first DC / AC converter block (100) on which an input voltage U1 is applied on the DC side between a second input terminal (Y2) and a first input terminal (Y1), a transistor block (300) which is connected on the input side to the AC-side output of the converter block, a second AC / DC converter block (200) which is connected to the output of the transistor block on the AC side and provides an output voltage U2 on the DC side, characterized by the fact that, the first DC / AC converter block (100) has a converter (10) which has a series connection of N transistor modules (1) between the input terminals (Y2, Y1), where N is an even number greater than zero, and each transistor module consists of a parallel connection of a transistor, a capacitor and optionally a resistor, where the voltage between the midpoint (L) of the series connection of the transistor modules forms the output voltage, wherein a damping element (9) is connected between the first and second input terminals and in parallel to the series connection of the transistor modules (11), which is connected via first and second connections to the first and second inputs via preferably each isolation capacitor (7,8), and via a third connection to the center point of the series connection of the transistor modules (L).
2. DC / DC converter according to claim 1, wherein the attenuator (9) consists of a series connection of at least one first and second high-frequency choke (5) and a resistor (6) connected in parallel thereto.
3. DC / DC converter according to claim 2, wherein the midpoint between the at least two high-frequency chokes (5) is connected via an additional inductor (4) to the midpoint of the series connection of the transistor modules (L). P154574 13 4. DC / DC converter according to one of claims 1-3, wherein the transistors (1) of the transistor modules (11) are designed as SIC field-effect transistors.
5. DC / DC converter according to one of claims 1-4, wherein the inductive reactive current iz through the inductance is small compared to the load current iL at the output.
6. DC / DC converter according to claim 5, wherein approximately iz = 14 iL applies.
7. DC / DC converter according to one of claims 1-6, wherein the charging times of the capacitors (1) of the transistor modules (11) are between Ti* 1 / 6 and Ti* 1 / 9, with Tl = 1 / f1.
8. DC / DC converter according to claim 7, wherein the high-frequency chokes (5) approximately only carry the current components fi and 2*fi.
9. DC / AC converter in which an input voltage U1 is applied on the DC side between a first input terminal (Y2) and a second input terminal (Y1), wherein the converter specifies: between the second (Y2) and first input terminals (Y1) a series circuit of N transistor modules (1), where N is an even number greater than zero, and each transistor module consists of a parallel circuit of a transistor, a capacitor and a resistor, the voltage between the midpoints of the series circuit of the transistor modules forms the output voltage, A damping element (9) is connected between the first and second input terminals and in parallel to the series connection of the transistor modules, which is connected via first and second connections to the first and second input terminals via a separating capacitor (7,8) and via a third connection to the center point of the series connection of the transistor modules.
10. AC / DC converter according to claim 9, wherein the attenuator (9) consists of a series connection of at least one first and second high-frequency choke (5) and a resistor (6) connected in parallel thereto.
11. AC / DC converter according to claim 10, wherein the midpoint between the at least two high-frequency chokes (5) is connected via an additional inductor (4) to the midpoint of the series connection of the transistor modules (L). P154574 14 12. AC / DC converter according to one of claims 9-11, wherein the transistors (1) of the transistor modules (11) are designed as SIC field-effect transistors.
13. AC / DC converter according to one of claims 9-12, wherein the inductive reactive current iz through the inductance is small compared to the load current iL at the output.
14. AC / DC converter according to claim 13, wherein approximately iz = 14 iL applies.
15. AC / DC converter according to one of claims 9-14, wherein the charging times of the capacitors (1) of the transistor modules (11) are between Ti* 1 / 6 and Ti* 1 / 9, with Tl = 1 / f1.
16. AC / DC converter according to claim 15, wherein the high-frequency chokes (5) approximately only carry the current components fi and 2*fi.
17. DC / DC converter according to one of claims 1-8, wherein the first converter block (100) comprises three AC / DC converters (10) connected in series between the second and first input terminals according to claim 9, and the corresponding three outputs (L1, L2, L3) of the first converter block (100) are connected to three single-phase transformers within the transistor block (300), wherein two of the outputs (L1, L3) are connected to the single-phase transformers via isolating capacitors (12).