A method for operating a hybrid si-sic switch
Patent Information
- Application Number
- PCT/EP2026/058649
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-27
- Filing Date
- 2026-03-25
- Publication Date
- 2026-10-01
Smart Images
Figure EP2026058649_01102026_PF_FP_ABST
Abstract
Description
[0001] 202500397
[0002] 1
[0003] Description
[0004] A method for operating a hybrid Si-SiC switch
[0005] The present invention relates to a method for controlling a hybrid silicon-silicon carbide (Si-SiC) switch. The present invention further relates to a hybrid Si-SiC switch. The present invention further relates to an AC / DC inverter or DC / DC converter including such a switch, and to an onboard-charging unit including such an inverter and / or converter.
[0006] Hybrid silicon-silicon carbide (Si-SiC) switches are becoming more and more interesting, also in the field of automotive applications.
[0007] Hybrid Si-SiC switches combine silicon (Si) insulated-gate bipolar transistors (IGBTs) with silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFET). Such hybrid switches offer advantages in terms of switching speed, losses and cost-effectiveness.
[0008] In the pursuit of enhanced efficiency and performance in power electronic applications, the hybrid silicon-silicon carbide (Si-SiC) switch has emerged as a promising candidate for use in inverter applications or other power electronic applications. The architecture of the hybrid switch leverages the complementary advantages of silicon (Si) and silicon carbide (SiC) technologies. Silicon, with its established use in semiconductor devices, offers robust performance at lower costs. In contrast, silicon carbide provides superior thermal conductivity, higher breakdown voltage, and enhanced efficiency in high-temperature environments.
[0009] Hybrid Si-SiC switch designs and / or architectures integrate and cooperate Si and SiC materials to optimize switching characteristics and reduce conduction losses, making it particularly suitable for electric vehicles and / or electric industrial motor drives. By enabling faster switching frequencies and improved thermal management, the hybrid Si-SiC switch allows for smaller, lighter, and more efficient power inverters. Given the global shift towards sustainable energy solutions, the202500397
[0010] 2
[0011] development and commercialization of the hybrid Si-SiC switch represent a significant advancement in the field, positioning it as a vital component in next-generation inverter systems.
[0012] It has been found, however, that under certain circumstances, such as under high load conditions, losses in the wide band gap components, particularly in the SiC component, such as the MOSFET, can be considerable. High losses can result in high (junction) temperatures which may exceed maximal specified ratings of the component. Moreover, this high peak current might exceed the safe operating area (SOA) of SiC chips, potentially causing damage or failure. This may limit the lifetime of the component. It is possible to add further IGBTs and / or MOSFETs on the same device, such as the inverter, so as to limit the losses and maintain safe operating (junction) temperatures on each of the IGBTs or MOSFETs. However, this comes at the cost of increased size, weight, and / or production costs.
[0013] It is thus an object of the present invention, to propose a method for operating a hybrid Si-SiC switch that not only allows to use a minimal number of chips (Si, SiC) but also ensures a reduced level of losses and / or safe operation of SiC chips during operation of the switch, especially during high load conditions. It is further an object of the present invention to propose a hybrid Si-SiC switch which offers reduced loss levels, especially during high load conditions, at a comparably small packing size and / or cost-fingerprint, as well as an AC / DC inverter, a DC / DC converter including such a switch, and an onboard-charging unit including such an inverter and / or converter.
[0014] The above objects are solved by the subject-matters of the independent claims. Preferred embodiments are given in the dependent claims.
[0015] According to a first aspect of the present invention, a method for operating a hybrid switch including at least one silicon (Si) insulated-gate bipolar transistor (IGBT) and at least one silicon carbide (SiC) metal-oxide semiconductor field-effect transistor (MOSFET) arranged in parallel to one another is described. The method comprises the steps of: determining a turn-ON gate signal time t0N IGBTof the Si transistor,202500397
[0016] 3
[0017] determining a turn-ON gate signal time t0N MOSFET of the SiC transistor, determining a negative turn-ON gate signal delay time At between the Si transistor and the SiC transistor by subtracting the determined turn-ON gate signal time t0N lGBTof the Si transistor from the determined turn-ON gate signal time of t0N MOSFET the SiC transistor, At = t0NMOSFET ~ toN IBGT, and operating the hybrid switch with the determined negative turn-ON gate signal delay time At.
[0018] The present invention is based on the idea that the turn-ON gate signal time of IGBTs (Si chips) are larger than that of MOSFETs (SiC chips). In other words, the SiC chip has a faster response time compared to the Si chip when both receive the gate signal at the same time. The idea is that, e.g. in high-current applications and / or particularly only during high-current situations, the activation of the silicon (Si) chip is timed to occur earlier, enabling both the SiC and Si IGBT components to conduct current simultaneously. This coordinated approach enhances current handling capabilities and optimizes performance during critical switching events. By strategically timing the activation, this method mitigates the risks associated with exceeding rated values and ensures operation remains within the safe operating area.
[0019] Preferably, the step of determining the tum-ON gate signal time t0N IGBTof the Si transistor, and / or determining the turn-ON gate signal time t0N MOSFET of the SiC transistor, takes into account and / or is based on (amongst other parameters) parasitic capacitances between gate and drain, Cgd, and parasitic capacitances between gate and source, Cgs. The capacitances may be determined based on mathematical models, look-up tables, calculations other other means.
[0020] Preferably, the turn-ON gate signal time t0N lGBTof the Si transistor is determined based on at least one of a threshold voltage for the Si transistor, a gate voltage for the Si transistor, and a gate charging timeIGBTof the Si transistor, and / or the turn-ON gate signal time t0NMOSFET of the SiC transistor is determined based on at least one of a threshold voltage for the SiC transistor, a gate voltage for the SiC transistor, and a gate charging time T MOSFET of the SiC transistor.202500397
[0021] 4
[0022] Preferably, the gate charging time TIGBT, TMOSFETis determined based on T = RgCiss, wherein Rgis a gate resistance and Cissis an input capacitance of the respective transistor.
[0023] Preferably, the input capacitance Cissis determined based on Ciss= Cgd+ Cgs, wherein Cgdis indicative of parasitic capacitances between gate and drain, and Cgsis indicative of parasitic capacitances between gate and source.
[0024] According to another, or second aspect of the present invention, a hybrid switch is proposed. The switch comprises: at least one silicon (Si) insulated-gate bipolar transistors (IGBT or Si chip), at least one silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFET or SiC chip) arranged in parallel to the at least one silicon (Si) insulated-gate bipolar transistors (IGBTs), and a gate driver configured for switching the hybrid switch with a negative turn-ON gate signal delay time At, wherein the negative turn-ON gate signal delay time At is determined based on the method according to the preceding claims.
[0025] According to another, or third aspect of the present invention, an AC / DC inverter is proposed. The AC / DC inverter comprises: a hybrid switch according to the second aspect, preferably wherein the AC / DC converter is adapted for use in an onboard-charging unit of an electric vehicle.
[0026] According to another, or fourth aspect of the present invention, a DC / DC converter is proposed. The DC / DC converter comprises: a hybrid switch according to the second aspect, preferably wherein the DC / DC converter is adapted for use in a wallbox or in an onboard-charging unit of an electric vehicle.
[0027] According to another, or fifth aspect of the present invention, an onboard-charging unit comprising an inverter according to third aspect and / or a converter according to fourth aspect is proposed.202500397
[0028] 5
[0029] Embodiments of the first aspect may be applicable to embodiments of the second, third, fourth and / or fifth aspect, and vice versa.
[0030] Exemplary embodiments of the invention are described by the accompanying drawings, which are incorporated herein and constitute a part of the specification. In the drawings:
[0031] FIG 1 is a schematic drawing of a hybrid switch according to the present invention;
[0032] FIGs. 2A-B are schematic drawings of a gate signal and gate voltage, respectively, for operating the hybrid switch;
[0033] FIGs. 3A-B are schematic drawings of a gate signal and gate voltage, respectively, of one example of a proposed switching strategy for operating the hybrid switch;
[0034] FIG 4 is another schematic drawing showing one example of the proposed switching strategy;
[0035] FIG 5 is a schematic drawing of a SiC MOSFET with parasitic capacitances;
[0036] FIG 6 is a schematic drawing showing one example of a switching concept for operating the hybrid switch;
[0037] FIGs. 7A-B are schematic drawings of a current versus time plot without applying the switching concept (FIG 7A) and with applying the switching concept (FIG 7B);
[0038] FIGs. 8A-B are schematic drawings of an electric power versus time plot without applying the switching concept (FIG 8A) and with applying the switching concept (FIG 8B).
[0039] Within the figures, same reference numerals refer to the same components.202500397
[0040] 6
[0041] Figure 1 a schematic drawing of a hybrid switch 10. In the exemplary embodiment shown in FIG 1 the switch includes one Si chip (IGBT) and two SiC chips (MOSFET) arranged in parallel to one another. In other embodiments not shown, the switch 10 may include a different number of Si chips and / or SiC chips. A diode is used in the switch and arranged in parallel, as is known to a person skilled in the art for such a hybrid switch.
[0042] Figures 2A-B show schematic drawings of a gate signal (FIG 2A) and a gate voltage (FIG 2B). As can be seen, when both the silicon (Si) and silicon carbide (SiC) components (chips) are switched simultaneously (indicated by the arrow 12), the SiC switch operates at a faster switching speed than the Si switch and has to handle the full current for a brief period. This can be seen, for example, by a SiC peak voltage portion 14 which occurs during a ramp-up phase (turn on phase) of the Si switch. This disadvantage of share of current may be more prominent during high load conditions, such as during 720 A current conditions. This disadvantage of share of current may lead to premature failure of the MOSFET and / or may result in an temperature of the MOSFET that may exceed a predetermined (safe operating) temperature. Such a distribution of current may thus be avoided, particularly during high load conditions.
[0043] Figure 3 shows one example of a proposed operating or switching strategy for operating a hybrid switch, such as hybrid switch 10 of FIG 1. Figure 3A shows the gate signal and FIG 3B shows the gate voltage.
[0044] As already mentioned, the SiC chip has a faster response time compared to the Si chip when both receive the gate signal at the same time. It is therefore proposed, for example in high-current applications, that the activation of the silicon (Si) chip (Si-IGBT) is timed to occur earlier, indicated by arrow 12 as compared to arrow 13, enabling both the SiC and Si IGBT components to conduct current simultaneously. This coordinated approach enhances current handling capabilities and optimizes performance during critical switching events. By strategically timing the activation,202500397
[0045] 7
[0046] this method mitigates the risks associated with exceeding rated values and ensures operation remains within the safe operating area.
[0047] The delay time between the activation of the SiC and Si IGBT must be precisely calculated. A lengthy delay can lead to increased switching losses in the IGBT, negatively impacting overall efficiency. Conversely, if the delay time is too short, the SiC component may be required to handle excessively high peak currents, which could result in damage to the chip. Therefore, optimizing this delay is critical to ensure both reliable performance and longevity of the components
[0048] Figure 4 shows a schematic drawing illustrating the idea.
[0049] As can be seen in FIG 4, the SiC chip switches faster than the Si chip. The idea is to determine the turn-ON gate signal time of the Si chip (Si transistor), t0N IGBT, and the turn-ON gate signal time of the SiC chip (SiC transistor), t0N MOSFET - AS mentioned, the turn-ON gate signal time of the SiC transistor is shorter than that of the Si transistor, which is also indicated by the graph in FIG 4. The idea is to determine a negative turn-ON gate signal delay time At between the Si transistor and the SiC transistor by subtracting the determined turn-ON gate signal time t0 / v IGBTof the Si transistor from the determined tum-ON gate signal time of ^ON MOSFET the SiC transistor, At —
[0050]
[0051] MOSFET ^ON IBGT' AS the SiC transistor is quicker during switch on than the Si transistor, by subtracting the turn-ON gate signal time of the IGBT from that of the MOSFET, a negative tum-ON gate signal delay time is obtained. This is the time which is used to switch on the IGBT earlier compared to the MOSFET. The hybrid switch is then operated using this determined negative turn-ON gate signal delay time At.
[0052] To accurately define the switching delay time between SiC and Si IGBTs, it is essential to utilize the characteristic parameters of the chips. The turn-on times for both SiC and Si devices are specified as follows:
[0053] _ ] T Vn_M0SFET\
[0054] tOn_ MOSFET ~ ~T1 ’ In I 1 VZ I
[0055]
[0056] ' ■'GS '202500397
[0057] 8
[0058] _ ] ( -t VTII_IGBT\
[0059] ton_ IGBT ~ ~T2 ’lnI177 I
[0060]
[0061] \ 'GE '
[0062] In this context, VTh M0SFETand VTh [GBTrepresent the threshold voltages for the SiC MOSFET and the Si IGBT, respectively. Meanwhile,
[0063]
[0064] and VGEdenote the gate voltage signals for the SiC MOSFET and the Si IGBT, respectively. The parameter T refers to the gate charging time which is specific for IGBT and MOSFET.
[0065] The gate charging time may be determined as follows:
[0066]
[0067] RgCiss
[0068] In this context, Rgis a gate resistance and Cissis an input capacitance of the respective transistor.
[0069] The input capacitance, Ciss, is the combined effect of Cgdand Cgs, and may be determined as follows:
[0070] Q
[0071]
[0072] ss—Cgd T Cgs
[0073] In this context, Cgdrefers to the parasitic capacitance between the gate and drain, while Cgsdenotes the capacitance between the gate and source. Cgsmay be considered a constant. Cgdmay be considered to be nonlinear and may be calculated based on nonlinear equations.
[0074] It is important to note that the values for VTfl, VG, Cissand Rgpresented in the above equations may differ between the Si transistors (IGBTs) and the SiC transistors (MOSFETs). Typically, Cissis higher for Si transistors, resulting in longer turn-on times compared to SiC transistors. Additionally, Cissmay not be static or constant and / or may vary with voltage, which means that the turn-ON gate signal time for the transistors is influenced by different operating conditions.202500397
[0075] 9
[0076] As an example, FIG 5 shows a schematic drawing of a SiC MOSFET with various capacitances. A similar drawing may be obtained for a Si IGBT.
[0077] By utilizing above equations and values for the various parameters involved, one can calculate the required delay time, At, between the Si IGBT and the SiC MOSFET. Depending on the specific operating conditions, this delay time can be adjusted to achieve a balance between reliable operation and efficient switching performance.
[0078] Figure 6 shows one example of a switching concept for a hybrid switch, such as the one shown in FIG 1 , which is based on the above approach. As can be seen, the Si IGBT is switched on earlier as the SiC MOSFET. The turn-ON switching of the SiC MOSFET occurs quicker than that of the Si IGBT.
[0079] Figures 7A-B are schematic drawings of a current versus time plot for high-load conditions without applying the switching concept (FIG 7A) and with applying the switching concept (FIG 7B). In FIG 7A no delay was used (0 delay) and in FIG 7B a negative delay was used (-Ve delay), as explained above.
[0080] Figures 7A-B present a current sharing of the MOSFET and IGBT switches within the hybrid switch.
[0081] When the electric motor operates at high power, the current flowing through each phase becomes substantial. During switching events, the silicon carbide (SiC) component must handle the entire current as it switches faster than the silicon (Si) component.
[0082] Specifically, at higher current levels (see FIG 7A), the associated losses in the SiC increase, resulting in elevated temperatures. Additionally, the peak current can exceed the rated values, placing the operation outside the safe operating area (SOA). This condition poses significant risks to the reliability and longevity of the components involved.202500397
[0083] 10
[0084] With the proposed solution of negative turn-ON gate delay time (FIG 7B), however, the Si IGBT switches on earlier, effectively reducing the peak current in the SiC MOSFET and ensuring that it remains within a Safe Operating Area.
[0085] In FIG 7A the peak 16 of the SiC MOSFET current overlaps almost entirely with the total peak current. In FIG 7B, however, the peak 16 is considerably lower than the total peak current at the expense of the Si IGBT. In other words, in FIG 7B current is shared between the SiC MOSFET and the Si IGBT.
[0086] Figures 8A-B illustrate the loss distribution at a current level of 720A, comparing scenarios without (FIG 8A) and with (FIG 8B) the negative turn-ON gate delay time implemented in the proposed strategy. As shown, the incorporation of this strategy leads to a reduction in losses for the SiC MOSFET, resulting in lower thermal stress. This reduction in thermal stress allows for a decrease in the SiC area required in the hybrid switch design.
[0087] The proposed switching strategy effectively reduces the peak current and power dissipation in SiC chips / transitors without compromising the efficiency of the hybrid switch. This innovative approach minimizes thermal stress on the SiC component, allowing for a smaller chip area in the hybrid design, thereby enhancing overall performance and reliability.
Claims
20250039711Patent claims1. A method for operating a hybrid switch including at least one silicon (Si) insulated-gate bipolar transistor (IGBT) and at least one silicon carbide (SiC) metal-oxide semiconductor field-effect transistor (MOSFET) arranged in parallel to one another, the method comprising the steps of:determining a turn-ON gate signal time t0N lGBTof the Si transistor, determining a turn-ON gate signal time t0NMOSFET of th® SiC transistor, determining a negative turn-ON gate signal delay time At between the Si transistor and the SiC transistor by subtracting the determined turn-ON gate signal time t0N IGBTof the Si transistor from the determined turn-ON gate signal time of t0NMOSFET the SiC transistor, At = t0NMOSFET ~ toN ZBGT. which isthetime which is used to switch on the IGBT earlier compared to the MOSFET, andoperating the hybrid switch with the determined negative turn-ON gate signal delay time At.
2. The method of claim 1 , wherein the step ofdetermining the turn-ON gate signal time t0N IGBTof the Si transistor, and / or determining the turn-ON gate signal time t0NMOSFET °f the SiC transistor, takes into account parasitic capacitances between gate and drain, Cgd, and parasitic capacitances between gate and source, Cgs.
3. The method of claim 1 or 2, wherein:the turn-ON gate signal time t0N IGBTof the Si transistor is determined based on at least one of a threshold voltage for the Si transistor, a gate voltage for the Si transistor, and a gate charging timeIGBTof the Si transistor, and / orthe turn-ON gate signal time t0NMOSFET of the SiC transistor is determined based on at least one of a threshold voltage for the SiC transistor, a gate voltage for the SiC transistor, and a gate charging timeMOSFETof the SiC transistor.202500397124. The method of claim 3, wherein the gate charging time TIGBT, TMOSFET is determined based on T = RgCiss, wherein Rgis a gate resistance and Cissis an input capacitance of the respective transistor.
5. The method of claim 4, wherein the input capacitance Cissis determined based on Ciss= Cgd+ Cgs, wherein Cgdis indicative of parasitic capacitances between gate and drain, and Cgsis indicative of parasitic capacitances between gate and source.
6. A hybrid switch comprising:at least one silicon (Si) insulated-gate bipolar transistors (IGBT), at least one silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFET) arranged in parallel to the at least one silicon (Si) insulated-gate bipolar transistors (IGBTs), anda gate driver configured for switching the hybrid switch with a negative turn-ON gate signal delay time At, wherein the negative tum-ON gate signal delay time At is determined based on the method according to the preceding claims.
7. An AC / DC inverter comprising:a hybrid switch according to claim 6, preferably wherein the AC / DC converter is adapted for use in an onboard-charging unit of an electric vehicle.
8. A DC / DC converter comprising:a hybrid switch according to claim 6, preferably wherein the DC / DC converter is adapted for use in a wallbox or in an onboard-charging unit of an electric vehicle.
9. An onboard-charging unit comprising an inverter according to claim 7 and / or a converter according to claim 8.