Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device comprising micro-sized transistors. The semiconductor device comprises two vertical transistors (a first transistor and a second transistor) and a first insulating layer. The first transistor is an n-channel transistor, and the second transistor is a p-channel transistor. The first insulating layer is provided in a band shape so as to have a region sandwiched between a source electrode and a drain electrode of the first transistor and between a source electrode and a drain electrode of the second transistor. The first transistor and the second transistor are connected in series. A semiconductor layer of the first transistor has a region facing a first side surface of the first insulating layer. A semiconductor layer of the second transistor has a region facing a second side surface of the first insulating layer. The first side surface and the second side surface of the first insulating layer face each other.

Description

Semiconductor device and method for manufacturing semiconductor device

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, a display module, a memory device, and an electronic device. One embodiment of the present invention relates to a method for manufacturing a transistor and a method for manufacturing a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), an electronic device including any of the above, a driving method thereof, and a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, and means a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like), a device including the circuit, or the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of a semiconductor device. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device are themselves semiconductor devices, and in some cases, each includes a semiconductor device.

[0004] A semiconductor device including a transistor is widely applied to display devices, memory devices, electronic devices, and the like, and higher integration and higher speed of semiconductor devices are required. For example, when a semiconductor device is applied to a high-definition display device or a highly integrated memory device, miniaturization and higher integration of the semiconductor device are required. As one means for achieving this, development of small-size transistors is underway.

[0005] In addition, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. Such a transistor is widely applied to electronic devices such as integrated circuits (ICs: Integrated Circuits) and display devices. As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known; however, oxide semiconductors have attracted attention as other materials.

[0006] For example, oxide semiconductors applicable to transistors include indium oxide (also called indium oxide) and indium gallium zinc oxide. Non-patent documents 1 and 2 disclose thin-film transistors using indium oxide.

[0007] Transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU (Central Processing Unit) that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors.

[0008] Furthermore, by using a vertical structure for transistors, it is possible to increase the density of integrated circuits, improve the resolution of display devices, and narrow the bezels. For example, Patent Document 3 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered by a gate electrode via a gate insulating layer.

[0009] Furthermore, the circuit configurations of semiconductor devices applied to display devices, memory devices, etc., can be realized by combinations of various logic circuits such as AND circuits, OR circuits, NAND circuits, NOR circuits, and NOT circuits. Logic circuits are generally composed of a combination of n-channel transistors and p-channel transistors. For example, in NOT circuits, a CMOS (Complementary Metal Oxide Semiconductor) circuit, which consists of one n-channel transistor and one p-channel transistor connected in series, is frequently used due to its high degree of design flexibility.

[0010] On the other hand, to achieve narrow bezels for display devices, for example, drive circuits consisting of logic circuits made up of only n-channel transistors or only p-channel transistors are also being considered. Circuits with such a configuration are also called "unipolar circuits." For example, Patent Document 4 discloses a technique for constructing a shift register circuit as a unipolar circuit.

[0011] Japanese Patent Publication No. 2012-257187, Japanese Patent Publication No. 2011-151383, Japanese Patent Publication No. 2013-211537, Japanese Patent Publication No. 2002-049333

[0012] Dhananjay & Chu, C. W. Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 1-4 (2007). Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022)

[0013] One aspect of the present invention aims to provide a semiconductor device having a minutely sized transistor and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a miniature semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with a large on-current and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device with high integration density and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device and a method for manufacturing the same.

[0014] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0015] To further increase the integration of semiconductor devices, it is effective to miniaturize the transistors in the semiconductor device and to devise a better layout for those transistors.

[0016] One aspect of the present invention comprises a first conductive layer to a fourth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer to a fourth insulating layer, wherein the first conductive layer and the second conductive layer are located on the same plane, and the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer are provided in this order on the first conductive layer and the second conductive layer, respectively, with overlapping regions with the first conductive layer and the second conductive layer, the upper surface shapes of the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer are substantially the same, and the third insulating layer has an overlapping region with the first conductive layer. In the region, the semiconductor layer is in contact with the sides of the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer, and in the region where the fourth insulating layer overlaps with the second conductive layer, the semiconductor layer is in contact with the sides of the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer, and the semiconductor layer is in contact with the upper surface of the first conductive layer, the third insulating layer, and a part of the upper surface of the fourth conductive layer, and the semiconductor layer is in contact with the upper surface of the second conductive layer, the fourth insulating layer, and another part of the upper surface of the fourth conductive layer, and the semiconductor layer is an n-type semiconductor layer.

[0017] Furthermore, one aspect of the present invention includes a first conductive layer to a fourth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer to a fourth insulating layer, wherein the first insulating layer, the second conductive layer and the second insulating layer are provided in this order on the first conductive layer, with a region overlapping the first conductive layer, the upper surface shapes of the first insulating layer, the second conductive layer and the second insulating layer are substantially the same, the third conductive layer is located on the first region of the second insulating layer and the fourth conductive layer is located on the second region of the second insulating layer, and the third insulating layer is located on the first insulating layer, The semiconductor device is configured such that the second conductive layer, the second insulating layer, and the third conductive layer are in contact with the side surfaces where their respective edges are aligned, the fourth insulating layer is in contact with the side surfaces where the respective edges of the first insulating layer, the second conductive layer, the second insulating layer, and the fourth conductive layer are aligned, the first semiconductor layer is in contact with a portion of the upper surface of the first conductive layer, the third insulating layer, and the upper surface of the third conductive layer, and the second semiconductor layer is in contact with another portion of the upper surface of the first conductive layer, the fourth insulating layer, and the upper surface of the fourth conductive layer, the first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer.

[0018] Furthermore, one aspect of the present invention includes a first conductive layer to a fourth conductive layer, a first semiconductor layer and a second semiconductor layer, a first insulating layer and a second insulating layer, wherein the first conductive layer and the second conductive layer are located on the same plane, and the first insulating layer and the third conductive layer are provided in this order on the first conductive layer and the second conductive layer, respectively, having regions that overlap with the first conductive layer and the second conductive layer, the upper surface shapes of the first insulating layer and the third conductive layer are substantially the same, the third conductive layer has a first region to a third region on its upper surface, and the first semiconductor layer has the upper surface of the first conductive layer, the first insulating layer and The semiconductor device is configured such that the third conductive layer is in contact with the side surfaces and first regions of each of the three conductive layers on the first conductive layer side, the second semiconductor layer is in contact with the top surface of the second conductive layer, the first insulating layer, and the side surfaces and second regions of each of the third conductive layer on the second conductive layer side, the second insulating layer is in contact with the top and side surfaces of the first semiconductor layer, the top and side surfaces of the second semiconductor layer, the top surface of the first conductive layer, the top surface of the second conductive layer, and the third region, and the fourth conductive layer is located on the second insulating layer such that it has regions that overlap with the first and second semiconductor layers, the first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer.

[0019] Furthermore, one aspect of the present invention includes a first conductive layer to a fourth conductive layer, a first semiconductor layer and a second semiconductor layer, a first insulating layer and a second insulating layer, wherein the first insulating layer is provided on the first conductive layer such that it overlaps with the first conductive layer, the second conductive layer is located on the first region of the first insulating layer, and the third conductive layer is located on the second region of the first insulating layer, and the first semiconductor layer is in contact with a part of the upper surface of the first conductive layer, the side surface on which the respective ends of the first insulating layer and the second conductive layer are aligned, and the upper surface of the second conductive layer, and the second semiconductor layer is in contact with the first conductive layer The semiconductor device is a part of the upper surface of the semiconductor layer, the side surface on which the respective ends of the first insulating layer and the third conductive layer are aligned, and the upper surface of the third conductive layer. The second insulating layer is in contact with the upper and side surfaces of the first semiconductor layer, the upper and side surfaces of the second semiconductor layer, the upper surface of the first conductive layer, the upper and side surfaces of the second conductive layer, the upper and side surfaces of the third conductive layer, and the upper surface of the first insulating layer. The fourth conductive layer is located on the second insulating layer such that it has a region that overlaps with the first and second semiconductor layers. The first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer.

[0020] Furthermore, in the above, it is preferable that the first semiconductor layer has indium and oxygen, and the second semiconductor layer has tellurium, tin, or copper and oxygen.

[0021] Furthermore, in the above, it is preferable that the first semiconductor layer comprises silicon and either phosphorus or arsenic, and the second semiconductor layer comprises silicon and either boron, aluminum, or gallium.

[0022] Furthermore, in the above, it is preferable that the first semiconductor layer has indium and oxygen, and the second semiconductor layer has silicon and any of boron, aluminum, or gallium.

[0023] Furthermore, in the above, it is preferable that the first semiconductor layer comprises silicon and either phosphorus or arsenic, and the second semiconductor layer comprises either tellurium, tin, or copper and oxygen.

[0024] Furthermore, in the above, the first insulating layer comprises a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer; the second insulating layer comprises an eighth insulating layer, a ninth insulating layer on the eighth insulating layer, and a tenth insulating layer on the ninth insulating layer; the fifth insulating layer, the seventh insulating layer, the eighth insulating layer, and the tenth insulating layer each contain silicon and nitrogen; and the sixth insulating layer and the ninth insulating layer each contain silicon and oxygen.

[0025] Furthermore, in the above, it is preferable that the first insulating layer comprises an eleventh insulating layer, a twelfth insulating layer on the eleventh insulating layer, and a thirteenth insulating layer on the twelfth insulating layer, wherein the eleventh insulating layer and the thirteenth insulating layer each contain silicon and nitrogen, and the twelfth insulating layer contains silicon and oxygen.

[0026] Furthermore, in the above, it is preferable that the area of ​​the first semiconductor layer is larger than the area of ​​the second semiconductor layer when viewed in plan.

[0027] Furthermore, in the above, it is preferable that the area of ​​the second semiconductor layer is larger than the area of ​​the first semiconductor layer when viewed in plan.

[0028] Furthermore, in the above, it is preferable that a portion of the second semiconductor layer has a region that is in contact with the upper surface and side surface of a portion of the first semiconductor layer.

[0029] Furthermore, in the above, it is preferable that a portion of the first semiconductor layer has a region that is in contact with the upper surface and side surface of a portion of the second semiconductor layer.

[0030] Furthermore, in one aspect of the present invention, a first conductive layer and a second conductive layer are formed, a first insulating film, a second insulating film, and a second conductive film are formed on the first conductive layer and the second conductive layer in this order, a portion of the second conductive film, the second insulating film, the first conductive film, and the first insulating film is removed to form a third conductive layer, a first insulating layer, a fourth conductive layer, and a second insulating layer having regions that overlap with the first conductive layer and the second conductive layer, and having substantially the same upper surface shape, a third insulating film is formed in contact with the upper surface of the first conductive layer, the upper surface of the second conductive layer, the upper surface and side surface of the third conductive layer, the side surface of the fourth conductive layer, the side surface of the first insulating layer, and the side surface of the second insulating layer, a portion of the third insulating film is removed to form a third insulating film in contact with the side surface of the third conductive layer, the first insulating layer, the fourth conductive layer, and the second insulating layer on the first conductive layer side This is a method for manufacturing a semiconductor device, comprising: forming an insulating layer and a fourth insulating layer in contact with the side surfaces of the third conductive layer, the third insulating layer, the fourth conductive layer, and the second insulating layer on the second conductive layer side; forming a first semiconductor film in contact with the upper surface of the first conductive layer, the third insulating layer, the upper surface of the third conductive layer, the fourth insulating layer, and the upper surface of the second conductive layer; removing a portion of the first semiconductor film to form a first semiconductor layer in contact with a portion of the upper surface of the first conductive layer, the third insulating layer, and a portion of the upper surface of the third conductive layer; forming a second semiconductor film in contact with another portion of the upper surface of the first conductive layer, the upper surface and side of the first semiconductor layer, another portion of the upper surface of the third conductive layer, the fourth insulating layer, and the upper surface of the second conductive layer; and removing a portion of the second semiconductor film to form a second semiconductor layer in contact with a portion of the upper surface of the second conductive layer, the fourth insulating layer, and another portion of the upper surface of the third conductive layer.

[0031] Furthermore, in the above, it is preferable that the first semiconductor layer is an n-type semiconductor layer and the second semiconductor layer is a p-type semiconductor layer.

[0032] Furthermore, in the above, it is preferable that the first semiconductor layer is a p-type semiconductor layer and the second semiconductor layer is an n-type semiconductor layer.

[0033] According to one aspect of the present invention, a semiconductor device having a minutely sized transistor and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a miniature semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with a large on-current and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good electrical characteristics and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high integration density and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device and a method for manufacturing the same can be provided.

[0034] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0035] Figure 1A is a plan view showing an example of a semiconductor device. Figure 1B is a cross-sectional view showing an example of a semiconductor device. Figure 1C is a circuit diagram illustrating a semiconductor device. Figures 2A and 2B are perspective views showing an example of a semiconductor device. Figures 3A and 3B are perspective views showing an example of a semiconductor device. Figures 4A, 4B, 4C, and 4D are cross-sectional views showing an example of a semiconductor device. Figures 5A, 5B, 5C, and 5D are cross-sectional views showing an example of a semiconductor device. Figures 6A and 6B are plan views showing an example of a semiconductor device. Figures 7A and 7B are plan views showing an example of a semiconductor device. Figures 8A and 8B are cross-sectional views showing an example of a semiconductor device. Figures 9A and 9B are cross-sectional views showing an example of a semiconductor device. Figure 10A is a plan view showing an example of a semiconductor device. Figure 10B is a cross-sectional view showing an example of a semiconductor device. Figure 10C is a circuit diagram illustrating a semiconductor device. Figure 11A is a plan view showing an example of a semiconductor device. Figure 11B is a cross-sectional view showing an example of a semiconductor device. Figure 11C is a circuit diagram illustrating a semiconductor device. Figure 12A is a plan view showing an example of a semiconductor device. Figure 12B is a cross-sectional view showing an example of a semiconductor device. Figure 12C is a circuit diagram illustrating a semiconductor device. Figure 13A is a plan view showing an example of a semiconductor device manufacturing method. Figure 13B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 14A is a plan view showing an example of a semiconductor device manufacturing method. Figure 14B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 15A is a plan view showing an example of a semiconductor device manufacturing method. Figure 15B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 16A is a plan view showing an example of a semiconductor device manufacturing method. Figure 16B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 17A is a plan view showing an example of a semiconductor device manufacturing method. Figure 17B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 18A is a plan view showing an example of a semiconductor device manufacturing method. Figure 18B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 19A is a plan view showing an example of a semiconductor device manufacturing method. Figure 19B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 20A is a plan view showing an example of a semiconductor device manufacturing method.Figure 20B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 21A is a plan view showing an example of a semiconductor device manufacturing method. Figure 21B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 22A is an equivalent circuit diagram of a logic circuit. Figure 22B is a diagram showing the circuit symbol of a logic circuit. Figure 22C is a timing chart explaining the operation of a logic circuit. Figures 23A and 23D are equivalent circuit diagrams of logic circuits. Figures 23B, 23C, 23E, and 23F are diagrams showing the circuit symbols of logic circuits. Figure 24A is a diagram showing the circuit symbol of a buffer circuit. Figure 24B is a diagram showing an example of a buffer circuit configuration. Figure 24C is a timing chart explaining the operation of a buffer circuit. Figure 24D is a diagram showing an example of a ring oscillator configuration. Figure 24E is a diagram illustrating the oscillation of a ring oscillator. Figure 25A is an equivalent circuit diagram of a DFF circuit. Figure 25B is a diagram showing the circuit symbol of a DFF circuit. Figure 26A is a diagram showing an example of a shift register circuit configuration. Figure 26B is a timing chart illustrating the operation of a shift register circuit. Figure 27 is a block diagram showing an example configuration of a display device. Figures 28A and 28B are block diagrams showing an example configuration of a semiconductor device. Figure 28C is a circuit diagram showing an example configuration of a semiconductor device. Figures 29A, 29B, 29C, and 29D are circuit diagrams showing an example configuration of a semiconductor device. Figure 30 is a block diagram showing an example configuration of a semiconductor device. Figures 31A and 31B are diagrams showing an example circuit configuration of a memory device. Figures 32A and 32B are diagrams showing an example of an electronic component. Figures 33A, 33B, and 33C are diagrams showing an example of a large-scale computer. Figure 33D is a diagram showing an example of space equipment. Figure 33E is a diagram showing an example of a storage system applicable to a data center. Figures 34A, 34B, 34C, 34D, 34E, and 34F are diagrams showing an example of electronic equipment. Figures 35A, 35B, 35C, 35D, 35E, 35F, and 35G show examples of electronic devices. Figures 36A, 36B, 36C, 36D, 36E, and 36F show examples of electronic devices.

[0036] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0037] Furthermore, the ordinal numbers "first," "second," and "third" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Also, for example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0038] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0039] The positions, sizes, and extents of each component shown in the drawings may not represent their actual positions, sizes, and extents for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the drawings.

[0040] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0041] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0042] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, etc., depending on the situation.

[0043] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0044] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0045] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0046] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0047] In this specification, holes or electrons may be referred to as "carriers." For example, in the operation of a transistor, holes or electrons in the channel-forming region can function as carriers. More specifically, in the case of an n-channel transistor, electrons can function as carriers, and in the case of a p-channel transistor, holes can function as carriers. Therefore, when the term "carrier" is used in this specification or in descriptions of semiconductor layers that can function as channel-forming regions of transistors, it shall include both holes and electrons unless otherwise specified.

[0048] In this specification, a light-emitting device (also called a light-emitting element) has an EL (Electroluminescence) layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, the layers (also called functional layers) of the EL layer include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer).

[0049] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated. If the separated island-like layer has a shape that extends in a certain direction, the shape of the layer may be described using the word "strip-like" instead of "island-like." In this specification, "strip-like" can be said to be a type of "island-like."

[0050] In this specification, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0051] In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "top surface shapes are approximately matching."

[0052] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0053] Furthermore, in this specification, "approximately matching height" refers to a configuration in which the height from a reference surface (for example, a flat surface such as the substrate surface) is approximately equal in a cross-sectional view. For example, when a planarization treatment (typically chemical mechanical polishing (CMP) treatment) is performed, the treated surface will have approximately matching height. However, even after a planarization treatment, the height may not be exactly the same depending on the film material, but in this specification, this is also considered to be "approximately matching height".

[0054] (Embodiment 1) This embodiment describes a semiconductor device, a method for manufacturing a semiconductor device, and the like according to one aspect of the present invention.

[0055] One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, and a first insulating layer.

[0056] The first transistor and the second transistor share some components and are mounted adjacent to each other on the same plane. The first transistor is an n-channel transistor, and the second transistor is a p-channel transistor.

[0057] Both the first and second transistors are vertical transistors in which the source electrode and drain electrode are positioned at different heights relative to the substrate surface, and the drain current flows in the vertical direction. Therefore, they can be miniaturized and have a smaller footprint than planar transistors in which the source electrode and drain electrode are positioned on the same plane.

[0058] Furthermore, since vertical transistors occupy less area than planar transistors, a semiconductor device according to one aspect of the present invention can be miniaturized and highly integrated by having the first and second transistors of the above structure.

[0059] The first insulating layer is provided in a strip shape, having regions sandwiched between the source electrode and drain electrode of the first transistor, and between the source electrode and drain electrode of the second transistor.

[0060] Herein, in both the first and second transistors, the electrode located closer to the substrate surface will be referred to as "one of the source electrodes or drain electrodes," and the electrode located further away from the substrate surface will be referred to as "the other of the source electrode or drain electrode."

[0061] The first transistor and the second transistor share a conductive layer that functions as either one of their source electrodes or drain electrodes, or the other of their source or drain electrodes. Furthermore, the first transistor and the second transistor share a conductive layer that functions as their gate electrode. In other words, the first transistor and the second transistor are connected in series.

[0062] The semiconductor layer that functions as the channel formation region of the first transistor (the first semiconductor layer) is provided such that it has a region facing the first side surface of the strip-shaped first insulating layer. The semiconductor layer that functions as the channel formation region of the second transistor (the second semiconductor layer) is provided such that it has a region facing the second side surface of the strip-shaped first insulating layer. Note that the first side surface and the second side surface of the first insulating layer are facing each other.

[0063] The gate electrodes of the first and second transistors can be configured to be located inside the first insulating layer, or they can be located on the first and second semiconductor layers, respectively.

[0064] As mentioned above, the first transistor is an n-channel type transistor, and the second transistor is a p-channel type transistor. Therefore, it can be said that a semiconductor device according to one aspect of the present invention has the same configuration as a CMOS circuit.

[0065] For example, silicon materials can be used as the first semiconductor layer (n-type semiconductor layer) and the second semiconductor layer (p-type semiconductor layer). For instance, an n-type silicon film doped with phosphorus or the like can be used as the first semiconductor layer, and a p-type silicon film doped with boron or the like can be used as the second semiconductor layer.

[0066] Alternatively, oxide semiconductor materials can be used as the first semiconductor layer (n-type semiconductor layer) and the second semiconductor layer (p-type semiconductor layer), respectively. For example, an n-type oxide semiconductor film such as indium oxide or indium gallium zinc oxide can be used as the first semiconductor layer, and a p-type oxide semiconductor film such as tellurium oxide, tin oxide, or copper oxide can be used as the second semiconductor layer.

[0067] Alternatively, for example, the first semiconductor layer (n-type semiconductor layer) can be made using the aforementioned n-type silicon material, and the second semiconductor layer (p-type semiconductor layer) can be made using the aforementioned p-type oxide semiconductor material.

[0068] Alternatively, for example, the first semiconductor layer (n-type semiconductor layer) can be made using the aforementioned n-type oxide semiconductor material, and the second semiconductor layer (p-type semiconductor layer) can be made using the aforementioned p-type silicon material.

[0069] Thus, in one embodiment of the present invention, the semiconductor device offers a wide range of choices for the combination of semiconductor materials that can be used for the first semiconductor layer (n-type semiconductor layer) and the second semiconductor layer (p-type semiconductor layer). Therefore, compared to, for example, the case of configuring a semiconductor device with the aforementioned "unipolar circuit," it becomes possible to select appropriate semiconductor materials according to the required performance, manufacturing conditions, etc., thereby increasing the design and manufacturing freedom of the semiconductor device.

[0070] Furthermore, as described above, in one aspect of the present invention, vertical transistors can be applied to both the first transistor and the second transistor in the semiconductor device. Therefore, the semiconductor device according to one aspect of the present invention can be an extremely compact, highly integrated, and highly design- and manufacturing-free semiconductor device.

[0071] A semiconductor device according to one aspect of the present invention can be applied to various technical fields. For example, a semiconductor device according to one aspect of the present invention can be applied to the drive circuit of a display device. This makes it possible to realize a display device with an extremely narrow bezel. Also, for example, a semiconductor device according to one aspect of the present invention can be applied to a storage device. This makes it possible to realize a storage device with an extremely high degree of integration. Furthermore, it makes it possible to realize a storage device with an extremely long data retention time and low power consumption.

[0072] In the following section, a specific example of the configuration of a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0073] <Example of Semiconductor Device Configuration 1> Figure 1A shows a plan view (also called a top view) of the semiconductor device 100A. Figure 1B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 1A. Figure 1C shows an equivalent circuit diagram of the semiconductor device 100A. Note that in Figure 1A, some components of the semiconductor device 100A (such as the insulating layer) are omitted. In subsequent drawings of semiconductor devices, some components may also be omitted in plan views, similar to Figure 1A.

[0074] The semiconductor device 100A is provided on a substrate 102. Although not shown in Figure 1B, etc., an insulating layer that functions as an underlay can also be provided between the substrate 102 and the semiconductor device 100A. The semiconductor device 100A includes a transistor 10An, a transistor 10Ap, an insulating layer 110_1, an insulating layer 110_2, and an insulating layer 195.

[0075] In Figure 1B, etc., the insulating layer 110_1 is shown to have a laminated structure consisting of insulating layer 110a1, insulating layer 110b1 on insulating layer 110a1, and insulating layer 110c1 on insulating layer 110b1. The insulating layer 110_2 is shown to have a laminated structure consisting of insulating layer 110a2, insulating layer 110b2 on insulating layer 110a2, and insulating layer 110c2 on insulating layer 110b2.

[0076] Transistors 10An and 10Ap are mounted on the same plane. Transistors 10An and 10Ap are mounted adjacent to each other. Transistors 10An and 10Ap share some components.

[0077] The transistor 10An has a conductive layer 104, an insulating layer 106n, a semiconductor layer 108n, a conductive layer 112an, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode. The insulating layer 106n functions as a gate insulating layer. The conductive layer 112an functions as either a source electrode or a drain electrode. The conductive layer 112b functions as either a source electrode or a drain electrode. Of the semiconductor layer 108n, the entire region that overlaps with the gate electrode via the gate insulating layer, between the region in contact with the source electrode and the region in contact with the drain electrode, functions as a channel forming region. Furthermore, of the semiconductor layer 108n, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region.

[0078] The above description relating to transistor 10An can be applied to transistor 10Ap by replacing the insulating layer 106n, semiconductor layer 108n, and conductive layer 112an with the insulating layer 106p, semiconductor layer 108p, and conductive layer 112ap, respectively.

[0079] In other words, the conductive layer 112b functions as the other source electrode or drain electrode of transistor 10An, and also functions as the other source electrode or drain electrode of transistor 10Ap. The conductive layer 104 functions as the gate electrode of transistor 10An, and also functions as the gate electrode of transistor 10Ap. Therefore, it can be said that transistor 10An and transistor 10Ap are connected in series with each other.

[0080] Furthermore, in one embodiment of the present invention, an n-type semiconductor material can be used for the semiconductor layer 108n, and a p-type semiconductor material can be used for the semiconductor layer 108p. Therefore, in the semiconductor device 100A, transistor 10An can function as an n-channel type transistor, and transistor 10Ap can function as a p-channel type transistor.

[0081] Therefore, as shown in Figure 1C, the semiconductor device 100A has a configuration in which an n-channel transistor 10An and a p-channel transistor 10Ap are connected in series with each other. As a result, the semiconductor device 100A can function as a CMOS circuit.

[0082] An insulating layer 195 is provided on transistors 10An and 10Ap so as to cover them.

[0083] Figure 2A shows a perspective view of the semiconductor device 100A with some components (insulating layer 195) omitted. Figure 2B shows a perspective view of the same device as in Figure 2A, with semiconductor layers 108n and 108p omitted. Figure 3A shows a perspective view of the same device as in Figure 2B, with insulating layers 106n and 106p omitted. Figure 3B shows a perspective view of the same device as in Figure 3A, with insulating layer 110_1, conductive layer 104, and insulating layer 110_2 omitted.

[0084] In Figure 2A, etc., insulating layer 110_1 is shown as a single layer without distinguishing between insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1, and insulating layer 110_2 is shown as a single layer without distinguishing between insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2.

[0085] The detailed configuration of the semiconductor device 100A will be described below.

[0086] Conductive layers 112an and 112ap are provided on different regions of the substrate 102. Figure 1A and others show an example in which conductive layer 112an extends toward A1 in the X direction, and conductive layer 112ap extends toward A2 in the X direction.

[0087] An insulating layer 110_1 is provided on the conductive layer 112an, on the conductive layer 112ap, and on the substrate 102. The insulating layer 110_1 is provided such that it has a region that overlaps with the upper end of the conductive layer 112an on the conductive layer 112ap side, and the upper end of the conductive layer 112ap on the conductive layer 112an side. A conductive layer 104 is provided on the insulating layer 110_1. An insulating layer 110_2 is provided on the conductive layer 104. A conductive layer 112b is provided on the insulating layer 110_2.

[0088] The insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b are arranged in a strip shape so as to have regions that overlap with conductive layer 112an and conductive layer 112ap, respectively. The strip-shaped structure composed of insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b can be said to be arranged so as to straddle conductive layer 112an and conductive layer 112ap in a plan view. The upper surface shapes of insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b are roughly the same. Therefore, the sides of insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b on the conductive layer 112an side are aligned. Furthermore, the sides of the insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b on the conductive layer 112ap side are aligned. Figure 3A and others show an example in which a strip-shaped structure composed of insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b is provided extending in the Y direction.

[0089] An insulating layer 106n is provided in contact with a portion of the upper surface of the conductive layer 112an, and with the sides of the insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b on the conductive layer 112an side. The upper end of the insulating layer 106n has a curved shape. In addition, an insulating layer 106p is provided in contact with a portion of the upper surface of the conductive layer 112ap, and with the sides of the insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b on the conductive layer 112ap side. The upper end of the insulating layer 106p has a curved shape. In the following, the area near the upper end of the insulating layer 106 (the portion where the surface of the insulating layer 106 has a curved shape in the cross-sectional view shown in Figure 1B, etc.) may be referred to as the curved portion.

[0090] A semiconductor layer 108n is provided in contact with the upper surface of the conductive layer 112an, the surface of the insulating layer 106n (including the curved portion), and a part of the upper surface of the conductive layer 112b. A semiconductor layer 108p is also provided in contact with the upper surface of the conductive layer 112ap, the surface of the insulating layer 106p (including the curved portion), and another part of the upper surface of the conductive layer 112b.

[0091] The semiconductor layer 108n has regions that, via the insulating layer 106n, face the sides of the insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b on the conductive layer 112an side. The semiconductor layer 108p also has regions that, via the insulating layer 106p, face the sides of the insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b on the conductive layer 112ap side.

[0092] As described above, the conductive layer 104 functions as the gate electrode of both transistor 10An and transistor 10Ap. Therefore, it can be said that the semiconductor device 100A has a configuration in which the gate electrode of the transistor is sandwiched between the insulating layer 110_1 and the insulating layer 110_2. Furthermore, it can be said that the laminated structure of the insulating layer 110_1, the conductive layer 104, and the insulating layer 110_2 has a configuration in which it is sandwiched between the source electrode and the drain electrode of the transistor. Therefore, it can also be said that the semiconductor device 100A has a configuration in which the gate electrode of the transistor is provided inside a single insulating layer (an insulating layer formed by the combination of insulating layer 110_1 and insulating layer 110_2) sandwiched between the source electrode and the drain electrode.

[0093] An n-type semiconductor material can be used for the semiconductor layer 108n. For example, an n-type silicon film doped with phosphorus or the like can be used as the semiconductor layer 108n. Alternatively, an n-type oxide semiconductor film such as indium oxide or indium gallium zinc oxide can be used as the semiconductor layer 108n.

[0094] A p-type semiconductor material can be used for the semiconductor layer 108p. For example, a p-type silicon film doped with boron or the like can be used as the semiconductor layer 108p. Alternatively, a p-type oxide semiconductor film such as tellurium oxide, tin oxide, or copper oxide can be used as the semiconductor layer 108p.

[0095] Note that in Figure 1B, etc., semiconductor layer 108n and semiconductor layer 108p are shown with the same film thickness, but this is not always the case. When the film thickness of semiconductor layer 108n and semiconductor layer 108p is the same, differences in the materials used for semiconductor layer 108n and semiconductor layer 108p, or differences in Hall mobility, may result in significant differences in the magnitude of the on-current of transistor 10An and transistor 10Ap. In such cases, the film thickness of semiconductor layer 108n and the film thickness of semiconductor layer 108p can be made different from each other, depending on the magnitude of the on-current required for transistor 10An and transistor 10Ap, respectively.

[0096] An insulating layer 195 is provided on the semiconductor layer 108n, the semiconductor layer 108p, the conductive layer 112an, the conductive layer 112ap, the conductive layer 112b, and the substrate 102 so as to cover them. The insulating layer 195 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108n, the upper and side surfaces of the semiconductor layer 108p, the upper and side surfaces of the conductive layer 112an, the upper and side surfaces of the conductive layer 112ap, the upper surface of the conductive layer 112b, the surface of the insulating layer 106n (including the curved portion), the surface of the insulating layer 106p (including the curved portion), and the upper surface of the substrate 102, respectively. The insulating layer 195 functions as a protective layer for transistors 10An and 10Ap.

[0097] Here, it is preferable that the insulating layer 106n and the insulating layer 106p are insulating layers containing oxygen. Furthermore, it is preferable that they are insulating layers that release oxygen upon heating. This allows, for example, when metal oxides are used for the semiconductor layer 108n and the semiconductor layer 108p, to supply oxygen from the insulating layers 106n and 106p to the metal oxide. This allows for the repair of oxygen deficiencies in the metal oxide, thereby improving the electrical characteristics and reliability of transistors 10An and 10Ap.

[0098] Furthermore, of the insulating layers 110_1, insulating layer 110b1 is preferably an insulating layer containing oxygen. It is also preferable that it is an insulating layer that releases oxygen upon heating. Similarly, of the insulating layers 110_2, insulating layer 110b2 is preferably an insulating layer containing oxygen. It is also preferable that it is an insulating layer that releases oxygen upon heating. This allows, for example, when metal oxides are used for semiconductor layer 108n and semiconductor layer 108p, the oxygen contained in insulating layer 110b1 and insulating layer 110b2 to be supplied to the metal oxide via insulating layer 106n or insulating layer 106p.

[0099] In contrast, it is preferable that insulating layers 110a1 and 110c1 of insulating layer 110_1 are insulating layers that have barrier properties against gases such as oxygen and hydrogen. Similarly, it is preferable that insulating layers 110a2 and 110c2 of insulating layer 110_2 are insulating layers that have barrier properties against gases such as oxygen and hydrogen. This makes it possible to suppress the release of oxygen contained in insulating layer 110b1 to the outside through insulating layer 110a1 or insulating layer 110c1. Similarly, it is possible to suppress the release of oxygen contained in insulating layer 110b2 to the outside through insulating layer 110a2 or insulating layer 110c2.

[0100] In this specification, "barrier properties" refer to the function of suppressing the diffusion of the corresponding substance (also known as low permeability), or the function of capturing or fixing the corresponding substance (also known as gettering). Furthermore, in this specification, "barrier film" refers to a film that possesses barrier properties.

[0101] Furthermore, it is possible to suppress the diffusion of hydrogen from outside the insulating layer 110_1 into the insulating layer 110b1 via the insulating layer 110a1 or insulating layer 110c1, and the diffusion of said hydrogen into the semiconductor layer 108n and semiconductor layer 108p. Similarly, it is possible to suppress the diffusion of hydrogen from outside the insulating layer 110_2 into the insulating layer 110b2 via the insulating layer 110a2 or insulating layer 110c2, and the diffusion of said hydrogen into the semiconductor layer 108n and semiconductor layer 108p. For example, when metal oxides are used for each of the semiconductor layer 108n and semiconductor layer 108p, hydrogen in the semiconductor layer 108n can be a factor that degrades the electrical characteristics and reliability of transistor 10An. Also, hydrogen in the semiconductor layer 108p can be a factor that degrades the electrical characteristics and reliability of transistor 10Ap.

[0102] For example, when hydrogen diffuses into semiconductor layer 108n and semiconductor layer 108p, the hydrogen contained in semiconductor layer 108n and semiconductor layer 108p reacts with oxygen bonded to metal atoms to form water, creating oxygen vacancies (V) in semiconductor layer 108n and semiconductor layer 108p. ＯIn some cases, an oxygen vacancy may be formed. Furthermore, a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V) may form. Ｏ Hydrogen (denoted as H) functions as a donor, and electrons, which are carriers, may be generated. Therefore, if hydrogen diffuses into semiconductor layer 108n and semiconductor layer 108p, the threshold voltage of transistors 10An and 10Ap may fluctuate, and reliability may deteriorate. Accordingly, by having insulating layer 110_1 have insulating layer 110a1 and insulating layer 110c1, and insulating layer 110_2 have insulating layer 110a2 and insulating layer 110c2, the above-mentioned problems in transistors 10An and 10Ap can be suppressed.

[0103] In transistors 10An and 10Ap, the source electrode and drain electrode are positioned at different heights relative to the surface of the substrate 102, which is the surface to be formed, and the drain current flows perpendicular or approximately perpendicular to the surface of the substrate 102. In other words, in each of transistors 10An and 10Ap, the drain current can be said to flow in the vertical direction. Therefore, a transistor according to one aspect of the present invention can be called a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).

[0104] Since both transistor 10An and transistor 10Ap can have their source and drain electrodes stacked, they can be miniaturized compared to so-called planar transistors, which have their source and drain electrodes arranged on the same plane. Furthermore, because vertical transistors occupy a smaller area than planar transistors, having both transistor 10An and transistor 10Ap be vertical transistors allows for miniaturization and high integration of the entire semiconductor device 100A.

[0105] For example, by using the semiconductor device 100A according to one aspect of the present invention in the drive circuit of a display device, an extremely narrow-bezel display device can be realized. Also, for example, by using the semiconductor device 100A according to one aspect of the present invention in a storage device, an extremely highly integrated storage device can be realized.

[0106] The channel length and channel width of transistor 10An will be described below. Note that the information described below can also be applied to transistor 10Ap, which is also a vertical transistor, by appropriately substituting the symbols indicating the components of transistor 10An.

[0107] In the semiconductor layer 108n, the region in contact with the conductive layer 112an functions as either a source region or a drain region, the region in contact with the conductive layer 112b functions as either a source region or a drain region, and the region between the source region and the drain region functions as a channel-forming region.

[0108] In Figure 1B, the channel length L10An of transistor 10An is indicated by a dashed double arrow. In Figure 1B, the distance between the region of semiconductor layer 108n that is in contact with conductive layer 112an and the region that is in contact with conductive layer 112b (the distance along the surface of insulating layer 106n, including the curved portion) is shown as the channel length L10An of transistor 10An.

[0109] In addition, the channel length L10An of transistor 10An may be the length of the region of semiconductor layer 108n facing the conductive layer 104 in the cross-sectional view shown in Figure 1B. Alternatively, the channel length L10An of transistor 10An may be the sum of the thicknesses of insulating layer 110_1, conductive layer 104, and insulating layer 110_2 in the region sandwiched between the upper surface of conductive layer 112an and the lower surface of conductive layer 112b. Alternatively, the channel length L10An of transistor 10An may be the sum of the thicknesses of insulating layer 110_1, conductive layer 104, and insulating layer 110_2 in the aforementioned region and the thickness of conductive layer 112b. Alternatively, the channel length L10An of transistor 10An may be the height of insulating layer 106n (the distance between the upper and lower ends of insulating layer 106n in a direction perpendicular to the substrate surface).

[0110] Here, the channel length L10An of transistor 10An is determined by the thickness of insulating layer 110_1, the thickness of conductive layer 104, the thickness of insulating layer 110_2, the angle θ110 between the formed surface of insulating layer 106n (here, the side surface of insulating layer 110_1, the side surface of conductive layer 104, the side surface of insulating layer 110_2, and the side surface of conductive layer 112b) and the formed surface of insulating layer 110a1 (here, the upper surface of conductive layer 112an), etc., and is not affected by the performance of the exposure apparatus used to manufacture the transistor. Therefore, the channel length can be set to a value smaller than the limiting resolution of the exposure apparatus, and a transistor of a very small size can be realized.

[0111] The channel length L10An can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L10An can also be 100 nm or more and 1 μm or less. By shortening the channel length L10An, the on-current of transistor 10An can be increased.

[0112] The thickness of insulating layer 110_1 and insulating layer 110_2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0113] The angle θ110 can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less. The angle θ110 can also be 90 degrees. A smaller angle θ110 is preferable because it improves the coverage of the layer (in this case, the semiconductor layer 108n, etc.) formed along the surface (including the curved portion) of the insulating layer 106n. On the other hand, a value closer to 90 degrees is preferable because it reduces the area occupied by the transistor 10An on the substrate surface.

[0114] The channel width of transistor 10An is the length of the region where the channel formation area in the semiconductor layer 108n and the conductive layer 104 overlap in a plan view. In Figure 1A, the channel width W10An of transistor 10An is shown by a double-headed arrow.

[0115] When forming the semiconductor layer 108n and the conductive layer 104 using lithography, the channel width W10An is greater than or equal to the limiting resolution of the exposure apparatus. The channel width W10An can be, for example, 20 nm or more and less than 500 μm, 50 nm or more and 200 μm or less, 100 nm or more and 100 μm or less, 200 nm or more and 50 μm or less, 500 nm or more and 20 μm or less, 1 μm or more and 10 μm or less, or 1 μm or more and 5 μm or less.

[0116] Figure 4A is an enlarged view of the region 151 shown in Figure 1B. Figure 4A shows a configuration in which the height of the upper end of the insulating layer 106n matches or approximately matches the height of the upper surface of the conductive layer 112b (the configuration shown in Figure 1B, etc.). In this configuration, no step is formed between the upper end of the insulating layer 106n and the side surface of the conductive layer 112b. Therefore, compared to a configuration with such a step, the coverage of the semiconductor layer 108n, which is provided in contact with the surface of the insulating layer 106n (including the curved portion) and the upper surface of the conductive layer 112b, can be improved.

[0117] In transistor 10An, the height of the upper end of the insulating layer 106n is not limited to a configuration that matches or approximately matches the height of the upper surface of the conductive layer 112b, as shown in Figure 1B, etc. The configurations shown in Figures 4B to 4D are examples of configurations in which the height of the upper end of the insulating layer 106n differs from that in Figure 4A.

[0118] Figure 4B shows a configuration in which the height of the upper end of the insulating layer 106n is lower than the height of the upper surface of the conductive layer 112b, and higher than the height of the upper surface of the insulating layer 110c2 located below the conductive layer 112b. In the configuration shown in Figure 4B, the side surface of the conductive layer 112b has a region that is in contact with the semiconductor layer 108n. When the semiconductor layer 108n is in contact with the side surface of the conductive layer 112b, the contact area between the semiconductor layer 108n and the conductive layer 112b is increased, and the contact resistance between the semiconductor layer 108n and the conductive layer 112b may be reduced.

[0119] Figure 4C shows a configuration in which the height of the upper end of the insulating layer 106n is lower than the height of the upper surface of the insulating layer 110c2. In the configuration shown in Figure 4C, the side surface of the conductive layer 112b has a region in contact with the semiconductor layer 108n, and the side surface of the insulating layer 110c2 has a region in contact with the semiconductor layer 108n. In this configuration, since the semiconductor layer 108n is in contact with the entire side surface of the conductive layer 112b, the contact resistance between the semiconductor layer 108n and the conductive layer 112b may be reduced compared to the configuration shown in Figure 4B.

[0120] Figure 4D shows a configuration in which the height of the upper end of the insulating layer 106n is lower than the height of the upper surface of the insulating layer 110b2. In the configuration shown in Figure 4D, the side surface of the conductive layer 112b has a region in contact with the semiconductor layer 108n, the side surface of the insulating layer 110c2 has a region in contact with the semiconductor layer 108n, and the side surface of the insulating layer 110b2 has a region in contact with the semiconductor layer 108n. In this configuration, it is possible to obtain effects similar to those obtained in the configuration shown in Figure 4C described above.

[0121] During etching for the formation of the insulating layer 106n, the height of the insulating layer 106n (the distance between the upper and lower ends of the insulating layer 106n in a direction perpendicular to the substrate surface) can sometimes be reduced by increasing the etching time. When the etching time is increased, the height of the upper end of the insulating layer 106n may become lower than the height of the upper surface of the conductive layer 112b. Preferably, the height of the upper end of the insulating layer 106n is at least higher than the height of the upper surface of the conductive layer 104. That is, it is preferable that the insulating layer 106n faces the entire side surface of the conductive layer 104. As described above, the insulating layer 106n is an insulating layer that functions as a gate insulating layer for the transistor 10An. Therefore, by having a region of the insulating layer 106n that faces the entire side surface of the conductive layer 104, the entire region of the semiconductor layer 108n that faces the conductive layer 104 via the insulating layer 106n can be made to function as a channel formation region.

[0122] Figure 5A is an enlarged view of the region 153 shown in Figure 1B. Figure 5A shows a configuration (as shown in Figure 1B, etc.) in which a single-layer insulating layer 106n is provided in contact with a part of the upper surface of the conductive layer 112an, the side surface of the insulating layer 110a1, the side surface of the insulating layer 110b1, the side surface of the insulating layer 110c1, the side surface of the conductive layer 104, the side surface of the insulating layer 110a2, the side surface of the insulating layer 110b2, the side surface of the insulating layer 110c2, and the side surface of the conductive layer 112b. In this configuration, as described above, the oxygen contained in the insulating layer 106n can be supplied to the semiconductor layer 108n (mainly the channel formation region). In addition, the oxygen contained in the insulating layer 110b1 and the insulating layer 110b2 can be supplied to the semiconductor layer 108n via the insulating layer 106n.

[0123] In transistor 10An, the configuration of the insulating layer 106n, which functions as a gate insulating layer, and the conductive layer 104, which functions as a gate electrode, is not limited to the configuration shown in Figure 1B, etc. The configurations shown in Figures 5B to 5D are examples in which the configuration of the insulating layer 106n, conductive layer 104, etc. differs from that of Figure 5A.

[0124] Figure 5B shows a configuration in which the surface of the conductive layer 104 is covered with an insulating layer 118, and there are no insulating layers 110c1 and 110a2. In the configuration shown in Figure 5B, the insulating layer 106n and the conductive layer 104 face each other via the insulating layer 118. Also, the insulating layer 110b1 and the conductive layer 104 are laminated with the insulating layer 118 in between. Furthermore, the conductive layer 104 and the insulating layer 110b2 are laminated with the insulating layer 118 in between.

[0125] The insulating layer 118 has, for example, an oxide of an element present in the conductive layer 104. If the conductive layer 104 is a metal, for example, the insulating layer 118 is an oxide of that metal. If the conductive layer 104 is silicon, for example, the insulating layer 118 is silicon oxide. As the insulating layer 118, for example, a metal oxide such as aluminum oxide or tantalum oxide can be used, and the use of aluminum oxide is particularly preferred.

[0126] Furthermore, the insulating layer 118 can function as a gate insulating layer for transistor 10An. In the configuration shown in Figure 5B, for example, the laminated structure of insulating layer 106n sandwiched between semiconductor layer 108n and conductive layer 104 and insulating layer 118 functions as a gate insulating layer for transistor 10An.

[0127] The insulating layer 118 can be formed self-aligned by using a conductive material that is easily oxidized for the conductive layer 104. For example, when aluminum is used for the conductive layer 104, the insulating layer 118 (in this case, aluminum oxide) can be formed on the surface of the conductive layer 104 by oxidizing the surface of the conductive layer 104 with oxygen supplied from the insulating layers 110b1, 110b2, and 106n, which are in contact with the conductive layer 104.

[0128] In the configuration shown in Figure 5B, the formation of insulating layers 110c1 and 110a2 is unnecessary, thus reducing the number of steps involved in the manufacturing of the semiconductor device compared to the configuration shown in Figure 5A.

[0129] Figure 5C shows a configuration in which the side edge of the insulating layer 110a1 protrudes outward from the side edge of the upper layers (insulating layer 110b1, insulating layer 110c1, conductive layer 104, insulating layer 110a2, insulating layer 110b2, insulating layer 110c2, and conductive layer 112b) of the insulating layer 110a1, and the upper surface of the protruding side edge of the insulating layer 110a1 is in contact with the lower edge of the insulating layer 106n. In the configuration shown in Figure 5C, unlike the configuration shown in Figure 5A, the lower edge of the insulating layer 106n is not in contact with the upper surface of the conductive layer 112an. Therefore, it is possible to suppress the oxidation of the conductive layer 112an by the oxygen contained in the insulating layer 106n, which would increase the electrical resistance of the conductive layer 112an. For this reason, the configuration shown in Figure 5C allows for a wider range of material selection that can be used for the conductive layer 112an than the configuration shown in Figure 5A.

[0130] Figure 5D shows a configuration in which the insulating layer 106n has a laminated structure consisting of insulating layer 106n1 and insulating layer 106n2 on insulating layer 106n1. In the configuration shown in Figure 5D, the insulating layer 106n1 is provided in contact with the upper surface of conductive layer 112an, the side surface of insulating layer 110a1, the side surface of insulating layer 110b1, the side surface of insulating layer 110c1, the side surface of conductive layer 104, the side surface of insulating layer 110a2, the side surface of insulating layer 110b2, the side surface of insulating layer 110c2, and the side surface of conductive layer 112b. The insulating layer 106n2 is provided so as to face, via the insulating layer 106n1, the upper surface of the conductive layer 112an, the side surface of the insulating layer 110a1, the side surface of the insulating layer 110b1, the side surface of the insulating layer 110c1, the side surface of the conductive layer 104, the side surface of the insulating layer 110a2, the side surface of the insulating layer 110b2, the side surface of the insulating layer 110c2, and the side surface of the conductive layer 112b.

[0131] It is preferable to use a material that does not easily permeate oxygen for the insulating layer 106n1. For example, the insulating layer 106n1 can be made from materials that can be used for insulating layers 110a1, 110c1, 110a2, and 110c2, respectively.

[0132] It is preferable to use a material for the insulating layer 106n2 that contains oxygen and releases oxygen upon heating. For example, the insulating layer 106n2 can be made from materials that can be used for insulating layer 110b1 and insulating layer 110b2, respectively.

[0133] In the configuration shown in Figure 5D, of the insulating layers 106n (insulating layers 106n1 and 106n2) that function as gate insulating layers for transistor 10An, insulating layer 106n2 has the function of supplying oxygen to semiconductor layer 108n, and insulating layer 106n1 has the function of suppressing the diffusion of oxygen from insulating layer 106n2 to conductive layer 112an, conductive layer 112b, and conductive layer 104, respectively. Therefore, even if materials that release oxygen are not used for insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2), oxygen can be supplied to semiconductor layer 108n by oxygen release from insulating layer 106n2. Furthermore, by providing an insulating layer 106n1 below the insulating layer 106n2, oxygen released from the insulating layer 106n2 diffuses into the conductive layer 112an, conductive layer 112b, and conductive layer 104, suppressing oxidation of these layers and preventing an increase in electrical resistance.

[0134] On the other hand, when conductive materials that are resistant to oxidation, conductive materials that maintain low electrical resistance even when oxidized, or oxide conductors are used for conductive layer 112an, conductive layer 112b, and conductive layer 104, it is preferable to apply the configuration shown in Figure 5A. This reduces the number of steps involved in manufacturing the semiconductor device compared to the configuration shown in Figure 5D. Furthermore, in the configuration shown in Figure 5A, in addition to the oxygen released by the insulating layer 106n, the oxygen released by the insulating layer 110b1 and insulating layer 110b2 can also be supplied to the semiconductor layer 108n. Therefore, the configuration shown in Figure 5A can supply more oxygen to the semiconductor layer 108n than the configuration shown in Figure 5D.

[0135] The following describes the materials that can be used for each component of semiconductor devices.

[0136] [Semiconductor layer 108n, semiconductor layer 108p] The semiconductor materials that can be used for semiconductor layer 108n and semiconductor layer 108p are not particularly limited. For example, elemental semiconductors or compound semiconductors can be used. For example, silicon or germanium can be used as elemental semiconductors. For example, gallium arsenide and silicon germanium can be used as compound semiconductors. For example, organic materials having semiconductor properties or metal oxides (also called oxide semiconductors) having semiconductor properties can be used as compound semiconductors. These semiconductor materials can also be configured to contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron). For example, as semiconductor layer 108n, which is an n-type semiconductor layer, silicon with elements such as phosphorus added as dopants can be used. Also, for example, as semiconductor layer 108p, which is a p-type semiconductor layer, silicon with elements such as boron added as dopants can be used.

[0137] The crystallinity of the semiconductor material used for semiconductor layer 108n and semiconductor layer 108p is not particularly limited, and either an amorphous semiconductor or a crystalline semiconductor (single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a crystalline semiconductor is preferable because it can suppress the degradation of transistor characteristics.

[0138] Silicon can be used for both the semiconductor layer 108n and the semiconductor layer 108p. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0139] Transistors using amorphous silicon for both semiconductor layer 108n and semiconductor layer 108p can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon for both semiconductor layer 108n and semiconductor layer 108p have high field-effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon for both semiconductor layer 108n and semiconductor layer 108p have higher field-effect mobility than transistors using amorphous silicon and can operate at high speed.

[0140] Preferably, the semiconductor layer 108n and the semiconductor layer 108p each have a metal oxide (oxide semiconductor).

[0141] Examples of metal oxides that can be used in the semiconductor layer 108n, which is an n-type semiconductor layer, include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium, and tin. Gallium is more preferred for element M.

[0142] For the semiconductor layer 108n, for example, indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also written as IWO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. Alternatively, indium tin oxide containing silicon, etc., can be used.

[0143] Furthermore, examples of metal oxides that can be used in the semiconductor layer 108p, which is a p-type semiconductor layer, include tellurium oxide (Te oxide), tin oxide (Sn oxide), and copper oxide (Cu oxide).

[0144] For the formation of metal oxides, suitable formation methods include sputtering, atomic layer deposition (ALD), or vacuum deposition. However, when forming metal oxides by sputtering, the atomic ratio of the target material may differ from that of the metal oxide. In particular, with zinc, the atomic ratio of the metal oxide may be lower than that of the target material. Specifically, the atomic ratio of zinc in the metal oxide may be between 40% and 90% of that of the target material.

[0145] When forming metal oxides by ALD, it is preferable to use a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD). Thermal ALD is preferred because it exhibits extremely high step coverage. PEALD is also preferred because, in addition to exhibiting high step coverage, it allows for low-temperature film formation.

[0146] The composition of the metal oxides in semiconductor layer 108n and semiconductor layer 108p significantly affects the electrical characteristics and reliability of transistors 10An and 10Ap, respectively.

[0147] For example, by increasing the indium content of the metal oxide, a transistor with a high on-current can be realized. Also, for example, by using a metal oxide that does not contain gallium or has a low gallium content, a transistor with high reliability against positive bias application can be realized. Also, for example, by using a metal oxide with a low content of element M, a transistor with high reliability against positive bias application can be realized. Also, for example, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be realized.

[0148] Details of the metal oxide composition that can be used in the semiconductor layer 108n, which is an n-type semiconductor layer, will be described later.

[0149] It is preferable to use a crystalline metal oxide layer for each of the semiconductor layer 108n and semiconductor layer 108p. For example, metal oxide layers having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, etc., can be used. By using a crystalline metal oxide layer for the semiconductor layer 108n and semiconductor layer 108p, the defect level density in the semiconductor layer 108n and semiconductor layer 108p can be reduced, and a highly reliable transistor can be realized. The CAAC structure is a crystalline structure in which multiple nanocrystals (typically multiple IGZO nanocrystals) have c-axis orientation, and in the a-b plane, the multiple nanocrystals are linked without orientation. In the CAAC structure, the grain boundaries are not as clearly visible in the a-b plane as in the polycrystalline structure, thus enabling the realization of a highly reliable transistor.

[0150] The higher the crystallinity of the metal oxide layers used in semiconductor layers 108n and 108p, the lower the defect level density in semiconductor layers 108n and 108p can be. On the other hand, by using metal oxide layers with low crystallinity, it is possible to realize transistors that can carry large currents.

[0151] The semiconductor layer 108n and the semiconductor layer 108p can each be a single layer or a stacked structure of two or more layers.

[0152] The thickness of the semiconductor layer 108n and the semiconductor layer 108p is preferably 3 nm to 100 nm, more preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, more preferably 10 nm to 70 nm, more preferably 15 nm to 70 nm, more preferably 15 nm to 50 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and more preferably 25 nm to 40 nm.

[0153] Here, we will explain the oxygen vacancies that may be formed in the semiconductor layer 108n and the semiconductor layer 108p.

[0154] As described above, when oxide semiconductors are used for both semiconductor layer 108n and semiconductor layer 108p, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, thus forming oxygen vacancies in the oxide semiconductor. Furthermore, a defect called V can form when hydrogen is added to the oxygen vacancy. Ｏ H can function as a donor, generating electrons as carriers. Additionally, some hydrogen can combine with oxygen atoms bonded to metal atoms, also generating electrons. Therefore, transistors using oxide semiconductors with high hydrogen content tend to exhibit fluctuating threshold voltages (for example, n-channel transistors are prone to normally-on characteristics). Furthermore, because hydrogen in oxide semiconductors is easily affected by stresses such as heat and electric fields, a high hydrogen content in the oxide semiconductor may degrade the reliability of the transistor.

[0155] V ＯH can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in oxide semiconductors, evaluation is sometimes performed based on carrier concentration instead of donor concentration. Accordingly, in this specification and the like, carrier concentration assuming a state where no electric field is applied may be used as a parameter of an oxide semiconductor instead of donor concentration. That is, the “carrier concentration” described in this specification and the like can in some cases be rephrased as “donor concentration”.

[0156] From the above, when an oxide semiconductor is used for the semiconductor layer 108n and the semiconductor layer 108p, each V in the semiconductor layer 108n and the semiconductor layer 108p Ｏ H is preferably reduced as much as possible to achieve highly purified intrinsic or substantially highly purified intrinsic properties. To obtain an oxide semiconductor in which V Ｏ H is sufficiently reduced, it is necessary to remove impurities such as water and hydrogen from the oxide semiconductor (this is sometimes referred to as dehydration or dehydrogenation treatment) and supply oxygen to the oxide semiconductor to fill oxygen vacancies (V Ｏ ). It is important to repair these oxygen vacancies. V Ｏ When an oxide semiconductor in which defects such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be imparted. Note that supplying oxygen to an oxide semiconductor to repair oxygen vacancies (V Ｏ ) is sometimes referred to as oxygenation treatment.

[0157] When an oxide semiconductor is used for each of the semiconductor layer 108n and the semiconductor layer 108p, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 １８ cm −３ or less, preferably 1×10 １７ cm −３ or less, more preferably less than 1×10 １６ cm −３ or less, even more preferably less than 1×10 １３ cm −３ or less, still more preferably less than 1×10 １２ cm −３It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration of the oxide semiconductor in the region that functions as a channel-forming region, but for example, 1 × 10 −９ cm −３ It can be done this way.

[0158] Transistors using oxide semiconductors (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. In addition, OS transistors have remarkably low source-drain leakage current (hereinafter also referred to as off-current) in the off state.

[0159] Therefore, OS transistors are preferably applied to memory devices. For example, by applying a semiconductor device according to one embodiment of the present invention, which is composed of OS transistors, to a memory device, it is possible to realize a memory device with lower leakage current and extremely low power consumption compared to when a semiconductor device composed of amorphous silicon is applied.

[0160] Furthermore, OS transistors are preferably applied to display devices. To increase the luminescence brightness of a light-emitting device included in the pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to silicon transistors (hereinafter referred to as Si transistors), OS transistors have a higher breakdown voltage between the source and drain, so a high voltage can be applied between the source and drain of an OS transistor. Therefore, by applying an OS transistor to the drive transistor of a pixel circuit, the amount of current flowing through the light-emitting device can be increased, and the luminescence brightness of the light-emitting device can be increased.

[0161] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thus allowing for precise control of the current flowing to the light-emitting device. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0162] In terms of the saturation characteristics of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting device, for example, even if there are variations in the current-voltage characteristics of the light-emitting device. In other words, when operating in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is increased, thus stabilizing the luminescence brightness of the light-emitting device.

[0163] As described above, by using OS transistors in the drive transistors included in the pixel circuit, it is possible to achieve "suppression of black level floating," "increase in luminescence brightness," "multi-gradation," and "suppression of variations in light-emitting devices."

[0164] Furthermore, as described in Embodiment 4, a semiconductor device according to one aspect of the present invention can be applied to the driving circuit of a display device. Therefore, by using OS transistors in the transistors constituting the semiconductor device according to one aspect of the present invention, both the pixel circuit and the driving circuit of the display device can be constructed using OS transistors. This reduces the number of manufacturing steps involved in the production of the display device compared to when the pixel circuit and the driving circuit of the display device are made from transistors made of different materials (for example, OS transistors and Si transistors).

[0165] OS transistors exhibit small fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0166] [Insulating Layer] In a transistor according to one aspect of the present invention, and in a semiconductor device to which a transistor according to one aspect of the present invention is applied, an inorganic insulating material or an organic insulating material can be used as the insulating layer (insulating layer 110_1, insulating layer 110_2, insulating layer 106n, insulating layer 106p, and insulating layer 195). Furthermore, a laminated structure of an inorganic insulating material and an organic insulating material can also be used as the insulating layer.

[0167] As the inorganic insulating material, one or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used.

[0168] In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content. The term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, silicon oxide-nitride refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride oxide refers to a material in which the nitrogen content is greater than the oxygen content.

[0169] For the analysis of oxygen and nitrogen content, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing elemental content, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0170] Furthermore, for evaluating the film density of insulating layers, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR) can be used. Differences in film density can also sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Even when applying the same material to the insulating layer, differences in film density can sometimes be observed as differences in contrast at the boundaries between these densities in the cross-sectional TEM image.

[0171] The nitrogen content of an insulating layer can be confirmed, for example, by energy-dispersive X-ray spectroscopy (EDX). For example, when silicon nitride, silicon oxynitride, etc. are used for the insulating layer, the nitrogen content can be evaluated using the ratio of the peak height of nitrogen to the peak height of silicon. In EDX, the peak of a given element refers to the point where the count number of that element reaches its maximum value in a spectrum where the energy of the characteristic X-ray is shown on the horizontal axis and the count number (detection value) of the characteristic X-ray is shown on the vertical axis. Alternatively, the difference in nitrogen content can be confirmed by using the count number at the characteristic X-ray energy specific to that element and comparing it with the count number of nitrogen to the count number of silicon. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0172] The hydrogen concentration in the insulating layer can be evaluated, for example, using SIMS.

[0173] When hydrogen diffuses into semiconductor layer 108n and semiconductor layer 108p, it reacts with oxygen atoms contained in the oxide semiconductor to form water, creating oxygen vacancies (V) in semiconductor layer 108n and semiconductor layer 108p. Ｏ ) may be formed in the semiconductor layer 108n and the semiconductor layer 108p Ｏ H may be formed, and the carrier concentration in the semiconductor layer 108n and semiconductor layer 108p may become high. By using a barrier film that suppresses hydrogen diffusion as an insulating layer in contact with each of the semiconductor layer 108n and semiconductor layer 108p, or as an insulating layer located around each of the semiconductor layer 108n and semiconductor layer 108p, oxygen vacancies (V) in the semiconductor layer 108n and semiconductor layer 108p can be suppressed. Ｏ ) and V Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0174] Oxygen deficiency (V) in the channel formation region of transistor 10An and transistor 10Ap, respectively. Ｏ ) and V ＯH is preferably low. For example, V from the source region or drain region to the channel formation region. Ｏ When H diffuses, the carrier concentration in the channel formation region increases, which may cause fluctuations in the threshold voltages of transistors 10An and 10Ap, or a decrease in reliability. Ｏ The effect of H diffusion on the electrical characteristics and reliability of transistors 10An and 10Ap increases as the channel length decreases. In semiconductor layers 108n and 108p, in particular, oxygen vacancies (V) in the channel formation region Ｏ ) and V Ｏ By reducing H, it is possible to realize transistors with short channel lengths that have good electrical characteristics and high reliability.

[0175] By using an oxygen-releasing insulating layer as an insulating layer in contact with each of the semiconductor layer 108n and semiconductor layer 108p (for example, insulating layer 106n or insulating layer 106p), or as an insulating layer located around each of the semiconductor layer 108n and semiconductor layer 108p (for example, insulating layer 110b1 and insulating layer 110b2), oxygen can be supplied from the insulating layer to the semiconductor layer 108n or semiconductor layer 108p. By supplying oxygen to the channel formation regions of each of the semiconductor layer 108n and semiconductor layer 108p, oxygen deficiencies (V) in the semiconductor layer 108n and semiconductor layer 108p can be reduced. Ｏ ) and V Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable. Other methods for supplying oxygen to the semiconductor layer 108n and semiconductor layer 108p include heating in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.

[0176] It is preferable that insulating layers in contact with the semiconductor layer 108n and the semiconductor layer 108p, or insulating layers located around the semiconductor layer 108n and the semiconductor layer 108p, release little impurities (e.g., water and hydrogen) from themselves. The impurities referred to here are those that diffuse into the semiconductor layer 108n and the semiconductor layer 108p, resulting in oxygen vacancies (V) in the semiconductor layer 108n and the semiconductor layer 108p. Ｏ ) and VＯ This refers to substances that can adversely affect the electrical characteristics of a transistor, such as by generating H. By reducing the release of impurities, the diffusion of these impurities into the semiconductor layer 108n and semiconductor layer 108p is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0177] In some cases, oxygen may be removed from semiconductor layers 108n and 108p due to heat applied in processes after the formation of semiconductor layers 108n and 108p. However, oxygen is supplied to semiconductor layers 108n and 108p from insulating layers in contact with each of them, or from insulating layers located around each of them, thereby preventing oxygen deficiencies (V) in semiconductor layers 108n and 108p. Ｏ ) and V Ｏ This method can suppress the increase in H. Furthermore, it allows for greater flexibility in the processing temperature during processes following the formation of semiconductor layers 108n and 108p. Specifically, the processing temperature can be increased even during processes following the formation of semiconductor layers 108n and 108p. Therefore, it is possible to form transistors that exhibit good electrical characteristics and high reliability.

[0178] [Insulating layer 110_1, insulating layer 110_2] Insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) can be made from inorganic insulating materials or organic insulating materials, respectively. Insulating layer 110_1 and insulating layer 110_2 can also be made from a laminated structure of inorganic insulating material and organic insulating material, respectively.

[0179] Inorganic insulating materials can be suitably used as insulating layer 110_1 and insulating layer 110_2. One or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used as inorganic insulating materials. For example, one or more silicon oxide, silicon oxidized nitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon oxide nitride, and aluminum nitride can be used as insulating layer 110_1 and insulating layer 110_2.

[0180] The insulating layer 110_1 and insulating layer 110_2 can each be made into a laminated structure of two or more layers. In Figure 1B, etc., insulating layer 110_1 has a laminated structure of insulating layer 110a1, insulating layer 110b1 on insulating layer 110a1, and insulating layer 110c1 on insulating layer 110b1, and insulating layer 110_2 has an insulating layer 110a2, insulating layer 110b2 on insulating layer 110a2, and insulating layer 110c2 on insulating layer 110b2. Note that the insulating layers 110a1, 110b1, 110c1, 110a2, 110b2, and 110c2 can be made of the same material or different materials.

[0181] It is preferable that insulating layers 110_1 and 110_2 release very little impurities (e.g., water and hydrogen) from themselves.

[0182] The thickness of insulating layer 110b1 can be greater than the thickness of insulating layer 110a1 and insulating layer 110c1. Similarly, the thickness of insulating layer 110b2 can be greater than the thickness of insulating layer 110a2 and insulating layer 110c2. As described above, insulating layer 110b1 and insulating layer 110b2 are insulating layers that have oxygen to supply to semiconductor layer 108n and semiconductor layer 108p. Therefore, among the three insulating layers constituting insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and the three insulating layers constituting insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2), by making the thickness of insulating layer 110b1 and insulating layer 110b2 the thickest, the amount of oxygen that can be contained in the entire insulating layer 110_1 and insulating layer 110_2 can be increased. It is preferable that the deposition rate of insulating layer 110b1 is faster than the deposition rate of insulating layer 110a1 and insulating layer 110c1. Similarly, it is preferable that the deposition rate of insulating layer 110b2 is faster than the deposition rate of insulating layer 110a2 and insulating layer 110c2. By increasing the deposition rate of thicker films, productivity can be increased.

[0183] The insulating layer 110a1 and the insulating layer 110c1 each function as barrier films that suppress the leaching of gas from the insulating layer 110b1. Similarly, the insulating layer 110a2 and the insulating layer 110c2 each function as barrier films that suppress the leaching of gas from the insulating layer 110b2. Therefore, it is preferable to use materials that are resistant to gas diffusion for each of the insulating layers 110a1, 110c1, 110a2, and 110c2. It is preferable that the insulating layer 110a1 and the insulating layer 110c1 each have regions with a higher film density than the insulating layer 110b1. Similarly, it is preferable that the insulating layer 110a2 and the insulating layer 110c2 each have regions with a higher film density than the insulating layer 110b2. By increasing the film density of the insulating layer, the barrier properties against gas can be improved. By slowing down the film deposition rate of the insulating layer, the film density can be increased, and the barrier properties against gas can be improved.

[0184] It is preferable to use oxides or oxidized nitrides as insulating layers 110b1 and 110b2. It is preferable to use films that release oxygen upon heating as insulating layers 110b1 and 110b2. For example, silicon oxide or silicon oxidized nitride can be suitably used as insulating layers 110b1 and 110b2.

[0185] The insulating layers 110b1 and 110b2 release oxygen, thereby supplying oxygen from the insulating layers 110b1 and 110b2 to the semiconductor layers 108n and 108p. It is preferable that the insulating layers 110b1 and 110b2 each have high oxygen diffusion coefficients. By increasing the oxygen diffusion coefficient, oxygen can diffuse more easily through the insulating layers 110b1 and 110b2, allowing for efficient oxygen supply to the semiconductor layers 108n and 108p. Furthermore, as described above, by configuring the insulating layer 110b1 to be thicker than the insulating layers 110a1 and 110c1, and the insulating layer 110b2 to be thicker than the insulating layers 110a2 and 110c2, more oxygen can be supplied to the semiconductor layers 108n and 108p.

[0186] The insulating layer 110_1 and the insulating layer 110_2 are preferably formed by a film deposition method such as sputtering, ALD, or plasma CVD (Chemical Vapor Deposition).

[0187] In particular, by using the sputtering method and a film deposition method that does not use a hydrogen-containing gas as the deposition gas, it is possible to create a film with an extremely low hydrogen content. Therefore, the supply of hydrogen to the semiconductor layer 108n and semiconductor layer 108p can be suppressed, and the electrical characteristics of transistors 10An and 10Ap can be stabilized. When depositing silicon oxide by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing an oxygen-containing gas. Similarly, when depositing silicon nitride by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing a nitrogen-containing gas. Furthermore, when depositing aluminum oxide by sputtering, for example, the film can be deposited using an aluminum target in an atmosphere containing an oxidizing gas.

[0188] Furthermore, silicon oxide and silicon nitride can be deposited using, for example, the PEALD method. Aluminum oxide and hafnium oxide can also be deposited using, for example, the thermal ALD method. By depositing an insulating layer using the PEALD method and the thermal ALD method, a dense insulating film can be formed, thereby improving barrier properties against oxygen and hydrogen.

[0189] The insulating layer 110a1 and insulating layer 110c1 can each be made of a material with a higher nitrogen content than insulating layer 110b1. Similarly, the insulating layer 110a2 and insulating layer 110c2 can each be made of a material with a higher nitrogen content than insulating layer 110b2. By increasing the nitrogen content of the insulating layer, the barrier properties against oxygen and hydrogen can be improved.

[0190] Furthermore, insulating layer 110a1 and insulating layer 110c1 may each have regions where the hydrogen concentration in the film is lower than that of insulating layer 110b1. Similarly, insulating layer 110a2 and insulating layer 110c2 may each have regions where the hydrogen concentration in the film is lower than that of insulating layer 110b2.

[0191] It is preferable that insulating layers 110a1, 110c1, 110a2, and 110c2 are impermeable to oxygen. Furthermore, it is preferable that insulating layers 110a1, 110c1, 110a2, and 110c2 are impermeable to hydrogen. Insulating layers 110a1, 110c1, 110a2, and 110c2 function as barrier films that suppress the diffusion of hydrogen from outside the transistor through these insulating layers to semiconductor layers 108n and 108p. It is preferable that the film density of insulating layer 110a1 and insulating layer 110c1 is higher than the film density of insulating layer 110b1. Similarly, it is preferable that the film density of insulating layer 110a2 and insulating layer 110c2 is higher than the film density of insulating layer 110b2. By increasing the film density of the insulating layers, the barrier properties against oxygen and hydrogen can be improved. When silicon oxide or silicon oxide nitride is used for insulating layers 110b1 and 110b2, silicon nitride or silicon nitride oxide can be used for insulating layers 110a1, 110c1, 110a2, and 110c2. Furthermore, hafnium oxide or aluminum oxide can be suitably used for insulating layers 110a1, 110c1, 110a2, and 110c2.

[0192] Furthermore, the insulating layers 110a1, 110c1, 110a2, and 110c2 can be constructed by laminating two or more materials selected from silicon nitride, silicon oxide nitride, hafnium oxide, and aluminum oxide, respectively.

[0193] If oxygen contained in insulating layer 110b1 diffuses downward (towards substrate 102), the amount of oxygen supplied from insulating layer 110b1 to semiconductor layer 108n and semiconductor layer 108p may decrease. By providing insulating layer 110a1 below insulating layer 110b1, the diffusion of oxygen contained in insulating layer 110b1 downward can be suppressed. Similarly, if oxygen contained in insulating layer 110b2 diffuses downward from insulating layer 110b2, the amount of oxygen supplied from insulating layer 110b2 to semiconductor layer 108n and semiconductor layer 108p may decrease. By providing insulating layer 110a2 below insulating layer 110b2, the diffusion of oxygen contained in insulating layer 110b2 downward can be suppressed.

[0194] Furthermore, if the oxygen contained in the insulating layer 110b1 diffuses upward from the insulating layer 110b1, the amount of oxygen supplied from the insulating layer 110b1 to the semiconductor layer 108n and semiconductor layer 108p may decrease. By providing an insulating layer 110c1 on top of the insulating layer 110b1, the diffusion of oxygen contained in the insulating layer 110b1 upward from the insulating layer 110b1 can be suppressed. Therefore, the amount of oxygen supplied from the insulating layer 110b1 to the semiconductor layer 108n and semiconductor layer 108p increases, and oxygen deficiencies (V) in the semiconductor layer 108n and semiconductor layer 108p are reduced. Ｏ ) and V Ｏ H can be reduced. Similarly, if the oxygen contained in the insulating layer 110b2 diffuses upward from the insulating layer 110b2, the amount of oxygen supplied from the insulating layer 110b2 to the semiconductor layer 108n and semiconductor layer 108p may decrease. By providing an insulating layer 110c2 on top of the insulating layer 110b2, the diffusion of oxygen contained in the insulating layer 110b2 upward from the insulating layer 110b2 can be suppressed. Therefore, the amount of oxygen supplied from the insulating layer 110b2 to the semiconductor layer 108n and semiconductor layer 108p increases, and oxygen deficiencies (V) in the semiconductor layer 108n and semiconductor layer 108p are reduced. Ｏ ) and V Ｏ H can be reduced.

[0195] Furthermore, by providing insulating layers 110a1, 110c1, 110a2, and 110c2, the diffusion of hydrogen into semiconductor layer 108n and semiconductor layer 108p is suppressed, and oxygen vacancies (V) in semiconductor layer 108n and semiconductor layer 108p are reduced. Ｏ ) and V Ｏ H can be reduced.

[0196] It is preferable that the insulating layers 110a1, 110c1, 110a2, and 110c2 each have a thickness that functions as a barrier film for oxygen and hydrogen. If the film thickness is too thin, the barrier function may be reduced. On the other hand, if the film thickness is too thick, the region of semiconductor layer 108n and the region of semiconductor layer 108p facing insulating layer 110b1 or insulating layer 110b2 become narrower, which may reduce the amount of oxygen supplied to semiconductor layer 108n and semiconductor layer 108p. The film thickness of insulating layer 110a1, insulating layer 110c1, insulating layer 110a2, and insulating layer 110c2 is preferably 1 nm to 200 nm, 1 nm to 100 nm, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 2 nm to 5 nm, respectively.

[0197] [Insulating layer 106n, insulating layer 106p] The insulating layer 106n and insulating layer 106p, which function as gate insulating layers, preferably have a low defect density. A low defect density in the insulating layer 106n and insulating layer 106p allows for a transistor that exhibits good electrical characteristics. Furthermore, it is preferable that the insulating layer 106n and insulating layer 106p have a high dielectric breakdown voltage. A high dielectric breakdown voltage in the insulating layer 106n and insulating layer 106p allows for a highly reliable transistor.

[0198] Furthermore, it is preferable that the insulating layer 106n and insulating layer 106p are insulating layers containing oxygen. It is also preferable that they are insulating layers that release oxygen upon heating. This allows, for example, when metal oxides are used for the semiconductor layer 108n and semiconductor layer 108p, to supply oxygen from the insulating layer 106n and insulating layer 106p to the metal oxide. This allows for the repair of oxygen deficiencies in the metal oxide, thereby improving the electrical characteristics and reliability of transistors 10An and 10Ap.

[0199] For insulating layer 106n and insulating layer 106p, one or more insulating oxides, oxidized nitrides, nitride oxides, and nitrides can be used. For insulating layer 106n and insulating layer 106p, one or more silicon oxide, silicon oxidized nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, and Ga-Zn oxide can be used. It is preferable to use the same materials for insulating layer 110b1 and insulating layer 110b2 described above for insulating layer 106n and insulating layer 106p. For example, silicon oxide or silicon oxidized nitride can be suitably used for insulating layer 106n and insulating layer 106p. Insulating layer 106n and insulating layer 106p can each be a single layer or a laminate. The insulating layer 106n and the insulating layer 106p can also be, for example, a laminated structure of oxide and nitride.

[0200] In the case of miniature transistors, if the thickness of the gate insulating layer becomes thin, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0201] It is preferable that the insulating layer 106n and insulating layer 106p release little impurities (e.g., water and hydrogen) from themselves. By reducing the release of impurities from the insulating layer 106n and insulating layer 106p, the diffusion of such impurities into the semiconductor layer 108n and semiconductor layer 108p is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0202] Here, we will specifically explain the insulating layer 106n and the insulating layer 106p, using a configuration in which metal oxides are used for both the semiconductor layer 108n and the semiconductor layer 108p as an example.

[0203] To improve the interface characteristics with the semiconductor layer 108n, it is preferable to use one or more oxides and oxiditrides on at least the side of the insulating layer 106n that is in contact with the semiconductor layer 108n. Similarly, to improve the interface characteristics with the semiconductor layer 108p, it is preferable to use one or more oxides and oxiditrides on at least the side of the insulating layer 106p that is in contact with the semiconductor layer 108p. For example, silicon oxide and one or more silicon oxiditrides can be suitably used for the insulating layer 106n and the insulating layer 106p. Furthermore, it is more preferable to use films that release oxygen upon heating for the insulating layer 106n and the insulating layer 106p.

[0204] Furthermore, the insulating layer 106n and the insulating layer 106p can each be configured as a laminated structure. The insulating layer 106n can be configured as a laminated structure of an oxide film or oxynitride film on the side in contact with the semiconductor layer 108n and a nitride film on the side in contact with the conductive layer 104. Similarly, the insulating layer 106p can be configured as a laminated structure of an oxide film or oxynitride film on the side in contact with the semiconductor layer 108p and a nitride film on the side in contact with the conductive layer 104. For example, silicon oxide and silicon oxynitride can be suitably used as the oxide film or the oxynitride film. For example, silicon nitride can be suitably used as the nitride film.

[0205] The thickness of the insulating layer 106n and the insulating layer 106p is preferably between 1 nm and 100 nm. It is preferable that the insulating layer 106n and the insulating layer 106p have regions with the above-mentioned thickness in at least a portion of their respective areas.

[0206] [Conductive layer 112an, conductive layer 112ap, conductive layer 112b] The conductive layers 112an, 112ap, and 112b, which function as source and drain electrodes, can be formed using one or more of the following: chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the aforementioned metals. Low-resistance conductive materials containing one or more of copper, silver, gold, or aluminum can be suitably used for the conductive layers 112an, 112ap, and 112b, respectively. Copper or aluminum are particularly preferred due to their excellent mass-producibility.

[0207] A metal oxide film (also called an oxide conductor) can be used for the conductive layer 112an, conductive layer 112ap, and conductive layer 112b, respectively. Examples of oxide conductors (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0208] Here, we will explain oxide conductors (OCs). For example, when an oxygen vacancy is formed in a metal oxide with semiconductor properties, and hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0209] The conductive layers 112an, 112ap, and 112b can each be a laminated structure of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0210] The conductive layers 112an, 112ap, and 112b can each be coated with a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, processing can be performed by wet etching, thus reducing manufacturing costs.

[0211] Furthermore, the conductive layer 112an and conductive layer 112ap (i.e., conductive layers that function as either the source electrode or the drain electrode of the transistor) and conductive layer 112b (i.e., conductive layer that functions as the other source electrode or the drain electrode of the transistor) can be made of the same material, or they can be made of different materials. Also, the conductive layer 112an and conductive layer 112ap can be made of the same material, or they can be made of different materials.

[0212] Here, we will take a configuration in which metal oxides are used for semiconductor layers 108n and 108p as an example and specifically explain the conductive layers 112an, 112ap, and 112b.

[0213] When oxide semiconductors are used for semiconductor layer 108n and semiconductor layer 108p, the oxygen contained in semiconductor layer 108n and semiconductor layer 108p may oxidize the conductive layer 112an, conductive layer 112ap, and conductive layer 112b, potentially increasing their resistance. Similarly, the oxygen contained in insulating layer 106n and insulating layer 106p may oxidize the conductive layer 112an, conductive layer 112ap, and conductive layer 112b, potentially increasing their resistance. Furthermore, the oxygen contained in insulating layer 110_1 and insulating layer 110_2 may oxidize the conductive layer 112an, conductive layer 112ap, and conductive layer 112b, potentially increasing their resistance.

[0214] Furthermore, the oxygen contained in semiconductor layer 108n and semiconductor layer 108p oxidizes conductive layer 112an, conductive layer 112ap, and conductive layer 112b, resulting in oxygen vacancies (V) in semiconductor layer 108n and semiconductor layer 108p. Ｏ In some cases, the amount of oxygen supplied from insulating layer 106n and insulating layer 106p to semiconductor layer 108n and semiconductor layer 108p may decrease due to the oxidation of conductive layer 112an, conductive layer 112ap, and conductive layer 112b by the oxygen contained in insulating layer 106n and insulating layer 106p. In addition, in some cases, the amount of oxygen supplied from insulating layer 110_1 and insulating layer 110_2 to semiconductor layer 108n and semiconductor layer 108p may decrease due to the oxidation of conductive layer 112an, conductive layer 112ap, and conductive layer 112b by the oxygen contained in insulating layer 110_1 and insulating layer 110_2.

[0215] It is preferable to use materials that are resistant to oxidation for each of the conductive layers 112an, 112ap, and 112b. It is preferable to use oxide conductors for each of the conductive layers 112an, 112ap, and 112b. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) can be suitably used. Nitride conductors can also be used for each of the conductive layers 112an, 112ap, and 112b. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 112an, 112ap, and 112b can each have a laminated structure of the aforementioned materials.

[0216] By using materials that are resistant to oxidation for each of the conductive layers 112an, 112ap, and 112b, it is possible to suppress oxidation caused by oxygen contained in the semiconductor layer 108n and 108p, oxygen contained in the insulating layer 106n and 106p, or oxygen contained in the insulating layer 110_1 and 110_2, which can increase resistance. Furthermore, oxygen vacancies (V) in the semiconductor layer 108n and 108p can be suppressed. Ｏ The increase in ) is suppressed, and the amount of oxygen supplied from insulating layer 106n, insulating layer 106p, insulating layer 110_1, and insulating layer 110_2 to semiconductor layer 108n and semiconductor layer 108p can be increased.

[0217] [Conductive Layer 104] The conductive layer 104, which functions as a gate electrode, can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy composed of one or more of the aforementioned metals. Alternatively, the conductive layer 104 can be made from the same materials used for the conductive layers 112an, 112ap, and 112b described above.

[0218] Although Figure 1B and other figures show the conductive layer 104 as a single layer, this is not limited to that. For example, the conductive layer 104 can also be a laminated structure of two or more layers.

[0219] [Insulating Layer 195] It is preferable to use a material that does not easily allow impurities to diffuse for the insulating layer 195, which functions as a protective layer for transistors 10An and 10Ap. By providing the insulating layer 195, the diffusion of impurities into the transistors from the outside can be effectively suppressed, and the reliability of the transistors can be improved. Examples of impurities include water and hydrogen. The insulating layer 195 can be an insulating layer having an inorganic material or an insulating layer having an organic material. For example, an inorganic material such as an oxide, an oxide nitride, an oxide nitride, or a nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. As the organic material, one or more of acrylic resin and polyimide resin can be used. Photosensitive materials can also be used as the organic material. Furthermore, two or more of the above insulating films can be laminated and used. The insulating layer 195 can also be a laminated structure of an insulating layer having an inorganic material and an insulating layer having an organic material.

[0220] The insulating layer 195 is formed on the semiconductor layer 108n and the semiconductor layer 108p. Therefore, it is preferable that the insulating layer 195 is a film formed under conditions that minimize damage to the semiconductor layer 108n and the semiconductor layer 108p. For example, it is preferable to form it under conditions where the deposition rate (also called the deposition rate) is sufficiently slow. For example, when forming an insulating film that will become the insulating layer 195 by plasma CVD, forming it under low power conditions can reduce the damage to the semiconductor layer 108n and the semiconductor layer 108p.

[0221] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or organic resin substrates can be used as the substrate 102. In addition, substrates on which semiconductor elements are provided can also be used as the substrate 102. The shape of the semiconductor substrate and insulating substrate can be circular or rectangular.

[0222] A flexible substrate can be used as the substrate 102, and the semiconductor device 100A, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the semiconductor device 100A, etc. The release layer can be used to separate the semiconductor device from the substrate 102 after it has been partially or completely completed on it, and to transfer it to another substrate. In this case, the semiconductor device 100A, etc., can be transferred to a substrate with poor heat resistance or to a flexible substrate.

[0223] [Composition of metal oxide in semiconductor layer 108n] The following describes in detail the composition of metal oxide that can be used in semiconductor layer 108n, which is an n-type semiconductor layer.

[0224] The composition of the metal oxide in the semiconductor layer 108n significantly affects the electrical characteristics and reliability of the transistor 10An.

[0225] For example, by increasing the indium content of the metal oxide, a transistor 10An with a large on-current can be realized.

[0226] When using an In-Zn oxide for the semiconductor layer 108n, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, metal oxides with atomic ratios of metal elements of In:Zn = 1:1, In:Zn = 2:1, In:Zn = 3:1, In:Zn = 4:1, In:Zn = 5:1, In:Zn = 7:1, or In:Zn = 10:1, or close to these, can be used.

[0227] When using an In-Sn oxide for the semiconductor layer 108n, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than that of tin. For example, metal oxides with atomic ratios of metal elements of In:Sn = 1:1, In:Sn = 2:1, In:Sn = 3:1, In:Sn = 4:1, In:Sn = 5:1, In:Sn = 7:1, or In:Sn = 10:1, or close to these ratios, can be used.

[0228] When using an In-M-Zn oxide for the semiconductor layer 108n, a metal oxide can be applied in which the atomic ratio of indium to the total number of metal elements is higher than the atomic ratio of element M. Furthermore, it is even more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M. For example, in the semiconductor layer 108n, the atomic ratios of the metal elements are In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1 Metal oxides with the following ratios can be used: 6, In:M:Zn = 10:1:3, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, or near these ratios.

[0229] Furthermore, if element M contains multiple metallic elements, the sum of the atomic ratios of those metallic elements can be used as the atomic ratio of element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as elements M, the sum of the atomic ratios of gallium and aluminum can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as elements M, the sum of the atomic ratios of gallium and tin can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges.

[0230] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the total number of metal elements contained in the metal oxide is 30 atomic% to 100 atomic%, preferably 30 atomic% to 95 atomic%, more preferably 35 atomic% to 95 atomic%, more preferably 35 atomic% to 90 atomic%, more preferably 40 atomic% to 90 atomic%, more preferably 45 atomic% to 90 atomic%, more preferably 50 atomic% to 80 atomic%, more preferably 60 atomic% to 80 atomic%, and more preferably 70 atomic% to 80 atomic. For example, when using In-Ga-Zn oxide for the semiconductor layer 108n, it is preferable that the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is within the aforementioned range.

[0231] In this specification, the ratio of indium atoms to the total number of atoms of other metal elements may be referred to as the indium content. The same applies to other metal elements.

[0232] By increasing the indium content of the metal oxide, a transistor with a high on-current can be created. Applying this transistor to a transistor requiring a high on-current results in a semiconductor device with excellent electrical characteristics.

[0233] For the analysis of the composition of metal oxides, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may not be detected.

[0234] In this specification, the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when describing an atomic ratio of In:M:Zn = 4:2:3 or a composition near that, it includes cases where the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Also, when describing an atomic ratio of In:M:Zn = 5:1:6 or a composition near that, it includes cases where the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, when describing an atomic ratio of In:M:Zn = 1:1:1 or a composition near that, it includes cases where the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is greater than 0.1 and 2 or less.

[0235] <Example of semiconductor device configuration 2> Figure 6A shows an example of a semiconductor device 100B with a configuration different from that of semiconductor device 100A shown in Figures 1A and 1B. Figure 6A is a plan view of semiconductor device 100B.

[0236] The semiconductor device 100B includes a transistor 10Bn, a transistor 10Bp, an insulating layer 110, an insulating layer 110_1 (not shown), an insulating layer 110_2 (not shown), and an insulating layer 195 (not shown).

[0237] In semiconductor device 100B, transistor 10Bn corresponds to transistor 10An in semiconductor device 100A, and transistor 10Bp in semiconductor device 100B corresponds to transistor 10Ap in semiconductor device 100A.

[0238] The arrangement of semiconductor layer 108n and semiconductor layer 108p and conductive layer 104, etc., in semiconductor device 100B differs from that of semiconductor device 100A in a plan view.

[0239] In semiconductor device 100A, as shown in Figure 1A, the Y-direction end of a strip-shaped structure composed of conductive layer 104, etc., is provided to protrude outward from the respective Y-direction ends of conductive layer 112an and conductive layer 112ap. Furthermore, semiconductor layer 108n overlaps with the A1 side surface of the structure, and semiconductor layer 108p overlaps with the A2 side surface of the structure.

[0240] In contrast, in semiconductor device 100B, as shown in Figure 6A, the Y-direction end of the structure is positioned inward from the respective Y-direction ends of the conductive layer 112an and conductive layer 112ap. Furthermore, the semiconductor layer 108n overlaps not only the A1-side surface of the structure but also the A1-side corner, and the semiconductor layer 108p overlaps not only the A2-side surface of the structure but also the A2-side corner.

[0241] As a result, in semiconductor device 100B, the length of the region where the semiconductor layer 108n and the conductive layer 104 overlap, and the length of the region where the semiconductor layer 108p and the conductive layer 104 overlap, are different from those of semiconductor device 100A. Therefore, it can be said that the channel widths of the transistors in semiconductor device 100A and semiconductor device 100B are different. In Figure 6A, the channel width W10Bn of transistor 10Bn and the channel width W10Bp of transistor 10Bp are shown by double-headed arrows.

[0242] In semiconductor device 100B, the Y-direction end of the strip-shaped structure composed of the conductive layer 104, etc., does not protrude as much as in semiconductor device 100A, thus reducing the overall occupied area of ​​the semiconductor device compared to semiconductor device 100A.

[0243] On the other hand, in semiconductor device 100A, each of the semiconductor layer 108n and semiconductor layer 108p has a configuration in which it overlaps with only one of the sides of the structure. Therefore, compared to semiconductor device 100B, in which each of the semiconductor layer 108n and semiconductor layer 108p overlaps with two of the sides of the structure, the coverage of each semiconductor layer 108n and semiconductor layer 108p on the surface to which it is formed can be improved. Therefore, in some cases, semiconductor device 100A can achieve a higher manufacturing yield than semiconductor device 100B.

[0244] Regarding semiconductor device 100B, other than the points mentioned above, you can refer to the content described in semiconductor device 100A.

[0245] <Example of semiconductor device configuration 3> Figure 6B shows an example of a semiconductor device 100C with a configuration different from that of semiconductor device 100A shown in Figures 1A and 1B. Figure 6B is a plan view of semiconductor device 100C.

[0246] The semiconductor device 100C includes a transistor 10Cn, a transistor 10Cp, an insulating layer 110_1 (not shown), an insulating layer 110_2 (not shown), and an insulating layer 195 (not shown).

[0247] In semiconductor device 100C, transistor 10Cn corresponds to transistor 10An in semiconductor device 100A, and transistor 10Cp in semiconductor device 100C corresponds to transistor 10Ap in semiconductor device 100A.

[0248] The semiconductor device 100C has different dimensions (areas) of the semiconductor layer 108n and the semiconductor layer 108p in a planar view compared to the semiconductor device 100A.

[0249] In semiconductor device 100A, as shown in Figure 1A, the width of semiconductor layer 108n in the Y direction is smaller than the width of conductive layer 112an in the Y direction, and the width of semiconductor layer 108p in the Y direction is smaller than the width of conductive layer 112ap in the Y direction.

[0250] On the other hand, in semiconductor device 100C, as shown in Figure 6B, the width of semiconductor layer 108n in the Y direction is greater than the width of conductive layer 112an in the Y direction, and the width of semiconductor layer 108p in the Y direction is greater than the width of conductive layer 112ap in the Y direction. In other words, semiconductor device 100C has a configuration in which the size (area) of each semiconductor layer 108n and semiconductor layer 108p in a plan view is larger than that of semiconductor device 100A.

[0251] Therefore, the length of the region where semiconductor layer 108n and conductive layer 104 overlap in semiconductor device 100C, and the length of the region where semiconductor layer 108p and conductive layer 104 overlap in semiconductor device 100A, are longer than the length of the region where semiconductor layer 108n and conductive layer 104 overlap in semiconductor device 100A, and the length of the region where semiconductor layer 108p and conductive layer 104 overlap. In other words, the channel width of the transistors (transistor 10Cn and transistor 10Cp) in semiconductor device 100C is larger than the channel width of the transistors (transistor 10An and transistor 10Ap) in semiconductor device 100A. In Figure 6B, the channel width W10Cn of transistor 10Cn and the channel width W10Cp of transistor 10Cp are shown by double-headed arrows.

[0252] When the channel length of a transistor is constant, the on-current of the transistor can be increased by increasing the channel width of the transistor. Therefore, the transistor in semiconductor device 100C can achieve a higher on-current than the transistor in semiconductor device 100A.

[0253] On the other hand, if the magnitude of the transistor's on-current is not particularly important, the channel width of the transistor can be made smaller than the respective Y-direction widths of the conductive layer 112an and conductive layer 112ap, as in semiconductor device 100A. Thus, in one embodiment of the present invention, the magnitude of the transistor's on-current can be varied simply by adjusting the respective Y-direction widths of the semiconductor layer 108n and semiconductor layer 108p, without changing the respective Y-direction widths of the conductive layer 112an and conductive layer 112ap. Therefore, a transistor with a required on-current can be manufactured for each semiconductor device without affecting the overall occupied area of ​​the semiconductor device.

[0254] Regarding semiconductor device 100C, other than the points mentioned above, you can refer to the content described in semiconductor device 100A.

[0255] <Example of semiconductor device configuration 4> Figure 7A shows an example of the configuration of a semiconductor device 100D, which has a different configuration from the semiconductor device 100A shown in Figures 1A and 1B. Figure 7A is a plan view of the semiconductor device 100D.

[0256] The semiconductor device 100D includes a transistor 10Dn, a transistor 10Dp, an insulating layer 110_1 (not shown), an insulating layer 110_2 (not shown), and an insulating layer 195 (not shown).

[0257] In semiconductor device 100D, transistor 10Dn corresponds to transistor 10An in semiconductor device 100A, and transistor 10Dp in semiconductor device 100D corresponds to transistor 10Ap in semiconductor device 100A.

[0258] The semiconductor device 100D differs from the semiconductor device 100A in that the size (area) of the semiconductor layer 108n in a planar view and the size (area) of the semiconductor layer 108p in a planar view are different from each other.

[0259] In semiconductor device 100A, as shown in Figure 1A, the size (area) of semiconductor layer 108n in a planar view is approximately equal to the size (area) of semiconductor layer 108p in a planar view.

[0260] On the other hand, in semiconductor device 100D, as shown in Figure 7A, the size (area) of semiconductor layer 108n in a plan view is larger than the size (area) of semiconductor layer 108p in a plan view. Specifically, the width of semiconductor layer 108n in the Y direction is larger than the width of conductive layer 112an in the Y direction, while the width of semiconductor layer 108p in the Y direction is smaller than the width of conductive layer 112ap in the Y direction.

[0261] Therefore, in semiconductor device 100D, the length of the region where semiconductor layer 108n and conductive layer 104 overlap is longer than the length of the region where semiconductor layer 108p and conductive layer 104 overlap. In other words, in semiconductor device 100D, the channel width of transistor 10Dn is larger than the channel width of transistor 10Dp. In Figure 7A, the channel width W10Dn of transistor 10Dn and the channel width W10Dp of transistor 10Dp are shown by double-headed arrows.

[0262] Even with the same transistor size, there may be differences in on-current between an n-channel transistor, transistor 10Dn, and a p-channel transistor, transistor 10Dp, due to differences in the Hall mobility of the semiconductor layers 108n and 108p. Therefore, if you want to make the magnitude of the on-current of transistors 10Dn and 10Dp, which have the same channel length, roughly the same, one method is to make the channel widths of each transistor different.

[0263] For example, if the Hole mobility of semiconductor layer 108n (here, the Hole mobility of electrons) is lower than the Hole mobility of semiconductor layer 108p (here, the Hole mobility of holes), then, as in semiconductor device 100D, the channel width of transistor 10Dn can be made larger than the channel width of transistor 10Dp, thereby making the magnitudes of the on-currents of transistors 10Dn and 10Dp roughly the same.

[0264] Regarding semiconductor device 100D, other than the points mentioned above, you can refer to the content described in semiconductor device 100A.

[0265] <Example of semiconductor device configuration 5> Figure 7B shows an example of the configuration of a semiconductor device 100E, which has a different configuration from the semiconductor device 100D shown in Figure 7A. Figure 7B is a plan view of the semiconductor device 100E.

[0266] The semiconductor device 100E includes a transistor 10En, a transistor 10Ep, an insulating layer 110_1 (not shown), an insulating layer 110_2 (not shown), and an insulating layer 195 (not shown).

[0267] In semiconductor device 100E, transistor 10En corresponds to transistor 10Dn in semiconductor device 100D, and transistor 10Ep in semiconductor device 100E corresponds to transistor 10Dp in semiconductor device 100D.

[0268] The semiconductor device 100E differs from the semiconductor device 100D in that the size (area) of the semiconductor layer 108p in a planar view is larger than the size (area) of the semiconductor layer 108n in a planar view.

[0269] In semiconductor device 100E, as shown in Figure 7B, the size (area) of semiconductor layer 108p in a plan view is larger than the size (area) of semiconductor layer 108n in a plan view. Specifically, the width of semiconductor layer 108n in the Y direction is smaller than the width of conductive layer 112an in the Y direction, while the width of semiconductor layer 108p in the Y direction is larger than the width of conductive layer 112ap in the Y direction.

[0270] Therefore, in semiconductor device 100E, the length of the region where the semiconductor layer 108p and the conductive layer 104 overlap is longer than the length of the region where the semiconductor layer 108n and the conductive layer 104 overlap. In other words, in semiconductor device 100E, the channel width of transistor 10Ep is larger than the channel width of transistor 10En. In Figure 7B, the channel width W10En of transistor 10En and the channel width W10Ep of transistor 10Ep are shown by double-headed arrows.

[0271] For example, if the Hole mobility of semiconductor layer 108p (here, the Hole mobility of positive holes) is lower than the Hole mobility of semiconductor layer 108n (here, the Hole mobility of electrons), then, as in semiconductor device 100E, the channel width of transistor 10Epp can be made larger than the channel width of transistor 10En, thereby making the magnitudes of the on-currents of transistors 10En and 10Ep approximately the same.

[0272] Regarding semiconductor device 100E, points other than those mentioned above can be found in the descriptions of semiconductor device 100D and semiconductor device 100A, respectively.

[0273] <Example of semiconductor device configuration 6> Figure 8A shows an example of a semiconductor device 100F with a configuration different from that of the semiconductor device 100A shown in Figures 1A and 1B. Figure 8A is a cross-sectional view of the semiconductor device 100F corresponding to the dashed line A1-A2 of the semiconductor device 100A shown in Figure 1A.

[0274] The semiconductor device 100F includes a transistor 10Fn, a transistor 10Fp, an insulating layer 110_1, an insulating layer 110_2, and an insulating layer 195.

[0275] In semiconductor device 100F, transistor 10Fn corresponds to transistor 10An in semiconductor device 100A, and transistor 10Fp in semiconductor device 100F corresponds to transistor 10Ap in semiconductor device 100A.

[0276] The semiconductor device 100F differs from the semiconductor device 100A in that it has a region on the conductive layer 112b where the edge of the semiconductor layer 108n and the edge of the semiconductor layer 108p overlap each other.

[0277] In semiconductor device 100F, as shown in Figure 8A, a portion of semiconductor layer 108p is provided on the conductive layer 112b in contact with the upper and side surfaces of a portion of semiconductor layer 108n. Here, semiconductor layer 108n is the semiconductor layer of an n-channel type transistor 10Fn that uses electrons as carriers, and semiconductor layer 108p is the semiconductor layer of a p-channel type transistor 10Fp that uses holes as carriers. In other words, transistors 10Fn and 10Fp use different types of carriers for their respective operations. Therefore, even with a configuration in which portions of semiconductor layer 108n and semiconductor layer 108p are in contact, as in semiconductor device 100F, normal operation can be achieved without causing any malfunctions.

[0278] In the case of semiconductor device 100F, the processing precision required during the formation of semiconductor layer 108n and semiconductor layer 108p is not as high as in semiconductor device 100A. Therefore, the degree of freedom in manufacturing the semiconductor device can be increased compared to semiconductor device 100A.

[0279] Regarding semiconductor device 100F, other than the points mentioned above, you can refer to the content described in semiconductor device 100A.

[0280] <Example of semiconductor device configuration 7> Figure 8B shows an example of a semiconductor device 100G with a configuration different from that of the semiconductor device 100F shown in Figure 8A. Figure 8B is a cross-sectional view of the semiconductor device 100G corresponding to the dashed line A1-A2 of the semiconductor device 100A shown in Figure 1A.

[0281] The semiconductor device 100G includes a transistor 10Gn, a transistor 10Gp, an insulating layer 110_1, an insulating layer 110_2, and an insulating layer 195.

[0282] In semiconductor device 100G, transistor 10Gn corresponds to transistor 10Fn in semiconductor device 100F, and in semiconductor device 100G, transistor 10Gp corresponds to transistor 10Fp in semiconductor device 100F.

[0283] As shown in Figure 8B, semiconductor device 100G differs from semiconductor device 100F in that, on the conductive layer 112b, a portion of the semiconductor layer 108n is provided in contact with the upper and side surfaces of a portion of the semiconductor layer 108p.

[0284] By configuring semiconductor device 100G, the same effects obtained with semiconductor device 100F described above can be enjoyed.

[0285] Regarding semiconductor device 100G, other than the points mentioned above, you can refer to the contents described for semiconductor device 100F and semiconductor device 100A, respectively.

[0286] <Example of semiconductor device configuration 8> Figure 9A shows an example of a semiconductor device 100H with a configuration different from that of semiconductor device 100A shown in Figures 1A and 1B. Figure 9A is a cross-sectional view of semiconductor device 100H corresponding to the dashed line A1-A2 of semiconductor device 100A shown in Figure 1A.

[0287] The semiconductor device 100H includes a transistor 10Hn, a transistor 10Hp, an insulating layer 110_1, an insulating layer 110_2, and an insulating layer 195.

[0288] In semiconductor device 100H, transistor 10Hn corresponds to transistor 10An in semiconductor device 100A, and transistor 10Hp in semiconductor device 100H corresponds to transistor 10Ap in semiconductor device 100A.

[0289] The semiconductor device 100H differs from the semiconductor device 100A in terms of the formation position of the conductive layer 104, etc.

[0290] In semiconductor device 100H, as shown in Figure 9A, the conductive layer 104, which functions as the gate electrode of transistors 10Hn and 10Hp, is provided on the lower side (substrate 102 side) than semiconductor device 100A. Furthermore, in semiconductor device 100A, the insulating layer 110_1 provided between the conductive layers 112an and 112ap and the conductive layer 104 has a three-layer stacked structure consisting of insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1, whereas in semiconductor device 100H, it has a single-layer structure consisting only of insulating layer 110a1.

[0291] Because semiconductor device 100H does not have insulating layers 110b1 and 110c1, the number of manufacturing steps for semiconductor device 100H can be reduced compared to semiconductor device 100A. On the other hand, semiconductor device 100A has insulating layer 110b1, which allows it to have more layers capable of supplying oxygen to semiconductor layer 108n and semiconductor layer 108p than semiconductor device 100H. Therefore, semiconductor device 100A can supply more oxygen to semiconductor layer 108n and semiconductor layer 108p than semiconductor device 100H.

[0292] Regarding semiconductor device 100H, other than the points mentioned above, you can refer to the content explained in semiconductor device 100A.

[0293] <Example of semiconductor device configuration 9> Figure 9B shows an example of a semiconductor device 100I with a configuration different from that of the semiconductor device 100A shown in Figures 1A and 1B. Figure 9B is a cross-sectional view of the semiconductor device 100I corresponding to the dashed line A1-A2 of the semiconductor device 100A shown in Figure 1A.

[0294] The semiconductor device 100I includes a transistor 10In, a transistor 10Ip, an insulating layer 110_1, an insulating layer 110_2, and an insulating layer 195.

[0295] In semiconductor device 100I, transistor 10In corresponds to transistor 10An in semiconductor device 100A, and in semiconductor device 100I, transistor 10Ip corresponds to transistor 10Ap in semiconductor device 100A.

[0296] The semiconductor device 100I differs from the semiconductor device 100A in the configuration of the insulating layer sandwiched between the conductive layers 112an and 112ap and the conductive layer 112b.

[0297] As shown in Figure 9B, the semiconductor device 100I has a configuration in which only a single-layer insulating layer 110a is provided between the conductive layers 112an and 112ap and the conductive layer 104, and only a single-layer insulating layer 110c is provided between the conductive layer 104 and the conductive layer 112b.

[0298] In semiconductor device 100I, insulating layer 110a and insulating layer 110c can each be made of the same material used for insulating layer 110a1, insulating layer 110c1, insulating layer 110a2, and insulating layer 110c2 in semiconductor device 100A. That is, a material that does not easily permeate oxygen can be used. As a result, in semiconductor device 100I, oxygen is not supplied from insulating layer 110a and insulating layer 110c to semiconductor layer 108n and semiconductor layer 108p. However, by using an oxygen-releasing material (for example, the same material as insulating layer 110b1 and insulating layer 110b2 in semiconductor device 100A) for both insulating layer 106n in contact with semiconductor layer 108n and insulating layer 106p in contact with semiconductor layer 108p, oxygen can be supplied from insulating layer 106n to semiconductor layer 108n and from insulating layer 106p to semiconductor layer 108p, respectively.

[0299] The semiconductor device 100I has a configuration in which only one insulating layer is provided between the conductive layer 112an and conductive layer 112ap and conductive layer 104, and between conductive layer 104 and conductive layer 112b. Therefore, the number of manufacturing steps for the semiconductor device can be reduced compared to the semiconductor device 100A, which has a configuration in which three insulating layers are provided in each of these locations.

[0300] Regarding semiconductor device 100I, other than the points mentioned above, you can refer to the content described in semiconductor device 100A.

[0301] <Example of Semiconductor Device Configuration 10> Figures 10A and 10B show an example of the configuration of a semiconductor device 100J, which has a different configuration from the semiconductor device 100A shown in Figures 1A and 1B. Figure 10A is a plan view of the semiconductor device 100J. Figure 10B is a cross-sectional view of the semiconductor device 100J along the dashed line A1-A2 shown in Figure 10A. Figure 10C shows an equivalent circuit diagram of the semiconductor device 100J.

[0302] The semiconductor device 100J includes a transistor 10Jn, a transistor 10JP, an insulating layer 110_1, an insulating layer 110_2, and an insulating layer 195.

[0303] In semiconductor device 100J, transistor 10Jn corresponds to transistor 10An in semiconductor device 100A, and transistor 10Jp in semiconductor device 100J corresponds to transistor 10Ap in semiconductor device 100A.

[0304] The semiconductor device 100J has a different configuration of the conductive layer that functions as the source electrode or drain electrode of the transistor compared to the semiconductor device 100A.

[0305] As shown in Figure 1B and the like, the semiconductor device 100A has a configuration in which two conductive layers (conductive layer 112an and conductive layer 112ap) are provided on the substrate 102, which function as either the source electrode or the drain electrode of the transistors (transistor 10An and transistor 10Ap), and only one conductive layer (conductive layer 112b) is provided on the insulating layer 110_2, which functions as the other source electrode or drain electrode of the transistors.

[0306] In contrast, the semiconductor device 100J, as shown in Figure 10B, has a configuration in which only one conductive layer (conductive layer 112a) is provided on the substrate 102, which functions as either the source electrode or the drain electrode of the transistors (transistors 10Jn and 10Jp), and two conductive layers (conductive layer 112bn and conductive layer 112bp) are provided on the insulating layer 110_2, which function as either the source electrode or the drain electrode of the transistors.

[0307] The A1-side surfaces of the insulating layer 110_1, the conductive layer 104, the insulating layer 110_2, and the conductive layer 112bn are aligned (or, in a plan view, their respective A1-side edges are aligned), and the insulating layer 106n is provided in contact with these surfaces. The upper end of the insulating layer 106n has a curved shape. The semiconductor layer 108n has regions that are in contact with the A1-side upper surface of the conductive layer 112a, the surface of the insulating layer 106n (including the curved portion), and the upper surface of the conductive layer 112bn.

[0308] The A2-side surfaces of the insulating layer 110_1, the conductive layer 104, the insulating layer 110_2, and the conductive layer 112bp are aligned (or, in a plan view, the A2-side ends of each are aligned), and the insulating layer 106p is provided in contact with these surfaces. The upper end of the insulating layer 106p has a curved shape. The semiconductor layer 108p has regions that are in contact with the A2-side upper surface of the conductive layer 112a, the surface of the insulating layer 106p (including the curved portion), and the upper surface of the conductive layer 112bp.

[0309] The insulating layer 195 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108n, the upper and side surfaces of the semiconductor layer 108p, the upper and side surfaces of the conductive layer 112bn, the upper and side surfaces of the conductive layer 112bp, the upper surface of the conductive layer 112a, and the upper surface of the insulating layer 110_2.

[0310] In the semiconductor device 100J, the conductive layer 112a functions as either the source electrode or the drain electrode of transistor 10Jn, and also functions as either the source electrode or the drain electrode of transistor 10JPp. The conductive layer 112bn functions as the other source electrode or drain electrode of transistor 10Jn. The conductive layer 112bp functions as the other source electrode or drain electrode of transistor 10JPp.

[0311] Even with a configuration like semiconductor device 100J, the overall circuit configuration of the semiconductor device is the same as that of semiconductor device 100A (see Figures 1C and 10C). Thus, in one aspect of the present invention, as long as the overall circuit configuration of the semiconductor device remains unchanged, it can be configured like semiconductor device 100A or like semiconductor device 100J. This increases the degree of freedom in manufacturing semiconductor devices.

[0312] Furthermore, the conductive layer 112a in semiconductor device 100J can be made of the same material as the conductive layer 112an and conductive layer 112ap in semiconductor device 100A. Also, the conductive layer 112bn and conductive layer 112bp in semiconductor device 100J can be made of the same material as the conductive layer 112b in semiconductor device 100A.

[0313] Regarding semiconductor device 100J, other than the points mentioned above, you can refer to the content described in semiconductor device 100A.

[0314] <Example of semiconductor device configuration 11> Figures 11A and 11B show an example of a semiconductor device 100K with a configuration different from that of the semiconductor device 100A shown in Figures 1A and 1B. Figure 11A is a plan view of the semiconductor device 100K. Figure 11B is a cross-sectional view of the semiconductor device 100K along the dashed line A1-A2 shown in Figure 11A. Figure 11C shows an equivalent circuit diagram of the semiconductor device 100K.

[0315] The semiconductor device 100K includes a transistor 10Kn, a transistor 10Kp, and an insulating layer 110.

[0316] In semiconductor device 100K, transistor 10Kn corresponds to transistor 10An in semiconductor device 100A, and transistor 10Kp in semiconductor device 100K corresponds to transistor 10Ap in semiconductor device 100A.

[0317] The semiconductor device 100K differs from the semiconductor device 100A in the configuration of the insulating layer that functions as the gate insulating layer of the transistor, and the configuration of the conductive layer that functions as the gate electrode of the transistor.

[0318] In the semiconductor device 100A, as shown in Figure 1B and the like, a conductive layer 104 that functions as the gate electrode of a transistor (transistor 10An and transistor 10Ap) is provided sandwiched between the source electrode and drain electrode of the transistor (between conductive layer 112an and conductive layer 112b, and between conductive layer 112ap and conductive layer 112b) via two insulating layers (insulating layer 110_1 and insulating layer 110_2). In addition, insulating layers (insulating layer 106n and insulating layer 106p) that function as the gate insulating layer of the transistor are provided on the underside of the semiconductor layer (semiconductor layer 108n and semiconductor layer 108p). Furthermore, the gate insulating layer is provided independently for each transistor.

[0319] In contrast, in semiconductor device 100K, as shown in Figure 11B, an insulating layer 106 that functions as a gate insulating layer for transistors (transistor 10Kn and transistor 10Kp) is provided so as to cover the upper surfaces of both semiconductor layer 108n and semiconductor layer 108p. Also, on the insulating layer 106, a conductive layer 104 that functions as a gate electrode for transistors is provided so as to cover the upper surfaces of both semiconductor layer 108n and semiconductor layer 108p. Furthermore, in semiconductor device 100K, the insulating layer 110 sandwiched between the source electrode and drain electrode of the transistor (between conductive layer 112an and conductive layer 112b, and between conductive layer 112ap and conductive layer 112b) has a three-layer stacked structure consisting of insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b. Also, semiconductor device 100K does not have the insulating layer 195 that semiconductor device 100A has.

[0320] In semiconductor device 100K, semiconductor layer 108n has regions that are in contact with the upper surface of conductive layer 112an, the A1-side surface of insulating layer 110, the A1-side surface of conductive layer 112b, and a portion of the upper surface of conductive layer 112b. Semiconductor layer 108p has regions that are in contact with the upper surface of conductive layer 112ap, the A2-side surface of insulating layer 110, the A2-side surface of conductive layer 112b, and another portion of the upper surface of conductive layer 112b. Insulating layer 106 has regions that are in contact with the upper and side surfaces of semiconductor layer 108n, the upper and side surfaces of semiconductor layer 108p, the upper surface of conductive layer 112an, the upper surface of conductive layer 112ap, and the upper surface of conductive layer 112b (the upper surface of the region where semiconductor layers 108n and 108p are not provided). Conductive layer 104 has a region that is in contact with the upper surface of insulating layer 106. The conductive layer 104 has regions that overlap with the conductive layer 112b via the semiconductor layer 108n and the insulating layer 106, and via the semiconductor layer 108p and the insulating layer 106.

[0321] In the semiconductor layer 108n, the region overlapping with the A1 side surface of the insulating layer 110 faces the conductive layer 104 via the insulating layer 106. Similarly, in the semiconductor layer 108p, the region overlapping with the A2 side surface of the insulating layer 110 faces the conductive layer 104 via the insulating layer 106.

[0322] Even with a configuration like semiconductor device 100K, the overall circuit configuration of the semiconductor device is the same as that of semiconductor device 100A (see Figures 1C and 11C). Thus, in one aspect of the present invention, as long as the overall circuit configuration of the semiconductor device remains the same, it can be configured like semiconductor device 100A or like semiconductor device 100K. This increases the degree of freedom in manufacturing semiconductor devices.

[0323] Furthermore, the insulating layer 106 in semiconductor device 100K can be made of the same material as insulating layer 106n and insulating layer 106p in semiconductor device 100A. Also, the insulating layer 110a and insulating layer 110c in semiconductor device 100K can be made of the same material as insulating layer 110a1, insulating layer 110c1, insulating layer 110a2, and insulating layer 110c2 in semiconductor device 100A. In addition, the insulating layer 110b in semiconductor device 100K can be made of the same material as conductive layer 110b1 and insulating layer 110b2 in semiconductor device 100A.

[0324] Regarding semiconductor device 100K, other than the points mentioned above, you can refer to the content described in semiconductor device 100A.

[0325] <Example of semiconductor device configuration 12> Figures 12A and 12B show an example of a semiconductor device 100L with a configuration different from that of the semiconductor device 100K shown in Figures 11A and 11B. Figure 12A is a plan view of the semiconductor device 100L. Figure 12B is a cross-sectional view of the semiconductor device 100L along the dashed line A1-A2 shown in Figure 12A. Figure 12C shows an equivalent circuit diagram of the semiconductor device 100L.

[0326] The semiconductor device 100L includes a transistor 10Ln, a transistor 10Lp, and an insulating layer 110.

[0327] In semiconductor device 100L, transistor 10Ln corresponds to transistor 10Kn in semiconductor device 100K, and transistor 10Lp in semiconductor device 100L corresponds to transistor 10Kp in semiconductor device 100K.

[0328] The semiconductor device 100L has a different configuration of the conductive layer that functions as the source electrode or drain electrode of the transistor compared to the semiconductor device 100K.

[0329] As shown in Figure 11B, the semiconductor device 100K has a configuration in which two conductive layers (conductive layer 112an and conductive layer 112ap) are provided on the substrate 102, which function as either the source electrode or the drain electrode of the transistors (transistor 10Kn and transistor 10Kp), and only one conductive layer (conductive layer 112b) is provided on the insulating layer 110, which functions as either the source electrode or the drain electrode of the transistors.

[0330] In contrast, the semiconductor device 100L, as shown in Figure 12B, has a configuration in which only one conductive layer (conductive layer 112a) is provided on the substrate 102, which functions as either the source electrode or the drain electrode of the transistors (transistor 10Ln and transistor 10Lp), and two conductive layers (conductive layer 112bn and conductive layer 112bp) are provided on the insulating layer 110, which function as either the source electrode or the drain electrode of the transistors.

[0331] In the semiconductor device 100L, the conductive layer 112a functions as either the source electrode or the drain electrode of transistor 10Ln, and also functions as either the source electrode or the drain electrode of transistor 10Lp. The conductive layer 112bn functions as the other source electrode or drain electrode of transistor 10Ln. The conductive layer 112bp functions as the other source electrode or drain electrode of transistor 10Lp.

[0332] Even with a configuration like semiconductor device 100L, the overall circuit configuration of the semiconductor device is no different from that of semiconductor device 100A, semiconductor device 100K, etc. (see Figures 1C, 11C, and 12C). Thus, in one aspect of the present invention, as long as the overall circuit configuration of the semiconductor device does not change, it can be configured like semiconductor device 100A, semiconductor device 100K, or semiconductor device 100L. This increases the degree of freedom in manufacturing semiconductor devices.

[0333] Regarding semiconductor device 100L, other than the points mentioned above, you can refer to the contents described for semiconductor device 100K and semiconductor device 100A, respectively.

[0334] <Example of Semiconductor Device Manufacturing Method> Below, an example of a semiconductor device manufacturing method according to one aspect of the present invention will be described with reference to the drawings. Here, the semiconductor device 100A shown in Figures 1A to 1C will be used as an example.

[0335] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0336] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0337] CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. Furthermore, depending on the source gas used, they can be divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD).

[0338] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices can become charged by receiving charge from the plasma. This accumulated charge can damage the wiring, electrodes, or components in the semiconductor device. In contrast, thermal CVD, which does not use plasma, avoids this plasma damage, resulting in a higher yield for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0339] As ALD methods, thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants, can be used.

[0340] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable, for example, for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0341] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers, because time required for transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0342] Furthermore, the ALD method allows for the deposition of films of any composition by using multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0343] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0344] Thin films constituting semiconductor devices can be processed using methods such as photolithography. In addition, thin films can also be processed using nanoimprint lithography, sandblasting, and lift-off methods. Furthermore, island-like thin films can be directly formed using deposition methods that utilize shielding masks such as metal masks.

[0345] Photolithography typically involves two main methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, followed by exposure and development, to process the thin film into the desired shape.

[0346] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0347] For etching thin films, methods such as dry etching, wet etching, or sandblasting can be used.

[0348] For planarization of thin films, polishing methods such as the CMP method are typically suitable. Alternatively, the reflow method, which involves heat treatment of the conductive layer to fluidize it, can also be suitably used. Furthermore, a combination of the reflow method and the CMP method can be employed.

[0349] Furthermore, a process can be used in which a planarization film is formed on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching (e.g., dry etching) on ​​the planarization film, or a process in which a planarization film and a photoresist are formed in that order on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching on the planarization film and the photoresist, thereby filling only the planarization film into the depressions and flattening the entire top surface (these processes are sometimes called etch-back processes). When using an etch-back process, high-temperature heating treatment (e.g., around 800°C) like that of the reflow method is not required, so there is no need to worry about damage to the device during fabrication caused by such heating treatment. In addition, an etch-back process is suitable because it can be applied to devices on large substrates that are difficult to process with the CMP method due to the effects of bending, etc.

[0350] Other thin film planarization processes that can be used include dry etching and plasma treatment. Polishing, dry etching, and plasma treatment can be performed multiple times, or they can be combined. When combining these processes, the order of the steps is not particularly limited and can be appropriately set according to the surface irregularities of the workpiece.

[0351] To precisely process a thin film to a desired thickness, for example, the CMP method can be used. In this method, first, the thin film is polished at a constant processing speed until a portion of its upper surface is exposed. Then, by polishing at a slower processing speed until the thin film reaches the desired thickness, high-precision processing becomes possible.

[0352] Methods for detecting the end point of polishing include optical methods that involve irradiating the surface of the workpiece with light and detecting changes in the reflected light, physical methods that involve detecting changes in the polishing resistance that the processing equipment receives from the workpiece, and methods that use changes in magnetic field lines caused by eddy currents generated when magnetic field lines are applied to the workpiece.

[0353] After the upper surface of the thin film is exposed, the thickness of the thin film can be precisely controlled by performing a polishing process at a slow processing speed while monitoring its thickness using an optical method such as a laser interferometer. If necessary, the polishing process can be repeated multiple times until the thin film reaches the desired thickness.

[0354] Figures 13A to 21B illustrate the method for manufacturing the semiconductor device 100A. Figure (A) in each figure shows a plan view corresponding to Figure 1A. Figure (B) in each figure shows a cross-sectional view along the dashed line A1-A2 in the plan view shown in Figure 1A.

[0355] First, conductive films that will become conductive layers 112an and 112ap are formed on the substrate 102, and then a portion of the conductive film is removed to form conductive layers 112an and 112ap, respectively (Figures 13A and 13B). For example, sputtering can be used to form the conductive films. In addition, either or both of the wet etching method and the dry etching method can be used to process the conductive films.

[0356] Next, insulating films 110a1f, 110b1f, and 110c1f are formed on the conductive layer 112an, the conductive layer 112ap, and the substrate 102 in this order.

[0357] For the insulating film 110a1f, any material that can be used for the insulating layer 110a1 described above can be used as appropriate.

[0358] As the insulating film 110a1f, for example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide can be suitably used.

[0359] Specifically, as the insulating film 110a1f, silicon nitride can be deposited using, for example, a sputtering method. Alternatively, silicon nitride can be deposited using, for example, a PEALD method. Alternatively, aluminum oxide can be deposited using, for example, a sputtering method.

[0360] Furthermore, for example, a configuration in which aluminum oxide and silicon nitride are layered can be used. For instance, aluminum oxide deposited using the sputtering method and silicon nitride deposited using the PEALD method can be used in a layered configuration.

[0361] The insulating film 110b1f can be made from any of the materials that can be used for the insulating layer 110b1 described above.

[0362] For example, silicon oxide, silicon oxide, silicon nitride, and the like can be suitably used as the insulating film 110b1f.

[0363] Specifically, as the insulating film 110b1f, silicon oxide can be deposited using, for example, a sputtering method. Alternatively, silicon oxide can be deposited using, for example, a PECVD method. Alternatively, silicon oxynitride can be deposited using, for example, a PECVD method.

[0364] Furthermore, for example, silicon oxide deposited using the sputtering method and silicon oxide or silicon oxidnitride deposited using the PECVD method can be used in a layered configuration.

[0365] Furthermore, after forming the insulating film 110b1f, a process (such as CMP treatment) can be performed to flatten the upper surface of the insulating film 110b1f. This eliminates any steps that occur on the insulating film 110b1f due to the conductive layer 112an or the conductive layer 112ap, thereby improving the coverage of structures later provided on the upper layer of the semiconductor device 100A.

[0366] On the other hand, if the step created on the insulating film 110b1f due to the conductive layer 112an or the conductive layer 112ap does not pose a problem in subsequent processes, the process of flattening the upper surface of the insulating film 110b1f may be omitted. In this case, the number of processes involved in the manufacture of the semiconductor device can be reduced compared to when the above process is performed.

[0367] The insulating film 110b1f can also be subjected to heat treatment after it has been formed. By performing heat treatment, water and hydrogen can be removed from the surface and within the insulating film 110b1f.

[0368] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate 102, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can also be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a very low content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 110b1f as much as possible. Heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. Using an RTA device can shorten the heat treatment time.

[0369] After the above heat treatment, a step of supplying oxygen to the insulating film 110b1f can also be performed. For example, after the insulating film 110b1f is formed, a metal oxide layer can be formed on the insulating film 110b1f to supply oxygen to the insulating film 110b1f. Alternatively, the heat treatment can be performed after the formation of the metal oxide layer. By performing the heat treatment after the formation of the metal oxide layer, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110b1f, and oxygen can be contained in the insulating film 110b1f. The oxygen supplied to the insulating film 110b1f is then supplied to the semiconductor layer 108n and the semiconductor layer 108p in a later step, thereby creating oxygen vacancies (V) in the semiconductor layer 108n and the semiconductor layer 108p, respectively. Ｏ ) and V Ｏ H can be reduced.

[0370] After forming the metal oxide layer, or after the aforementioned heat treatment, oxygen can be further supplied to the insulating film 110b1f through the metal oxide layer. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. As the plasma treatment, a device that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that convert gas into plasma using high-frequency power include plasma etching devices and plasma ashing devices.

[0371] The metal oxide layer may be an insulating layer or a conductive layer. The metal oxide layer may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0372] It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108n or semiconductor layer 108p as the metal oxide layer. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108n or semiconductor layer 108p. This allows, for example, when forming the semiconductor film that will become the semiconductor layer 108n or semiconductor layer 108p using a sputtering method, the metal oxide layer can be formed using the same sputtering target as the semiconductor layer 108n or semiconductor layer 108p, thereby reducing manufacturing costs.

[0373] When using a metal oxide material containing indium and gallium in the metal oxide layer, a material with a higher gallium composition (content) than the semiconductor layer 108n or semiconductor layer 108p can be used. By using a material with a higher gallium composition (content) in the metal oxide layer, the barrier properties against oxygen can be further enhanced. This is preferable because it can suppress the detachment of oxygen contained in the insulating film 110b1f to the outside.

[0374] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferable to form it by sputtering in an atmosphere containing oxygen. This allows for a suitable supply of oxygen to the insulating film 110b1f during the formation of the metal oxide layer.

[0375] Next, the metal oxide layer is removed. For example, a wet etching method can be suitably used to remove the metal oxide layer.

[0376] The process of supplying oxygen to the insulating film 110b1f is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc., can be supplied to the insulating film 110b1f by ion doping, ion implantation, plasma treatment, etc. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110b1f, and then oxygen can be supplied to the insulating film 110b1f through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.

[0377] For the insulating film 110c1f, any material that can be used for the insulating layer 110c1 described above can be used as appropriate.

[0378] For materials and film formation methods that can be used for the insulating film 110c1f, refer to the description of materials and film formation methods that can be used for the insulating film 110a1f mentioned above.

[0379] Next, a conductive film 104f is formed on the insulating film 110c1f. The conductive film 104f can be made from any material that can be used for the conductive layer 104 described above. Furthermore, for the formation of the conductive film 104f, methods such as sputtering, CVD, molecular beam epitaxy (MBE), PLD, and ALD can be used as appropriate.

[0380] Next, insulating films 110a2f, 110b2f, and 110c2f are formed on the conductive film 104f in this order.

[0381] For the insulating film 110a2f, any material that can be used for the insulating layer 110a2 described above may be used as appropriate. For the insulating film 110b2f, any material that can be used for the insulating layer 110b2 described above may be used as appropriate. For the insulating film 110c2f, any material that can be used for the insulating layer 110c2 described above may be used as appropriate.

[0382] For the method of forming the insulating film 110a2f, insulating film 110b2f, and insulating film 110c2f, refer to the description above relating to the method of forming the insulating film 110a1f, insulating film 110b1f, and insulating film 110c1f.

[0383] After forming the insulating film 110b2f, a process to flatten the upper surface of the insulating film 110b2f (such as CMP processing) can be performed. However, this process is not required.

[0384] A heat treatment can also be performed after the insulating film 110b2f has been formed. For details of this heat treatment, refer to the description of the heat treatment that can be performed after the formation of the insulating film 110b1f mentioned above.

[0385] After the above heat treatment, a step of supplying oxygen to the insulating film 110b2f may also be performed. For details of this step, refer to the description of the oxygen supply step that can be performed on the insulating film 110b1f mentioned above.

[0386] Next, a conductive film 112bf is formed on the insulating film 110c2f (Figures 14A and 14B). The conductive film 112bf can be made from any material that can be used for the conductive layer 112b described above. Furthermore, for the formation of the conductive film 112bf, for example, a sputtering method can be used.

[0387] Next, a portion of each of the conductive film 112bf, insulating film 110c2f, insulating film 110b2f, insulating film 110a2f, conductive film 104f, insulating film 110c1f, insulating film 110b1f, and insulating film 110a1f is removed to form the conductive layer 112b, insulating layer 110_2 (insulating layer 110c2, insulating layer 110b2, and insulating layer 110a2), conductive layer 104, and insulating layer 110_1 (insulating layer 110c1, insulating layer 110b1, and insulating layer 110a1) (Figures 15A and 15B).

[0388] The conductive layer 112b, insulating layer 110_2, conductive layer 104, and insulating layer 110_1 are formed to have regions that overlap with conductive layer 112an and conductive layer 112ap, respectively. Wet etching and / or dry etching can be used to process the conductive film 112bf, insulating film 110c2f, insulating film 110b2f, insulating film 110a2f, conductive film 104f, insulating film 110c1f, insulating film 110b1f, and insulating film 110a1f. This processing forms strip-shaped conductive layers 112b, insulating layer 110_2, conductive layer 104, and insulating layer 110_1 with substantially matching upper surface shapes. Furthermore, this processing exposes the upper surfaces of conductive layer 112an and conductive layer 112ap in regions that do not overlap with conductive layer 112b, insulating layer 110_2, conductive layer 104, and insulating layer 110_1.

[0389] Next, an insulating film 106f is formed in contact with the upper surface of the conductive layer 112an, the upper surface of the conductive layer 112ap, the side surface of the insulating layer 110_1, the side surface of the conductive layer 104, the side surface of the insulating layer 110_2, and the upper and side surfaces of the conductive layer 112b (Figures 16A and 16B). The insulating film 106f can be made from materials that can be used for the insulating layer 106n and insulating layer 106p as described above. For forming the insulating film 106f, for example, the PECVD method, the sputtering method, or the ALD method can be suitably used. By using the ALD method, the insulating film 106f can be formed with good coverage on the side surfaces of the insulating layer 110_1, the conductive layer 104, the insulating layer 110_2, and the side surface of the conductive layer 112b.

[0390] Next, insulating layers 106n and 106p are formed by etching away a portion of the insulating film 106f (Figures 17A and 17B). Specifically, a portion of the insulating film 106f (the region in contact with the upper surface of the conductive layer 112an, the region in contact with the upper surface of the conductive layer 112ap, and the region in contact with the upper surface of the conductive layer 112b) is removed by etching. Then, by leaving only the regions of the insulating film 106f that are in contact with the side surfaces of insulating layer 110_1, conductive layer 104, insulating layer 110_2, and conductive layer 112b, insulating layers 106n and 106p can be formed. Note that, as shown in Figure 17B, the etching may result in the upper ends of insulating layers 106n and 106p becoming curved.

[0391] For etching the insulating film 106f, for example, anisotropic etching can be used. More specifically, for example, by performing highly anisotropic etching in dry etching, the insulating layer 106n and the insulating layer 106p can be formed.

[0392] By changing the anisotropic etching conditions, the height of the upper end of the insulating layer 106n (and insulating layer 106p) can be adjusted, as shown in Figures 4A to 4D.

[0393] Next, a semiconductor film 108nf is formed in contact with the upper surface of the conductive layer 112an, the surface of the insulating layer 106n (including the curved portion), the upper surface of the conductive layer 112b, the surface of the insulating layer 106p (including the curved portion), and the upper surface of the conductive layer 112ap (Figures 18A and 18B).

[0394] For the semiconductor film 108nf, any material that can be used for the semiconductor layer 108n described above can be used as appropriate.

[0395] For example, sputtering can be used to form the semiconductor film 108nf. For instance, when a metal oxide is used for the semiconductor layer 108n, it can be formed by sputtering using a metal oxide target. Sputtering is preferable because it allows for the relatively easy formation of films with low hydrogen content.

[0396] Further, when a metal oxide is used for the semiconductor layer 108n, the semiconductor layer can also be formed by an ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0397] For example, when forming an In-Ga-Zn oxide, three precursors, namely a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used. Alternatively, two precursors, namely a precursor containing indium and a precursor containing gallium and zinc, can also be used.

[0398] As the precursor containing indium, triethylindium, indium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cyclopentadienyl indium, indium(III) chloride, and the like can be used.

[0399] Further, as the precursor containing gallium, trimethylgallium, triethylgallium, gallium trichloride, gallium(III) tris(dimethylamide), gallium(III) acetylacetonate, gallium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchlorogallium, diethylchlorogallium, and the like can be used.

[0400] Further, as the precursor containing zinc, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, and the like can be used.

[0401] As the oxidizing agent, for example, ozone, oxygen, water, and the like can be used.

[0402] Examples of methods for controlling the composition of the obtained film include adjusting the flow rate ratio of raw material gases, the duration for flowing raw material gases, the order of flowing raw material gases, and the like. Further, by adjusting these conditions, a film with a continuously varying composition can be formed. It is also possible to continuously form films having different compositions.

[0403] Use of the ALD method for forming the semiconductor film 108nf is preferable because the semiconductor layer 108n can be formed on the side surface of the insulating layer 110 with a uniform thickness.

[0404] Furthermore, when silicon is used for the semiconductor layer 108n, the semiconductor film 108nf can be formed by a PECVD method.

[0405] When an amorphous silicon film is formed as the semiconductor film 108nf, it is preferable to perform heat treatment or laser light irradiation after the semiconductor film 108nf is formed. Thereby, the semiconductor film 108nf can be crystallized.

[0406] Note that in the case where a silicon film having crystallinity from the beginning is formed as the semiconductor film 108nf, the above crystallization treatment does not necessarily need to be performed.

[0407] When silicon is used for the semiconductor layer 108n, a treatment of adding a p-type impurity (acceptor) or an n-type impurity (donor) to the semiconductor film 108nf (hereinafter also referred to as channel doping) can be performed after the crystallization treatment (or after forming the semiconductor film 108nf). Channel doping can be selectively performed on the entire semiconductor film 108nf or a part of the semiconductor film 108nf by a method such as an ion implantation method, an ion doping method, or the like. Examples of elements contained in the p-type impurity include boron, aluminum, gallium, and the like. Examples of elements contained in the n-type impurity include phosphorus, arsenic, and the like. The type of impurity used for channel doping is preferably appropriately selected according to the electrical characteristics required for the transistor 10An. Threshold voltage of the transistor 10An can be adjusted by performing channel doping. Note that channel doping does not need to be performed if it is not required.

[0408] Subsequently, in the semiconductor film 108nf, it is preferable to perform a treatment of adding an n-type impurity such as phosphorus or arsenic (hereinafter also referred to as n+ doping) to regions that will later become the source region and the drain region of the transistor 10An (specifically, a region in contact with the top surface of the conductive layer 112an and a region in contact with the top surface of the conductive layer 112b in the semiconductor film 108nf). For example, PH ３ gas or the like is used as a source gas, and phosphorus can be added to the region by using a method such as an ion implantation method, an ion doping method, or the like.

[0409] As described above, the transistor in one embodiment of the present invention has a vertical transistor structure. Therefore, for example, by doping the semiconductor film 108nf with n+ from a direction perpendicular to the substrate surface, the regions that will later become the source and drain regions of the transistor 10An can be made n-type in particular. When using ion implantation, ion doping, etc., it is preferable to appropriately adjust various conditions such as the dose amount of n-type impurity to be added and the acceleration voltage during addition, depending on the composition, density, film thickness of the semiconductor film 108nf, the electrical characteristics to be obtained for the transistor 10An, etc.

[0410] n+ doping can also be performed after the semiconductor film 108nf has been processed into a semiconductor layer 108n.

[0411] Furthermore, n+ doping can also be performed via the insulating layer 195 after forming the insulating layer 195, which functions as a protective layer for transistors 10An and 10Ap.

[0412] Furthermore, when forming an n-type semiconductor film from the outset as the semiconductor film 108nf, it may not be necessary to perform n+ doping.

[0413] Next, it is preferable to perform an activation treatment. As the activation treatment, heat treatment or laser irradiation can be used. The activation treatment can lower the electrical resistance of the region of the semiconductor film 108nf (or semiconductor layer 108n) to which n-type impurities have been added, repair defects in the semiconductor film 108nf (or semiconductor layer 108n) that occurred during the addition of impurities, and restore crystallinity. Furthermore, when heat treatment is used as the activation treatment, oxygen can also be supplied to the semiconductor film 108nf (or semiconductor layer 108n) from the insulating layer 110. Note that the activation treatment can also be combined with a subsequent heat treatment or a process that applies heat. Furthermore, the activation treatment can be a combination of heat treatment and laser irradiation.

[0414] Even when a metal oxide is used as the semiconductor layer 108n, it is preferable to perform a heat treatment after the formation of the semiconductor film 108nf. This heat treatment reduces the amount of water and hydrogen contained in the semiconductor film 108nf and allows oxygen to be supplied to the semiconductor film 108nf from the insulating layer 110. This heat treatment can also be performed after the semiconductor film 108nf has been processed into the semiconductor layer 108n.

[0415] When a metal oxide is used as the semiconductor layer 108n, the substrate temperature (stage temperature) during the formation of the semiconductor film 108nf is preferably between room temperature (25°C) and 200°C, and more preferably between room temperature and 130°C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when using a large-area glass substrate.

[0416] The higher the substrate temperature during the formation of the metal oxide layer, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the oxygen flow rate ratio, the more crystalline the metal oxide layer can be formed.

[0417] Next, a portion of the semiconductor film 108nf is removed by etching to form a semiconductor layer 108n having regions that overlap with the conductive layer 112an and the conductive layer 112b, respectively (Figures 19A and 19B).

[0418] The semiconductor layer 108n is provided such that it has regions that are in contact with a part of the upper surface of the conductive layer 112an, the surface of the insulating layer 106n (including the curved portion), and a part of the upper surface of the conductive layer 112b.

[0419] Next, a semiconductor film 108pf is formed in contact with the other part of the upper surface of the conductive layer 112an, the upper and side surfaces of the semiconductor layer 108n, another part of the upper surface of the conductive layer 112b, the surface of the insulating layer 106p (including the curved portion), and the upper surface of the conductive layer 112ap (Figures 20A and 20B).

[0420] For the semiconductor film 108pf, any material that can be used for the semiconductor layer 108p described above can be used as appropriate.

[0421] For the formation of the semiconductor film 108pf, methods such as sputtering, ALD, vacuum deposition, or PECVD can be used. For example, when a metal oxide is used for the semiconductor layer 108p, it can be formed by sputtering using a metal oxide target, similar to the semiconductor film 108nf described above. Also, when a metal oxide is used for the semiconductor layer 108p, it can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent, similar to the semiconductor film 108nf described above. Furthermore, when a metal oxide is used for the semiconductor layer 108p, it can also be formed by vacuum deposition.

[0422] Furthermore, when silicon is used for the semiconductor layer 108p, the semiconductor film 108pf can be formed by the PECVD method, similar to the semiconductor film 108nf described above.

[0423] When forming an amorphous silicon film as the semiconductor film 108pf, it is preferable to perform a heat treatment or laser irradiation after the formation of the semiconductor film 108pf. This allows the semiconductor film 108pf to crystallize.

[0424] Furthermore, if a silicon film with crystalline properties is formed from the outset as the semiconductor film 108pf, the above crystallization treatment may not be necessary.

[0425] When silicon is used for the semiconductor layer 108p, channel doping can be performed on the semiconductor film 108pf after the crystallization treatment (or after the formation of the semiconductor film 108pf). For details on channel doping, please refer to the description related to the semiconductor film 108nf mentioned above. Channel doping allows for adjustment of the threshold voltage of the transistor 10Ap. Channel doping can be omitted if it is not necessary.

[0426] Next, it is preferable to perform a process (hereinafter also referred to as p+ doping) in which p-type impurities such as boron, aluminum, and gallium are added to the regions of the semiconductor film 108pf that will later become the source region and drain region of the transistor 10Ap (specifically, the region of the semiconductor film 108pf that is in contact with the upper surface of the conductive layer 112ap and the region that is in contact with the upper surface of the conductive layer 112b). For example, B２ H ６ Gas, or BF ３ Boron can be added to the region in question by using gases or other materials as raw material gases and employing methods such as ion implantation or ion doping.

[0427] As described above, the transistor in one embodiment of the present invention has a vertical transistor structure. Therefore, for example, by performing p+ doping into the semiconductor film 108pf from a direction perpendicular to the substrate surface, the regions that will later become the source and drain regions of the transistor 10Ap can be made p-type in particular. When using ion implantation, ion doping, etc., it is preferable to appropriately adjust various conditions such as the dose amount of p-type impurity to be added and the acceleration voltage during addition, depending on the composition, density, film thickness of the semiconductor film 108pf, the electrical characteristics to be obtained for the transistor 10Ap, etc.

[0428] p+ doping can also be performed after the semiconductor film 108pf has been processed into a semiconductor layer 108p.

[0429] Furthermore, p+ doping can also be performed via the insulating layer 195 after forming the insulating layer 195, which functions as a protective layer for transistors 10An and 10Ap.

[0430] Furthermore, when forming a p-type semiconductor film from the outset as the semiconductor film 108pf, p+ doping may not be necessary.

[0431] Next, it is preferable to perform an activation treatment. For details on the activation treatment, refer to the description of the semiconductor film 108nf mentioned above. The activation treatment can lower the electrical resistance of the region of the semiconductor film 108pf (or semiconductor layer 108p) to which p-type impurities have been added, repair defects in the semiconductor film 108pf (or semiconductor layer 108p) that occurred during the addition of impurities, and restore crystallinity. Furthermore, if heat treatment is used as the activation treatment, oxygen can be supplied to the semiconductor film 108pf (or semiconductor layer 108p) from the insulating layer 110. Note that the activation treatment can also be combined with a subsequent heat treatment or a process in which heat is applied.

[0432] Even when a metal oxide is used as the semiconductor layer 108p, it is preferable to perform heat treatment after forming the semiconductor film 108pf. The heat treatment can reduce water and hydrogen contained in the semiconductor film 108pf, and supply oxygen from the insulating layer 110 to the semiconductor film 108pf. Note that the heat treatment can also be performed after processing the semiconductor film 108pf into the semiconductor layer 108p.

[0433] For the substrate temperature at the time of forming the semiconductor film 108pf when a metal oxide is used as the semiconductor layer 108p, reference can be made to the above description relating to the substrate temperature at the time of forming the semiconductor film 108nf.

[0434] Next, part of the semiconductor film 108pf is removed by etching to form the semiconductor layer 108p having regions overlapping with the conductive layer 112ap and the conductive layer 112b, respectively (FIGS. 21A and 21B).

[0435] The semiconductor layer 108p is provided so as to have regions respectively in contact with part of the upper surface of the conductive layer 112ap, the surface (including the curved portion) of the insulating layer 106p, and another part of the upper surface of the conductive layer 112b.

[0436] Note that although an example in which the semiconductor layer 108n is formed first and then the semiconductor layer 108p is formed is described above, the present invention is not limited thereto. In one embodiment of the present invention, the semiconductor layer 108p may be formed first, and then the semiconductor layer 108n may be formed.

[0437] In addition, although an example in which a semiconductor film is formed twice (formation of the semiconductor film 108nf and formation of the semiconductor film 108pf) to form the semiconductor layer 108n and the semiconductor layer 108p respectively is described above, when silicon is used for both the semiconductor layer 108n and the semiconductor layer 108p, the semiconductor film may be formed only once.

[0438] For example, after forming the semiconductor film 108nf (FIGS. 18A and 18B), a first resist mask is formed in a region other than the region overlapping with the semiconductor layer 108n on the semiconductor film 108nf. Next, the above-described n+ doping is performed on the exposed region of the semiconductor film 108nf (the region where the first resist mask is not formed). After that, the first resist mask is removed.

[0439] Next, a second resist mask is formed on the semiconductor film 108nf, excluding the region that overlaps with the semiconductor layer 108p. Subsequently, the p+ doping described above is performed on the exposed region of the semiconductor film 108nf (the region where the second resist mask is not formed). After that, the second resist mask is removed.

[0440] Subsequently, the areas of the semiconductor film 108nf that do not overlap with the semiconductor layer 108n and the semiconductor layer 108p are removed by etching. This allows the semiconductor layer 108n and the semiconductor layer 108p to be formed (Figures 21A and 21B).

[0441] In this case, the semiconductor layer 108n and semiconductor layer 108p can be formed by performing semiconductor film formation and etching only once each. Therefore, the number of steps required for the overall fabrication of the semiconductor device can be reduced, which is preferable.

[0442] Thus, in one aspect of the present invention, the manufacturing method can be appropriately varied depending on the material used for each of the semiconductor layers 108n and 108p.

[0443] Although the above example shows an example where n+ doping is performed followed by p+ doping, this is not the only option; it is also possible to perform p+ doping followed by n+ doping.

[0444] Furthermore, various treatments such as crystallization after semiconductor film formation, channel doping, and activation treatments after n+ doping and p+ doping can also be performed.

[0445] Next, an insulating layer 195 is formed by covering the semiconductor layer 108n, semiconductor layer 108p, conductive layer 112b, conductive layer 112an, and conductive layer 112ap. The insulating layer 195 has regions that are in contact with the upper and side surfaces of semiconductor layer 108n, the upper and side surfaces of semiconductor layer 108p, the upper and side surfaces of conductive layer 112b, the surface of insulating layer 106n (including the curved portion), the surface of insulating layer 106p (including the curved portion), the upper and side surfaces of conductive layer 112an, the upper and side surfaces of conductive layer 112ap, the side surfaces of insulating layer 110_2, the side surfaces of conductive layer 104, the side surfaces of insulating layer 110_1, and the upper surface of the substrate 102.

[0446] The insulating layer 195 can be made from any of the materials described above as appropriate.

[0447] For example, the ALD method can be used to form the insulating layer 195. The ALD method is preferable because it allows for the formation of the insulating layer 195 with good coverage on the upper surfaces of the semiconductor layer 108n and the semiconductor layer 108p. Furthermore, the ALD method can suppress deposition damage to the semiconductor layer 108n and the semiconductor layer 108p. In addition, if the semiconductor layer 108n and the semiconductor layer 108p can be sufficiently covered, methods other than the ALD method can be used to form the insulating layer 195. For example, the PECVD method or sputtering method can be used. This allows for a faster deposition rate of the insulating layer 195 than when using the ALD method, thereby increasing productivity.

[0448] By following the above steps, a semiconductor device 100A having transistors 10An and 10Ap can be manufactured (Figures 1A and 1B).

[0449] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0450] (Embodiment 2) In this embodiment, an indium oxide film that can be used in the semiconductor layer (semiconductor layer 108n) of an n-channel type transistor, one of the two transistors in a semiconductor device according to one aspect of the present invention, will be described.

[0451] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0452] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0453] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0454] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single-crystal indium oxide.

[0455] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0456] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0457] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0458] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. It is especially preferable to use elements in which the oxide is conductive or semiconducting.

[0459] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0460] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0461] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0462] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0463] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0464] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0465] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0466] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include group 13 elements of the periodic table such as gallium and aluminum, and group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0467] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0468] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0469] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0470] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0471] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10 −２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0472] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0473] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0474] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0475] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0476] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified forms. YbFe ２ O４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0477] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0478] (Embodiment 3) This embodiment describes an example of the configuration and operation of a logic circuit to which a semiconductor device according to one aspect of the present invention can be applied. As described in Embodiment 1, OS transistors and Si transistors can be used for each of the n-channel and p-channel transistors that constitute the semiconductor device according to one aspect of the present invention. Furthermore, vertical transistors can be used for each of the transistors that constitute the semiconductor device. Therefore, a logic circuit to which a semiconductor device according to one aspect of the present invention is applied has a high degree of design freedom and manufacturing freedom, and can also reduce the occupied area.

[0479] Below, we will describe examples of logic circuits using a semiconductor device according to one aspect of the present invention, including configurations of NOT circuits, NOR circuits, and NAND circuits. We will also describe configurations of buffer circuits, ring oscillators, DFF circuits (DFF: Delay Flip Flop, also called D flip-flop circuits), and shift register circuits using DFF circuits.

[0480] [NOT Circuit] Figure 22A is a circuit diagram showing an example of a NOT circuit (NOT). A NOT circuit is also called an inverting circuit or inverter circuit. Figure 22B shows the circuit symbol for a NOT circuit. Figure 22C is a timing chart explaining the operation of a NOT circuit.

[0481] The NOT circuit shown in Figure 22A has transistors Tr11 and Tr12. Transistor Tr11 is a p-channel type transistor, and transistor Tr12 is an n-channel type transistor. That is, the NOT circuit is a CMOS type NOT circuit composed of one n-channel type transistor and one p-channel type transistor. Therefore, the semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to the NOT circuit. A potential H (for example, a high power supply potential VDD) is supplied to either the source or the drain of transistor Tr11. The other source or drain of transistor Tr11 is connected to either the source or the drain of transistor Tr12 and to terminal Y. A potential L (for example, a low power supply potential VSS) is supplied to the other source or drain of transistor Tr12. The gates of transistor Tr11 and transistor Tr12 are connected to terminal A.

[0482] In the NOT gate shown in Figure 22A, terminal A functions as the input terminal and terminal Y functions as the output terminal. When a potential H is input to terminal A, a potential L is output from terminal Y, and when a potential L is input to terminal A, a potential H is output from terminal Y (see Figure 22C).

[0483] Furthermore, as shown in Figure 22C, the NOT circuit has the function of correcting an input signal that has been degraded by wiring resistance, parasitic capacitance, noise, etc., into a signal that is undegraded or has reduced degradation (also called the "waveform shaping function"). The NOT circuit also has the function of amplifying the voltage amplitude of the input signal and outputting it. The output of the NOT circuit is supplied to a load such as a capacitive element Cx or a transistor Trx. Since power is supplied to the output of the NOT circuit via transistor Tr11 or transistor Tr12, the ability to drive the load connected to the output can be increased. The NOT circuit has the function of increasing the ability to drive the load (also called the "driving force improvement function").

[0484] [NOR Circuit] Figure 23A is a circuit diagram showing an example configuration of a 2-input 1-output NOR circuit (NOR). Figure 23B shows the circuit symbol for the NOR circuit. The NOR circuit shown in Figure 23A has transistors Tr21, Tr22, Tr23, and Tr24. Transistors Tr21 and Tr22 are p-channel transistors, and transistors Tr23 and Tr24 are n-channel transistors.

[0485] In Figure 23A, a potential H is supplied to either the source or drain of transistor Tr21. The other source or drain of transistor Tr21 is connected to either the source or drain of transistor Tr22. The other source or drain of transistor Tr22 is connected to either the source or drain of transistor Tr23, either the source or drain of transistor Tr24, and terminal Y. A potential L is supplied to either the source or drain of transistor Tr23 and the other source or drain of transistor Tr24.

[0486] Furthermore, the gate of transistor Tr21 is connected to the gate and terminal A of transistor Tr23. Also, the gate of transistor Tr22 is connected to the gate and terminal B of transistor Tr24.

[0487] The NOR circuit shown in Figures 23A and 23B has the function of outputting a potential H from terminal Y when a potential L is input to both terminals A and B. It also has the function of outputting a potential L from terminal Y when a potential H is input to one or both terminals A and B.

[0488] In the NOR circuit shown in Figure 23A, the portion composed of the combination of transistors Tr22 and Tr24 has a configuration equivalent to that of a CMOS circuit. Therefore, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to this portion.

[0489] Furthermore, as shown in Figure 23C, an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit. The semiconductor device according to one embodiment of the present invention described in Embodiment 1 can also be applied to this NOT circuit.

[0490] [NAND Circuit] Figure 23D is a circuit diagram showing an example configuration of a 2-input, 1-output NAND circuit (NAND). Figure 23E shows the circuit symbol for the NAND circuit. The NAND circuit shown in Figure 23D has transistors Tr31, Tr32, Tr33, and Tr34. Transistors Tr31 and Tr32 are p-channel transistors, and transistors Tr33 and Tr34 are n-channel transistors.

[0491] In Figure 23D, a potential H is supplied to one of the sources or drains of transistor Tr31 and one of the sources or drains of transistor Tr32. The other source or drain of transistor Tr31 and the other source or drain of transistor Tr32 are connected to one of the sources or drains of transistor Tr33 and terminal Y. The other source or drain of transistor Tr33 is connected to one of the sources or drains of transistor Tr34. A potential L is supplied to the other source or drain of transistor Tr34.

[0492] The gate of transistor Tr31 is connected to the gate and terminal B of transistor Tr34. The gate of transistor Tr32 is connected to the gate and terminal A of transistor Tr33.

[0493] The NAND circuits shown in Figures 23D and 23E have the function of outputting a potential L from terminal Y when a potential H is input to both terminals A and B. Furthermore, they have the function of outputting a potential H from terminal Y when a potential L is input to either or both terminals A and B.

[0494] In the NAND circuit shown in Figure 23D, the portion composed of the combination of transistors Tr32 and Tr33 has a configuration equivalent to that of a CMOS circuit. Therefore, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to this portion.

[0495] Furthermore, as shown in Figure 23F, an AND circuit can be realized by combining a NAND circuit with a NOT circuit. The semiconductor device according to one embodiment of the present invention described in Embodiment 1 can also be applied to this NOT circuit.

[0496] [Buffer Circuit] Figure 24A shows the circuit symbol for a buffer circuit. A buffer circuit (BF) can be realized by connecting an even number of NOT gates in series. Figure 24B shows an example of a buffer circuit configuration consisting of two NOT gates. Figure 24C is a timing chart explaining the operation of the buffer circuit.

[0497] In a buffer circuit, no logical operations are performed; instead, the same value as the input logical value is output. Specifically, if a potential H is input, a potential H is output, and if a potential L is input, a potential L is output. Furthermore, like a NOT gate, a buffer circuit has waveform shaping functions (see Figure 24C) and driving force enhancement functions. By using a buffer circuit, it is possible to correct signals that have become distorted and improve the driving force for the load without inverting the signal.

[0498] In the buffer circuit shown in Figure 24B, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to each of the two NOT gates constituting the buffer circuit.

[0499] [Ring Oscillator] A ring oscillator (also called an "oscillating circuit") can be realized by connecting an odd number of NOT gates in a ring. Figure 24D shows an example of a ring oscillator (RO) configuration made up of NOT gates. Figure 24D shows a ring oscillator made up of five NOT gates. A ring oscillator has the function of generating an AC signal (oscillating) when power is supplied. Figure 24E is a diagram illustrating the oscillation of a ring oscillator.

[0500] Generally, in a ring oscillator, the first of the n NOT gates (where n is an odd number greater than or equal to 3) that make up the ring oscillator is sometimes called the "first stage," and the nth gate is sometimes called the "nth stage." A ring oscillator composed of NOT gates has a configuration where the output of each stage's NOT gate is connected to the input of the next stage's NOT gate. Also, the output of the nth stage's NOT gate is connected to the input of the first stage's NOT gate.

[0501] Furthermore, in a NOT gate, a certain delay time occurs before the inverted signal of the input signal is output. Since n is an odd number, the output signal of the first stage is input to the first stage with a delay of n stages. This causes the ring oscillator to oscillate. That is, an AC signal is supplied to terminal Y shown in Figure 24C. By using a ring oscillator, for example, a clock signal can be generated within the circuit. Also, by measuring the oscillation frequency of the ring oscillator, the delay time of the NOT gate can be determined.

[0502] In the ring oscillator shown in Figure 24D, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to each of the five NOT circuits constituting the ring oscillator.

[0503] [DFF Circuit] Figure 25A is a circuit diagram showing an example configuration of a D flip-flop circuit (DFF). Figure 25B shows the circuit symbol for a D flip-flop circuit. A DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0504] The D flip-flop circuit shown in Figure 25A has transistors Tr41 to Tr49, Tr51 to Tr59, Tr61, Tr62, Tr71, and Tr72. Each of the transistors Tr41 to Tr49, Tr61, and Tr62 is a p-channel transistor, and each of the transistors Tr51 to Tr59, Tr71, and Tr72 is an n-channel transistor.

[0505] A potential H is supplied to either the source or drain of transistor Tr41, either the source or drain of transistor Tr42, either the source or drain of transistor Tr44, either the source or drain of transistor Tr46, either the source or drain of transistor Tr48, either the source or drain of transistor Tr61, and either the source or drain of transistor Tr62.

[0506] The source or drain of transistor Tr41 is connected to either the source or drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to the clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0507] The other source or drain of transistor Tr42 is connected to one source or drain of transistor Tr43. The other source or drain of transistor Tr44 is connected to one source or drain of transistor Tr45. The other source or drain of transistor Tr43 is connected to the other source or drain of transistor Tr45, one source or drain of transistor Tr52, one source or drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0508] The other source or drain of transistor Tr52 is connected to one source or drain of transistor Tr53. The other source or drain of transistor Tr54 is connected to one source or drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other source or drain of transistor Tr61, one source or drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other source or drain of transistor Tr46 is connected to one source or drain of transistor Tr47. The other source or drain of transistor Tr48 is connected to one source or drain of transistor Tr49.

[0509] The other source or drain of transistor Tr47 is connected to one source or drain of transistor Tr56, the other source or drain of transistor Tr49, one source or drain of transistor Tr58, the gate of transistor Tr62, and the gate of transistor Tr72. The other source or drain of transistor Tr62 is connected to one source or drain of transistor Tr72, the gate of transistor Tr49, the gate of transistor Tr58, and the output terminal Q.

[0510] The other source or drain of transistor Tr56 is connected to one source or drain of transistor Tr57. The other source or drain of transistor Tr58 is connected to one source or drain of transistor Tr59. A potential L is supplied to the other source or drain of transistor Tr51, the other source or drain of transistor Tr53, the other source or drain of transistor Tr55, the other source or drain of transistor Tr71, the other source or drain of transistor Tr57, the other source or drain of transistor Tr59, and the other source or drain of transistor Tr72.

[0511] The DFF shown in Figures 25A and 25B has the function of writing information (potential) supplied to input terminal D to the DFF when the signal input to clock signal input terminal CK changes from potential L to potential H, and retaining this information until the next time the signal input to clock signal input terminal CK changes from potential L to potential H. In addition, a signal (potential H or potential L) based on the information held by the DFF is always output from output terminal Q.

[0512] In the DFF circuit shown in Figure 25A, the sections composed of the combination of transistors Tr41 and Tr51, Tr43 and Tr52, Tr45 and Tr54, Tr61 and Tr71, Tr47 and Tr56, Tr49 and Tr58, and Tr62 and Tr72 all have configurations equivalent to CMOS circuits. Therefore, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to these sections.

[0513] [Shift Register Circuit] Figure 26A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification, the first stage (first) DFF is indicated as "DFF[1]", and the potential (data) output from the output terminal Q of DFF[1] is indicated as "Data OUT[1]". Figure 26A shows a block diagram of an SR including four stages (four) DFFs (DFF[1] to DFF[4]). In Figure 26A, the data output from the output terminal Q of each of DFF[1] to DFF[4] is indicated as Data OUT[1] to Data OUT[4].

[0514] Figure 26B is a timing chart illustrating the operation of the SR. The clock signal CLK is input to the clock signal input terminal CK of the odd-numbered stage DFFs. The inverted signal of CLK is input to the clock signal input terminal CK of the even-numbered stage DFFs.

[0515] The input terminal D of DFF[1] receives the pulse signal SPL. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the signal CLK and outputs it as dataOUT[1]. The value of dataOUT[1] will be a value corresponding to the data held by DFF[1].

[0516] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with the signal CLK and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0517] Thus, the SR has the function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the signal CLK. In addition, the SR has the function of sequentially switching the potential of the data OUT output from multiple DFFs in synchronization with the signal CLK.

[0518] The shift register circuit shown in Figure 26A can be described as a configuration that combines many DFF circuits shown in Figure 25A and NOT circuits shown in Figure 22A. Therefore, the semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to many parts of the shift register circuit.

[0519] As described above, the larger the logic circuit, such as a DFF circuit or a shift register circuit, the more locations where CMOS circuits can be applied. Therefore, by applying a semiconductor device according to one aspect of the present invention as the CMOS circuit, the effect of reducing the occupied area can be enhanced, especially for larger logic circuits.

[0520] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0521] (Embodiment 4) In this embodiment, an example of applying a semiconductor device according to one aspect of the present invention to a display device will be described with reference to the drawings. The semiconductor device according to one aspect of the present invention can be applied, for example, to the drive circuit of a display device. By applying the semiconductor device according to one aspect of the present invention to a display device, an extremely narrow-bezel display device can be realized.

[0522] <Example of Display Device Configuration> Figure 27 is a block diagram showing an example of the configuration of a display device 11 according to one aspect of the present invention. The display device 11 includes a display unit 20, a scan line driving circuit 12, a signal line driving circuit 13, and a protection circuit 14. The display unit 20 has a plurality of pixels 21 arranged in a matrix.

[0523] The scan line drive circuit 12 is connected to the pixels 21 via wiring 31. The wiring 31 extends, for example, in the row direction of the matrix.

[0524] The signal line drive circuit 13 is connected to the pixel 21 via wiring 33. The wiring 33 extends, for example, in the column direction of the matrix.

[0525] In Figure 27, wiring 31 and wiring 33 are shown as straight lines, but a single straight line does not necessarily represent a single wire; multiple wires may be represented by a single straight line. In subsequent block diagrams, circuit diagrams, etc., multiple wires may also be represented by a single straight line. Furthermore, multiple wires other than wiring 31 and wiring 33 may also be represented by a single straight line.

[0526] Each pixel 21 has a display element (also called a display device), and an image can be displayed on the display unit 20 using the display element. As the display element, for example, a light-emitting element can be used, specifically an organic EL element (also called an organic EL device). Alternatively, a liquid crystal element (also called a liquid crystal device) can be used as the display element. Furthermore, as the display element, a display element using a shutter type or optical interference type MEMS (Micro Electro Mechanical Systems), a microcapsule type, an electrophoretic type, an electrowetting type, or an electronic powder fluid (registered trademark) type can also be used. Additionally, a QLED (Quantum-dot Light Emitting Diode) using a light source and a color conversion technology using quantum dot materials can also be used.

[0527] The scan line drive circuit 12 has a function to select, for example, pixels 21 on which image data is written, row by row. Specifically, the scan line drive circuit 12 can select pixels 21 on which image data is written by outputting a signal to the wiring 31. Here, the scan line drive circuit 12 can select all pixels 21 by outputting the above signal to the wiring 31 of the first row, then to the wiring 31 of the second row, and so on, up to the wiring 31 of the last row. Therefore, the signal that the scan line drive circuit 12 outputs to the wiring 31 is a scan signal, and the wiring 31 can be called a scan line. The scan line drive circuit 12 can be configured to include, for example, a shift register circuit, a level shift circuit, and an analog amplifier circuit.

[0528] The signal line drive circuit 13 has the function of generating image data. The image data is supplied to the pixels 21 via the wiring 33. For example, the image data can be written to all pixels 21 included in the row selected by the scan line drive circuit 12. Here, the image data can be represented as a signal (image signal). Therefore, the wiring 33 can be called a signal line.

[0529] The protection circuit 14 has the function of preventing damage to transistors and other components of pixels 21 when surge voltages, for example, caused by static electricity, are applied to various wirings of the display device 11, such as scan lines and signal lines. For example, it can be configured to discharge the charge to common wiring when a surge voltage is applied. The protection circuit 14 can be composed of nonlinear elements arranged in parallel with the target wiring in between. The nonlinear elements can be composed of two-terminal elements such as diodes or three-terminal elements such as transistors. For example, by connecting the gate terminal and drain terminal of a transistor (also called a diode connection), it can be given characteristics similar to those of a diode.

[0530] <Example of Signal Line Driving Circuit Configuration> Figure 28A is a block diagram showing an example of the configuration of the signal line driving circuit 13 shown in Figure 27. As shown in Figure 28A, it includes a shift register circuit 15, a latch circuit 16, a level shift circuit 17, a digital-to-analog (D-A) conversion circuit 18, and a sampling switch circuit 19.

[0531] The output terminal of the shift register circuit 15 is connected to the input terminal of the latch circuit 16. The output terminal of the latch circuit 16 is connected to the input terminal of the level shift circuit 17. The output terminal of the level shift circuit 17 is connected to the input terminal of the D-A conversion circuit 18. The output terminal of the D-A conversion circuit 18 is connected to the input terminal of the sampling switch circuit 19. The output terminal of the sampling switch circuit 19 is connected to wiring 33, which functions as a signal line. Here, wiring 39 is the wiring that connects the output terminal of the shift register circuit 15 and the input terminal of the latch circuit 16.

[0532] The shift register circuit 15 has the function of generating signals to control the drive of the latch circuit 16. For example, when a start pulse signal is supplied to the shift register circuit 15, a signal to control the drive of the latch circuit 16 is output to the wiring 39.

[0533] The latch circuit 16 has the function of holding or outputting digital image data. Whether the latch circuit 16 holds or outputs the image data is selected based on the signal supplied to the latch circuit 16 from the shift register circuit 15.

[0534] The level shift circuit 17 has the function of changing the potential level of the signal representing the image data output from the latch circuit 16. Specifically, the level shift circuit 17 has the function of changing the potential level of the signal representing the image data output from the latch circuit 16 to a potential level that can be processed by the D-A conversion circuit 18.

[0535] The D-A conversion circuit 18 has the function of converting the digital image data output by the level shift circuit 17 into analog image data and outputting it to the sampling switch circuit 19. For example, the larger the digital value of the image data output by the level shift circuit 17, the larger the potential output to the sampling switch circuit 19 can be.

[0536] The sampling switch circuit 19 has the function of controlling the output of analog image data to the wiring 33. A pulse signal (a signal whose potential changes over time) is supplied to the sampling switch circuit 19, thereby controlling the output of analog image data to the wiring 33.

[0537] Figure 28B is a block diagram showing an example configuration of the signal line drive circuit 13 when the sampling switch circuit 19 shown in Figure 28A is replaced with a selection circuit 25. The selection circuit 25 has a demultiplexer circuit 26. The demultiplexer circuit 26 has one input terminal and two or more output terminals. Different wiring 33 is connected to each of the two or more output terminals of the demultiplexer circuit 26.

[0538] The demultiplexer circuit 26 has the function of outputting analog image data input from the D-A conversion circuit 18 from one of its output terminals. The output terminal from which image data is output is selected by a selection signal input to the demultiplexer circuit 26. For example, if the demultiplexer circuit 26 has a first output terminal and a second output terminal, the potential of the selection signal determines whether the image data supplied to the input terminal of the demultiplexer circuit 26 is output from the first output terminal or the second output terminal.

[0539] The inclusion of a selection circuit 25 in the signal line drive circuit 13 allows for a reduction in the circuit size of the signal line drive circuit 13. Specifically, for example, the number of transistors in the signal line drive circuit 13 can be reduced. Here, if n wires 33 (where n is an integer of 2 or more) are connected to the signal line drive circuit 13, the number of wires 39 can be reduced to less than n. For example, if the demultiplexer circuit 26 has two output terminals, the number of wires 39 can be reduced to n / 2. The demultiplexer circuit 26 can also have three or more output terminals.

[0540] As described above, by having a selection circuit 25 in the signal line drive circuit 13, the area occupied by the signal line drive circuit 13 can be reduced. Therefore, since the signal line drive circuit 13 can be miniaturized, the display device 11 can be made into a smaller display device, and the display device 11 can be made into a display device with a narrow bezel.

[0541] Figure 28C is a circuit diagram showing an example configuration of the shift register circuit 15. The shift register circuit 15 can be configured with multiple register circuits 50 connected in series. In Figure 28C, the four stages of register circuits 50 are indicated as register circuit 50[1], register circuit 50[2], register circuit 50[3], and register circuit 50[4], respectively. Note that a shift register circuit with a configuration similar to that shown in Figure 28C can also be provided in the scan line drive circuit 12.

[0542] The register circuit 50 includes a clocked inverter circuit 51, an inverter circuit 53, a clocked inverter circuit 55, and a NAND circuit 57. The input terminal of the clocked inverter circuit 51 and the first input terminal of the NAND circuit 57 receive signals output from the preceding register circuit 50, specifically the signals output from the inverter circuit 53. The input terminal of the inverter circuit 53 receives signals output from either the clocked inverter circuit 51 or the clocked inverter circuit 55. The signal wave output by the inverter circuit 53 is input to the input terminal of the clocked inverter circuit 51, the input terminal of the clocked inverter circuit 55, and the second input terminal of the NAND circuit 57 of the next-stage register circuit 50. Wiring 39 is connected to the output terminal of the NAND circuit 57.

[0543] A clocked inverter circuit is a circuit in which the output of an inverted signal of the input signal is controlled by a clock signal. Clocked inverter circuits 51 and 55 are controlled by clock signals CLK1 and CLKB1, respectively. Here, clock signal CLKB1 is the inverted signal of clock signal CLK1. That is, when clock signal CLK1 is at a high potential, clock signal CLKB1 is at a low potential, and when clock signal CLK1 is at a low potential, clock signal CLKB1 is at a high potential.

[0544] The clocked inverter circuit 51 has the function of outputting an inverted signal of the input signal when, for example, the clock signal CLK1 is at a high potential and the clock signal CLKB1 is at a low potential. The clocked inverter circuit 55 has the function of outputting an inverted signal of the input signal when, for example, the clock signal CLK1 is at a low potential and the clock signal CLKB1 is at a high potential. Here, since the clock signal CLKB1 is the inverted signal of the clock signal CLK1, the signal is output from either the clocked inverter circuit 51 or the clocked inverter circuit 55.

[0545] A start pulse signal is input to the first-stage register circuit 50. As a result, the register circuit 50 sequentially outputs signals to the wiring 39. In the example shown in Figure 28C, register circuits 50[1], 50[2], 50[3], and 50[4] output signals to the wiring 39 in this order. Thus, image data is sequentially supplied to the pixels 21 of each row, for example, as shown in Figure 27.

[0546] As described in Embodiment 3, the semiconductor device according to one aspect of the present invention described in Embodiment 1 can be applied to various logic circuits such as NOT circuits (inverter circuits) and NAND circuits. Therefore, the clocked inverter circuit 51, inverter circuit 53, clocked inverter circuit 55, and NAND circuit 57 that constitute the shift register circuit 15 shown in Figure 28C can each be applied to the semiconductor device according to one aspect of the present invention.

[0547] Figures 29A to 29D are circuit diagrams showing examples of the configuration of the signal line drive circuit 13, specifically the CMOS circuit. At least some of these circuits can also be provided in the scan line drive circuit 12.

[0548] Figure 29A shows an example configuration of a clocked inverter circuit 60. The clocked inverter circuit 60 includes a p-channel transistor 61, a p-channel transistor 62, an n-channel transistor 63, and an n-channel transistor 64.

[0549] In the clocked inverter circuit 60 shown in Figure 29A, the portion composed of the combination of transistors 62 and 63 has a configuration equivalent to that of a CMOS circuit. Therefore, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to this portion.

[0550] The input signal IN is input to the gates of transistor 62 and transistor 63. The clock signal CLK2 is input to the gate of transistor 64. The clock signal CLKB2 is input to the gate of transistor 61. The clock signal CLKB2 is the inverted signal of the clock signal CLK2.

[0551] A high potential is supplied to either the source or the drain of transistor 61. The other source or drain of transistor 61 is connected to either the source or the drain of transistor 62. An output signal OUT is output from the other source or drain of transistor 62 and from either the source or the drain of transistor 63. The other source or drain of transistor 63 is connected to either the source or the drain of transistor 64. A low potential is supplied to either the source or the drain of transistor 64.

[0552] The clocked inverter circuit 60 can be applied to the clocked inverter circuit 51 shown in Figure 28C by replacing the clock signal CLK2 with the clock signal CLK1 and the clock signal CLKB2 with the clock signal CLKB1. The clocked inverter circuit 60 can be applied to the clocked inverter circuit 55 shown in Figure 28C by replacing the clock signal CLK2 with the clock signal CLKB1 and the clock signal CLKB2 with the clock signal CLK1.

[0553] Figure 29B shows an example configuration of the NAND circuit 70. The NAND circuit 70 includes a p-channel transistor 71, a p-channel transistor 72, an n-channel transistor 73, and an n-channel transistor 74.

[0554] In the NAND circuit 70 shown in Figure 29B, the portion composed of the combination of transistors 72 and 73 has a configuration equivalent to that of a CMOS circuit. Therefore, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to this portion.

[0555] Input signal IN1 is input to the gates of transistor 72 and transistor 73. Input signal IN2 is input to the gates of transistor 71 and transistor 74.

[0556] A high potential is supplied to either the source or drain of transistor 71, and to either the source or drain of transistor 72. The output signal OUT is output from the other source or drain of transistor 71, the other source or drain of transistor 72, and one source or drain of transistor 73. The other source or drain of transistor 73 is connected to one source or drain of transistor 74. A low potential is supplied to the other source or drain of transistor 74.

[0557] The NAND circuit 70 can be applied, for example, to the NAND circuit 57 shown in Figure 28C. In this case, the signal input to the first input terminal of the NAND circuit 57 can be one of input signal IN1 and input signal IN2, and the signal input to the second input terminal of the NAND circuit 57 can be the other of input signal IN1 and input signal IN2. The output signal OUT can also be output to the wiring 39.

[0558] Figure 29C shows an example configuration of the NOR circuit 80. The NOR circuit 80 includes a p-channel transistor 81, a p-channel transistor 82, an n-channel transistor 83, and an n-channel transistor 84.

[0559] In the NOR circuit 80 shown in Figure 29C, the portion composed of the combination of transistors 82 and 83 has a configuration equivalent to that of a CMOS circuit. Therefore, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to this portion.

[0560] Input signal IN1 is input to the gates of transistor 82 and transistor 83. Input signal IN2 is input to the gates of transistor 81 and transistor 84.

[0561] A high potential is supplied to either the source or the drain of transistor 81. The other source or drain of transistor 81 is connected to either the source or the drain of transistor 82. An output signal OUT is output from the other source or drain of transistor 82, one source or drain of transistor 83, and one source or drain of transistor 84. A low potential is supplied to the other source or drain of transistor 83 and the other source or drain of transistor 84.

[0562] Figure 29D shows an example of the configuration of circuit 160. Circuit 160 includes a p-channel transistor 161, a p-channel transistor 162, an n-channel transistor 163, an n-channel transistor 164, a p-channel transistor 165, and a p-channel transistor 166.

[0563] In the circuit 160 shown in Figure 29D, the sections composed of the combination of transistors 163 and 165, and the sections composed of the combination of transistors 164 and 166, each have a configuration equivalent to a CMOS circuit. Therefore, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to these sections.

[0564] The input signal IN is input to the gates of transistor 163 and transistor 165. The input signal INB is input to the gates of transistor 164 and transistor 166. The input signal INB is the inverse of the input signal IN.

[0565] A high potential is supplied to either the source or drain of transistor 161, and to either the source or drain of transistor 162. The other source or drain of transistor 161 is connected to either the source or drain of transistor 165. The other source or drain of transistor 162 is connected to either the source or drain of transistor 166. The other source or drain of transistor 165 is connected to the gate of transistor 162. The gate of transistor 162 is connected to either the source or drain of transistor 163.

[0566] An output signal OUT is output from the gate of transistor 161, either the source or drain of transistor 164, and the other source or drain of transistor 166. A low potential is supplied to the other source or drain of transistor 163 and the other source or drain of transistor 164.

[0567] Circuit 160 can be provided, for example, in the level shift circuit 17 shown in Figures 28A and 28B. In this case, the signal output by the latch circuit 16 can be used as the input signal IN, and the signal supplied by the level shift circuit 17 to the D-A conversion circuit 18 can be used as the output signal OUT. The level shift circuit 17 can have as many circuits 160 as there are wires 39, for example. Circuit 160 can also be called a level shifter or a level shift circuit. Furthermore, circuit 160 can also be provided in the scan line drive circuit 12.

[0568] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0569] (Embodiment 5) In this embodiment, an example of applying a semiconductor device according to one aspect of the present invention to a storage device will be described with reference to the drawings. By applying a semiconductor device according to one aspect of the present invention to a storage device, a storage device with extremely high integration density can be realized. Furthermore, a storage device with extremely long data retention time and low power consumption can be realized.

[0570] Figure 30 shows a block diagram illustrating an example configuration of the storage device 900. The storage device 900 shown in Figure 30 includes a drive circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Figure 30 shows an example in which the memory array 920 has multiple memory cells 950 arranged in a matrix.

[0571] A semiconductor device according to one embodiment of the present invention, as described in Embodiment 1, can be applied to the memory cell 950. By applying a semiconductor device according to one embodiment of the present invention to the memory cell 950, the operating speed of the storage device 900 can be improved. Furthermore, miniaturization and high integration of the storage device 900 can be achieved. In addition, the capacity per unit area of ​​the storage device 900 can be increased.

[0572] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912 (Control Circuit), and a voltage generation circuit 928.

[0573] A semiconductor device according to one embodiment of the present invention, as described in Embodiment 1, can also be applied to each circuit constituting the drive circuit 910. This makes it possible to reduce the circuit area and power consumption.

[0574] In the storage device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0575] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 can also be generated by the control circuit 912.

[0576] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the storage device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0577] The voltage generation circuit 928 has the function of generating voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates voltage.

[0578] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0579] The row decoder 941 and the column decoder 942 have a function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has a function of selecting a row specified by the row decoder 941. The column driver 924 has a function of writing data to the memory cell 950, a function of reading data from the memory cell 950, a function of holding the read data, and the like.

[0580] The input circuit 925 has a function of holding the signal WDA. Data held by the input circuit 925 is output to the column driver 924. Output data from the input circuit 925 is data (Din) to be written to the memory cell 950. Data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. The output circuit 926 also has a function of outputting Dout to the outside of the storage device 900. Data output from the output circuit 926 is the signal RDA.

[0581] The PSW 931 supplies V to the peripheral circuit 915 ＤＤ and has a function of controlling the supply. The PSW 932 supplies V to the row driver 923 ＨＭ and has a function of controlling the supply. Here, the high power supply potential of the storage device 900 is V ＤＤ , and the low power supply potential is GND (ground potential). Further, V ＨＭ is a high power supply potential used for setting a word line to a high level, and is higher than V ＤＤ . ON / OFF of the PSW 931 is controlled by the signal PON1, and ON / OFF of the PSW 932 is controlled by the signal PON2. In FIG. 30, in the peripheral circuit 915, V ＤＤ is supplied, and the number of power supply domains is set to 1 herein, but the number may be plural. In this case, a power switch may be provided for each power supply domain.

[0582] A configuration example of another memory cell that can be applied to the memory cell 950 will be described with reference to FIG. 31A.

[0583] [Example Configuration of Memory Cell 950] Figure 31A shows an example of an SRAM (Static Random Access Memory) using an OS transistor that can be applied to the memory cell 950 described above. Note that the memory cell 950 shown in Figure 31A is a memory cell of a backup-capable SRAM.

[0584] The memory cell 950 includes transistors M7 to M10, transistors MS1 to MS4, capacitive element CD1, and capacitive element CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0585] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0586] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0587] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0588] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0589] Wiring BIL and BILB function as bit lines, wiring WOL functions as a word line, and wiring BRL controls the conduction and non-conduction states of transistors M9 and M10.

[0590] Wiring VDL is a wiring that provides a high-level potential, and wiring GNDL is a wiring that provides a low-level potential.

[0591] In the memory cell 950 shown in Figure 31A, the portion composed of the combination of transistor MS1 and transistor MS3, and the portion composed of the combination of transistor MS2 and transistor MS4, each have a configuration equivalent to a CMOS circuit. Therefore, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to these portions.

[0592] In the memory cell 950, data is written by applying a high-level potential to the wiring WOL and to the wiring BRL. Specifically, when transistor M10 is conducting, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the second terminal side of transistor M10.

[0593] Incidentally, since the memory cell 950 is configured with an inverter loop by transistors MS1 to MS4, an inverted signal of the data signal corresponding to the potential is input to the second terminal of transistor M8. Because transistor M8 is conducting, the wiring BILB outputs an inverted signal of the potential applied to wiring BIL, i.e., the signal input to wiring BIL. Also, because transistors M9 and M10 are conducting, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and making transistors M7 to M10 non-conductive, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are maintained.

[0594] The data reading process is described below. First, wiring BIL and wiring BILB are precharged to a predetermined potential. Next, a high-level potential is applied to wiring WOL and wiring BRL. At this time, the potential of the first terminal of capacitive element CD1 is refreshed by the inverter loop of memory cell 950 and output to wiring BILB. Also, the potential of the first terminal of capacitive element CD2 is refreshed by the inverter loop of memory cell 950 and output to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0595] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes, or even eliminating the need for memory cell refresh operations altogether.

[0596] Furthermore, Si transistors can also be used as transistors MS7 through MS10.

[0597] [Example of Sense Amplifier 927 Configuration] Figure 31B shows a circuit diagram corresponding to the sense amplifier 927 described above. The sense amplifier 927 has a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplification circuit 485. In addition to wiring BL and wiring BLB, Figure 31B also shows wiring SA_OUT and wiring SA_OUTB, which output the signal to be read.

[0598] As shown in Figure 31B, the switch circuit 482 has, for example, n-channel type transistors 482_1 and 482_2, respectively. Transistors 482_1 and 482_2 switch the conduction state of the wiring pair SA_OUT, SA_OUTB and the wiring pair BL, BLB, in response to the signal CSEL.

[0599] As shown in Figure 31B, the pre-charge circuit 483 is composed of n-channel transistors 483_1 to 483_3, respectively. The pre-charge circuit 483 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQ.

[0600] As shown in Figure 31B, the pre-charge circuit 484 is composed of p-channel transistors 484_1 to 484_3, respectively. The pre-charge circuit 484 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQB.

[0601] As shown in Figure 31B, the amplification circuit 485 consists of p-channel transistors 485_1 and 485_2, and n-channel transistors 485_3 and 485_4, connected to wiring SAP or wiring SAN. Wiring SAP or wiring SAN is wiring that has the function of providing VDD or VSS. Transistors 485_1 to 485_4 are transistors that constitute an inverter loop.

[0602] In the amplification circuit 485 shown in Figure 31B, the sections composed of transistors 485_1 and 485_3, and the sections composed of transistors 485_2 and 485_4, each have a configuration equivalent to a CMOS circuit. Therefore, a semiconductor device according to one embodiment of the present invention described in Embodiment 1 can be applied to these sections.

[0603] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0604] (Embodiment 6) In this embodiment, an application example of a semiconductor device according to one aspect of the present invention will be described with reference to Figures 32A to 36F.

[0605] A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, large computers, space equipment, data centers (also referred to as DCs), and various electronic devices. The logic circuits described in Embodiment 3, the display devices described in Embodiment 4, the storage devices described in Embodiment 5, etc., can be applied to the electronic components, large computers, space equipment, data centers, and various electronic devices described below. Therefore, by using a semiconductor device according to one aspect of the present invention in the electronic components, large computers, space equipment, data centers, and various electronic devices described below, miniaturization, reduced power consumption, and improved performance can be achieved.

[0606] For example, a display device having a semiconductor device according to one aspect of the present invention can be used in the display unit of various electronic devices. A display device having a semiconductor device according to one aspect of the present invention can be easily made high-definition and high-resolution.

[0607] Examples of electronic devices include television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0608] In particular, a display device according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as head-mounted displays for virtual reality (VR), glasses-type devices for augmented reality (AR), and devices for mixed reality (MR).

[0609] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (detail) of the display device according to one aspect of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having one or both of these high resolution and / or high detail, it is possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention. For example, the display device can support various aspect ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0610] The electronic device of this embodiment may have sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0611] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, or text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0612] [Electronic Components] Figure 32A shows a perspective view of a substrate (mounted substrate 989) on which electronic components 980 are mounted. The electronic component 980 shown in Figure 32A has a semiconductor device 981 inside a mold 984. Some details are omitted in Figure 32A to show the inside of the electronic component 980. The electronic component 980 has a land 985 on the outside of the mold 984. The land 985 is connected to an electrode pad 986, and the electrode pad 986 is connected to the semiconductor device 981 via a wire 987. The electronic component 980 is mounted on a printed circuit board 988, for example. Multiple such electronic components are combined and connected on the printed circuit board 988 to complete the mounted substrate 989.

[0613] Furthermore, the semiconductor device 981 has a drive circuit layer 982 and a storage layer 983. The storage layer 983 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 982 and the storage layer 983 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the storage layer 983, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0614] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0615] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 983 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 983, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0616] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0617] Next, a perspective view of the electronic component 990 is shown in Figure 32B. The electronic component 990 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 are provided on the interposer 991.

[0618] Electronic component 990 shows an example where the semiconductor device 981 is used as a high-bandwidth memory (HBM). Furthermore, the semiconductor device 994 can be used in integrated circuits such as a CPU, GPU (Graphics Processing Unit), or FPGA (Field Programmable Gate Array).

[0619] The package substrate 992 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 991 can be, for example, a silicon interposer or a resin interposer.

[0620] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also has the function of connecting integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 991, and these through electrodes may be used to connect the integrated circuits and the package substrate 992. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0621] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0622] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0623] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0624] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 990. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the heights of the semiconductor device 981 and the semiconductor device 994.

[0625] To mount the electronic component 990 onto another substrate, electrodes 993 may be provided at the bottom of the package substrate 992. Figure 32B shows an example in which the electrodes 993 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 993 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0626] The electronic component 990 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0627] [Large-scale computer] Next, Figure 33A shows a perspective view of the large-scale computer 5600. In the large-scale computer 5600 shown in Figure 33A, multiple rack-mount type computers 5620 are housed in rack 5610. The large-scale computer 5600 may also be referred to as a supercomputer.

[0628] The computer 5620 can have the configuration shown in the perspective view in Figure 33B, for example. In Figure 33B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0629] The PC card 5621 shown in Figure 33C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 33C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for details on these semiconductor devices.

[0630] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0631] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0632] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0633] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5627 include FPGAs, GPUs, and CPUs. For example, an electronic component 990 can be used as the semiconductor device 5627.

[0634] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 990 can be used as the semiconductor device 5628.

[0635] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0636] [Space Equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0637] A semiconductor device according to one aspect of the present invention may include an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller fluctuations in electrical prop...

Claims

It comprises a first conductive layer to a fourth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer to a fourth insulating layer. The first conductive layer and the second conductive layer are located on the same plane. On the first conductive layer and the second conductive layer, the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer are provided in this order, such that they have regions that overlap with the first conductive layer and the second conductive layer, respectively. The first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer have substantially the same upper surface shape. The third insulating layer, in the region overlapping with the first conductive layer, is in contact with the respective sides of the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer. The fourth insulating layer, in the region overlapping with the second conductive layer, is in contact with the respective sides of the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer. The first semiconductor layer is in contact with the upper surface of the first conductive layer, the third insulating layer, and a portion of the upper surface of the fourth conductive layer. The second semiconductor layer is in contact with the upper surface of the second conductive layer, the fourth insulating layer, and another portion of the upper surface of the fourth conductive layer. The first semiconductor layer is an n-type semiconductor layer, The aforementioned second semiconductor layer is a p-type semiconductor layer. Semiconductor equipment. 　 It comprises a first conductive layer to a fourth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer to a fourth insulating layer. On the first conductive layer, the first insulating layer, the second conductive layer, and the second insulating layer are provided in this order, such that they overlap with the first conductive layer. The first insulating layer, the second conductive layer, and the second insulating layer have substantially the same upper surface shape. The third conductive layer is located on the first region of the second insulating layer. The fourth conductive layer is located on the second region of the second insulating layer. The third insulating layer is in contact with the side surface where the ends of the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are aligned. The fourth insulating layer is in contact with the side surface where the ends of the first insulating layer, the second conductive layer, the second insulating layer, and the fourth conductive layer are aligned. The first semiconductor layer is in contact with a part of the upper surface of the first conductive layer, the third insulating layer, and the upper surface of the third conductive layer. The second semiconductor layer is in contact with another portion of the upper surface of the first conductive layer, the fourth insulating layer, and the upper surface of the fourth conductive layer. The first semiconductor layer is an n-type semiconductor layer, The aforementioned second semiconductor layer is a p-type semiconductor layer. Semiconductor equipment. 　 It comprises a first conductive layer to a fourth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer and a second insulating layer. The first conductive layer and the second conductive layer are located on the same plane. The first insulating layer and the third conductive layer are provided on the first conductive layer and the second conductive layer, respectively, in this order, such that they have regions that overlap with the first conductive layer and the second conductive layer. The first insulating layer and the third conductive layer have substantially the same upper surface shape. The third conductive layer has a first region to a third region on its upper surface, The first semiconductor layer is in contact with the upper surface of the first conductive layer, the side surfaces of the first insulating layer and the third conductive layer on the side facing the first conductive layer, and the first region. The second semiconductor layer is in contact with the upper surface of the second conductive layer, the side surfaces of the first insulating layer and the third conductive layer on the side facing the second conductive layer, and the second region. The second insulating layer is in contact with the upper and side surfaces of the first semiconductor layer, the upper and side surfaces of the second semiconductor layer, the upper surface of the first conductive layer, the upper surface of the second conductive layer, and the third region. The fourth conductive layer is located on the second insulating layer such that it has an overlapping region with the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is an n-type semiconductor layer, The aforementioned second semiconductor layer is a p-type semiconductor layer. Semiconductor equipment. 　 It comprises a first conductive layer to a fourth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer and a second insulating layer. A first insulating layer is provided on the first conductive layer such that it has a region that overlaps with the first conductive layer. The second conductive layer is located on the first region of the first insulating layer. The third conductive layer is located on the second region of the first insulating layer. The first semiconductor layer is in contact with a part of the upper surface of the first conductive layer, the side surface where the ends of the first insulating layer and the second conductive layer are aligned, and the upper surface of the second conductive layer. The second semiconductor layer is in contact with another portion of the upper surface of the first conductive layer, the side surface where the ends of the first insulating layer and the third conductive layer are aligned, and the upper surface of the third conductive layer. The second insulating layer is in contact with the upper and side surfaces of the first semiconductor layer, the upper and side surfaces of the second semiconductor layer, the upper surface of the first conductive layer, the upper and side surfaces of the second conductive layer, the upper and side surfaces of the third conductive layer, and the upper surface of the first insulating layer. The fourth conductive layer is located on the second insulating layer such that it has an overlapping region with the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is an n-type semiconductor layer, The aforementioned second semiconductor layer is a p-type semiconductor layer. Semiconductor equipment. 　 In any one of claims 1 to 4, The first semiconductor layer comprises indium and oxygen, The second semiconductor layer comprises tellurium, tin, or copper, and oxygen. Semiconductor equipment. 　 In any one of claims 1 to 4, The first semiconductor layer comprises silicon and either phosphorus or arsenic. The second semiconductor layer comprises silicon and one of boron, aluminum, or gallium. Semiconductor equipment. 　 In any one of claims 1 to 4, The first semiconductor layer comprises indium and oxygen, The second semiconductor layer comprises silicon and one of boron, aluminum, or gallium. Semiconductor equipment. 　 In any one of claims 1 to 4, The first semiconductor layer comprises silicon and either phosphorus or arsenic. The second semiconductor layer comprises tellurium, tin, or copper, and oxygen. Semiconductor equipment. 　 In claim 1 or claim 2, The first insulating layer comprises a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer. The aforementioned second insulating layer comprises an eighth insulating layer, a ninth insulating layer on the eighth insulating layer, and a tenth insulating layer on the ninth insulating layer. The fifth insulating layer, the seventh insulating layer, the eighth insulating layer, and the tenth insulating layer each contain silicon and nitrogen. The sixth insulating layer and the ninth insulating layer each contain silicon and oxygen, Semiconductor equipment. 　 In claim 3 or claim 4, The first insulating layer comprises an eleventh insulating layer, a twelfth insulating layer on the eleventh insulating layer, and a thirteenth insulating layer on the twelfth insulating layer. The 11th insulating layer and the 13th insulating layer each contain silicon and nitrogen, The 12th insulating layer comprises silicon and oxygen. Semiconductor equipment. 　 In any one of claims 1 to 4, In a plan view, the area of ​​the first semiconductor layer is larger than the area of ​​the second semiconductor layer. Semiconductor equipment. In any one of claims 1 to 4, In a plan view, the area of ​​the second semiconductor layer is larger than the area of ​​the first semiconductor layer. Semiconductor equipment. 　 In any one of claims 1 to 4, A portion of the second semiconductor layer has a region that is in contact with the upper surface and side surface of a portion of the first semiconductor layer. Semiconductor equipment. 　 In any one of claims 1 to 4, A portion of the first semiconductor layer has a region that is in contact with the upper surface and side surface of a portion of the second semiconductor layer. Semiconductor equipment. 　 A first conductive layer and a second conductive layer are formed. A first insulating film, a first conductive film, a second insulating film, and a second conductive film are formed on the first conductive layer and the second conductive layer in this order. By removing the second conductive film, the second insulating film, the first conductive film, and a portion of the first insulating film, a third conductive layer, a first insulating layer, a fourth conductive layer, and a second insulating layer are formed, each having a region that overlaps with the first conductive layer and the second conductive layer, and each having a substantially matching upper surface shape. A third insulating film is formed in contact with the upper surface of the first conductive layer, the upper surface of the second conductive layer, the upper surface and side surfaces of the third conductive layer, the side surfaces of the fourth conductive layer, the side surfaces of the first insulating layer, and the side surfaces of the second insulating layer. A portion of the third insulating film is removed to form a third insulating layer in contact with the side surface of the third conductive layer, the first insulating layer, the fourth conductive layer, and the second insulating layer on the side surface of the first conductive layer, and a fourth insulating layer in contact with the side surface of the third conductive layer, the first insulating layer, the fourth conductive layer, and the second insulating layer on the side surface of the second conductive layer. A first semiconductor film is formed in contact with the upper surface of the first conductive layer, the third insulating layer, the upper surface of the third conductive layer, the fourth insulating layer, and the upper surface of the second conductive layer. A portion of the first semiconductor film is removed to form a first semiconductor layer that is in contact with a portion of the upper surface of the first conductive layer, the third insulating layer, and a portion of the upper surface of the third conductive layer. A second semiconductor film is formed in contact with the other part of the upper surface of the first conductive layer, the upper and side surfaces of the first semiconductor layer, the other part of the upper surface of the third conductive layer, the fourth insulating layer, and the upper surface of the second conductive layer. A portion of the second semiconductor film is removed to form a second semiconductor layer that is in contact with a portion of the upper surface of the second conductive layer, the fourth insulating layer, and another portion of the upper surface of the third conductive layer. Method for manufacturing semiconductor devices. 　 In claim 15, The first semiconductor layer is an n-type semiconductor layer, The aforementioned second semiconductor layer is a p-type semiconductor layer. Method for manufacturing semiconductor devices. 　 In claim 15, The first semiconductor layer is a p-type semiconductor layer, The aforementioned second semiconductor layer is an n-type semiconductor layer. Method for manufacturing semiconductor devices.

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