Computation device

Abstract

Provided is a computation device. The computation device has: a computation circuit unit that has a plurality of computation cells for retaining first data; a drive circuit that outputs second data to the computation circuit unit; a first sample-and-hold circuit unit; a switch unit; and a second sample-and-hold circuit unit. The computation circuit unit supplies a first current to the first sample-and-hold circuit unit, said first current corresponding to the sum of currents flowing through the computation cells to which the second data has been supplied. First sample-and-hold circuits retain a plurality of items of third data that correspond to the first current, by switching the second data. The switch unit supplies a second current to the second sample-and-hold circuit unit, said second current corresponding to the sum of currents flowing from the plurality of first sample-and-holds circuits via switches. Second sample-and-hold circuits retain a plurality of items of fourth data that correspond to the second current, by switching switch paths.

Description

computing device

[0001] One aspect of the present invention relates to a computing device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them.

[0003] Convolutional neural networks (CNNs) are used in the field of image recognition. In CNNs, the computational processing involves repeatedly performing multiply-accumulate operations. When the memory and the processing unit are located separately, power consumption increases due to data transmission and reception.

[0004] To reduce power consumption, Computing in Memory (CiM) technology, which integrates the memory and the computing unit, is effective. For example, Patent Document 1 discloses a circuit configuration for inputting image data to the computing unit in a CiM configuration for computing CNNs. Patent Document 2 also discloses a configuration for performing sum-of-accumulate operations in a CiM configuration for computing analog image data, in which filter data (also called weight values, kernels, masks, etc.) is held in the computing cell that holds the data, and the data to be processed (also called activation signals, image data, etc.) is sequentially supplied to the computing cell.

[0005] International Publication No. 2018 / 234919, International Publication No. 2022 / 13680

[0006] In a CIM (Computer-Input Mechanism) that performs CNN calculations by storing filter data in the calculation cell that holds the data, it is necessary to store data such as the data to be processed in the previous layer and the data to be processed acquired by sensors in an external memory device separate from the calculation unit. In this case, writing and reading data to and from the external memory device may become complicated.

[0007] Furthermore, stride processing in CNN involves performing a sum-of-accumulate operation on the same filter data, but with different data addresses to be processed. This configuration requires supplying different data to the processing cell multiple times, which could complicate data writing and reading in configurations where the data to be processed is stored in an external memory device.

[0008] One aspect of the present invention aims to provide a computing device that can easily perform CNN calculations in a CiM configuration. Alternatively, one aspect of the present invention aims to provide a computing device that can easily write and read data to and from an external storage device in a CiM configuration. Alternatively, one aspect of the present invention aims to provide a novel computing device that offers superior convenience.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0010] One aspect of the present invention is a computing device comprising: a computing circuit section having a plurality of computing cells that hold first data; a drive circuit that outputs second data to the computing circuit section; a first sample-and-hold circuit section having a plurality of first sample-and-hold circuits; a switch section having a plurality of switches; and a second sample-and-hold circuit section having a plurality of second sample-and-hold circuits, wherein the computing circuit section supplies a first current to the first sample-and-hold circuit section corresponding to the sum of the currents flowing through the computing cells to which the second data is supplied; each of the first sample-and-hold circuits holds a plurality of third data corresponding to the first current by switching the second data; the switch section supplies a second current to the second sample-and-hold circuit section corresponding to the sum of the currents flowing from the plurality of first sample-and-hold circuits through the switches; and each of the second sample-and-hold circuits holds a plurality of fourth data corresponding to the second current by switching the paths of the switches.

[0011] In one embodiment of the present invention, a arithmetic device is preferred in which a first wiring is provided in the row direction, a plurality of arithmetic cells are arranged in a matrix, and the third data is data corresponding to a sum-of-products operation of the first data held in the arithmetic cells in the column direction and the second data output from the drive circuit via the first wiring.

[0012] In one embodiment of the present invention, a arithmetic device is preferred in which the first data is the data to be processed and the second data is the filtered data.

[0013] In one embodiment of the present invention, a arithmetic device is preferred in which the second data is output to a calculation cell via a first wiring provided in the row direction, and the first wiring is arranged in multiples for each row in which a calculation cell is provided, according to the row size of the filter data.

[0014] In one embodiment of the present invention, a arithmetic device is preferred in which the data to be processed is image data.

[0015] In one embodiment of the present invention, a preferred arithmetic device is one in which the arithmetic cell receives second data from a drive circuit via first wiring provided in the row direction, and supplies a current corresponding to the product of the first data and the second data to the first sample-and-hold circuit section via second wiring provided in the column direction.

[0016] In one embodiment of the present invention, a arithmetic device is preferred in which the arithmetic cell is a variable resistor element having a resistance value corresponding to the first data.

[0017] In one embodiment of the present invention, a preferred arithmetic device comprises a capacitive element, a first transistor in which one electrode of the capacitive element is electrically connected to a gate, and a second transistor in which a charge corresponding to a first data is held at the gate of the first transistor, wherein the other electrode of the capacitive element is electrically connected to a first wiring.

[0018] In one embodiment of the present invention, a computing device is preferred in which the first transistor and the second transistor each have a semiconductor layer having a metal oxide.

[0019] In one embodiment of the present invention, electronic devices are preferred in which the metal oxide is an oxide containing at least one of indium, element M (where M is Al, Ga, Y, or Sn), or zinc.

[0020] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings.

[0021] One aspect of the present invention can provide a computing device that can easily perform CNN calculations in a CiM configuration. Alternatively, one aspect of the present invention can provide a computing device that can easily write and read data to and from an external storage device in a CiM configuration. Alternatively, one aspect of the present invention can provide a novel computing device with excellent convenience.

[0022] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0023] Figure 1 illustrates an example of the configuration of a calculation unit. Figures 2A, 2B, 2C, and 2D illustrate an example of the configuration of a calculation unit. Figure 3 illustrates an example of the configuration of a calculation unit. Figure 4 illustrates an example of the configuration of a calculation unit. Figure 5 illustrates an example of the configuration of a calculation unit. Figure 6 illustrates an example of the configuration of a calculation unit. Figure 7 illustrates an example of the configuration of a calculation unit. Figure 8 illustrates an example of the configuration of a display device. Figure 9 illustrates an example of the configuration of a calculation unit. Figure 10 illustrates an example of the configuration of a calculation unit. Figure 11 illustrates an example of the configuration of a calculation unit. Figure 12 illustrates an example of the configuration of a calculation unit. Figure 13 illustrates an example of the configuration of a calculation unit. Figure 14 illustrates an example of the configuration of a calculation unit. Figure 15 illustrates an example of the configuration of a calculation unit. Figure 16 illustrates an example of the configuration of a calculation unit. Figure 17 illustrates an example of the configuration of a calculation unit. Figure 18 illustrates an example of the configuration of a calculation unit. Figure 19 illustrates an example of the configuration of a calculation unit. Figure 20 illustrates an example of the configuration of a calculation unit. Figure 21 is a diagram illustrating an example of the configuration of the arithmetic unit. Figure 22 is a diagram illustrating an example of the configuration of the arithmetic unit. Figure 23 is a diagram illustrating an example of the configuration of the arithmetic unit. Figure 24 is a diagram illustrating an example of the configuration of the arithmetic unit. Figure 25 is a diagram illustrating an example of the configuration of the arithmetic unit. Figure 26 is a diagram illustrating an example of the configuration of the arithmetic unit. Figure 27 is a diagram illustrating an example of the configuration of the arithmetic unit. Figure 28 is a diagram illustrating an example of the configuration of the arithmetic unit. Figures 29A, 29B, and 29C are diagrams illustrating an example of the configuration of the arithmetic unit. Figure 30 is a diagram illustrating an example of the configuration of the arithmetic unit. Figures 31A and 31B are diagrams illustrating an example of the configuration of the arithmetic unit. Figures 32A and 32B are diagrams illustrating an example of the configuration of the arithmetic unit. Figure 33 is a diagram illustrating an example of the configuration of the arithmetic unit. Figures 34A, 34B, and 34C are diagrams illustrating an example of the configuration of the arithmetic unit. Figures 35A, 35B, 35C, and 35D are diagrams illustrating an example of the configuration of the arithmetic unit. Figure 36 is a diagram illustrating an example of the configuration of the arithmetic unit. Figure 37 illustrates an example of the configuration of the arithmetic unit. Figure 38 illustrates an example of the configuration of the arithmetic unit. Figure 39 illustrates an example of the configuration of the arithmetic unit.Figure 40 is a diagram illustrating an example of the configuration of an arithmetic unit. Figure 41 is a diagram illustrating an example of the configuration of an arithmetic unit. Figure 42 is a diagram illustrating an example of the configuration of an arithmetic unit. Figure 43 is a diagram illustrating an example of the configuration of an arithmetic unit. Figures 44A and 44B are diagrams illustrating an example of the configuration of a transistor. Figures 45A, 45B, and 45C are diagrams illustrating an example of an electronic component. Figures 46A and 46B are diagrams illustrating an example of an electronic device.

[0024] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different forms, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0025] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0026] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0027] (Embodiment 1) This embodiment describes a computing device according to one aspect of the present invention. The computing device according to one aspect of the present invention is suitable for performing convolution operations, including sum-of-products operations, between data to be processed, such as image data, and filter data (also called kernels or weight values).

[0028] <Example of arithmetic unit configuration> Figure 1 is a block diagram illustrating an example of the configuration of the arithmetic unit 100. The arithmetic unit 100 includes an arithmetic circuit section 59, a drive circuit 11, a sample-and-hold circuit section 41, a switch section 42, and a sample-and-hold circuit section 43.

[0029] The calculation circuit section 59 has a plurality of calculation cells 31. The calculation cells 31 are connected to the drive circuit 11 via wiring XCL. The calculation cells 31 are connected to the sample-and-hold circuit section 41 via wiring YCL. The calculation cells 31 can be connected to wiring XCL arranged in the row direction and wiring YCL arranged in the column direction, and can be arranged in a matrix.

[0030] The calculation cell 31 has the function of holding (also called storing) data (also called first data) by applying electrical signals such as voltage and current via the wiring YCL. The calculation cell 31 can hold this data as physical quantities such as voltage and resistance. The physical quantities held in the calculation cell 31 are of a magnitude corresponding to the first data in analog value. In the following description, the physical quantities held in the calculation cell 31 may be referred to as analog data.

[0031] The calculation cell 31 has the function of supplying a current to the sample-and-hold circuit 41 via the wiring YCL, corresponding to the product of the analog data held within the calculation cell 31 and the electrical signal data (also called the second data), such as current and voltage, supplied via the wiring XCL. The electrical signal, such as current and voltage, supplied to the calculation cell 31 via the wiring XCL is a signal corresponding to the second data, which is an analog value. In the following explanation, the electrical signal of analog value supplied to the calculation cell 31 via the wiring XCL may be referred to as the analog signal. Furthermore, the current flowing through the wiring YCL when an analog signal is supplied to the calculation cell 31, which holds the analog data, is an analog current corresponding to the calculation of the product of the first data and the second data. In the following explanation, the current flowing through the wiring YCL may be referred to as the analog current.

[0032] The analog current flowing through wiring YCL is the sum of the analog currents flowing through the calculation cells 31 connected to wiring YCL. Therefore, the sum-of-products calculation data obtained by adding up the product calculation results in each calculation cell 31 can be obtained from the magnitude of the analog current flowing through the sample-and-hold circuit 41.

[0033] The calculation cell 31 is a calculation cell capable of holding the first data and performing the product of the first data and the second data. The calculation cell 31 is a calculation cell applicable to CiM technology, which integrates the memory device and the arithmetic unit as described above.

[0034] The arithmetic circuit unit 59 supplies the analog current flowing through the arithmetic cell 31 of the row to which the analog signal is applied to the sample-and-hold circuit unit 41. The analog current flowing between the arithmetic cell 31 and the sample-and-hold circuit unit 41 is sometimes referred to as the first current. The magnitude of the first current corresponds to the data of the sum-of-products operation. The magnitude of the analog current corresponds to the data (sum-of-products operation data) corresponding to the sum-of-products operation of the first data (analog data) held in each of the arithmetic cells 31 in the column direction and the second data (analog signal) output from the drive circuit 11 via the wiring XCL provided in the row direction. The sum-of-products operation data is sometimes referred to as the third data.

[0035] In one embodiment of the present invention, the analog data held in the arithmetic cell 31 is the data to be processed. In one embodiment of the present invention, the analog signal supplied to the arithmetic cell 31 from the drive circuit 11 is the filtered data. The configuration in which the arithmetic cell 31 holds the data to be processed and the drive circuit 11 supplies the filtered data is suitable for performing CNN arithmetic processing such as stride. Stride can be achieved by supplying the same filtered data to the data to be processed held in the arithmetic cell 31 to different addresses of the arithmetic cell 31.

[0036] In the arithmetic processing of CNN, the amount of data of the data to be processed is larger than that of filter data. When filter data is held in the arithmetic cell 31 and the data to be processed is supplied from the drive circuit 11 to the arithmetic cell 31, the data to be processed supplied from the drive circuit 11 has a large data amount, and thus it is necessary to hold the data in an external storage device. In an external storage device, access becomes complicated due to reading (also referred to as loading) and holding of the data to be processed.

[0037] In one aspect of the present invention, holding the data to be processed in the arithmetic cell 31 makes it possible to hold filter data having a relatively small data amount in a storage device with a small storage capacity. For example, it becomes possible to hold filter data in a storage device within the drive circuit 11. Filter data can be held in the drive circuit 11 and supplied to different addresses of the arithmetic cell 31, so that the arithmetic processing of CNN can be easily implemented. Even in a configuration where filter data is held in an external storage device, unlike data to be processed whose content changes over time, the update frequency of filter data once held is low, so writing and reading of data in an external storage device can be simplified.

[0038] It should be noted that the data to be processed is preferably image data. Image data is data that changes over time and has a large data amount. In the arithmetic circuit unit 59, by arranging arithmetic cells 31 in a matrix according to the size of image data, it is possible to collectively hold the image data.

[0039] The drive circuit 11 has a function of outputting an analog signal to the arithmetic cell 31 via a wiring XCL. The arithmetic cell 31 can pass an analog current corresponding to the magnitude of a product operation of filter data of an analog signal supplied from the drive circuit 11 and the held data to be processed which is analog data.

[0040] The sample-and-hold circuit section 41 has the function of holding a voltage corresponding to the magnitude of the analog current flowing through the wiring YCL. The sample-and-hold circuit section 41 has a plurality of sample-and-hold circuits SH1. Each sample-and-hold circuit SH1 holds a voltage corresponding to the magnitude of the analog current flowing through each column of wiring YCL. Each sample-and-hold circuit SH1 can supply an analog current corresponding to the magnitude of the held voltage. Therefore, each sample-and-hold circuit SH1 can hold an analog current. The sample-and-hold circuit section 41 can hold the analog current flowing through the wiring YCL of a selected column by switching the analog signal supplied to the wiring XCL.

[0041] The switch unit 42 has the function of supplying the analog current held by the sample-and-hold circuit SH1 to the sample-and-hold circuit unit 43. The switch unit 42 has a plurality of switches SW12. The switches SW12 switch the current path between the sample-and-hold circuit unit 41 and the sample-and-hold circuit unit 43. The switch unit 42 can add up and supply the analog currents held by the sample-and-hold circuit SH1 corresponding to the wiring YCL of each row. The switch unit 42 can supply a current to the sample-and-hold circuit unit 43 corresponding to the sum of the analog currents.

[0042] The sample-and-hold circuit section 43 has the function of holding a current corresponding to the sum of the analog currents flowing through the switch section 42. The sample-and-hold circuit section 43 has a plurality of sample-and-hold circuits SH2. Similar to the sample-and-hold circuit SH1, the sample-and-hold circuit SH2 holds a voltage corresponding to the magnitude of the current. The current corresponding to the sum of the analog currents flowing through the switch section 42 is sometimes called the second current. The second current (and the voltage held by the sample-and-hold circuit SH2) corresponds to the data obtained by the convolution of the filtered data and the data to be processed to which the filtered data is applied (convolution data). The convolution data is sometimes called the fourth data.

[0043] Figure 2A is a schematic diagram showing an example of filter data. The filter data F exemplified in Figure 2A Ｄis filter data represented in a 3-row by 3-column format. In FIG. 2A, as filter values, the element at the 1st row and 1st column is f １ , and the element at the 1st row and 2nd column is f ２ , and so on. Note that in the filter data, the number of channels, bias values, and the like used in CNN operations are omitted to facilitate understanding. The same applies to processing target data and convolution data described later.

[0044] FIG. 2B is a schematic diagram showing a part of the processing target data. The processing target data D exemplified in FIG. 2B Ｐ has 6 rows and 4 columns illustrated as a part thereof. In FIG. 2B, as an address of the processing target data, the 1st row and 1st column is D １１ , the 1st row and 2nd column is D １２ , and so on. For example, convolution operation processing in CNN is performed using the filter data F of FIG. 2A Ｄ , and matrix multiplication is performed with analog data at addresses in a 3-row by 3-column region surrounded by a thick line.

[0045] FIG. 2C is a schematic diagram showing a part of convolution data. The convolution data C exemplified in FIG. 2C ＯＵＴ has 2 rows and 4 columns illustrated as a part thereof. In FIG. 2C, as an address of the convolution data, the 1st row and 1st column is C １１ , the 1st row and 2nd column is C １２ , and so on. For example, through convolution operation processing in CNN, analog data at an address in a region surrounded by a thick line in FIG. 2B becomes the convolution data C in FIG. 2C １１

[0046] Furthermore, FIG. 2D shows processing target data D held in the arithmetic circuit unit 59 in FIG. 1 Ｐ , filter data F supplied from the drive circuit 11 to the arithmetic circuit unit 59 Ｄ , and convolution data C held in the sample and hold circuit unit 43 ＯＵＴ ​This is schematically shown. In Figure 2D, the data flow from the drive circuit 11 to the arithmetic circuit 59, from the arithmetic circuit 59 to the sample-and-hold circuit 41, from the sample-and-hold circuit 41 to the switch unit 42, and from the switch unit 42 to the sample-and-hold circuit 43 is schematically represented by arrows. Note that the arrows representing the data flow in the figure are included for ease of understanding, and signals such as current may flow in the opposite direction to the data flow.

[0047] In one aspect of the present invention, the arithmetic device 100 stores data to be processed D in the arithmetic cell 31. Ｐ The first data corresponds to this, and the filtered data F in the CNN's computational processing. Ｄ A sum-of-products operation is performed on the second data corresponding to the first data. By providing different filter data to the calculation cell 31 via the wiring XCL for each row, a third data corresponding to the product of the filter value of the row in the filter data and the data at the address of the column in the data to be processed, i.e., the analog current corresponding to the product of the row and the column, can be obtained. In addition, in one aspect of the present invention, the calculation device 100 can obtain a fourth data by adding up the analog currents that flow by switching the path of the switch unit 42 and holding the third data held in the sample-and-hold circuit unit 41 in the sample-and-hold circuit unit 43. The fourth data can be convolution data corresponding to a matrix operation of the filter value of each row in the filter data and the data at the address of the data to be processed to which the filter data is applied. Therefore, one aspect of the present invention can provide a calculation device that can easily perform CNN calculations in a CiM configuration.

[0048] <Example of Operation of the Calculation Unit> Figures 3 to 28 illustrate an example of the operation of a calculation unit 100 according to one embodiment of the present invention. Figure 3 shows a calculation circuit unit 59 having a calculation cell 31 that holds 4 rows and 6 columns of data to be processed, a drive circuit 11 and wiring XCL1 to XCL4 connected to the calculation cell 31, wiring YCL1 to YCL6 connected to either the calculation cell 31 or the sample-and-hold circuit SH1 of the sample-and-hold circuit unit 41, a switch SW12 in the switch unit 42, and a sample-and-hold circuit SH2 in the sample-and-hold circuit unit 43. The switch SW12 switches the path of the current flowing between terminals P1 to P6 of the sample-and-hold circuit SH1 and terminals Q1 to Q4 of the sample-and-hold circuit SH2.

[0049] In the example operation described below, a 3x3 filter data is applied, and the convolution data C is obtained by sliding it in the row direction with padding 1. １１ ~C １４ , and the convolution data C obtained by sliding in the column direction with padding 1 ２１ ~C ２４ An example of obtaining the data C will be explained. １１ ~C １４ , C ２１ ~C ２４ The data can be stored in an external memory device, and after performing pooling operations and other operations for the convolution operation of the next layer, it can be stored in the calculation cell 31.

[0050] The 3x3 filter data is the filter data F shown in Figure 2A. Ｄ This will be explained using the filter values. The data to be processed is the data to be processed D shown in Figure 2B. Ｐ The explanation will use the following: and the address. The convolution data is the convolution data C shown in Figure 2C. ＯＵＴ This will be explained using , and addresses.

[0051] In the sample-and-hold circuit section 41, the number of sample-and-hold circuits SH1 should be set up to correspond to the number of columns of calculation cells, and in the case of wiring YCL1 to YCL6, a configuration of six circuits is shown as an example. In the sample-and-hold circuit section 43, the number of sample-and-hold circuits SH2 should be set up to correspond to the number of convolution data determined according to the stride number, etc. Since the convolution data is smaller than the data to be processed, the number of sample-and-hold circuits SH2 can be less than the number of sample-and-hold circuits SH1. As shown in the figure, the switch SW12 in the switch section 42 is arranged to switch the conduction state between terminals P1 to P6 and terminals Q1 to Q4.

[0052] In the arithmetic unit 100, the arithmetic cell 31 holds the data to be processed.

[0053] Figure 4 schematically shows the data to be processed held in the calculation cell 31 in the calculation unit 100 of Figure 3. The analog data held in the calculation cells of each row and column can be held at each address by controlling the wiring XCL (XCL1 to XCL4), wiring YCL (YCL1 to YCL6), or other control lines.

[0054] Furthermore, Figure 4 shows the filter data F held within the drive circuit 11. Ｄ This is illustrated. Filtered data F Ｄ In addition to being held within the drive circuit 11, the data may also be held in an external storage device and read from the drive circuit 11 as needed.

[0055] The arrows in the diagram schematically represent the flow of data, current, etc. For example, in the case of data held from the calculation cell 31 to the sample-and-hold circuit SH1, an arrow is drawn from the calculation cell 31 to the sample-and-hold circuit SH1, but the direction of the current can be either from the calculation cell 31 to the sample-and-hold circuit SH1 or from the sample-and-hold circuit SH1 to the calculation cell 31.

[0056] In Figures 5 to 16, the filtered data F Ｄ To be processed, Data D ＰThe first to third rows of the diagram explain how this applies to the addresses in columns 1 through 6. In the diagram, calculation cells 31 that contribute to the calculation (activated calculation cells 31) are shown with solid lines, and calculation cells 31 that do not contribute to the calculation (inactive calculation cells) are shown with dotted lines.

[0057] As shown in Figure 5, the first column of the filtered data is the filter value f １ , f ４ , f ７ The current is supplied to the wiring XCL1 to XCL3 in the first to third rows. Additionally, the switches in each column are controlled to allow current to flow to the calculation cells 31 in the first and fourth columns of the calculation circuit section 59. With this configuration, the calculation cells 31 in the first to third rows of the first column, and in the first to third rows of the fourth column, are activated.

[0058] In the activated calculation cell 31, an analog current flows corresponding to the product of the analog signal based on the filter value and the analog data of the data to be processed. Each current is added together in the column-direction wirings YCL1 and YCL4, respectively. Current I flows through wiring YCL1. ｓ１ａ Current I ｓ４ａ Current I flows. ｓ１ａ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL1. Current I ｓ４ａ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL4. Current I ｓ１ａ is, "f １ ・D １１ +f ４ ・D ２１ +f ７ ・D ３１ This is a current of magnitude corresponding to the calculation of ". Current I ｓ４ａ is, "f １ ・D １４ +f ４ ・D ２４ +f ７ ・D ３４ This is a current of a magnitude corresponding to the calculation of "[...]".

[0059] As shown in Figure 6, the filter value f in the second column of the filtered data ２ , f ５ , f ８The current is supplied to the wiring XCL1 to XCL3 in the first to third rows. Additionally, the switches in each column are controlled to allow current to flow to the calculation cells 31 in the second and fifth columns of the calculation circuit section 59. With this configuration, the calculation cells 31 in the first to third rows of the second column, and in the first to third rows of the fifth column, are activated.

[0060] In the activated calculation cell 31, an analog current flows corresponding to the product of the analog signal based on the filter value and the analog data of the data to be processed. Each current is added together in the column-direction wirings YCL2 and YCL5, respectively. Wiring YCL2 has I ｓ２ａ , wiring YCL5 is I ｓ５ａ Current I flows. ｓ２ａ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL2. Current I ｓ５ａ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL5. Current I ｓ２ａ is, "f ２ ・D １２ +f ５ ・D ２２ +f ８ ・D ３２ This is a current of magnitude corresponding to the calculation of ". Current I ｓ５ａ is, "f ２ ・D １５ +f ５ ・D ２５ +f ８ ・D ３５ This is a current of a magnitude corresponding to the calculation of "[...]".

[0061] As shown in Figure 7, the filter value f in the third column of the filtered data ３ , f ６ , f ９ This is applied to the wiring XCL1 to XCL3 in the first to third rows. Additionally, the switches in each column are controlled to allow current to flow to the calculation cells 31 in the third and sixth columns of the calculation circuit section 59. With this configuration, the calculation cells 31 in the first to third rows of the third column, and in the first to third rows of the sixth column, are activated.

[0062] In the activated arithmetic cell 31, an analog current corresponding to the product of an analog signal based on a filter value and analog data of held data to be processed flows. Each current is summed by column-direction wirings YCL3 and YCL6, respectively. I flows through the wiring YCL3 ｓ３ａ , and I flows through the wiring YCL6 ｓ６ａ flows. A voltage corresponding to the current I ｓ３ａ is held in the sample-and-hold circuit SH1 connected to the wiring YCL3. A voltage corresponding to the current I ｓ６ａ is held in the sample-and-hold circuit SH1 connected to the wiring YCL6. The current I ｓ３ａ is a current having a magnitude corresponding to the operation of "f ３ ・D １３ + f ６ ・D ２３ + f ９ ・D ３３ ". The current I ｓ６ａ is a current having a magnitude corresponding to the operation of "f ３ ・D １６ + f ６ ・D ２６ + f ９ ・D ３６ ".

[0063] Through the above operation, a voltage corresponding to the product-sum operation result of each column is held in the sample-and-hold circuit SH1 included in the sample-and-hold circuit section 41 connected to the wiring YCL of each column.

[0064] As illustrated in FIG. 8, in order to sum the product-sum operation results of each column held in the sample-and-hold circuit SH1, the switch SW12 included in the switch section 42 is controlled to switch the current path. In the switch section 42, the conduction state of the switch SW12 is switched such that the terminals P1, P2, and P3 in the sample-and-hold circuit section 41 and the terminal Q1 in the sample-and-hold circuit section 43 are brought into conduction. In the switch section 42, the conduction state of the switch SW12 is switched such that the terminals P4, P5, and P6 in the sample-and-hold circuit section 41 and the terminal Q4 in the sample-and-hold circuit section 43 are brought into conduction.

[0065] By switching the current path with the switch unit 42, the current I flows from the terminals P1, P2, P3 in the sample-and-hold circuit SH1 to the terminal Q1 in the sample-and-hold circuit SH2 Ｃ１１ flows. The current I Ｃ１１ is a current having a magnitude corresponding to the calculation of "f １ ・D １１ + f ４ ・D ２１ + f ７ ・D ３１ + f ２ ・D １２ + f ５ ・D ２２ + f ８ ・D ３２ + f ３ ・D １３ + f ６ ・D ２３ + f ９ ・D ３３ ". That is, convolution data C obtained by applying filter data F Ｄ to data to be processed １１ can be obtained. The current I flows from the terminals P4, P5, P6 in the sample-and-hold circuit SH1 to the terminal Q4 in the sample-and-hold circuit SH2 Ｃ１４ flows. The current I Ｃ１４ is a current having a magnitude corresponding to the calculation of "f １ ・D １４ + f ４ ・D ２４ + f ７ ・D ３４ + f ２ ・D １５ + f ５ ・D ２５ + f ８ ・D ３５ + f ３ ・D １６ + f ６ ・D ２６ + f ９ ・D ３６ ". That is, convolution data C obtained by applying filter data F Ｄ to data to be processed １４ can be obtained. In the sample-and-hold circuit SH2 included in the sample-and-hold circuit unit 43, the current I Ｃ１１ , the current I Ｃ１４A voltage corresponding to the magnitude of the current is maintained.

[0066] Next, filtered data F Ｄ This is applied to the data to be processed in the following region. Here, the filtered data F is applied with a stride of 1. Ｄ This explains when to apply this rule.

[0067] As shown in Figure 9, the first column of the filtered data is the filter value f １ , f ４ , f ７ This is applied to the wiring XCL1 to XCL3 in the first to third rows. Additionally, the switches in each column are controlled to allow current to flow through the calculation cell 31 in the second column of the calculation circuit unit 59. With this configuration, the calculation cells 31 in the second column, from the first to the third row, are activated.

[0068] In the activated arithmetic cell 31, an analog current flows corresponding to the product of the analog signal based on the filter value and the analog data of the data to be processed. Each current is added together in the column wiring YCL2. Wiring YCL2 has I ｓ２ｂ Current I flows. ｓ２ｂ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL2. Current I ｓ２ｂ is, "f １ ・D １２ +f ４ ・D ２２ +f ７ ・D ３２ This is a current of a magnitude corresponding to the calculation of "[...]".

[0069] As shown in Figure 10, the filter value f in the second column of the filtered data ２ , f ５ , f ８ This is applied to the wiring XCL1 to XCL3 in the first to third rows. Additionally, the switches in each column are controlled to allow current to flow through the calculation cell 31 in the third column of the calculation circuit unit 59. With this configuration, the calculation cells 31 in the third column, from the first to the third row, are activated.

[0070] In the activated arithmetic cell 31, an analog current flows in accordance with the product of the analog signal based on the filter value and the analog data of the held data to be processed. Each current is summed in the column-direction wiring YCL3. I flows through the wiring YCL3 ｓ３ｂ flows. Current I ｓ３ｂ A voltage corresponding to is held in the sample-and-hold circuit SH1 connected to the wiring YCL3. Current I ｓ３ｂ is "f ２ ・D １３ +f ５ ・D ２３ +f ８ ・D ３３ ", the current has a magnitude corresponding to the operation of

[0071] As illustrated in FIG. 11, the filter values f in the third column of the filter data ３ , f ６ , f ９ are supplied to the first to third row wirings XCL1 to XCL3. Further, the switches of each column are controlled so that a current flows through the fourth-column arithmetic cells 31 in the arithmetic circuit unit 59. With this configuration, the arithmetic cells 31 in the first to third rows of the fourth column are activated.

[0072] In the activated arithmetic cell 31, an analog current flows in accordance with the product of the analog signal based on the filter value and the analog data of the held data to be processed. Each current is summed in the column-direction wiring YCL4. I flows through the wiring YCL4 ｓ４ｂ flows. Current I ｓ４ｂ A voltage corresponding to is held in the sample-and-hold circuit SH1 connected to the wiring YCL4. Current I ｓ４ｂ is "f ３ ・D １４ +f ６ ・D ２４ +f ９ ・D ３４ ", the current has a magnitude corresponding to the operation of

[0073] Through the above operation, the sample-and-hold circuit SH1 included in the sample-and-hold circuit unit 41 connected to the wirings YCL2 to YCL4 holds a voltage corresponding to the product-sum operation result of each column.

[0074] As shown in Figure 12, in order to sum the sum-of-products calculation results of each column held in the sample-and-hold circuit SH1, the switch SW12 of the switch unit 42 is controlled to switch the current path. The switch unit 42 switches the conduction state of the switch SW12 so that terminals P2, P3, and P4 in the sample-and-hold circuit unit 41 and terminal Q2 in the sample-and-hold circuit unit 43 become conductive.

[0075] The switch unit 42 switches the current path, thereby transferring current I from terminals P2, P3, and P4 in sample-and-hold circuit SH1 to terminal Q2 in sample-and-hold circuit SH2. Ｃ１２ Current I flows. Ｃ１２ is, "f １ ・D １２ +f ２ ・D ２２ +f ３ ・D ３２ +f ２ ・D １３ +f ５ ・D ２３ +f ８ ・D ３３ +f ３ ・D １４ +f ６ ・D ２４ +f ９ ・D ３４ This is a current of magnitude corresponding to the calculation of ". In other words, the filter data F Ｄ Convolutional data C obtained by applying this to the data to be processed. １２ It is possible to obtain it.

[0076] Next, filtered data F Ｄ This is applied to the data to be processed in the following region. Here, the filtered data F is applied with a stride of 1, similar to Figures 9 to 12. Ｄ This explains when to apply this rule.

[0077] As shown in Figure 13, the first column of the filtered data is the filter value f １ , f ４ , f ７This is applied to the wiring XCL1 to XCL3 in the first to third rows. Additionally, the switches in each column are controlled to allow current to flow through the calculation cell 31 in the third column of the calculation circuit unit 59. With this configuration, the calculation cells 31 in the third column, from the first to the third row, are activated.

[0078] In the activated calculation cell 31, an analog current flows corresponding to the product of the analog signal based on the filter value and the analog data of the data to be processed. Each current is added together in the column wiring YCL3. Wiring YCL3 has I ｓ３ｃ Current I flows. ｓ３ｃ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL3. Current I ｓ３ｃ is, "f １ ・D １３ +f ４ ・D ２３ +f ７ ・D ３３ This is a current of a magnitude corresponding to the calculation of "[...]".

[0079] As shown in Figure 14, the filter value f in the second column of the filtered data ２ , f ５ , f ８ This is applied to the wiring XCL1 to XCL3 in the first to third rows. Additionally, the switches in each column are controlled to allow current to flow through the calculation cell 31 in the fourth column of the calculation circuit unit 59. With this configuration, the calculation cells 31 in the first to third rows of the fourth column are activated.

[0080] In the activated calculation cell 31, an analog current flows corresponding to the product of the analog signal based on the filter value and the analog data of the data to be processed. Each current is added together in the column wiring YCL4. Wiring YCL4 has I ｓ４ｃ Current I flows. ｓ４ｃ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL4. Current I ｓ４ｃ is, "f ２ ・D １４ +f ５ ・D ２４ +f ８ ・D ３４ This is a current of a magnitude corresponding to the calculation of "[...]".

[0081] As shown in Figure 15, the filter value f in the third column of the filtered data ３ , f ６ , f ９ This is applied to the wiring XCL1 to XCL3 in the first to third rows. Additionally, the switches in each column are controlled to allow current to flow to the calculation cell 31 in the fifth column of the calculation circuit unit 59. With this configuration, the calculation cells 31 in the fifth column, in the first to third rows, are activated.

[0082] In the activated calculation cell 31, an analog current flows corresponding to the product of the analog signal based on the filter value and the analog data of the data to be processed. Each current is added together in the column wiring YCL5. Wiring YCL4 has I ｓ５ｃ Current I flows. ｓ５ｃ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL5. Current I ｓ５ｃ is, "f ３ ・D １５ +f ６ ・D ２５ +f ９ ・D ３５ This is a current of a magnitude corresponding to the calculation of "[...]".

[0083] As a result of the above operation, the sample-and-hold circuit SH1 in the sample-and-hold circuit section 41 connected to wiring YCL3 to YCL5 holds a voltage corresponding to the sum-of-products calculation result of each column.

[0084] As shown in Figure 16, in order to sum the sum-of-products results of each column held in the sample-and-hold circuit SH1, the switch SW12 of the switch unit 42 is controlled to switch the current path. The switch unit 42 switches the conduction state of the switch SW12 so that terminals P3, P4, and P5 in the sample-and-hold circuit unit 41 and terminal Q3 in the sample-and-hold circuit unit 43 become conductive.

[0085] The switch unit 42 switches the current path, thereby transferring current I from terminals P3, P4, and P5 in sample-and-hold circuit SH1 to terminal Q3 in sample-and-hold circuit SH2. Ｃ１３ Current I flows. Ｃ１３ is, "f１ ・D １３ +f ２ ・D ２３ +f ３ ・D ３３ +f ２ ・D １４ +f ５ ・D ２４ +f ８ ・D ３４ +f ３ ・D １５ +f ６ ・D ２５ +f ９ ・D ３５ This is a current of magnitude corresponding to the calculation of ". In other words, the filter data F Ｄ Convolutional data C obtained by applying this to the data to be processed. １３ It is possible to obtain it.

[0086] As a result of the above operations, the convolved data C is obtained by convolving the data to be processed in rows 1 through 3 and columns 1 through 6. １１ ~C １４ It is possible to find this.

[0087] In Figures 17 to 28, the filtered data F Ｄ To be processed, Data D Ｐ The second through fourth lines will explain how this applies to each address in columns 1 through 6. In other words, it will explain the case where the stride in the column direction is 1. Note that in the following explanation, explanations that are repetitions of Figures 5 through 16 may be omitted, with the explanation being left to the drawings.

[0088] As shown in Figure 17, the first column of the filtered data is the filter value f １ , f ４ , f ７ Give this to wiring XCL2 to XCL4 in rows 2 to 4. Wiring YCL1 has I ｓ１ｄ Wiring YCL4 is I ｓ４ｄ Current I flows. ｓ１ｄ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL1. Current I ｓ４ｄ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL4. Current I ｓ１ｄ is, "f １ ・D２１ +f ４ ・D ３１ +f ７ ・D ４１ This is a current of magnitude corresponding to the calculation of ". Current I ｓ４ｄ is, "f １ ・D ２４ +f ４ ・D ３４ +f ７ ・D ４４ This is a current of a magnitude corresponding to the calculation of "[...]".

[0089] As shown in Figure 18, the filter value f in the second column of the filtered data ２ , f ５ , f ８ Give this to wiring XCL2 to XCL4 in rows 2 to 4. Wiring YCL2 has I ｓ２ｄ , wiring YCL5 is I ｓ５ｄ Current I flows. ｓ２ｄ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL2. Current I ｓ５ｄ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL5. Current I ｓ２ｄ is, "f ２ ・D ２２ +f ５ ・D ３２ +f ８ ・D ４２ This is a current of magnitude corresponding to the calculation of ". Current I ｓ５ｄ is, "f ２ ・D ２５ +f ５ ・D ３５ +f ８ ・D ４５ This is a current of a magnitude corresponding to the calculation of "[...]".

[0090] As shown in Figure 19, the filter value f in the third column of the filtered data ３ , f ６ , f ８ Give this to wiring XCL2 to XCL4 in rows 2 to 4. Wiring YCL3 is I ｓ３ｄ Wiring YCL6 is I ｓ６ｄ Current I flows. ｓ３ｄ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL3. Current Iｓ６ｄ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL6. Current I ｓ３ｄ is, "f ３ ・D ２３ +f ６ ・D ３３ +f ９ ・D ４３ This is a current of magnitude corresponding to the calculation of ". Current I ｓ６ｄ is, "f ３ ・D ２６ +f ６ ・D ３６ +f ９ ・D ４６ This is a current of a magnitude corresponding to the calculation of "[...]".

[0091] As a result of the above operation, the sample-and-hold circuit SH1 of the sample-and-hold circuit section 41 connected to wiring YCL1 to YCL6 holds a voltage corresponding to the sum-of-products calculation result of each column.

[0092] As shown in Figure 20, in order to sum the sum-of-products calculation results of each column held in the sample-and-hold circuit SH1, the switch SW12 of the switch unit 42 is controlled to switch the current path. By switching the current path in the switch unit 42, current I is supplied from terminals P1, P2, and P3 in the sample-and-hold circuit SH1 to terminal Q1 in the sample-and-hold circuit SH2. Ｃ２１ Current I flows. Ｃ２１ is, "f １ ・D ２１ +f ４ ・D ３１ +f ７ ・D ４１ +f ２ ・D ２２ +f ５ ・D ３２ +f ８ ・D ４２ +f ３ ・D ２３ +f ６ ・D ３３ +f ９ ・D ４３This is a current of a magnitude corresponding to the calculation of ". By switching the current path in the switch section 42, current I is supplied from terminals P4, P5, and P6 in the sample-and-hold circuit SH1 to terminal Q4 in the sample-and-hold circuit SH2. Ｃ２４ Current I flows. Ｃ２４ is, "f １ ・D ２４ +f ４ ・D ３４ +f ７ ・D ４４ +f ２ ・D ２５ +f ５ ・D ３５ +f ８ ・D ４５ +f ３ ・D ２６ +f ６ ・D ３６ +f ９ ・D ４６ This is a current of a magnitude corresponding to the calculation of "[...]".

[0093] Next, filtered data F Ｄ This applies to the data being processed in the following areas.

[0094] As shown in Figure 21, the first column of the filtered data is the filter value f １ , f ４ , f ７ Give this to wiring XCL2 to XCL4 in rows 2 to 4. Wiring YCL2 has I ｓ２ｅ Current I flows. ｓ２ｅ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL2. Current I ｓ２ｅ is, "f １ ・D ２２ +f ４ ・D ３２ +f ７ ・D ４２ This is a current of a magnitude corresponding to the calculation of "[...]".

[0095] As shown in Figure 22, the filter value f in the second column of the filtered data ２ , f ５ , f ８ Give this to wiring XCL2 to XCL4 in rows 2 to 4. Wiring YCL3 is I ｓ３ｅ Current I flows. ｓ３ｅThe corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL3. Current I ｓ３ｅ is, "f ２ ・D ２３ +f ５ ・D ３３ +f ８ ・D ４３ This is a current of a magnitude corresponding to the calculation of "[...]".

[0096] As shown in Figure 23, the filter value f in the third column of the filtered data ３ , f ６ , f ８ Give this to wiring XCL2 to XCL4 in rows 2 to 4. Wiring YCL4 has I ｓ４ｅ Current I flows. ｓ４ｅ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL4. Current I ｓ４ｅ is, "f ３ ・D ２４ +f ６ ・D ３４ +f ９ ・D ４４ This is a current of a magnitude corresponding to the calculation of "[...]".

[0097] As a result of the above operation, the sample-and-hold circuit SH1 in the sample-and-hold circuit section 41 connected to wiring YCL2 to YCL4 holds a voltage corresponding to the sum-of-products calculation result of each column.

[0098] As shown in Figure 24, in order to sum the sum-of-products calculation results of each column held in the sample-and-hold circuit SH1, the switch SW12 of the switch unit 42 is controlled to switch the current path. By switching the current path in the switch unit 42, current I is supplied from terminals P2, P3, and P4 in the sample-and-hold circuit SH1 to terminal Q2 in the sample-and-hold circuit SH2. Ｃ２２ Current I flows. Ｃ２２ is, "f １ ・D ２２ +f ４ ・D ３２ +f ７ ・D ４２ +f ２ ・D ２３ +f ５ ・D ３３ +f８ ・D ４３ +f ３ ・D ２４ +f ６ ・D ３４ +f ９ ・D ４４ This is a current of a magnitude corresponding to the calculation of "[...]".

[0099] Next, filtered data F Ｄ This applies to the data being processed in the following areas.

[0100] As shown in Figure 25, the first column of the filtered data is the filter value f １ , f ４ , f ７ Give this to wiring XCL2 to XCL4 in rows 2 to 4. Wiring YCL3 is I ｓ３ｆ Current I flows. ｓ３ｆ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL3. Current I ｓ３ｆ is, "f １ ・D ２３ +f ４ ・D ３３ +f ７ ・D ４３ This is a current of a magnitude corresponding to the calculation of "[...]".

[0101] As shown in Figure 26, the filter value f in the second column of the filtered data ２ , f ５ , f ８ Give this to wiring XCL2 to XCL4 in rows 2 to 4. Wiring YCL4 has I ｓ４ｆ Current I flows. ｓ４ｆ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL4. Current I ｓ４ｆ is, "f ２ ・D ２４ +f ５ ・D ３４ +f ８ ・D ４４ This is a current of a magnitude corresponding to the calculation of "[...]".

[0102] As shown in Figure 27, the filter value f in the third column of the filtered data ３ , f ６ , f ８Give this to wiring XCL2 to XCL4 in rows 2 to 4. Wiring YCL5 is I ｓ５ｆ Current I flows. ｓ５ｆ The corresponding voltage is held in the sample-and-hold circuit SH1 connected to wiring YCL5. Current I ｓ５ｆ is, "f ３ ・D ２５ +f ６ ・D ３５ +f ９ ・D ４５ This is a current of a magnitude corresponding to the calculation of "[...]".

[0103] As a result of the above operation, the sample-and-hold circuit SH1 in the sample-and-hold circuit section 41 connected to wiring YCL3 to YCL5 holds a voltage corresponding to the sum-of-products calculation result of each column.

[0104] As shown in Figure 28, in order to sum the sum-of-products calculation results of each column held in the sample-and-hold circuit SH1, the switch SW12 of the switch unit 42 is controlled to switch the current path. By switching the current path in the switch unit 42, current I is supplied from terminals P3, P4, and P5 in the sample-and-hold circuit SH1 to terminal Q3 in the sample-and-hold circuit SH2. Ｃ２３ Current I flows. Ｃ２３ is, "f １ ・D ２３ +f ４ ・D ３３ +f ７ ・D ４３ +f ２ ・D ２４ +f ５ ・D ３４ +f ８ ・D ４４ +f ３ ・D ２５ +f ６ ・D ３５ +f ９ ・D ４５ This is a current of a magnitude corresponding to the calculation of "[...]".

[0105] As a result of the above operations, the convolved data C is obtained by convolving the data to be processed in the first to sixth columns of the second to fourth rows. ２１ ~C ２４ It is possible to find this.

[0106] After the acquisition of convolution data is completed through a series of processes, the convolution data can be stored in an external storage device. The analog data held in the calculation cell 31 can be updated to perform convolution calculations on other data to be processed. The drive circuit 11 only needs to update the filter data, making the update process simple and convenient. By using the example of operation of the calculation device described above, calculations of the convolutional neural network can be performed effectively.

[0107] <Example of the configuration of the arithmetic circuit section> Figures 29A to 29C illustrate an example of the configuration of the arithmetic cell 31 of the arithmetic circuit section 59. As described above, the arithmetic cell 31 of the arithmetic circuit section 59 holds analog data corresponding to the first data and supplies an analog signal corresponding to the second data to the wiring XCL, thereby allowing an analog current corresponding to the third data to flow to the wiring YCL.

[0108] As an example, the calculation cell 31 can use a variable resistor element 19, as shown in Figure 29A. The variable resistor element 19 can be placed between wiring XCL and wiring YCL, as shown in Figure 29A. Preferably, the variable resistor element 19 is an element that holds a resistance value of a magnitude corresponding to the first data. For example, resistance change elements such as magnetoresistive materials, ferroelectric materials, and phase change materials can be used. By applying a current or voltage of a magnitude corresponding to the second data to wiring XCL, an analog current can be passed through wiring YCL.

[0109] Furthermore, as shown in Figure 29B, the calculation cell 31 can also be configured to have multiple transistors. The calculation cell 31 shown in Figure 29B includes a capacitive element 35, transistors 32, 33, and 34. Transistor 32 functions as a switch whose conduction or non-conduction state is controlled by the wiring WSL. Transistor 33 is a transistor whose gate is connected to the wiring VBL that provides a constant potential. Note that transistor 33 can also be omitted, as shown in Figure 29C.

[0110] In the calculation cell 31 shown in Figure 29B, the capacitive element 35, transistor 32, transistor 33, and transistor 34 are connected as shown. For example, one source or drain of transistor 32 is connected to one electrode of the capacitive element 35. The other source or drain of transistor 32 is connected to wiring YCL. The gate of transistor 34 is connected to one electrode of the capacitive element 35. The other electrode of the capacitive element 35 is connected to wiring XCL.

[0111] With this configuration, the charge on the gate of transistor 34 can be maintained by making transistor 32 non-conductive. Furthermore, the gate of transistor 34 can be left floating.

[0112] Transistors 32 to 34 are preferably transistors having a semiconductor layer with a metal oxide (also called an oxide semiconductor (OS)) (OS transistors). OS transistors have an extremely small current flowing between the source and drain in the non-conductive state (off state), i.e., a leakage current. For example, by applying an OS transistor to transistor 32, it is possible to easily maintain the charge held in the gate of transistor 34 and the floating state of the gate of transistor 34.

[0113] The metal oxide is preferably an oxide containing at least one of indium, element M (where M is Al, Ga, Y, or Sn), or zinc. This configuration allows for a transistor with extremely low off-state activity. It also allows for a large current to flow when conducting (on-current).

[0114] The operation of the calculation cell 31 shown in Figure 29B will be explained below. Specifically, the storage of the data to be processed and the sum-of-products operation between the stored data to be processed and the filtered data will be explained.

[0115] <<Calculation Cell 31>> Figure 30 is a diagram illustrating an example configuration of a calculation circuit unit 59 including one calculation cell 31. In addition to the calculation cell 31, the calculation circuit unit 59 has a reference cell 21. The reference cell 21 has transistors 22, 23, 24 and a capacitive element 25. The calculation cell 31 has transistors 32, 33, 34 and a capacitive element 35. The transistors and capacitive elements of the reference cell 21 and the calculation cell 31 are connected to at least one of the wirings WSL, XCL, VBL, YCL and the wiring that provides the ground potential, as shown in Figure 30.

[0116] The reference cell 21 maintains a reference voltage within it by receiving a reference current when the data to be processed (x) is written to it. During calculation processing, the reference cell 21 has the function of controlling the current flowing to the calculation cell 31 by supplying a current to the reference cell 21 according to the filter data (w) supplied to the calculation cell 31. The reference cell 21 is sometimes simply referred to as a cell.

[0117] Next, I will explain the connection relationships within reference cell 21.

[0118] The gate of transistor 22 is connected to wiring WSL. One of the sources or drains of transistor 22 is connected to one of the sources or drains of transistor 23 and wiring XCL. The other of the sources or drains of transistor 22 is connected to the gate of transistor 24 and one electrode of capacitive element 25. Transistor 22 can write the reference voltage to the holding node (gate of transistor 24) in the reference cell 21 when the data to be processed is written, and can hold the reference voltage in the reference cell 21 by turning it off.

[0119] The gate of transistor 23 is connected to wiring VBL. The back gate of transistor 23 is connected to the other source or drain of transistor 24. One source or drain of transistor 23 is connected to one source or drain of transistor 22 and wiring XCL. The other source or drain of transistor 23 is connected to one source or drain of transistor 24. Transistor 23 sets the potential of one source or drain of transistor 24 to a potential corresponding to the potential of the gate of transistor 23.

[0120] The gate of transistor 24 is connected to the other side of the source or drain of transistor 22, and to one electrode of the capacitive element 25. The node to which the gate of transistor 24, the other side of the source or drain of transistor 22, and one electrode of the capacitive element 25 are connected is also called a holding node. The holding node can be set to a potential corresponding to the current flowing through transistor 24. The back gate of transistor 24 is connected to the other side of the source or drain of transistor 24. The other side of the source or drain of transistor 24 is connected to a wire that provides a low power supply potential (e.g., ground potential). This wire that provides the ground potential functions as a wire for current to flow between the source and drain of transistor 24. The other side of the source or drain of transistor 24 is connected to the back gate of transistor 23 and the back gate of transistor 24. A fixed potential is applied to the back gates of transistor 23 and transistor 24, stabilizing the transistor characteristics of transistors 23 and 24. Transistor 24 flows an output current corresponding to the potential of its gate to the other side of the source or drain.

[0121] One electrode of the capacitive element 25 is connected to the other side of the source or drain of transistor 22 and to the gate of transistor 24. The other electrode of the capacitive element 25 is connected to wiring XCL. When one electrode of the capacitive element 25 is in a floating state, it changes the potential of one electrode in response to a change in the potential of the other electrode.

[0122] The calculation cell 31 has the function of maintaining a voltage corresponding to the current when the data to be processed is written, by supplying a current corresponding to the data to be processed. Furthermore, during calculation processing, the calculation cell 31 has the function of supplying a current corresponding to the sum-of-products operation (wx) of the filter data (w) and the data to be processed (x) by boosting the voltage held when the data to be processed was written according to the current flowing through the reference cell 21. Note that the calculation cell 31 is sometimes simply referred to as a cell.

[0123] Next, I will explain the connections within the calculation cell 31.

[0124] The gate of transistor 32 is connected to wiring WSL. One of the sources or drains of transistor 32 is connected to one of the sources or drains of transistor 33 and wiring YCL. The other of the sources or drains of transistor 32 is connected to the gate of transistor 34 and one electrode of capacitive element 35. Transistor 32 can be turned ON when writing data to be processed, writing a voltage corresponding to the data to be processed into the calculation cell 31, and can be turned OFF to retain a voltage corresponding to the data to be processed in the calculation cell 31.

[0125] The gate of transistor 33 is connected to wiring VBL. The back gate of transistor 33 is connected to the other source or drain of transistor 34. One source or drain of transistor 33 is connected to one source or drain of transistor 32 and wiring YCL. The other source or drain of transistor 33 is connected to one source or drain of transistor 34. Transistor 33 sets the potential of one source or drain of transistor 34 to a potential corresponding to the potential of the gate of transistor 33.

[0126] The gate of transistor 34 is connected to the other source or drain of transistor 32 and to one electrode of the capacitive element 35. The node to which the gate of transistor 34, the other source or drain of transistor 32, and one electrode of the capacitive element 35 are connected is also called a holding node. The back gate of transistor 34 is connected to the other source or drain of transistor 34. The other source or drain of transistor 34 is connected to a wire that provides a low power supply potential (e.g., ground potential). This wire that provides the ground potential functions as a wire for current to flow between the source and drain of transistor 34. The other source or drain of transistor 34 is connected to the back gate of transistor 33 and the back gate of transistor 34. A fixed potential is applied to the back gates of transistor 33 and transistor 34, stabilizing the transistor characteristics of transistors 33 and 34. Transistor 34 flows an output current to the other source or drain corresponding to the potential of its gate.

[0127] One electrode of the capacitive element 35 is connected to the other source or drain of transistor 32 and to the gate of transistor 34. The other electrode of the capacitive element 35 is connected to wiring XCL. When one electrode of the capacitive element 35 is floating, it changes the potential of the other electrode in response to a change in the potential of the other electrode.

[0128] Next, the transistors in the reference cell 21 and the calculation cell 31 will be described.

[0129] Transistors 24 and 34 operate in the subthreshold region unless otherwise specified. The drain current Id of transistors operating in the subthreshold region can be expressed by equation (1).

[0130]

[0131] In formula (1), I ０ is V ｇ = V ｔｈ The drain current at this time is q, where q is the elementary charge, and Vｇ V is the gate voltage. ｔｈ η is the threshold voltage, η is a coefficient determined by the device structure, etc., k Ｂ θ is the Boltzmann constant, and T is the temperature. As shown in equation (1), the drain current Id of a transistor operating in the subthreshold region does not depend on the drain voltage. The current flowing through transistors 24 and 34 is the amount of current that flows when operating in the subthreshold region. The current in the subthreshold region of transistors 24 and 34 can reduce the effect of variations in drain voltage. Therefore, the accuracy of the data obtained by calculation can be improved.

[0132] In this specification, the subthreshold region refers to the region in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the gate voltage is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, deviating from the gradient dual-channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where the drain current increases exponentially with increasing gate voltage. Alternatively, the subthreshold region includes regions that can be considered as the regions described in each of the above explanations.

[0133] Furthermore, the drain current when a transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with respect to the gate voltage, regardless of the drain voltage. Circuit operation using the subthreshold current can reduce the effects of variations in drain voltage.

[0134] Furthermore, transistors 32 and 22 have the function of maintaining the potential of the gates of transistor 24 and transistor 34 when they are in the off state. Specifically, they have the function of maintaining a potential corresponding to the data supplied to the gate of transistor 34 via transistor 32. Transistors 32 and 22 are preferably OS transistors, as an example.

[0135] As mentioned above, OS transistors have extremely low leakage current, or current flowing between the source and drain in the off state. By using OS transistors as transistors 32 and 22, the leakage current of transistors 32 and 22 can be suppressed, thereby reducing the power consumption of the arithmetic circuit 59. Specifically, the fluctuation of the potential held at the gates of transistors 24 and 34 can be made very small, thus reducing the need for potential refresh operations. Reducing refresh operations also reduces the power consumption of the arithmetic circuit 59. Furthermore, by making the leakage current from the holding node to wiring YCL or wiring XCL very small, the cell can maintain the potential of the holding node for a long time.

[0136] Furthermore, when the gate voltage of an OS transistor is less than the transistor's threshold voltage, it is 1 × 10⁻¹⁰ −２０ Less than A, 1 x 10 −２２ Less than A, or 1 x 10 −２４ It is possible to pass extremely small currents as drain current per 1 μm of channel width, such as less than A. Furthermore, when the gate voltage of an OS transistor is the transistor's threshold voltage, it can pass 1.0 × 10⁻¹⁰ −８ A or less, 1.0×10 −１２ A or less, or 1.0 × 10 −１５ It is possible to pass a drain current of less than A per 1 μm channel width. Therefore, OS transistors can pass subthreshold currents of different magnitudes within the gate voltage range in which they operate in the subthreshold region. In other words, OS transistors can have a wide gate voltage range in which they operate in the subthreshold region. Specifically, the threshold voltage of the OS transistor is set to V ｔｈ In that case, in the subthreshold region, (V ｔｈ -1.0V) or more V ｔｈ The following, or (V ｔｈ -0.5V) or more V ｔｈ The circuit can be operated using gate voltages within the following voltage range.

[0137] On the other hand, Si transistors have a large off-current and a narrow gate voltage range in which they operate in the subthreshold region. When utilizing subthreshold current, OS transistors can operate in a wider gate voltage range than Si transistors.

[0138] Next, the wiring WSL, wiring XCL, wiring VBL, and wiring YCL connected to the reference cell 21 and calculation cell 31 will be described.

[0139] Wiring WSL receives signals that control the on / off state of transistors 22 and 32, which function as switches. Wiring WSL also functions as a write word line when writing data to reference cell 21 and calculation cell 31. Data is written to reference cell 21 and calculation cell 31 by applying current or voltage corresponding to the data to be written to wiring XCL and wiring YCL. This data is written by turning on transistors 22 and 32. In this case, wiring WSL is at an H level (high potential). In reference cell 21 and calculation cell 31, the data is held in reference cell 21 and calculation cell 31 by controlling transistors 22 and 32 to be turned off. In this case, wiring WSL is at an L level (low potential).

[0140] The wiring YCL supplies a current (data current or current I) to the calculation cell 31 according to the data to be processed. Ｙｕｔ It has the function of supplying current, or the function of supplying a voltage Vd to supply current according to the potential held in the calculation cell 31.

[0141] The wiring XCL supplies current (reference current or current I) to the reference cell 21 and the calculation cell 31 according to the reference data. Ｗｕｔ ), or current amount corresponding to the filter data (weighted current or current I Ｗ It has the function of distributing (a substance).

[0142] Wiring VBL is a wiring to which a constant potential Vb is applied. The constant potential Vb is the potential used to fix the potential of the drain terminals of transistors 24 and 34 in the reference cell 21 and the calculation cell 31. By applying a constant potential Vb to the gates of transistors 23 and 33, the transistor characteristics of transistors 24 and 34, such as the threshold voltage, can be stabilized in response to fluctuations in the potential of wiring YCL.

[0143] In particular, if transistors 34 and 24 are short-channel transistors with short channel lengths, the threshold voltage decreases due to drain-induced barrier lowering (DIBL), causing the drain current to become dependent on the drain voltage. Therefore, a configuration that applies a constant potential Vb to the gates of transistors 23 and 33 and reduces the change in the drain voltage of transistors 24 and 34 is effective. This configuration can improve the accuracy of the data obtained by calculations.

[0144] Next, the configuration in which multiple reference cells 21 and calculation cells 31 are provided in Figure 30 will be explained with reference to Figures 31A and 31B. Figure 31A shows an overview of the operation when data to be processed is written, and Figure 31B shows an overview of the operation when calculation processing is performed.

[0145] Figures 31A and 31B show a reference cell section 20 comprising multiple cells 21_1 to 21_m (corresponding to the reference cell 21 in Figure 30), and a calculation cell section 30 comprising multiple calculation cells 31_1, 1 to 31_m, n (corresponding to the calculation cell 31 in Figure 30). In Figures 31A and 31B, multiple wirings XCL are shown as wirings XCL_1 to XCL_m. In Figures 31A and 31B, multiple wirings YCL are shown as wirings YCL_1 to YCL_n. Both m and n are natural numbers.

[0146] In Figures 31A and 31B, the cells of the reference cell section 20 and the calculation cell section 30 are arranged in a matrix with n+1 cells in the row direction and m cells in the column direction. However, the cells of the reference cell section 20 and the calculation cell section 30 can be arranged in a matrix with two or more cells in the row direction and one or more cells in the column direction.

[0147] In Figures 31A and 31B, the reference cell 21 and calculation cell 31 are shown in a simplified manner for illustrative purposes. Terminal C of the reference cell 21 in the reference cell section 20. Ｐ This corresponds to the other electrode of the capacitive element 25 in Figure 30. Terminal T of the reference cell 21 in the reference cell section 20. Ｗ This corresponds to the terminal to which one of the source or drain of transistor 22 and one of the source or drain of transistor 23 are connected in Figure 30. Terminal C of calculation cell 31 in calculation cell unit 30 Ｐ This corresponds to the other electrode of the capacitive element 35 in Figure 30. Terminal T of the calculation cell 31 in the calculation cell unit 30. Ｘ This corresponds to the terminals to which one of the source or drain of transistor 32 and one of the source or drain of transistor 33 are connected in Figure 30.

[0148] In the operation when writing the data to be processed shown in Figure 31A, current I is applied to the reference cell 21 of each row. Ｗｕｔ The current is passed through each row. The current supplied to each row is the normalized current I Ｗｕｔ The current I is equal to the current I. Ｗｕｔ This corresponds to the amount of current (reference current) corresponding to the reference data. No current flows through the calculation cells 31 in each row because they are connected via capacitors. The reference cell 21 operates to maintain a voltage corresponding to the current flowing through it.

[0149] Furthermore, in the operation when writing the data to be processed shown in Figure 31A, current I is applied to the calculation cells in each column. Ｙ１ ~I Ｙｎ (I Ｙ ) is passed through. The current supplied to each column is the normalized current I Ｙｕｔ This corresponds to the amount of current obtained by multiplying the data to be processed Y by (I Ｙ = Y × I Ｙｕｔ ). current I Ｙ１ ~IＹｎ These values ​​may differ from column to column.

[0150] In the calculation process shown in Figure 31B, current I is supplied to the reference cell 21 of each row. Ｗ１ ~I Ｗｍ (I Ｗ ) is passed through. Current I is applied to each row. Ｗ１ ~I Ｗｍ This is a normalized current I Ｗｕｔ This corresponds to the current amount obtained by multiplying by the filter data W (I Ｗ = W × I Ｗｕｔ ). current I Ｗ１ ~I Ｗｍ The values ​​may differ from row to row. Note that current I Ｗｕｔ is current I Ｙｕｔ It is preferable that it be equal to.

[0151] In the operation during the calculation process shown in Figure 31B, the current I Ｗ１ ~I Ｗｍ The voltage held in reference cell 21 is increased. In response to this increase, the voltages of wiring XCL_1 to XCL_m are also increased, so the voltage held by the capacitive coupling of capacitive element 35 in calculation cell 31 is increased. The potential of wiring YCL_1 to YCL_n is then set to voltage Vd. At this time, the current I flowing through transistor 34 ｒ This is the current value (I) held in the calculation cell 31 when writing the data to be processed. Ｙ ) and the current value (I) that flowed through the reference cell 21 during the calculation process. Ｗ ) and the product of (current I ｒ１１ ~I ｒｍｎ ). Current I flowing through each column ｒ１１ ~I ｒｍｎ By estimating the sum of these values, it is possible to output data equivalent to the result of the sum of products calculation between the processed data and the filtered data.

[0152] It is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors 32 to 34 contained in each cell of the calculation cell unit 30 are equal. It is also preferable that the sizes of the transistors 22 to 24 contained in each cell of the reference cell unit 20 are equal. Furthermore, it is preferable that the sizes of transistors 22 and 32 are equal. Furthermore, it is preferable that the sizes of transistors 23 and 33 are equal. Furthermore, it is preferable that the sizes of transistors 24 and 34 are equal.

[0153] By making the sizes of the transistors equal, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of the transistor 32 contained in each of cells 31_1,1 to 31_m,n equal, the size of the transistor 33 contained in each of cells 31_1,1 to 31_m,n equal, and the size of the transistor 34 contained in each of cells 31_1,1 to 31_m,n equal, each of cells 31_1,1 to 31_m,n can perform approximately the same operation under identical conditions. These identical conditions refer to, for example, the input potentials to the source, drain, and gate of transistor 32, the input potentials to the source, drain, and gate of transistor 33, the input potentials to the source, drain, and gate of transistor 34, and the voltages held in each of cells 31_1,1 to 31_m,n. Furthermore, by making the size of the transistors 22, 23, and 24 contained in each of cells 21_1 to 21_m equal, for example, cells 21_1 to 21_m can be made to operate and produce substantially the same results. They can perform substantially the same operation under the same conditions. The same conditions here refer to, for example, the input potentials to the source, drain, and gate of transistor 22, the input potentials to the source, drain, and gate of transistor 23, the input potentials to the source, drain, and gate of transistor 24, and the voltages held in each of cells 21_1 to 21_m.

[0154] The operation of the reference cell 21 and the calculation cell 31 when writing the data to be processed will be explained with reference to Figure 32A.

[0155] Set wiring WSL to the high level, and turn on transistors 22 and 32. A current I corresponding to the reference current is drawn into wiring XCL. Ｗｕｔ A current is passed through the wiring YCL. Ｙ Current IＹ This is a current I normalized to the data Y being processed. Ｙｕｔ The current obtained by multiplying by (in the figure, I Ｙ = Y * I Ｙｕｔ This corresponds to ).

[0156] In reference cell 21, transistor 22 is turned ON. The potential of the holding node, which is the gate of transistor 24, is such that transistor 24 is subjected to current I Ｗｕｔ V is the potential through which the current flows. ｇ１ As a result, transistor 24 receives current I Ｗｕｔ The current can be passed between the source and drain of transistor 24. In this specification, this operation is referred to as "the current flowing between the source and drain of transistor 24 of reference cell 21 is I Ｗｕｔ It is sometimes referred to as "setting (programming) it."

[0157] In the calculation cell 31, transistor 32 is turned ON. The potential of the holding node, which is the gate of transistor 34, is such that transistor 34 is subjected to current I Ｙ V is the potential through which the current flows. ｇ２ This results in the current flowing between the source and drain of the transistor 34 of the calculation cell 31 being I Ｙ Set to this.

[0158] Current I supplied to the reference cell 21 via wiring XCL when writing data to be processed Ｗｕｔ This can be expressed by equation (2).

[0159]

[0160] In equation (2), V ｇ１ V is the potential of the holding node, which is the gate of transistor 24. In equation (2), V ｔｈ１ ' is the threshold voltage of transistor 24.

[0161] Current I supplied to the calculation cell 31 via wiring YCL when writing the data to be processed Ｙ This can be expressed by equation (3).

[0162]

[0163] In equation (3), Vｇ２ V is the potential of the holding node, which is the gate of transistor 34. In equation (3), V ｔｈ１ This is the threshold voltage of transistor 34. Current I Ｙ This consists of the data to be processed Y and the normalized current I. Ｙｕｔ It can be expressed as a product of .

[0164] Furthermore, the constant potential Vb applied to the wiring VBL is V ｔｈ２ The threshold voltage of transistor 33, V ｔｈ２ If we let ' be the threshold voltage of transistor 23, then Vb > V ｔｈ２ ', and Vb > V ｔｈ２ This configuration allows the drain voltage of transistor 24 to be (Vb- Ｖｔｈ２ ) can be set to (Vb-V ｔｈ２ This can be done by setting the drain voltages of transistors 24 and 34 to a potential independent of the potentials of wiring YCL and XCL. This suppresses the decrease in threshold voltage due to DIBL of transistors 34 and 24, and improves the accuracy of the data obtained by the calculation.

[0165] The operation of the reference cell 21 and the calculation cell 31 during calculation processing will be explained with reference to Figure 32B. A period can be provided during which a set current is held between the time of writing the data to be processed and the time of calculation processing. During this period of holding the set current, transistors 22 and 32 are set to the OFF state. By making transistors 22 and 32 OS transistors, the potential of the holding node corresponding to the set current can be continuously maintained.

[0166] In reference cell 21, the wiring WSL is set to the L level, and the transistor 22 is turned OFF. A current I corresponding to the weight current is applied to the wiring XCL. Ｗ Current I Ｗ This is the current I normalized to the filter data W. Ｗｕｔ The current obtained by multiplying by (in the figure, I Ｗ =W*I ＷｕｔThis corresponds to the current I of transistor 24. Ｗ As V flows ｇ１ As the voltage fluctuates by +Δ, the potential of the wiring XCL also fluctuates along with it.

[0167] In the calculation cell 31, the wiring WSL is set to the L level, and the transistor 32 is turned off. Therefore, the holding node of the calculation cell 31 is in a floating state. Due to the capacitive coupling of the capacitive element 35 caused by the fluctuation in the potential of the wiring XCL due to the operation of the reference cell 21, the potential V of the holding node of the calculation cell 31 is affected. ｇ２ V fluctuates, ｇ２ The result is +Δ. The potential of the holding node of the calculation cell 31 is V ｇ２ As it fluctuates by +Δ, the transistor 34 of the calculation cell 31 receives current I ｒ It plays.

[0168] Current I supplied to the reference cell 21 via the wiring WSL during calculation processing Ｗ This can be expressed by equation (4). V ｇ１ +Δ represents current I Ｗ This is the change in potential of the holding node of reference cell 21 due to the flow of the current through reference cell 21.

[0169]

[0170] In equation (4), Δ can be represented by the data to be processed Y shown in equation (5).

[0171]

[0172] From equations (4) and (5), the current I Ｗ This consists of the filter data W and the normalized current I. Ｗｕｔ It can be expressed as a product of .

[0173] During calculation processing, the wiring YCL is voltage V so that current flows to the calculation cell 31 in each row. ｄ Set to V. Then, the potential of the holding node of the calculation cell 31 is V. ｇ２ The change to +Δ causes the current I flowing through the transistor 34 of the calculation cell 31. ｒ This can be expressed by equation (6).

[0174]

[0175] I in equations (3), (5) to (6) ｒ This current can be estimated to be equivalent to the product of the filtered data W and the data to be processed Y. Since the currents flowing through the calculation cells 31 in each row can be added together, by outputting the current flowing through the wiring YCL to the outside, a signal corresponding to the calculation result of the sum-of-products calculation process based on the filtered data W and the data to be processed Y can be output.

[0176] Figure 33 shows an example configuration of the arithmetic circuit unit 59 that performs a sum-of-products operation on the data to be processed (first data) and the filtered data (second data), as well as peripheral circuits (drive circuit 11, drive circuit 12, drive circuit 13, circuit SWS1, circuit SWS2, sample-and-hold circuit unit 41, switch unit 42, sample-and-hold circuit unit 43). The arithmetic circuit unit 59 shown in Figure 33 is a circuit that performs a sum-of-products operation on the first data corresponding to the potential held in each cell and the input second data.

[0177] The arithmetic circuit section 59 has cells 31_1,1 to 31_m,n and cells 21_1 to 21_m. Each of cells 31_1,1 to 31_m,n has, for example, a transistor 32, a transistor 33, a transistor 34, and a capacitive element 35, similar to the arithmetic cell 31 described above. Each of cells 21_1 to 21_m has, for example, a transistor 22, a transistor 23, a transistor 24, and a capacitive element 25, similar to the reference cell 21 described above. In the following description, the "source or drain" described above may be referred to as the "first terminal," and the "other source or drain" as the "second terminal." Also, in the following description, one electrode of a capacitor may be referred to as the "first terminal," and the "other electrode" as the "second terminal."

[0178] In Figure 33, in cell 31_1,1, the connection point between the first terminal of transistor 32, the gate of transistor 34, and the first terminal of capacitive element 35 is designated as node NN_11. Similarly, in Figure 33, in cells 31_1,n, 31_m,1, and 31_m,n, the same connection points are designated as nodes NN_1n, NN_m1, and NN_mn. Similarly, in Figure 33, in cells 21_1 and 21_m, the same connection points are designated as nodes NN_ref1 and NNref_m. Note that nodes NN_11 through NN_mn, and nodes NNref_1 through NNref_m, function as holding nodes for their respective cells.

[0179] Circuit SWS1, as an example, includes transistors F3_1 to F3_n. The first terminal of transistor F3_1 is connected to wiring YCL_1, the second terminal of transistor F3_1 is connected to the drive circuit 12, and the gate of transistor F3_1 is connected to wiring SWL1. The first terminal of transistor F3_n is connected to wiring YCL_n, the second terminal of transistor F3_n is connected to the drive circuit 12, and the gate of transistor F3_n is connected to wiring SWL1.

[0180] For each of transistors F3_1 to F3_n, for example, transistors applicable to the transistors in the arithmetic circuit section 59 can be used. In particular, it is preferable to use OS transistors for each of transistors F3_1 to F3_n.

[0181] Circuit SWS1 functions as a circuit that switches the connection state between the drive circuit 12 and each of the wirings YCL_1 to YCL_n.

[0182] Circuit SWS2, as an example, includes transistors F4_1 to F4_n. The first terminal of transistor F4_1 is connected to wiring YCL_1, the second terminal of transistor F4_1 is connected to the input terminal of sample-and-hold circuit SH1_1 of sample-and-hold circuit section 41, and the gate of transistor F4_1 is connected to wiring SWL2. The first terminal of transistor F4_n is connected to wiring YCL_n, the second terminal of transistor F4_n is connected to the input terminal of sample-and-hold circuit SH1_n of sample-and-hold circuit section 41, and the gate of transistor F4_n is connected to wiring SWL2.

[0183] For each of transistors F4_1 to F4_n, for example, transistors applicable to the transistors in the arithmetic circuit section 59 can be used. In particular, it is preferable to use OS transistors for each of transistors F4_1 to F4_n.

[0184] Circuit SWS2 functions as a circuit that switches the connection state between wiring YCL_1 and sample-and-hold circuit SH1_1, and between wiring YCL_n and sample-and-hold circuit SH1_n.

[0185] The drive circuit 12 has the function of supplying data to be stored in each cell of the arithmetic circuit unit 59. When the cells of the arithmetic circuit unit 59 perform calculations in pairs of cells that handle positive data and cells that handle negative data, the drive circuit 12 has the function of supplying positive data and negative data to the cells in each column.

[0186] The drive circuit 11 is connected to wiring XCL_1 to XCL_m. The drive circuit 11 has the function of supplying a current amount corresponding to the reference data described later, or a current amount corresponding to the second data, to each of the cells 21_1 and 21_m of the calculation circuit unit 59.

[0187] The drive circuit 13 is connected to wiring WSL_1 to WSL_m. When writing first data to cells 31_1,1 to 31_m,n, the drive circuit 13 has the function of selecting the row of the arithmetic circuit unit 59 to which the first data will be written by supplying a predetermined signal to wiring WSL_1 to WSL_m. In other words, wiring WSL_1 to WSL_m function as write word lines.

[0188] Furthermore, the drive circuit 13 is connected, for example, to wiring SWL1 and wiring SWL2. The drive circuit 13 has the function of switching the connection state between the drive circuit 12 and the calculation circuit unit 59 by supplying a predetermined signal to wiring SWL1, and the function of switching the connection state between the sample-and-hold circuit unit 41 and the calculation circuit unit 59 by supplying a predetermined signal to wiring SWL2.

[0189] The sample-and-hold circuit section 41 has a plurality of sample-and-hold circuits SH1 to SH_n, which correspond to the sample-and-hold circuit SH1 described above. Each of the sample-and-hold circuits SH1 to SH_n can hold the analog current flowing through the wiring YCL_1 to YCL_n.

[0190] The sample-and-hold circuit section 43 has a plurality of sample-and-hold circuits SH2_1 to SH2_q (where p is an integer less than n) that correspond to the sample-and-hold circuit SH2 described above. Each sample-and-hold circuit SH2_1 to SH2_q can hold a voltage corresponding to the sum of the analog currents flowing from any plurality of sample-and-hold circuits SH1_1 to SH1_n.

[0191] The switch section 42 has a plurality of switches SW12_1 to SW12_p (where p is an integer greater than or equal to n) corresponding to the switch SW12 described above. Switches SW12_1 to SW12_p can switch the conduction state between any plurality of sample-and-hold circuits SH1_1 to SH1_n and any one of sample-and-hold circuits SH2_1 to SH2_q.

[0192] The voltage held in the sample-and-hold circuit 43 is data corresponding to the convolution data. The convolution data can be used as the data to be processed in the next layer of the CNN's computational processing. After the convolution data is read from the sample-and-hold circuit 43, it is held in an external memory device. The held convolution data is then held in the computational circuit 59 as processing data as needed.

[0193] <<Drive Circuit 11, Drive Circuit 12>> Here, specific examples of drive circuit 11 and drive circuit 12 will be described.

[0194] First, the drive circuit 12 will be described. Figure 34A is a block diagram showing an example of the drive circuit 12. In addition, Figure 34A also shows circuit SWS1, transistor F3, wiring SWL1, and wiring YCL to show the connections of the drive circuit 12 to surrounding circuits. Transistor F3 is one of transistors F3_1 to F3_n shown in Figure 33, and wiring YCL is one of wiring YCL_1 to YCL_n shown in Figure 33.

[0195] The drive circuit 12 shown in Figure 34A includes a switch SWW as an example. The first terminal of switch SWW is connected to the second terminal of transistor F3, and the second terminal of switch SWW is connected to wiring VINIL1. Wiring VINIL1 functions as a wire that provides an initialization potential to wiring YCL, and the initialization potential can be ground potential (GND), low level potential, high level potential, etc. Note that switch SWW is ON only when providing an initialization potential to wiring YCL, and OFF at all other times.

[0196] As the switch SWW, for example, an analog switch or an electrical switch such as a transistor can be used. If a transistor is used as the switch SWW, for example, a transistor that can be used in the arithmetic circuit unit 59 can be used. In addition to electrical switches, mechanical switches may also be used.

[0197] Furthermore, the drive circuit 12 in Figure 34A has, as an example, multiple current sources CS. Specifically, the drive circuit 12 has K bits (2 Ｋ It has the function of outputting a first data value (where K is an integer greater than or equal to 1) as current, and in this case the drive circuit 12 is 2 Ｋ - It has one current source CS. The drive circuit 12 has one current source CS that outputs information corresponding to the value of the 1st bit as current, two current sources CS that output information corresponding to the value of the 2nd bit as current, and two current sources CS that output information corresponding to the Kth bit as current. Ｋ−１ To possess.

[0198] In Figure 34A, each current source CS has terminal T1 and terminal T2. Terminal T1 of each current source CS is connected to the second terminal of transistor F3 of circuit SWS1. Also, terminal T2 of one current source CS is connected to wiring DW_1, and each of the terminals T2 of two current sources CS is connected to wiring DW_2, Ｋ−１ Each of the terminals T2 of the current source CS is connected to the wiring DW_K.

[0199] The multiple current sources CS of the drive circuit 12 each have the same current I Ｙｕｔ It has the function of outputting current I from terminal T1. Ｙｕｔ This refers to the normalized current I described above. Ｙｕｔ This corresponds to [this]. However, in reality, errors may appear during the manufacturing stage of the display device due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the current I output from each of the terminals T1 of the multiple current sources CS Ｙｕｔ The error is preferably within 10%, more preferably within 5%, and most preferably within 1%. In this embodiment, the current I output from terminal T1 of the multiple current sources CS included in the drive circuit 12 Ｙｕｔ We will explain assuming there is no error.

[0200] Wirings DW_1 through DW_K receive current I from the connected current source CS. ＹｕｔIt functions as wiring that transmits a control signal to output I Ｙｕｔ When current flows through the second terminal of transistor F3, and a low-level potential is applied to wiring DW_1, the current source CS connected to wiring DW_1 is I Ｙｕｔ It does not output.

[0201] The current supplied by the single current source CS connected to wiring DW_1 corresponds to the value of the first bit, the current supplied by the two current sources CS connected to wiring DW_2 corresponds to the value of the second bit, and the current supplied by the K current sources CS connected to wiring DW_K corresponds to the value of the K bit.

[0202] Note that Figure 34A shows the drive circuit 12 when K is an integer of 3 or more. However, when K is 1, the drive circuit 12 in Figure 34A can be configured without the current source CS connected to wiring DW_2 to DW_K. Also, when K is 2, the drive circuit 12 in Figure 34A can be configured without the current source CS connected to wiring DW_3 to DW_K.

[0203] Next, we will explain a specific example of the configuration of the current source CS.

[0204] The current source CS shown in Figure 34B is a circuit that can be applied to the current source CS included in the drive circuit 12 of Figure 34A, and the current source CS has transistor Tr1 and transistor Tr2.

[0205] The first terminal of transistor Tr1 is connected to wiring VDDL, and the second terminal of transistor Tr1 is connected to the gate of transistor Tr1, the back gate of transistor Tr1, and the first terminal of transistor Tr2. The second terminal of transistor Tr2 is connected to terminal T1, and the gate of transistor Tr2 is connected to terminal T2. Terminal T2 is also connected to wiring DW.

[0206] Wiring DW is one of the wirings DW_1 to DW_K shown in Figure 34A.

[0207] The VDDL wiring functions as wiring that provides a constant voltage. This constant voltage can be, for example, a high-level potential.

[0208] When the constant voltage supplied by the wiring VDDL is set to a high-level potential, a high-level potential is input to the first terminal of transistor Tr1. The potential at the second terminal of transistor Tr1 is lower than this high-level potential. In this case, the first terminal of transistor Tr1 functions as the drain, and the second terminal functions as the source. Furthermore, since the gate and the second terminal of transistor Tr1 are connected, the gate-source voltage of transistor Tr1 is 0V. Therefore, if the threshold voltage of transistor Tr1 is within an appropriate range, a current (drain current) within the subthreshold current range flows between the first and second terminals of transistor Tr1. Note that this current is as described above. Ｙｕｔ , or I Ｗｕｔ It corresponds to this.

[0209] Transistor Tr2 functions as a switching element. When the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain and the second terminal of transistor Tr2 functions as a source. Also, since the back gate of transistor Tr2 and the second terminal of transistor Tr2 are connected, the back gate-source voltage is 0V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 will turn on when a high-level potential is input to its gate, and transistor Tr2 will turn off when a low-level potential is input to its gate. Specifically, when transistor Tr2 is on, a current within the current range of the subthreshold region described above flows from the second terminal of transistor Tr1 to terminal T1, and when transistor Tr2 is off, no current flows from the second terminal of transistor Tr1 to terminal T1.

[0210] Furthermore, transistors Tr1 and Tr2 can be, for example, transistors applicable to the transistors in the arithmetic circuit section 59. In particular, it is preferable to use OS transistors for transistors Tr1 and Tr2.

[0211] Next, a specific example of the drive circuit 11 will be described.

[0212] Figure 34C is a block diagram showing an example of the drive circuit 11. Figure 34C also shows wiring XCL to indicate the connections between the drive circuit 11 and surrounding circuits. Wiring XCL is one of the wirings XCL_1 to XCL_m shown in Figure 33.

[0213] The drive circuit 11 shown in Figure 34C includes a switch SWX as an example. The first terminal of switch SWX is connected to wiring XCL and a plurality of current sources CS, and the second terminal of switch SWX is connected to wiring VINIL2. Wiring VINIL2 functions as wiring that provides an initialization potential to wiring XCL, and the initialization potential can be ground potential (GND), low level potential, high level potential, etc. Also, the initialization potential provided by wiring VINIL2 may be equal to the potential provided by wiring VINIL1. Note that switch SWX is ON only when providing an initialization potential to wiring XCL, and OFF at all other times.

[0214] Switch SWX can, for example, be a switch that can be applied to switch SWW.

[0215] Furthermore, the circuit configuration of the drive circuit 11 in Figure 34C can be almost the same as that of the drive circuit 12 in Figure 34A. Specifically, the drive circuit 11 has the function of outputting reference data as current, and L bits (2 Ｌ It has a function to output a second data value (where L is an integer greater than or equal to 1) as current, and in this case the drive circuit 11 is 2 Ｌ- It has one current source CS. The drive circuit 11 has one current source CS that outputs information corresponding to the value of the 1st bit as current, two current sources CS that output information corresponding to the value of the 2nd bit as current, and two current sources CS that output information corresponding to the Lth bit as current. Ｌ−１ They possess it individually.

[0216] By the way, the reference data that the drive circuit 11 outputs as current can be, for example, information where the value of the first bit is "1" and the values ​​of the second bit and subsequent bits are "0".

[0217] In Figure 34C, terminal T2 of one current source CS is connected to wiring DX_1, and terminal T2 of each of the two current sources CS is connected to wiring DX_2, 2 Ｌ−１ Each of the terminals T2 of the current source CS is connected to the wiring DX_L.

[0218] The multiple current sources CS of the drive circuit 11 each have the same constant current I Ｗｕｔ It has the function of outputting from terminal T1. In addition, wiring DX_1 to wiring DX_L receive I from the connected current source CS. Ｗｕｔ It functions as a wire that transmits a control signal for outputting. In other words, the drive circuit 11 has the function of supplying current to the wire XCL according to the information of the L bit sent from wires DX_1 to DX_L.

[0219] Furthermore, if errors occur due to variations in the electrical characteristics of the transistors included in each current source CS of the drive circuit 11, the current I output from each of the terminals T1 of the multiple current sources CS will be affected. Ｗｕｔ The error is preferably within 10%, more preferably within 5%, and most preferably within 1%. In this embodiment, the current I output from terminal T1 of the multiple current sources CS included in the drive circuit 11 Ｗｕｔ We will explain assuming there is no error.

[0220] Furthermore, the current source CS of the drive circuit 11 can be the same as the current source CS of the drive circuit 12, as shown in Figure 34B. This allows the drive circuit 11 to supply current within the subthreshold current range to the wiring XCL as reference data or the second data of the L bit.

[0221] <<Switch SW12, Sample-and-Hold Circuits SH1, SH2>> Here, we will describe specific examples of switch SW12 that can be applied to switches SW12_1 to SW12_p in Figure 33, and specific examples of sample-and-hold circuits SH that can be applied to sample-and-hold circuits SH1_1 to SH1_n and sample-and-hold circuits SH2_1 to SH2_q in Figure 33.

[0222] Figure 35A shows the circuit block of switch SW12, which switches between a conductive state and a non-conductive state between terminals N1 and N2. Figure 35B shows an example of the circuit configuration of switch SW12.

[0223] The switch SW12 shown in Figure 35B includes, as an example, an analog switch AS. The analog switch AS includes, as an example, a p-channel transistor Tp and an n-channel transistor Tn. The gates of transistors Tp and Tn are connected to wiring SN, to which a control signal is supplied, and wiring SNB, to which an inverting control signal is supplied, and their conduction or non-conduction state is controlled. With this configuration, the switch SW12 can switch the connection state between terminals N1 and N2.

[0224] Figure 35C shows the circuit block of a sample-and-hold circuit SH that holds a voltage corresponding to the magnitude of the current flowing through the input terminal IN and allows a current of a corresponding magnitude to flow from the output terminal OUT. Figure 35D shows an example of the circuit configuration of the sample-and-hold circuit SH.

[0225] The sample-and-hold circuit SH shown in Figure 35D includes, as an example, multiple analog switches AS and a voltage-holding circuit SHN. The analog switches AS are connected to wiring SN and SNB, as in Figure 35B, and can switch the connection state between terminals. The voltage-holding circuit SHN is connected to wiring SSN, to which a control signal is supplied.

[0226] The voltage holding circuit SHN is an n-channel current mirror circuit having transistors Tn1 and Tn2, with a writing transistor (also called a holding transistor) transistor TW1 added to it. The wiring VS3 can, for example, function as a low-level potential wiring, such as a low power supply potential. Although Figure 35D illustrates an n-channel current mirror circuit, it is also possible to replace it with a p-channel current mirror circuit, or to use a circuit that combines an n-channel current mirror circuit and a p-channel current mirror circuit.

[0227] The operation of the sample-and-hold circuit SH will now be explained. In the voltage-holding circuit SHN, current flows through transistor TW1 to transistor Tn1 in response to a control signal supplied to wiring SSN. As a result, a voltage corresponding to the magnitude of the current flowing through the input terminal IN can be held at node SN1.

[0228] The analog switch AS can control the current flowing through transistor Tn2 by the control signals supplied to wiring SN and SNB. As a result, a current of a magnitude corresponding to the voltage held at node SN1 can be supplied to the output terminal OUT. By controlling the analog switch AS and the voltage holding circuit SHN with separate signals, it is possible to prevent the timing of transistor TW1 becoming conductive from overlapping with the timing of the analog switch becoming conductive, thereby more reliably maintaining a voltage at node SN1 that corresponds to the magnitude of the current.

[0229] As described above, a calculation cell according to one aspect of the present invention can hold analog data by flowing a current corresponding to the data to be processed. The calculation cell can also flow an analog current corresponding to the product of the filtered data and the data to be processed by supplying an analog signal with a current magnitude corresponding to the filtered data. The analog current is held as a voltage in the sample-and-hold circuit section, and a current corresponding to the held voltage can be flowed via a switch.

[0230] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0231] (Embodiment 2) This embodiment describes another configuration example of a computing device according to one aspect of the present invention. In the following description, the parts that differ from Embodiment 1 will be mainly described. Therefore, the description of parts that overlap with Embodiment 1 may be omitted.

[0232] Figures 36 to 40 illustrate an example of the operation of a calculation device 100B according to one embodiment of the present invention. Figure 36 shows a calculation device 100B having a calculation circuit section 59 that has calculation cells 31 that hold 4 rows and 6 columns of data to be processed, similar to the calculation device 100 shown in Figure 4.

[0233] The arithmetic unit 100B shown in Figure 36 differs from the arithmetic unit 100 shown in Figure 4 in that multiple wiring XCLs are provided in each row of the calculation cell 31 according to the row size of the filter data. Another difference from the arithmetic unit 100 shown in Figure 4 is that the wiring XCLs provided in each row of the calculation cell 31 are connected to the calculation cell 31 of a predetermined column according to the column size of the filter data. With this configuration, the arithmetic unit 100B of this embodiment can omit the sample-and-hold circuit section 41 compared to the configuration of the arithmetic unit 100 of Embodiment 1.

[0234] The row size of the filter size is the filter data F as exemplified in Figure 2A. ＤIn this case, the answer is 3. In this case, the wiring XCLs to be provided in each row of the calculation cell 31 are as shown in Figure 36, with wiring XCL_11 to XCL_13 in the first row. Similarly, in the second row and beyond, as shown in Figure 36, the wirings are XCL_21 to XCL_23, XCL_31 to XCL_33, and XCL_41 to XCL_43. The number of wiring XCLs provided in each row of the calculation cell 31 is set to be equal to the number of rows in the filter size (if the row size of the filter size is M, then M wirings each).

[0235] The column size of the filter size is the filter data F as exemplified in Figure 2A. Ｄ In this case, the answer is 3. Multiple wiring XCL_11 lines in each row are connected to the calculation cells 31 in the 1st and 4th columns, wiring XCL_12 lines are connected to the calculation cells 31 in the 2nd and 5th columns, and wiring XCL_13 lines are connected to the calculation cells 31 in the 3rd and 6th columns. Similarly, for the wiring XCL lines in the 2nd row and beyond (wiring XCL_21 to XCL_23, wiring XCL_31 to XCL_33, wiring XCL_41 to XCL_43), they are connected to the calculation cells 31 in each column, as shown in Figure 36. Multiple wiring XCL lines in each column of the calculation cell 31 are connected to the calculation cell 31 every number of columns equal to the filter size (if the column size is N, every N columns).

[0236] Furthermore, the wiring YCL1 to YCL6 connected to the calculation cells 31 in each column are connected to the switch SW12 of the switch unit 42, as shown in Figure 36. Switch SW12 is connected to the sample-and-hold circuit unit 43, which has a sample-and-hold circuit SH2. As shown in Figure 36, switch SW12 switches the path of the current flowing between the wiring YCL1 to YCL6 and the terminals Q1 to Q4 of the sample-and-hold circuit SH2.

[0237] Next, an example of the operation of the arithmetic unit 100B shown in Figure 36 will be described.

[0238] In the example operation described below, a 3x3 filter data is applied, and the convolution data C is obtained by sliding it in the row direction with padding 1. １１ ~C １４ An example of obtaining the data C will be explained.１１ ~C １４ The data can be stored in an external memory device, and after performing pooling operations and other operations for the convolution operation of the next layer, it can be stored in the calculation cell 31.

[0239] The 3x3 filter data is the filter data F shown in Figure 2A. Ｄ This will be explained using the filter values. The data to be processed is the data to be processed D shown in Figure 2B. Ｐ The explanation will use the following: and the address. The convolution data is the convolution data C shown in Figure 2C. ＯＵＴ This will be explained using , and addresses.

[0240] Figure 37 schematically shows the data to be processed held in the calculation cell 31 in the calculation unit 100B of Figure 36. The analog data held in the calculation cells of each row and column can be held at each address by controlling the wiring XCL (XCL_11 to XCL_13, XCL_21 to XCL_23, wiring XCL_31 to XCL_33, wiring XCL_41 to XCL_43), wiring YCL (YCL1 to YCL6), or other control lines.

[0241] Figure 37 also shows the filter data F held within the drive circuit 11. Ｄ This is illustrated. Filtered data F Ｄ In addition to being held within the drive circuit 11, the data may also be held in an external storage device and read from the drive circuit 11 as needed.

[0242] In Figures 38 to 40, the filtered data F Ｄ To be processed, Data D Ｐ The first to third rows of the diagram explain how this applies to the addresses in columns 1 through 6. In the diagram, calculation cells 31 that contribute to the calculation (activated calculation cells 31) are shown with solid lines, and calculation cells 31 that do not contribute to the calculation (inactive calculation cells) are shown with dotted lines.

[0243] As shown in Figure 38, the first column of the filtered data is the filter value f １ , f ４ , f ７This is applied to the wiring XCL_11, XCL_21, and XCL_31. Also, the filter value f in the second column of the filter data. ２ , f ５ , f ８ This is applied to wiring XCL_12, XCL_22, and XCL_32. Also, the filter value f in the third column of the filter data. ３ , f ６ , f ９ The current is supplied to the wiring XCL_13, XCL_23, and XCL_33. The switches in each column are controlled to allow current to flow to the calculation cells 31 in the first to sixth columns of the calculation circuit section 59. With this configuration, the calculation cells 31 in the first to third rows of the first to sixth columns are activated.

[0244] In the activated arithmetic cell 31, an analog current flows corresponding to the product of the analog signal based on the filter value and the analog data of the data to be processed. Each current is added together in the column-direction wiring YCL1 to YCL6. Current I flows through wiring YCL1 to YCL6. ｓ１ａ ~I ｓ６ａ Current I flows. ｓ１ａ ~I ｓ６ａ This is a current of a magnitude corresponding to the sum-of-products calculation, as described in Embodiment 1 above. A current corresponding to the sum-of-products calculation result for each column flows collectively through the wiring YCL1 to YCL6 of each column.

[0245] As shown in Figure 38, in order to add up the currents flowing through the wiring YCL1 to YCL6 of each row and the sum-of-products calculation results of each row, the switch SW12 of the switch unit 42 is controlled to switch the current path. The switch unit 42 switches the conduction state of the switch SW12 so that wiring YCL1 to YCL3 and terminal Q1 in the sample-and-hold circuit unit 43 become conductive. The switch unit 42 also switches the conduction state of the switch SW12 so that wiring YCL4 to YCL6 and terminal Q4 in the sample-and-hold circuit unit 43 become conductive.

[0246] The switch unit 42 switches the current path, thereby supplying current I from wiring YCL1 to YCL3 to terminal Q1 in the sample-and-hold circuit SH2. Ｃ１１ Current I flows.Ｃ１１ is, "f １ ・D １１ +f ４ ・D ２１ +f ７ ・D ３１ +f ２ ・D １２ +f ５ ・D ２２ +f ８ ・D ３２ +f ３ ・D １３ +f ６ ・D ２３ +f ９ ・D ３３ This is a current of magnitude corresponding to the calculation of ". In other words, the filter data F Ｄ Convolutional data C obtained by applying this to the data to be processed. １１ It is possible to obtain current I from wiring YCL4 to YCL6 to terminal Q4 in sample-and-hold circuit SH2. Ｃ１４ Current I flows. Ｃ１４ is, "f １ ・D １４ +f ４ ・D ２４ +f ７ ・D ３４ +f ２ ・D １５ +f ５ ・D ２５ +f ８ ・D ３５ +f ３ ・D １６ +f ６ ・D ２６ +f ９ ・D ３６ This is a current of magnitude corresponding to the calculation of ". In other words, the filter data F Ｄ Convolutional data C obtained by applying this to the data to be processed. １４ It is possible to obtain the current I. Ｃ１１ , current I Ｃ１４ A voltage corresponding to the magnitude of the current is maintained.

[0247] Next, filtered data F Ｄ This is applied to the data to be processed in the following region. Here, the filtered data F is applied with a stride of 1. ＤThis explains when to apply this rule.

[0248] As shown in Figure 39, the filter value f in the third column of the filtered data ３ , f ６ , f ９ This is applied to the wiring XCL_11, XCL_21, and XCL_31. Also, the filter value f in the first column of the filter data. １ , f ４ , f ７ This is applied to wiring XCL_12, XCL_22, and XCL_32. Also, the filter value f in the second column of the filter data. ２ , f ５ , f ８ The current is supplied to the wiring XCL_13, XCL_23, and XCL_33. The switches in each column are controlled to allow current to flow to the calculation cells 31 in the second to fourth columns of the calculation circuit section 59. With this configuration, the calculation cells 31 in the first to third rows of the second to fourth columns are activated.

[0249] In the activated arithmetic cell 31, an analog current flows corresponding to the product of the analog signal based on the filter value and the analog data of the data to be processed. Each current is added together in the column-direction wiring YCL2 to YCL4. Current I flows through wiring YCL2 to YCL4. ｓ２ｂ ~I ｓ４ｂ Current I flows. ｓ２ｂ ~I ｓ４ｂ This is a current of a magnitude corresponding to the sum-of-products calculation, as described in Embodiment 1 above. A current corresponding to the sum-of-products calculation result for each column flows collectively through the wiring YCL2 to YCL4 of each column.

[0250] As shown in Figure 39, in order to add up the currents flowing through the wiring YCL2 to YCL4 of each column and the sum-of-products calculation results of each column, the switch SW12 of the switch unit 42 is controlled to switch the current path. The switch unit 42 switches the conduction state of the switch SW12 so that the wiring YCL2 to YCL4 and terminal Q2 in the sample-and-hold circuit unit 43 become conductive.

[0251] The switch section 42 switches the current path, thereby supplying current I from wiring YCL2 to YCL4 to terminal Q2 in the sample-and-hold circuit SH2. Ｃ１２ Current I flows. Ｃ１２ is, "f １ ・D １２ +f ４ ・D ２２ +f ７ ・D ３２ +f ２ ・D １３ +f ５ ・D ２３ +f ８ ・D ３３ +f ３ ・D １４ +f ６ ・D ２４ +f ９ ・D ３４ This is a current of magnitude corresponding to the calculation of ". In other words, the filter data F Ｄ Convolutional data C obtained by applying this to the data to be processed. １２ It is possible to obtain it.

[0252] Next, filtered data F Ｄ This is applied to the data to be processed in the following region. Here, the filtered data F is applied with a stride of 1. Ｄ This explains when to apply this rule.

[0253] As shown in Figure 40, the filter value f in the second column of the filtered data ２ , f ５ , f ８ This is applied to the wiring XCL_11, XCL_21, and XCL_31. Also, the filter value f in the third column of the filter data. ３ , f ６ , f ９ This is applied to wiring XCL_12, XCL_22, and XCL_32. Also, the filter value f in the first column of the filter data. １ , f ４ , f ７ The current is supplied to the wiring XCL_13, XCL_23, and XCL_33. The switches in each column are controlled to allow current to flow to the calculation cells 31 in the third to fifth columns of the calculation circuit section 59. With this configuration, the calculation cells 31 in the first to third rows of the third to fifth columns are activated.

[0254] In the activated arithmetic cell 31, an analog current flows corresponding to the product of the analog signal based on the filter value and the analog data of the data to be processed. Each current is added together in the column-direction wiring YCL3 to YCL5. Current I flows through wiring YCL3 to YCL5. ｓ３ｃ ~I ｓ５ｃ Current I flows. ｓ３ｃ ~I ｓ５ｃ This is a current of a magnitude corresponding to the sum-of-products calculation, as described in Embodiment 1 above. A current corresponding to the sum-of-products calculation result for each column flows collectively through the wiring YCL3 to YCL5 of each column.

[0255] As shown in Figure 40, in order to add up the currents flowing through the wiring YCL3 to YCL5 of each column and the sum-of-products calculation results of each column, the switch SW12 of the switch unit 42 is controlled to switch the current path. The switch unit 42 switches the conduction state of the switch SW12 so that the wiring YCL3 to YCL5 and terminal Q3 in the sample-and-hold circuit unit 43 become conductive.

[0256] By switching the current path in the switch section 42, current I is supplied from wiring YCL3 to YCL5 to terminal Q3 in the sample-and-hold circuit SH2. Ｃ１３ Current I flows. Ｃ１３ is, "f １ ・D １３ +f ４ ・D ２３ +f ７ ・D ３３ +f ２ ・D １４ +f ５ ・D ２４ +f ８ ・D ３４ +f ３ ・D １５ +f ６ ・D ２５ +f ９ ・D ３５ This is a current of magnitude corresponding to the calculation of ". In other words, the filter data F Ｄ Convolutional data C obtained by applying this to the data to be processed. １３ It is possible to obtain it.

[0257] As a result of the above operations, the convolved data C is obtained by convolving the data to be processed in rows 1 through 3 and columns 1 through 6. １１ ~C １４ It is possible to find this.

[0258] Furthermore, the process of obtaining convolution data from the data to be processed in each column from the second row onward is performed using the convolution data C from the first to third rows as described above. １１ ~C １４ This can be done in the same way as the example of obtaining the data. For example, in the wiring XCL of the second to fourth rows (wiring XCL_21 to XCL_23, wiring XCL_31 to XCL_33, wiring XCL_41 to XCL_43), the filtered data F Ｄ By switching the analog signals corresponding to the filter values ​​in each column and supplying them to the calculation cell 31, the filtered data F Ｄ Convolutional data C obtained by applying this to the data to be processed. ２１ ~C ２４ It is possible to obtain it.

[0259] With the configuration of one aspect of the present invention described above, the sample-and-hold circuit section 41 can be reduced, and the number of filter data switching cycles can be reduced, allowing for the acquisition of convolution data. Therefore, it becomes possible to acquire convolution data with a simpler configuration.

[0260] This embodiment can be appropriately combined with the same or other embodiments described herein.

[0261] (Embodiment 3) In this embodiment, an example of the configuration of the arithmetic unit described in the above embodiment will be explained.

[0262] Figure 41 is a schematic perspective view of the arithmetic unit 100 described in Embodiments 1 and 2. The arithmetic unit 100 shown in Figure 41 includes, as an example, a drive circuit layer PHRL and an arithmetic cell layer OMAL. The drive circuit layer PHRL is located below the arithmetic cell layer OMAL.

[0263] Figure 42 is a block diagram showing example configurations of the drive circuit layer PHRL and the arithmetic cell layer OMAL shown in Figure 41.

[0264] In Figure 42, the drive circuit layer PHRL includes, for example, the drive circuits 11, 12, and 13, sample-and-hold circuit section 41, switch section 42, and sample-and-hold circuit section 43 described in Embodiments 1 and 2. The arithmetic cell layer OMAL includes, for example, the arithmetic circuit section 59 described in Embodiments 1 and 2. Each circuit in the drive circuit layer PHRL and the arithmetic circuit section 59 are connected by wiring XCL, YCL, WSL, etc., as shown in Figure 42.

[0265] The drive circuit layer (PHRL) can be constructed, for example, by providing circuit elements such as transistors and capacitive elements on a substrate. Furthermore, a semiconductor substrate containing silicon can be used for this substrate.

[0266] Furthermore, the laminated structure of the drive circuit layer PHRL and the arithmetic cell layer OMAL can be fabricated by directly forming the arithmetic cell layer OMAL on top of the drive circuit layer PHRL. Alternatively, the arithmetic cell layer OMAL can be fabricated by mounting the substrate on top of the drive circuit layer PHRL, with the substrate having circuit elements such as transistors and capacitive elements on it.

[0267] When the arithmetic cell layer OMAL is formed directly on top of the drive circuit layer PHRL, it is preferable that the arithmetic cell layer OMAL includes an OS transistor. Since the OS transistor can be formed not only on a semiconductor substrate but also on an insulating substrate, a conductive substrate, and even on a conductive film, an insulating film, or a semiconductor film, it can be easily provided on the semiconductor substrate (on the drive circuit layer PHRL) on which the Si transistor is formed.

[0268] <Example of Cross-Sectional Configuration of the Calculation Unit 1> Next, a specific example of the configuration of the calculation unit 100 shown in Figures 41 and 42 will be described. Figure 43 is a schematic cross-sectional view of an example of the calculation unit 100 shown in Figures 41 and 42.

[0269] Figure 43 shows a schematic cross-sectional view of the drive circuit layer PHRL and the arithmetic cell layer OMAL. Note that the arithmetic unit 100 in Figure 28 shows a configuration in which the arithmetic cell layer OMAL is formed directly on the drive circuit layer PHRL.

[0270] Figure 43 illustrates a transistor 400 in the drive circuit layer PHRL. The transistor 400 is provided on a substrate 311 and includes a conductive layer 316 that functions as a gate, insulating layers 315 and 317 that function as gate insulating films, a semiconductor region 313 that includes a part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region that includes a part of the substrate. The transistor 400 can be a p-channel type transistor or an n-channel type transistor. Furthermore, a single-crystal silicon substrate can be used as the substrate 311, for example.

[0271] In Figure 43, the transistor 400 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, a conductive layer 316 covers the side and top surfaces of the semiconductor region 313 via an insulating layer 315. The conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulating layer in contact with the upper part of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0272] Note that the transistor 400 shown in Figure 43 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0273] A wiring layer containing an interlayer film, wiring, and a plug may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plug connecting to the wiring may be a single integrated unit. That is, there may be cases where a part of the conductive layer functions as wiring, and cases where a part of the conductive layer functions as a plug.

[0274] For example, on the transistor 400, insulating layers 320, 324, and 326 are sequentially stacked as interlayer films. A conductive layer 328 is embedded in the insulating layer 320. A conductive layer 330 is embedded in the insulating layers 324 and 326. The conductive layers 328 and 330 function as contact plugs or wiring.

[0275] Furthermore, the insulating layer, which functions as an interlayer film, may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulating layer 320 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) to improve its flatness.

[0276] Wiring layers may be provided on the insulating layer 326 and the conductive layer 330. For example, in Figure 43, insulating layers 350, 357, 352, and 354 are sequentially laminated on the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed on insulating layers 350, 357, and 352. The conductive layer 356 functions as a contact plug or wiring.

[0277] An insulating layer 354 is provided on the insulating layer 352 and the conductive layer 356. Preferably, contact plugs or wiring for connecting to the circuit above (for example, a circuit included in the circuit included in the arithmetic cell layer OMAL) are embedded in the insulating layer 354.

[0278] Furthermore, Figure 43 illustrates transistor 500, which is an OS transistor in the OMAL arithmetic cell layer. OS transistors have a remarkably low off-current. Therefore, the power consumption of the arithmetic cell can be reduced. Thus, the power consumption of the arithmetic unit 100, including transistor 500, can be reduced.

[0279] <<Example of Transistor 500 Configuration>> Next, we will explain a specific example of a transistor configuration called a GL (Gate Last) structure that can be applied to the transistor 500 shown in Figure 43. Figure 44A shows a schematic cross-sectional view of the transistor 500 in the channel length direction, and Figure 44B shows a schematic cross-sectional view of the transistor 500 in the channel width direction.

[0280] As shown in Figures 44A and 44B, the transistor 500 includes, as an example, a semiconductor layer 531a, a semiconductor layer 531b, a conductive layer 505, a conductive layer 542a, a conductive layer 542b, an insulating layer 580, a conductive layer 560, an insulating layer 514, an insulating layer 516, an insulating layer 520, an insulating layer 522, an insulating layer 524, an insulating layer 550, an insulating layer 554, an insulating layer 574, an insulating layer 580, and an insulating layer 581. Note that the transistor 500 may not have all of the above-mentioned components. For example, although the conductive layer 505 functions as a back gate electrode in the transistor 500, the transistor 500 can also be configured without the conductive layer 505.

[0281] The materials applicable to the conductive layer, insulating layer, and semiconductor layer, as described above, will be discussed later.

[0282] The conductive layer 505 (conductive layer 505a and conductive layer 505b) and the insulating layer 516 are arranged above the substrate (not shown). In particular, it is preferable that the conductive layer 505 is embedded in the insulating layer 516. Specifically, it is preferable that the conductive layer 505a is provided in contact with the bottom surface and side wall of an opening provided in the insulating layer 516. It is also preferable that the conductive layer 505b is provided so as to be embedded in a recess formed in the conductive layer 505a. In the transistor 500 shown in Figures 44A and 44B, the height of the upper surface of the conductive layer 505b is approximately the same as the height of the upper surface of the conductive layer 505a and the height of the upper surface of the insulating layer 516.

[0283] The insulating layer 516, like the insulating layer 320, functions as a planarizing film that flattens steps caused by plugs and the like. Therefore, the insulating layer 516 can be made of a material that functions as a planarizing film, similar to the insulating layer 320. Furthermore, by using a material with a low dielectric constant for the insulating layer 516, parasitic capacitance between wiring can be reduced.

[0284] For this reason, the insulating layer 516 can be made of, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, or silicon nitride. Alternatively, the insulating layer 516 can be made of, for example, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. Silicon oxide and silicon oxide nitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxide nitride, or silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating. Alternatively, the insulating layer 516 can be made of, for example, resin. Furthermore, the material used for the insulating layer 516 may be a combination of the insulating materials described above as appropriate.

[0285] Furthermore, the semiconductor layer 531 and the conductive layer 560 are arranged in a region that overlaps with the conductive layer 505. The semiconductor layer 531b is arranged on top of the semiconductor layer 531a. The conductive layers 542a and 542b are arranged on top of the semiconductor layer 531b, spaced apart from each other. The insulating layer 580 is arranged on top of the conductive layers 542a and 542b. In particular, the insulating layer 580 has an opening formed in the region between the conductive layers 542a and 542b. The conductive layer 560 is arranged within this opening. The insulating layer 550 is arranged between the semiconductor layer 531b, the conductive layer 542a, the conductive layer 542b, the insulating layer 580, and the conductive layer 560. Here, as shown in Figures 44A and 44B, it is preferable that the upper surface of the conductive layer 560 substantially coincides with the upper surfaces of the insulating layer 550 and the insulating layer 580. In the following, conductive layers 505a and 505b may be collectively referred to as conductive layer 505. Also, semiconductor layers 531a and 531b may be collectively referred to as semiconductor layer 531. Furthermore, conductive layers 542a and 542b may be collectively referred to as conductive layer 542.

[0286] Furthermore, as shown in Figure 44A, a low-resistance region 543a may be formed at and near the interface of the semiconductor layer 531b with the conductive layer 542a. Similarly, a low-resistance region 543b may be formed at and near the interface of the semiconductor layer 531b with the conductive layer 542b. In this case, region 543a functions as either a source region or a drain region, and region 543b functions as either a source region or a drain region. Therefore, region 543a can be either a source electrode or a drain electrode, and region 543b can be either a source electrode or a drain electrode. In addition, a channel-forming region is formed in the region sandwiched between region 543a and region 543b.

[0287] By providing the conductive layer 542a (conductive layer 542b) in contact with the semiconductor layer 531, the oxygen concentration in region 543a (region 543b) may be reduced. In addition, a metal compound layer containing the metal contained in the conductive layer 542a (conductive layer 542b) and the components of the semiconductor layer 531 may be formed in region 543a (region 543b). Furthermore, the concentration of impurities such as hydrogen, nitrogen, and metal elements may be high in region 543a (region 543b). In such cases, the carrier concentration in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region. That is, the source region and drain region are n-type regions (low-resistance regions) with higher carrier concentrations compared to the channel-forming region.

[0288] On the other hand, the channel-forming region is a high-resistance region with a lower carrier concentration due to fewer oxygen vacancies or lower impurity concentrations compared to the source and drain regions. Therefore, the channel-forming region can be said to be type i (intrinsic) or substantially type i.

[0289] In the transistor 500 shown in Figures 44A and 44B, the sides of the conductive layers 542a and 542b facing the conductive layer 560 have a generally vertical shape. However, the transistor 500 shown in Figures 44A and 44B is not limited to this.

[0290] In the transistor 500, a configuration is shown in which two semiconductor layers, semiconductor layer 531a and semiconductor layer 531b, are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity. However, the present invention is not limited to this. For example, a single-layer structure of semiconductor layer 531b or a stacked structure of three or more layers may be provided. Furthermore, each of semiconductor layer 531a and semiconductor layer 531b may have a stacked structure of two or more layers.

[0291] The conductive layer 560 functions as the first gate electrode of the transistor (sometimes referred to as the top gate electrode or front gate electrode), and as described above, the conductive layers 542a and 542b function as the source electrode or drain electrode, respectively. As described above, the conductive layer 560 is formed to be embedded in the opening of the insulating layer 580 and in the region sandwiched between the conductive layers 542a and 542b. Here, the arrangement of the conductive layer 560, conductive layer 542a, and conductive layer 542b is selected in a self-aligned manner with respect to the opening of the insulating layer 580. In other words, in the transistor 500, the first gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductive layer 560 can be formed without providing a positional margin, the occupied area of ​​the transistor 500 can be reduced. This makes it possible to increase the density of arithmetic cells in the arithmetic unit.

[0292] Figures 44A and 44B show the conductive layer 560 as a two-layer structure. Here, it is preferable that the conductive layer 560 has a conductive layer 560a and a conductive layer 560b disposed on top of the conductive layer 560a. For example, it is preferable that the conductive layer 560a is arranged to enclose the bottom and sides of the conductive layer 560b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 560a.

[0293] The conductive layer 560a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules).

[0294] Furthermore, because the conductive layer 560a has the function of suppressing oxygen diffusion, it is possible to suppress oxidation of the conductive layer 560b and a decrease in conductivity due to oxygen contained in the insulating layer 580, etc. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0295] Furthermore, it is preferable to use a conductive layer with high conductivity for the conductive layer 560b. For example, the conductive layer 560b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductive layer 560b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0296] For conductive layers 542a and 542b, it is preferable to use conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductive layers 542a and 542b. When conductive materials containing metal and nitrogen are used as conductive layers 542a and 542b, conductive layers 542a and 542b become conductive layers having at least metal and nitrogen. For example, as materials to be applied to conductive layers 542a and 542b, conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen can be selected from the materials that can be applied to conductive layers 560a and 560b respectively as described above.

[0297] Furthermore, for example, it is preferable to use conductive materials mainly composed of tungsten, copper, or aluminum for the conductive layer 540a and conductive layer 540b.

[0298] Furthermore, for example, the conductive layer 540a and the conductive layer 540b can be a laminated structure having multiple layers. In particular, it is preferable to laminate a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen with a highly conductive material.

[0299] Furthermore, the conductive layer 505 may function as a second gate electrode (sometimes referred to as a bottom gate electrode or back gate electrode). In this case, by independently changing the potential applied to the conductive layer 505, separate from the potential applied to the conductive layer 560, the threshold voltage V of the transistor 500 can be controlled. ｔｈ This can be controlled. In particular, by applying a negative potential to the conductive layer 505, the V of the transistor 500 can be controlled. ｔｈThis makes it possible to increase the voltage and decrease the off-current. Therefore, applying a negative potential to the conductive layer 505 reduces the drain current when the potential applied to the conductive layer 560 is 0V compared to when no potential is applied.

[0300] The conductive layer 505 should be larger than the channel formation region in the semiconductor layer 531. In particular, as shown in Figure 44B, it is preferable that the conductive layer 505 extends as wiring even in the region outside the edge that intersects with the channel width direction of the semiconductor layer 531. That is, it is preferable that the conductive layer 505 and the conductive layer 560 are superimposed on the outside of the side surface in the channel width direction of the semiconductor layer 531 via an insulating layer.

[0301] As shown in Figure 44A, the conductive layer 560 preferably has a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Although Figures 44A and 44B show the conductive layer 560 as a two-layer laminated structure, the present invention is not limited thereto. For example, the conductive layer 560 may be a single-layer structure or a laminated structure of three or more layers.

[0302] As shown in Figures 44A and 44B, the transistor 500 preferably includes an insulating layer 512 placed on a substrate (not shown), an insulating layer 514 placed on the insulating layer 512, an insulating layer 516 placed on the insulating layer 514, a conductive layer 505 placed so as to be embedded in the insulating layer 516, an insulating layer 520 placed on the insulating layer 516 and the conductive layer 505, an insulating layer 522 placed on the insulating layer 520, and an insulating layer 524 placed on the insulating layer 522. It is preferable that a semiconductor layer 531a is placed on the insulating layer 524.

[0303] Furthermore, as shown in Figures 44A and 44B, it is preferable that an insulating layer 554 is placed between the insulating layer 522, insulating layer 524, semiconductor layer 531a, semiconductor layer 531b, conductive layer 542a, conductive layer 542b, and insulating layer 580. Here, as shown in Figures 44A and 44B, it is preferable that the insulating layer 554 is in contact with the side surface of the insulating layer 550, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the semiconductor layer 531a, the semiconductor layer 531b, the side and top surfaces of the insulating layer 524, and the top surface of the insulating layer 522.

[0304] It is preferable that insulating layers 574 and 581, which function as interlayer films, are arranged on the transistor 500. Here, it is preferable that the insulating layer 574 is arranged in contact with the upper surfaces of the conductive layer 560, the insulating layer 550, and the insulating layer 580. In this case, it is preferable that the upper surface of the insulating layer 580 is flattened.

[0305] It is preferable that a conductive layer 540 (conductive layer 540a and conductive layer 540b) is provided, which connects to the transistor 500 and functions as a plug. For this reason, the conductive layer 540 is provided in contact with the inner wall of the opening of the insulating layer 554, insulating layer 580, insulating layer 574, and insulating layer 581. In particular, a first conductive layer of the conductive layer 540 may be provided in contact with the inner wall, and a second conductive layer of the conductive layer 540 may be provided on the side surface of the first conductive layer. Here, the height of the upper surface of the conductive layer 540 and the height of the upper surface of the insulating layer 581 can be made to be approximately the same.

[0306] Specifically, for example, a first conductive layer of conductive layer 540a is provided in contact with one inner wall of two openings in insulating layer 581, insulating layer 574, insulating layer 580, and insulating layer 554, and a second conductive layer of conductive layer 540a is formed in contact with its side surface. A conductive layer 542a is located in a part of the bottom of the opening, and conductive layer 540a is in contact with conductive layer 542a. Similarly, for example, a first conductive layer of conductive layer 540b is provided in contact with the other inner wall of two openings in insulating layer 581, insulating layer 574, insulating layer 580, and insulating layer 554, and a second conductive layer of conductive layer 540b is formed in contact with its side surface. A conductive layer 542b is located in a part of the bottom of the opening, and conductive layer 540b is in contact with conductive layer 542b.

[0307] Although the transistor 500 shows a configuration in which a first conductive layer and a second conductive layer of the conductive layer 540 are stacked, the present invention is not limited thereto. For example, the conductive layer 540 may be provided as a single layer or as a stacked structure of three or more layers. When a structure has a stacked structure, an ordinal number may be assigned to distinguish it according to the order of formation.

[0308] As shown in Figure 44B, in the region of the semiconductor layer 531b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 531, the side surface of the semiconductor layer 531 is covered by the conductive layer 560. This makes it easier to apply the electric field of the conductive layer 560, which functions as the first gate electrode, to the side surface of the semiconductor layer 531, and as a result, the channel formation region of the semiconductor layer 531 can be electrically surrounded by the electric field of the conductive layer 560. Therefore, the on-current of the transistor 500 can be increased and the frequency characteristics can be improved.

[0309] For example, the insulating layer 580 preferably has a lower dielectric constant than the insulating layer 522. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For this reason, it is preferable to use one or more of the following materials with a low dielectric constant for the insulating layer 580: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies.

[0310] In particular, silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. Materials such as silicon oxide, silicon oxide-nitride, and silicon oxide with vacancies are especially preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0311] Furthermore, the upper surfaces of the insulating layer 580 may be flattened. In this way, the insulating layer 580 also functions as a flattened film.

[0312] Based on the above, the same material as the insulating layer 516 can be used for the insulating layer 580.

[0313] <<Materials Constituting the Transistor>> Next, we will explain the materials that make up the transistor 500.

[0314] [Metal Oxide (Oxide Semiconductor)] It is preferable that the transistor 500 uses a metal oxide that functions as an oxide semiconductor and includes a channel-forming region. For example, it is preferable to use a metal oxide that has a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more, as the metal oxide that forms the channel-forming region. Specifically, for example, in the case of the transistor 500 in Figures 44A and 44B, it is preferable to use a metal oxide that functions as an oxide semiconductor for the semiconductor layer 531.

[0315] Metal oxide structures can be classified into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include CAAC (c-axis aligned crystalline) structures, polycrystalline structures, nanocrystalline structures, a-like (amorphous-like) structures, and amorphous structures. The structure of the metal oxide in one aspect of the present invention is not particularly limited, and any of the above structures may be used. However, using crystalline metal oxides such as CAAC structures and nc structures is preferable because it allows for the creation of highly reliable semiconductor devices.

[0316] Furthermore, it is preferable that the above metal oxide contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains element M. As element M, one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony can be used. In particular, it is preferable that element M is one or more of aluminum, gallium, yttrium, or tin. Furthermore, it is even more preferable that element M contains one or both of aluminum, gallium, yttrium, and tin.

[0317] Specifically, for example, the metal oxide can be In-Ga-Zn oxide (indium-gallium-zinc oxide), Ga-Zn oxide, In-Ga oxide, gallium oxide, or indium oxide.

[0318] In particular, indium oxide is an oxide whose valence electrons can be controlled. For example, an element that imparts n-type properties to an oxide semiconductor layer containing indium oxide can be added. Alternatively, an element that imparts p-type properties to an oxide semiconductor layer containing indium oxide can be added. This makes it possible to control the threshold voltage of a transistor using an oxide semiconductor layer containing indium oxide.

[0319] As an element that imparts n-type properties, for example, tin (Sn) may be added to the oxide semiconductor layer having indium oxide. In this case, the concentration of the element that imparts n-type properties in the oxide semiconductor layer is 1 × 10⁻⁶ １６ atoms / cm ３ The above 8 x 10 ２０ atoms / cm ３ The following is preferable: 1 × 10 １６ atoms / cm ３ The above 4 x 10 ２０ atoms / cm ３ The following is more preferable: 1 × 10 １６atoms / cm ３ The above 8 x 10 １９ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following are even more preferable. Note that antimony (Sb) can also function as an element that confers the n-type.

[0320] As elements that impart p-type properties, for example, cadmium (Cd) and zinc (Zn), or both, may be added to the oxide semiconductor layer containing indium oxide. This may make it easier to make the oxide semiconductor layer i-type or substantially i-type. In this case, the concentration of the p-type imparting element in the oxide semiconductor layer is 1 × 10⁻⁶ １６ atoms / cm ３ The above 8 x 10 ２０ atoms / cm ３ The following is preferable: 1 × 10 １６ atoms / cm ３ The above 4 x 10 ２０ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 8 x 10 １９ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following are even more preferable.

[0321] Furthermore, a first element with a stronger bond strength than that between indium and oxygen can be added to the oxide semiconductor layer containing indium oxide. By adding the first element, oxygen vacancies (V) in the oxide semiconductor layer can be eliminated. ＯThis can suppress the formation of ) . Furthermore, it is preferable that the first element is an element that mainly exists as a trivalent cation, the same as indium. This allows the carrier concentration of the oxide semiconductor layer to be kept low. Therefore, it becomes possible to shift the threshold voltage of the transistor to the positive side. Also, normally-off becomes possible. Thus, a transistor with good electrical characteristics can be provided.

[0322] Examples of the first element include gallium, aluminum, yttrium, and scandium. The oxide semiconductor layer having indium oxide preferably contains at least one of gallium or aluminum as the first element. The concentration of the first element in the oxide semiconductor layer is 1 × 10⁻⁶. １６ atoms / cm ３ The above 8 x 10 ２０ atoms / cm ３ The following is preferable: 1 × 10 １６ atoms / cm ３ The above 4 x 10 ２０ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 8 x 10 １９ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following are even more preferable.

[0323] The elements that impart n-type, p-type, and the first element described above can be added to the oxide semiconductor layer by methods such as ion doping, ion implantation, and thermal diffusion, respectively. Alternatively, the elements that impart n-type, p-type, and the first element described above can be added to the sputtering target, deposition gas, ALD deposition precursor, etc., when depositing the oxide semiconductor layer. Alternatively, the elements that impart n-type, p-type, and the first element described above can be auto-doped from the chamber used when depositing the oxide semiconductor layer. Auto-doping refers to the automatic addition of elements contained in the chamber components, etc., into the oxide semiconductor layer during deposition.

[0324] Furthermore, as the metal oxide, metal oxides with In:Ga:Zn = 1:3:4 [atomic ratio], 1:3:2 [atomic ratio], 1:1:0.5 [atomic ratio], 1:1:1 [atomic ratio], 4:2:3 [atomic ratio], or 3:1:2 [atomic ratio] may be used. Alternatively, a metal oxide with In:Zn = 4:1 [atomic ratio] may also be used.

[0325] Metal oxides can be suitably formed using sputtering or ALD (Advanced Laser Deposition). When metal oxides are formed by sputtering, films with high crystallinity or high film density can be formed. When metal oxides are formed using ALD, atoms can be deposited layer by layer, resulting in film formation with fewer defects such as pinholes, excellent coverage, and the ability to form films at low temperatures. Furthermore, it is preferable to perform an impurity removal treatment after the formation of the metal oxide to remove impurities (typically water, hydrogen, carbon, nitrogen, etc.) from the metal oxide film. Examples of impurity removal treatments include plasma treatment, microwave treatment, and heat treatment.

[0326] [Conductive Layer] The conductive layer included in the transistor 500 preferably uses a metallic element selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy comprising two or more of the above-mentioned metallic elements, or an alloy combining two or more of the above-mentioned metallic elements. The conductive layer preferably uses, for example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. In addition, for the conductive layer, a semiconductor with high electrical conductivity, such as polycrystalline silicon containing impurity elements (e.g., phosphorus), or a silicide (e.g., nickel silicide) may be used.

[0327] Multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Furthermore, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0328] The conductive layer that functions as the second gate electrode, for example, the conductive layer 505 shown in Figures 44A and 44B, contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ２ O, NO, or NO ２It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, either or both oxygen atoms and oxygen molecules). Examples of conductive materials that have the function of suppressing the diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0329] In addition, it is preferable to use conductive materials mainly composed of tungsten, copper, or aluminum.

[0330] For the conductive layer that functions as a source electrode or drain electrode, for example, conductive layer 542a and conductive layer 542b shown in Figures 44A and 44B, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy comprising two or more of the above-mentioned metallic elements, or an alloy combining two or more of the above-mentioned metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel for the conductive layer. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0331] The conductive layer that functions as the first gate electrode, for example, the conductive layer 560 shown in Figures 44A and 44B, contains the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ２ O, NO, or NO ２It is preferable to use a conductive layer that has the function of suppressing the diffusion of impurities such as copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, either or both oxygen atoms and oxygen molecules). Examples of conductive materials that have the function of suppressing the diffusion of oxygen include tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, by providing a conductive material containing oxygen as the conductive layer, oxygen detached from the conductive material is more easily supplied to the channel-forming region.

[0332] Furthermore, the conductive layer that functions as the first gate electrode is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductive layer also functions as wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductive layer may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0333] Furthermore, the conductive layer may be made of, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or silicon-added indium tin oxide. Alternatively, the conductive layer may be made of, for example, indium gallium zinc oxide containing nitrogen. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen that is mixed in from the outer insulating layer, etc.

[0334] [Insulating layer] Examples of insulating layers included in the transistor 500 include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, or metal nitride oxides.

[0335] The insulating layer that can be provided on the transistor preferably functions as a barrier insulating film that suppresses the mixing of impurities such as water and hydrogen from the substrate side into the semiconductor layer of the transistor 500. Therefore, the insulating layer is preferably made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ２ O, NO, or NO ２ It is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as ) and copper atoms (i.e., the above impurities do not easily permeate). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., either or both oxygen atoms and oxygen molecules) (i.e., the above oxygen does not easily permeate).

[0336] An insulating layer having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, can be, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used as a single layer or in a laminated form. Specifically, examples of insulating layers having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. Another example of an insulating layer having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, is an oxide containing aluminum and hafnium (hafnium aluminate). Yet another example of an insulating layer having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, is a nitride such as aluminum nitride, silicon nitride, or silicon nitride.

[0337] It is preferable that the second gate insulating film, which is in contact with the metal oxide included in the channel formation region, for example, the insulating layer 522 and insulating layer 524 shown in Figures 44A and 44B, have oxygen removed by heating. In this specification, the oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride may be used as the second gate insulating film. By providing an insulating layer containing oxygen in contact with the metal oxide, the oxygen deficiency in the metal oxide can be reduced, and the reliability of the transistor can be improved.

[0338] Specifically, it is preferable to use an oxide material that partially desorbs oxygen upon heating as the insulating layer. An oxide that desorbs oxygen upon heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, as determined by thermal desorption spectrometry (TDS), is 1.0 × 10⁻¹⁶. １８ atoms / cm ３ Preferably 1.0 × 10 １９ atoms / cm ３ More preferably 2.0 × 10 １９ atoms / cm ３ The above, or 3.0 x 10 ２０ atoms / cm ３ The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0339] Furthermore, the insulating layer included in the transistor may be an insulating layer containing an oxide of one or both of the insulating materials aluminum and hafnium. Examples of insulating layers containing an oxide of one or both of aluminum and hafnium include aluminum oxide and hafnium oxide. Another example is an oxide containing aluminum and hafnium (hafnium aluminate). When an insulating layer is formed around a transistor using such a material, the insulating layer can function as a layer that suppresses the release of oxygen and the incorporation of impurities such as hydrogen from the periphery of the transistor into the metal oxide.

[0340] As the first gate insulating film, an insulating layer, for example, the insulating layer 550 shown in Figures 44A and 44B, is preferably placed in contact with the upper surface of the metal oxide. For this insulating layer, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies can be used. In particular, silicon oxide and silicon oxide nitride are preferred because they are stable with respect to heat.

[0341] This embodiment can be appropriately combined with the same or other embodiments described herein.

[0342] (Embodiment 4) This embodiment describes electronic components and electronic devices that can use the computing device described in Embodiments 1 and 2 above. Electronic components and electronic devices using the computing device according to one aspect of the present invention are effective in achieving high performance, such as low power consumption.

[0343] [Electronic Components] A perspective view of the electronic component 700 is shown in Figure 45A. The electronic component 700 shown in Figure 45A comprises a substrate 701, a semiconductor device 710 on the substrate 701, and a mold 711. In particular, the semiconductor device 710 is sealed by the mold 711. Note that in Figure 45A, some details have been omitted in order to show the inside of the electronic component 700.

[0344] For example, the substrate 701 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0345] The electronic component 700 is provided with, for example, a lead frame 712. A portion of the lead frame 712 located on the substrate 701 is covered by a mold 711, while another portion of the lead frame 712 is exposed to the outside of the mold 711. In particular, the lead frame 712 exposed to the outside of the mold 711 functions, for example, as a terminal for mounting the electronic component 700 onto the printed circuit board.

[0346] Within the mold 711, electrode pads 713 are provided on the lead frame 712, and the electrode pads 713 are connected to the semiconductor device 710 via wires 714. The electronic component 700 is mounted on the printed circuit board, for example, by bringing the lead frame 712 into contact with the wiring on the printed circuit board side. In this way, multiple electronic components are combined and connected on the printed circuit board to complete the mounted circuit board.

[0347] Next, the semiconductor device 710 will be described. For example, as shown in Figure 45B, the semiconductor device 710 has a drive circuit layer 715 and a calculation cell layer 716. The calculation cell layer 716 can be configured with stacked calculation cells. The configuration in which the drive circuit layer 715 and the calculation cell layer 716 are stacked can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology (for example, TSV (Through Silicon Via)) and bonding technology such as Cu-Cu direct bonding.

[0348] Next, Figure 45C shows an example of a modification of the electronic component 700. Unlike the electronic component 700, the electronic component 700A shown in Figure 45C does not use a lead frame 712, and instead has electrodes 733 provided at the bottom of the substrate 701. The electrodes 733 function as connection terminals for mounting the electronic component 700A onto the printed circuit board.

[0349] Figure 45C shows an example in which the electrode 733 is formed with solder balls. By arranging solder balls in a matrix at the bottom of the substrate 701, BGA (Ball Grid Array) mounting can be realized. For this purpose, the substrate 701 is provided with through-hole vias, and a conductive layer 732 that functions as wiring is provided on these vias. On the substrate 701, the electrode pad 713 is provided in contact with the conductive layer 732, and on the substrate 701, the electrode 733 is provided in contact with the conductive layer 732.

[0350] Alternatively, the electrodes 733 may be formed with conductive pins instead of solder balls. By arranging conductive pins in a matrix at the bottom of the substrate 701, PGA (Pin Grid Array) mounting can be realized.

[0351] Furthermore, the electronic component 700A can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0352] [Electronic Device] Next, a perspective view of the electronic device 6500 is shown in Figure 46A. The electronic device 6500 shown in Figure 46A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. An arithmetic device according to one aspect of the present invention can be applied to the display unit 6502, the control device 6509, etc.

[0353] The electronic device 6600 shown in Figure 46B is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. The control device 6616 includes one or more components selected from, for example, a CPU, a GPU, and a memory circuit. An arithmetic device according to one aspect of the present invention can be applied to the display unit 6615, the control device 6616, and the like.

[0354] Using the arithmetic circuit according to one aspect of the present invention in the control devices 6509 and 6616 described above is preferable because it can reduce power consumption. Furthermore, it can speed up the calculations of the artificial neural network.

[0355] This embodiment can be appropriately combined with the same or other embodiments described herein.

[0356] <Notes Regarding the Description in This Specification, etc.> The above embodiments and descriptions of each component in the embodiments are provided below.

[0357] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples can be appropriately combined.

[0358] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0359] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0360] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0361] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification and can be appropriately rephrased.

[0362] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0363] In this specification, when describing the connection relationships of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, etc.

[0364] Furthermore, in this specification, the terms "electrode" or "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0365] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0366] In this specification, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0367] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0368] In this specification, the channel length in a planar transistor refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a planar view of the transistor, or in the region where the channel is formed.

[0369] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0370] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Also, terminals, wiring, etc. can be replaced with "node."

[0371] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be short-circuited. For example, in an n-channel transistor, the state in which the voltage between the gate and source is higher than the threshold voltage, or in a p-channel transistor, the state in which the voltage between the gate and source is lower than the threshold voltage, is called the "on state." The "on state" of a transistor is a state in which current can flow between the source and drain. Therefore, the state in which a transistor is "on" is sometimes referred to as the "conducting state" of the transistor.

[0372] In this specification, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered disconnected. For example, in an n-channel transistor, the state in which the voltage between the gate and source is lower than the threshold voltage, or in a p-channel transistor, the state in which the voltage between the gate and source is higher than the threshold voltage, is called the "off state." In some cases, the state of a transistor being in the "off state" is also referred to as the transistor being in a "non-conducting state."

[0373] In this specification, the voltage between the gate and source (gate-source) is sometimes referred to as the "gate voltage," the voltage between the drain and source (drain-source) is sometimes referred to as the "drain voltage," and the voltage between the back gate and source (back gate-source) is sometimes referred to as the "back gate voltage." In addition, the current flowing from the drain to the source is sometimes referred to as the "drain current."

[0374] In this specification, unless otherwise specified, the "off-current" of a transistor refers to the drain current when the transistor is in the off state. In this specification, the off-current, as well as the current flowing from the gate to the source and drain (also called gate leakage current), may be referred to as leakage current.

[0375] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0376] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0377] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0378] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0379] XCL: Wiring, YCL: Wiring, 11: Drive circuit, 31: Calculation cell, 41: Sample-and-hold circuit section, 42: Switch section, 43: Sample-and-hold circuit section, 59: Calculation circuit section, 100: Calculation unit

Claims

A calculation circuit unit having multiple calculation cells that hold first data, The aforementioned calculation circuit unit includes a drive circuit that outputs second data, A first sample-and-hold circuit section having multiple first sample-and-hold circuits, A switch section having multiple switches, It has a second sample-and-hold circuit section having multiple second sample-and-hold circuits, The calculation circuit unit supplies a first current to the first sample-and-hold circuit unit that corresponds to the sum of the currents flowing through the calculation cell to which the second data is supplied. Each of the first sample-and-hold circuits holds a plurality of third data corresponding to the first current by switching the second data, The switch unit supplies a second current to the second sample-and-hold circuit unit, which corresponds to the sum of the currents flowing from the multiple first sample-and-hold circuits through the switch. Each of the second sample-and-hold circuits holds a plurality of fourth data corresponding to the second current by switching the path of the switch. Computing device. 　 In claim 1, It has a first wiring provided in the row direction, Multiple calculation cells are arranged in a matrix. The third data is data corresponding to the sum-of-products operation of the first data held in the calculation cells in the column direction and the second data output from the drive circuit via the first wiring. Computing device. 　 In claim 1, The first data is the data to be processed, The second data mentioned above is filtered data. Computing device. 　 In claim 3, The second data is output to the calculation cell via the first wiring provided in the row direction. The first wiring is arranged in multiples for each row where the calculation cell is provided, according to the row size of the filter data. Computing device. 　 In claim 3, The data to be processed is image data. Computing device. 　 In claim 1, The calculation cell receives the second data from the drive circuit via a first wiring provided in the row direction, and supplies a current corresponding to the product of the first data and the second data to the first sample-and-hold circuit section via a second wiring provided in the column direction. Computing device. 　 In claim 6, The calculation cell is a variable resistor element having a resistance value corresponding to the first data. Computing device. 　 In claim 6, The aforementioned calculation cell is Capacitive elements and, A first transistor in which one electrode of the aforementioned capacitive element is electrically connected to the gate, The gate of the first transistor is a second transistor that holds a charge corresponding to the first data, The other electrode of the capacitive element is electrically connected to the first wiring. Computing device. 　 In claim 8, The first transistor and the second transistor each have a semiconductor layer having a metal oxide, Computing device. 　 In claim 9, The metal oxide is an oxide containing at least one of indium, element M (where M is Al, Ga, Y, or Sn), or zinc. Computing device.

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