Semiconductor device, semiconductor product, and information processing device

Abstract

This semiconductor device has a data transmission / reception circuit block and a peripheral circuit block for controlling the transmission / reception circuit block. The transmission / reception circuit block has a clock generation circuit connected to a first power supply line, and a transmission buffer circuit that is for transmitting first data on the basis of a first clock and is connected to a second power supply line. The first and the second power supply lines are respectively connected to first and second power supply connection terminals independent of each other and are electrically isolated from each other. Thus, by making a power supply configuration appropriate for a data transmission / reception circuit installed on the semiconductor device, it is possible to inhibit degradation in an operation precision level of the transmission / reception circuit.

Description

Semiconductor device, semiconductor product and information processing apparatus

[0001] The present invention relates to a semiconductor device, a semiconductor product and an information processing apparatus.

[0002] In an SoC (System on Chip) system including a plurality of semiconductor devices such as chiplets, a technique is known in which the interior of each chiplet is divided into a plurality of power domains having mutually different power supply voltage levels. For example, each chiplet includes an interface circuit for enabling communication between chiplets.

[0003] US Patent Application Publication No. 2023 / 0009881

[0004] For example, the operation accuracy of a data transmission / reception circuit mounted on a chiplet changes depending on the influence of power supply quality such as power supply noise, and the power consumption of the chiplet changes depending on the power supply voltage level. Further, the operation accuracy of the data transmission / reception circuit mounted on the chiplet changes under the influence of a power supply drop or the like during operation of a circuit mounted on the chiplet. Therefore, it is required to optimize the power supply configuration of the data transmission / reception circuit mounted on the chiplet, but a specific method has not been clarified.

[0005] The present invention has been made in view of the above points, and an object of the present invention is to suppress a decrease in operation accuracy of a transmission / reception circuit by optimizing the power supply configuration of the data transmission / reception circuit mounted on a semiconductor device.

[0006] In one aspect of the present invention, a semiconductor device comprises: first to third power connection terminals that are physically independent of each other; first to third power lines; first to third power lines; a first transmit / receive circuit block connected to the first and second power lines for transmitting and receiving first data; and a first peripheral circuit block connected to the third power line for controlling the first transmit / receive circuit block, wherein the first transmit / receive circuit block comprises: a first clock generation circuit connected to the first power line for generating a first clock; and a first transmit buffer circuit connected to the second power line for transmitting first data based on the first clock; and the first to third power lines are connected to the first to third power connection terminals, respectively, and are electrically isolated from each other.

[0007] According to the disclosed technology, by appropriately configuring the power supply for data transmission and reception circuits mounted on a semiconductor device, it is possible to suppress a decrease in the operational accuracy of the transmission and reception circuits.

[0008] This is a block diagram showing an example of a chiplet in the first embodiment. This is a cross-sectional view showing an example configuration of a chiplet system in which multiple chiplets of Figure 1 are mounted. This is a block diagram showing an example of the circuit configuration of the chiplet in Figure 2 and an example of power lines formed on the interposer and package substrate of the chiplet system. This is a block diagram showing an example of the circuit configuration of the chiplet in Figure 2 and an example of power lines formed on the interposer and package substrate of the chiplet system. This is a circuit block diagram showing an example of UCIe(1) in Figures 3 and 4. This is a circuit block diagram showing an example of UCIe(2) in Figures 3 and 4. This is a circuit block diagram showing an example of the communication main unit in Figures 5 and 6. This is a block diagram showing an example of power connection wiring formed on the interposer and package substrate of the chiplet system in the second embodiment. This is a circuit block diagram showing an example of the interface circuit UCIe(1) in Figure 8. This is a circuit block diagram showing an example of the interface circuit UCIe(2) in Figure 8. This is a block diagram showing an example of power connection wiring formed on the interposer and package substrate of the chiplet system in the third embodiment. This is a block diagram showing a modified example of the power connection wiring formed on the interposer and package substrate of the chiplet system in Figure 11. This is a circuit block diagram showing an example of the interface circuit UCIe(1) in Figures 11 and 12. This is a circuit block diagram showing an example of the interface circuit UCIe(2) in Figures 11 and 12. This is a block diagram showing an example of power connection wiring formed on the interposer and package substrate of the chiplet system in the fourth embodiment. This is a block diagram showing a modified example of the power connection wiring formed on the interposer and package substrate of the chiplet system in Figure 15. This is a circuit block diagram showing an example of the interface circuit UCIe(1) in Figures 15 and 16. This is a circuit block diagram showing an example of the interface circuit UCIe(2) in Figures 15 and 16. This is a block diagram showing an example of the power connection wiring formed on the interposer and package substrate of the chiplet system in the fifth embodiment. This is a block diagram showing a modified example of the power connection wiring formed on the interposer and package substrate of the chiplet system in Figure 19.Figures 19 and 20 show an example of the interface circuit UCIe(1), which is shown in a circuit block diagram. Figures 19 and 20 show an example of the interface circuit UCIe(2), which is shown in a circuit block diagram.

[0009] Embodiments will be described below with reference to the drawings. In the following, symbols indicating signals are also used to indicate signal lines, signal terminals, or signal nodes. Symbols indicating voltage are also used to indicate voltage lines, voltage terminals, or voltage nodes.

[0010] (First Embodiment) Figure 1 shows an example of a chiplet block configuration in the first embodiment. The chiplet 100 shown in Figure 1 is a die formed by dicing a semiconductor wafer after the semiconductor manufacturing process has been completed, and functions as an SoC, for example. The chiplet 100 is an example of a semiconductor device.

[0011] The chiplet 100 includes a data transmission / reception circuit 110 containing multiple UCIe (Universal Chiplet Interconnect Express) lanes, which are interface circuits for sending and receiving data, and a CPU (Central Processing Unit) 120. Hereinafter, the UCIe lanes will also be referred to as interface circuits UCIe. The transmission / reception circuit 110 shown in Figure 1 has an interface circuit UCIe(1) that operates as a master and two interface circuits UCIe(2) that operate as slaves. Note that the number of interface circuits UCIe(2) that operate as slaves is not limited to two. Interface circuit UCIe(1) is an example of a first transmission / reception circuit block, and interface circuits UCIe(2) are an example of a second transmission / reception circuit block.

[0012] In the following, when interface circuits UCIe(1) and UCIe(2) are described without distinction, they will simply be referred to as interface circuit UCIe. Also, in the following, interface circuits UCIe(1), UCIe(2), and UCIe will simply be referred to as UCIe(1), UCIe(2), and UCIe, respectively.

[0013] UCIe(1) has a Phase Locked Loop (PLL) 1 that receives a reference clock refclk and generates a main clock lclk, and a PLL 2 that receives a reference clock refclk and generates a sideband clock sb_clk, and outputs the generated sideband clock sb_clk to UCIe(2). UCIe(2) has a PLL 1 that receives a reference clock refclk and generates a main clock lclk. UCIe(2) does not have a PLL that generates a sideband clock sb_clk.

[0014] UCIe(1) and UCIe(2) then send and receive data using the main clock lCLK and the sideband clock sb_CLK. Each UCIe receives data from outside the chiplet 100 and transmits the received data to the CPU 120. Each UCIe receives data from the CPU 120 and transmits the received data to outside the chiplet 100.

[0015] The CPU 120 processes the data received from each UCIe to generate data to be transmitted outside the chiplet 100, and transmits the generated data to each UCIe. Note that the CPU 120 may be provided in correspondence to each of UCIe(1) and UCIe(2). The level shifter LSFT, shown by the dashed box in Figure 1, is provided between each of UCIe(1) and UCIe(2) and the CPU 120 when the transmitting / receiving circuit 110 and the CPU 120 operate at different power supply voltages. However, when the transmitting / receiving circuit 110 and the CPU 120 operate at the same power supply voltage, the level shifter LSFT is not provided.

[0016] Figure 2 shows an example configuration of a chiplet system in which multiple chiplets 100 of Figure 1 are mounted. The chiplet system 200 shown in Figure 2 includes a chiplet 100a having a transmit / receive circuit 10a such as UCIe, a chiplet 100b having a transmit / receive circuit 10b such as UCIe, an interposer 210, and a package substrate 220. The chiplet system 200 is an example of a semiconductor product having a chiplet architecture.

[0017] The chiplets 100a and 100b are connected to the interposer 210 via microbumps 51 and 52, respectively. The transmit / receive circuit 10a of chiplet 100a and the transmit / receive circuit 10b of chiplet 100b may be interconnected via the microbumps 51 and 52 and wiring formed within the interposer 210. In the following description, when chiplets 100a and 100b are described without distinction, they will simply be referred to as chiplet 100.

[0018] The interposer 210 is connected to the surface of the package substrate 220 via bumps 53. In addition to the chiplets 100a and 100b, various other electronic components may be mounted on the surface of the package substrate 220. On the back surface of the package substrate 220, BGA (Ball Grid Array) balls 54 are provided for connecting the chiplet system 200 to the outside.

[0019] The package substrate 220 is connected to the circuit board (PCB; Printed Circuit Board) 310 via the BGA ball 54, and the information processing device 300 is formed by the circuit board 310 on which the chiplet system 200 is mounted. Note that other electronic components besides the chiplet system 200 may be mounted on the circuit board 310 that constitutes the information processing device 300. Also, in Figure 2, the package substrate 220 may be omitted, and the interposer 210 may be directly connected to the circuit board 310. In that case, the chiplet system 200 consists of a chiplet 100a, a chiplet 100b, and the interposer 210.

[0020] Figures 3 and 4 show the circuit configuration of the chiplet 100a in Figure 2 and an example of the power connection wiring formed on the interposer 210 and package substrate 220 of the chiplet system 200. The signal lines formed on the interposer 210 and package substrate 220 are omitted from the diagram.

[0021] In Figures 3 and 4, the rectangles shown on the outer circumference of each chiplet 100 indicate power connection terminals. The rectangles shown on the outer circumference of the chiplet system 200 indicate the external power terminals of the package substrate 220. The external power terminals of the package substrate 220 are connected to the external power terminals of the circuit board 310 via the BGA balls 54 in Figure 2. If the chiplet system 200 is composed of chiplets 100a and 100b and an interposer 210, the rectangles shown on the outer circumference of the chiplet system 200 indicate the external power terminals of the interposer 210, and the external power terminals of the interposer 210 are connected to the external power terminals of the circuit board 310 via the bumps 53 in Figure 2.

[0022] In Figures 3 and 4 onward, the power lines formed on each chiplet 100 and the power connection wiring formed on the chiplet system 200 (interposer 210 and package substrate 220) and the circuit board 310 are shown as thick solid lines. Power voltage is supplied to each circuit within each chiplet 100 via the power connection wiring and power lines.

[0023] In Figure 3, the chiplet 100a has a UCIe (1), two UCIe (2), a GPIO (General Purpose Input / Output), and three CPUs 120 connected to UCIe (1) and the two UCIe (2), respectively. One CPU 120 may be provided in common to UCIe (1) and the two UCIe (2).

[0024] The configuration of chiplet 100b is the same as that of chiplet 100a. Therefore, the configuration of the various power connection terminals and the configuration of the various power connection wiring connected to the various power connection terminals are the same for chiplets 100a and 100b. The description and explanation of the internal circuit of chiplet 100b are omitted below.

[0025] The GPIO outputs a reference clock refclock to the PLL1, PLL2 and communication unit UCIe_PHY of UCIe(1) and the PLL1 and communication unit UCIe_PHY of UCIe(2). Each CPU 120 receives and processes data dt from the corresponding UCIe and transmits the data dt to the UCIe. The data dt transmitted and received between each CPU 120 and each UCIe is an example of the sixth data.

[0026] UCIe(1) includes PLL1, PLL2, communication unit UCIe_PHY, and communication control unit CNTL. UCIe(2) also includes PLL1, communication unit UCIe_PHY, and communication control unit CNTL. In other words, UCIe(2) has the same configuration as UCIe(1) but without PLL2.

[0027] PLL1 generates the main clock lckk using the reference clock refckk and outputs the generated main clock lckk to the communication unit UCIe_PHY and the communication control unit CNTL of its own UCIe. PLL2 generates the sideband clock sb_ck using the reference clock refckk and outputs the generated sideband clock sb_ck to the communication unit UCIe_PHY of its own UCIe and the communication unit UCIe_PHY of each UCIe (2).

[0028] Each communication unit UCIe_PHY transmits and receives data to and from the outside of the chiplet 100a, and transmits and receives data dt to and from the CPU 120 via the communication control unit CNTL. Each communication control unit CNTL controls the operation of the corresponding communication unit UCIe_PHY and controls the transmission and reception of data dt between the communication unit UCIe_PHY and the CPU 120.

[0029] In each chiplet 100, each UCIe is connected to a physically independent power line, VDDH, VDDDC, VCCAON, VCCIO, and VDD_UCIe_DIG. In other words, each chiplet has three power lines each of VDDH, VDDDC, VCCAON, VCCIO, and VDD_UCIe_DIG.

[0030] Three power lines VDDH, VDDDC, VCCAON, and VCCIO are formed on each chiplet 100, and one of each is connected to the UCIe_PHY communication unit of each UCIe. Three power lines VDD_UCIe_DIG are formed on each chiplet 100, and are connected to the CNTL communication control unit of each UCIe.

[0031] Furthermore, in each chiplet 100, the power line VDD_UCIe_PLL is connected to the GPIO and the PLL2 of UCIe(1). A common power line VDD(DIE0) is connected to each CPU 120 of chiplet 100a, and a common power line VDD(DIE1) is connected to each CPU 120 of chiplet 100b (not shown). In the following, when power line VDD(DIE0) and power line VDD(DIE1) are described without distinction, they will simply be referred to as power line VDD.

[0032] The power lines VDDH, VDDDC, VCCAON, VCCIO, and VDD_UCIe_DIG, three of which are formed on each chiplet 100, are connected to the power connection terminals VDDH, VDDDC, VCCAON, VCCIO, and VDD_UCIe_DIG, which are physically independent and provided in three separate locations on each chiplet 100. The power line VDD_UCIe_PLL formed on each chiplet 100 is connected to the power connection terminal VDD_UCIe_PLL on each chiplet 100. The power line VDD formed on each chiplet 100 is connected to the power connection terminal VDD, which is common to the three CPUs 120.

[0033] The interposer 210 and the package substrate 220 have multiple power connection wires that correspond one-to-one with the multiple power connection terminals of each chiplet 100, and the package substrate 220 has multiple external power terminals that correspond one-to-one with the multiple power connection terminals of each chiplet 100. Three power connection terminals VDDH, VDDDC, VCCAON, VCCIO, and VDD_UCIe_DIG are formed on each chiplet 100, and are connected to three external power terminals VDDH, VDDDC, VCCAON, VCCIO, and VDD_UCIe_DIG are physically independent of each other and provided on the package substrate 220, via three power connection wires VDDH, VDDDC, VCCAON, VCCIO, and VDD_UCIe_DIG formed on the interposer 210 and the package substrate 220, respectively.

[0034] As shown in Figures 3 and 4, each chiplet 100 has multiple physically independent power connection terminals corresponding to each of the multiple power lines connected to each UCIe. The multiple power lines VDDH, VDDDC, VCCAON, VCCIO, and VDD_UCIe_DIG, which are connected to the communication unit UCIe_PHY and the communication control unit CNTL of each UCIe, are electrically isolated by the corresponding power connection wiring and connected to the external power terminals VDDH, VDDDC, VCCAON, VCCIO, and VDD_UCIe_DIG of the package substrate 220, respectively.

[0035] In Figure 3, the circuit board 310 is provided with PMICs (Power Management ICs) 1-3 that control the supply of power voltage to the chiplet 100a, and a noise filter circuit FLT. The noise filter circuit FLT is an example of a filter circuit device, such as a ferrite bead. PMIC 1 is connected to the external power terminal VDD (DIE0) of the package board 220. PMIC 2 is commonly connected to the external power terminals VDDDC, VCCAON, VCCIO, VDD_UCIe_DIG, and VDD_UCIe_PLL of the package board 220 via multiple noise filter circuits FLT. PMIC 3 is commonly connected to the three external power terminals VDDDH of the package board 220 via three noise filter circuits FLT.

[0036] In each chiplet 100, the power lines VDDH and VCCIO connected to UCIe(1) are examples of the first and second power lines, respectively. In each chiplet 100, the power line VDD_UCIe_PLL or the power line VDD_UCIe_DIG connected to UCIe(1) is an example of the third power line. In each chiplet 100, the power lines VDDH and VCCIO connected to UCIe(2) are examples of the fourth and fifth power lines, respectively.

[0037] In each chiplet 100, the power line VDD_UCIe_PLL or VDD_UCIe_DIG connected to UCIe(2) is an example of a sixth or seventh power line. In each chiplet 100, the power lines VDDDC and VCCAON connected to UCIe(1) are examples of an eighth and ninth power line, respectively. In each chiplet 100, the power line VDD connected in common to each CPU 120 is an example of a tenth power line.

[0038] In each chiplet 100, the power connection terminals VDDH and VCCI, which are connected to UCIe(1) via the power lines VDDH and VCCIO, are examples of the first and second power connection terminals, respectively. In each chiplet 100, the power connection terminal VDD_UCIe_DIG, which is connected to UCIe(1) via the power line VDD_UCIe_DIG, or the power connection terminal VDD_UCIe_PLL, which is connected to UCIe(1) via the power line VDD_UCIe_PLL, are examples of the third power connection terminal.

[0039] In each chiplet 100, the power connection terminals VDDH and VCCIO, which are connected to UCIe(2) via the power lines VDDH and VCCIO, are examples of the fourth and fifth power connection terminals, respectively. In each chiplet 100, the power connection terminal VDD_UCIe_DIG, which is connected to UCIe(2) via the power line VDD_UCIe_DIG, or the power connection terminal VDD_UCIe_PLL, which is connected to UCIe(2) via the power line VDD_UCIe_PLL, are examples of the sixth and seventh power connection terminals.

[0040] In each chiplet 100, the power connection terminals VDDDC and VCCAON, which are connected to UCIe(1) via power lines VDDDC and VCCAON, are examples of the eighth and ninth power connection terminals, respectively. In each chiplet 100, the power connection terminal VDD, which is commonly connected to each CPU 120 via power line VDD, is an example of the tenth power connection terminal.

[0041] In the interposer 210 and circuit board 310, the power connection wirings VDDH, VCCIO, and VDD_UCIe_DIG connected to UCIe(1) are examples of the first, second, and third power connection wirings, respectively. In the interposer 210 and circuit board 310, the power connection wirings VDDDC and VCCAON connected to UCIe(1) are examples of the eighth and ninth power connection wirings, respectively. In the interposer 210 and circuit board 310, the power connection wirings VDDH and VCCIO connected to UCIe(2) are examples of the fourth and fifth power connection wirings, respectively.

[0042] In Figure 4, the circuit board 310 is provided with PMICs 4-6 and a noise filter circuit FLT that control the supply of power voltage to the chiplet 100b. PMIC 4 is connected to the external power terminal VDD (DIE1) of the package board 220. PMIC 5 is connected in common to the external power terminals VDDDC, VCCAON, VCCIO, VDD_UCIe_DIG, and VDD_UCIe_PLL of the package board 220 via multiple noise filter circuits FLT. PMIC 5 is also connected in common to the three external power terminals VDDH of the package board 220 via three noise filter circuits FLT.

[0043] Then, a power management device (power management system) is configured by the plurality of PMIC1 to PMIC6. Although not particularly limited, PMIC1, PMIC2, PMIC4, and PMIC5 generate, for example, 0.75 V, and supply the generated 0.75 V to the chiplet system 200. PMIC3 and PMIC6 generate, for example, 1.2 V, and supply the generated 1.2 V to the chiplet system 200. In the first embodiment, PMIC3 and PMIC6 are examples of the first power management circuit, and PMIC2 and PMIC5 are examples of the second power management circuit. Hereinafter, when PMIC1 to PMIC6 are described without distinction, they are also simply referred to as PMICs.

[0044] In FIG. 3, between PMIC2 and the plurality of external power supply terminals for chiplet 100a on package substrate 220 (three VDDC, three VCCAON, three VCCIO, three VDD_UCIe_DIG, one VDD_UCIe_PLL), a noise filter circuit FLT such as a ferrite bead is respectively disposed. Similarly, between PMIC3 and the three external power supply terminals VDDH for chiplet 100a on package substrate 220, a noise filter circuit FLT is respectively disposed. The noise filter circuit FLT has a function of removing power supply noise.

[0045] In FIG. 4, between PMIC5 and the plurality of external power supply terminals for chiplet 100b on package substrate 220 (three VDDC, three VCCAON, three VCCIO, three VDD_UCIe_DIG, one VDD_UCIe_PLL), a noise filter circuit FLT such as a ferrite bead is respectively disposed. Similarly, between PMIC6 and the three external power supply terminals VDDH for chiplet 100b on package substrate 220, a noise filter circuit FLT is respectively disposed.

[0046] By providing a PMIC commonly to a plurality of external power supply terminals and a plurality of power supply connection wirings, and providing a noise filter circuit FLT between the PMIC and the plurality of external power supply terminals, the number of PMICs mounted on the circuit board 310 can be reduced. A PMIC is a high-cost and large-sized component compared to a noise filter circuit FLT. Accordingly, the number of high-cost components mounted on the circuit board 310 of the information processing apparatus 300 can be reduced, so that the cost of the information processing apparatus 300 can be reduced. Further, since the size of the circuit board 310 can be reduced, the cost of the circuit board 310 can be reduced. Furthermore, since the size of the package substrate 220 can be reduced, the cost of the chiplet system 200 can be reduced.

[0047] In FIG. 3, one PMIC 2 is provided for a plurality of types of external power supply terminals VDDC, VCCAON, VCCIO, VDD_UCIe_DIG, and VDD_UCIe_PLL, but PMICs may be individually provided corresponding to external power supply terminal lines of the same type. Further, PMICs may be individually provided corresponding to each external power supply terminal.

[0048] Similarly, in FIG. 4, one PMIC 5 is provided for a plurality of types of external power supply terminals VDDC, VCCAON, VCCIO, VDD_UCIe_DIG, and VDD_UCIe_PLL, but PMICs may be individually provided corresponding to external power supply terminals of the same type. Further, PMICs may be individually provided corresponding to each external power supply terminal.

[0049] By generating the power supply voltage supplied to the chiplet system 200 with a plurality of PMIC1 to PMIC6, the power supply lines respectively formed in the chiplets 100a and 100b can be electrically separated, and the power supply connection wirings respectively formed in the interposer 210 and the package substrate 220 can be electrically separated. Further, even when one PMIC is connected to a plurality of external power supply terminals, by arranging the noise filter circuit FLT between the PMIC and the external power supply terminals, the power supply lines respectively formed in the chiplets 100a, 100b, the interposer 210, and the package substrate 220 can be electrically separated.

[0050] Figure 5 shows an example of UCIe(1) in Figures 3 and 4. In Figure 5, UCIe(1) includes a communication main unit 111 which includes a communication unit UCIe_PHY and a communication control unit CNTL, a wrapper circuit 112, clock adjustment circuits CRG1 and CRG2, and a clock receiving circuit CLK_IO. Note that the wrapper circuit 112 is formed around the communication main unit 111 and does not include the communication main unit 111.

[0051] The wrapper circuit 112 has a main clock control circuit 113 and a test circuit 114 including registers. The clock adjustment circuit CRG1 has a control logic circuit 115 and PLLs 10 and 11. The clock adjustment circuit CRG2 has PLL 2. The triangles shown in the clock adjustment circuits CRG1 and CRG2 represent buffer circuits.

[0052] The UCIe_PHY communication unit of UCIe(1) is an example of a first transmit / receive circuit block. The CNTL communication control unit, wrapper circuit 112, clock adjustment circuits CRG1 and CRG2, and clock receiving circuit CLK_IO of UCIe(1) are examples of a first peripheral circuit block that functions as a peripheral circuit of the UCIe_PHY communication unit. The CNTL communication control unit of UCIe(1) is an example of a first transmit / receive control circuit.

[0053] Each chiplet 100 has a hierarchical circuit configuration consisting of the entire chiplet 100, UCIe(1) and UCIe(2), peripheral circuit blocks such as the wrapper circuit 112 and clock adjustment circuits CRG1 and CRG2, and the transmit / receive circuit block of the communication unit UCIe_PHY. Four physically independent and electrically isolated power lines VDDDC, VDDH, VCCIO, and VCCAON are connected to the communication unit UCIe_PHY. Two physically independent and electrically isolated power lines VDD_UCIe_DIG and VDD_UCIe_PLL are connected to the circuit block outside the communication unit UCIe_PHY. By hierarchically separating the power supply within a single chiplet 100, the effects of power quality degradation due to power supply noise and the effects of power drop due to fluctuations in power consumption during the operation of each circuit can be appropriately controlled.

[0054] The clock receiving circuit CLK_IO outputs the reference clock refclock, received from outside the chiplet 100, to the communication unit UCIe_PHY and the clock adjustment circuits CRG1 and CRG2 of UCIe(1), as well as to UCIe(2). The frequency of the reference clock refclock is, for example, 100 MHz. The clock receiving circuit CLK_IO is the circuit corresponding to the GPIO in Figures 3 and 4.

[0055] The clock adjustment circuit CRG1 is controlled by the control logic circuit 115 and generates the main clock lckk for the main band based on the reference clock refckk. The clock adjustment circuit CRG1 outputs the generated main clock lckk to the main clock control circuit 113. For example, the clock adjustment circuit CRG1 generates two main clock lckk of different frequencies (e.g., 1 GHz and 750 MHz) using two PLLs 10 and 11. The clock adjustment circuit CRG1 in UCIe(1) is an example of a first clock adjustment circuit, and the main clock lckk generated by the clock adjustment circuit CRG1 in UCIe(1) is an example of a third clock.

[0056] The main clock control circuit 113 receives the main clock lck (1 GHz, 750 MHz) from the two PLLs 10 and 11, and based on the switching control by the control logic of the communication control unit CNTL, outputs one of the 1 GHz or 750 MHz main clock lck for the main band to the communication unit UCIe_PHY and the communication control unit CNTL. The main clock control circuit 113 of UCIe(1) is an example of a first clock control circuit.

[0057] The clock adjustment circuit CRG2 generates a sideband clock sb_ck for the sideband based on the reference clock refck, and outputs it to the communication unit UCIe_PHY and also to UCIe(2). The frequency of the sideband clock sb_ck is, for example, 800 MHz. Note that the clock adjustment circuit CRG2 may be controlled by the control logic circuit 115 included in the clock adjustment circuit CRG1. The clock adjustment circuit CRG2 is an example of a third clock adjustment circuit, and the sideband clock sb_ck is an example of a first sideband clock.

[0058] The communication control unit CNTL includes control logic and memory, and controls various operations of the communication unit UCIe_PHY, sending and receiving data dt to and from the CPU 120. The control logic communicates control signals and status signals with the main band transmission data control circuit, the main band reception data control circuit, and the sideband transmission / reception data control circuit, which are provided in the communication unit UCIe_PHY (not shown), and controls the operation of these control circuits. For example, the memory functions as a buffer to store data sent and received between the communication unit UCIe_PHY and the CPU 120.

[0059] The communication unit UCIe_PHY communicates transmission and reception data and the clock to the outside of the chiplet 100 based on control by the communication control unit CNTL. For example, the communication unit UCIe_PHY may embed the clock in the transmission and reception data using 8B10B encoding. The CPU 120 communicates data with the communication control unit CNTL, processes the data received from the communication control unit CNTL, and generates transmission data to be sent to the outside of the chiplet 100.

[0060] The test circuit 114 tests, for example, the circuits included in the wrapper circuit 112. In addition to the wrapper circuit 112, the test circuit 114 may also test the circuits included in the communication main unit 111 and at least one of the clock adjustment circuits CRG1 and CRG2.

[0061] Figure 6 shows an example of UCIe(2) in Figures 3 and 4. UCIe(2) has the same circuit configuration as UCIe(1), except that it does not have the clock receiving circuit CLK_IO and clock adjustment circuit CRG2 in Figure 5, and instead receives the reference clock refCLK and sideband clock sb_CLK from UCIe(1).

[0062] For example, the sideband clock sb_CLK generated by the clock adjustment circuit CRG2 in Figure 5 does not require the same level of precision as the main clock lCLK. Therefore, the clock adjustment circuit CRG2 is not formed in UCIe(2), and UCIe(2) receives the sideband clock sb_CLK from UCIe(1). The clock adjustment circuit CRG1 of UCIe(2) is an example of a second clock adjustment circuit, and the main clock lCLK generated by the clock adjustment circuit CRG1 of UCIe(2) is an example of a fourth clock.

[0063] The UCIe_PHY communication unit of UCIe(2) is an example of a second transmit / receive circuit block. The CNTL communication control unit, wrapper circuit 112, and clock adjustment circuit CRG1 of UCIe(2) are examples of a second peripheral circuit block that functions as a peripheral circuit of the UCIe_PHY communication unit. The CNTL communication control unit of UCIe(2) is an example of a second transmit / receive control circuit. The main clock control circuit 113 of UCIe(2) is an example of a second clock control circuit.

[0064] UCIe(2), like UCIe(1) shown in Figure 5, has four physically independent and electrically isolated power terminals VDDDC, VDDH, VCCIO, and VCCAON connected to the communication unit UCIe_PHY. Also, like UCIe(1) shown in Figure 5, UCIe(2) has two physically independent and electrically isolated power lines VDD_UCIe_DIG and VDD_UCIe_PLL connected to a circuit block outside the communication unit UCIe_PHY. Similar to UCIe(1), by hierarchically separating the power supply within a single chiplet 100, the effects of power quality degradation due to power supply noise and the effects of power drop due to fluctuations in power consumption during the operation of each circuit can be appropriately controlled.

[0065] Figure 7 shows an example of the circuit block of the UCIe_PHY communication unit shown in Figures 5 and 6. The UCIe_PHY communication unit has a digital circuit section and an analog circuit section. The digital circuit section has an interface circuit 211, a transmit data control circuit 212 for the main band, a receive data control circuit 213 for the main band, a transmit / receive data control circuit 214 for the sideband, and a PLL circuit 215. The analog circuit section has a serializer circuit 221, a deserializer circuit 222, a transmit buffer circuit 223 for the main band, a receive buffer circuit 224 for the main band, a transmit / receive buffer circuit 225 for the sideband, and a PLL circuit 226.

[0066] The transmit data control circuit 212, receive data control circuit 213, serializer circuit 221, deserializer circuit 222, transmit buffer circuit 223, and receive buffer circuit 224 of UCIe(1) are examples of a first mainband transmit / receive circuit. The transmit / receive buffer circuit 225 and transmit / receive data control circuit 214 of the UCIe_PHY communication unit of UCIe(1) are examples of a first sideband transmit / receive circuit.

[0067] The mainband transceiver circuit can transfer data at a higher speed than the sideband transceiver circuit. For example, the mainband transceiver circuit is used for transmitting and receiving user data, etc., between multiple chiplets 100. The sideband transceiver circuit is used for transmitting and receiving data including control information, status information, etc., that accompanies the transmission and reception of user data, etc.

[0068] The transmit data control circuit 212, receive data control circuit 213, serializer circuit 221, deserializer circuit 222, transmit buffer circuit 223, and receive buffer circuit 224 of UCIe(2) are examples of a second mainband transmit / receive circuit. The transmit / receive buffer circuit 225 and transmit / receive data control circuit 214 of the UCIe_PHY communication unit of UCIe(2) are examples of a second sideband transmit / receive circuit.

[0069] The symbols shown in brackets within each circuit block indicate the power supply voltage supplied to that circuit block. That is, each circuit block is connected to one of the power terminals VDDDC, VDDH, VCCIO, or VCCAON of the communication unit UCIe_PHY via a power line (not shown) that supplies the power supply voltage indicated in brackets.

[0070] The interface circuit 211 operates, for example, based on the main clock lCLK for the main band supplied from the communication control unit CNTL. The interface circuit 211 outputs the transmission data tx_int received from the communication control unit CNTL to the main band transmission data control circuit 212 or the sideband transmit / receive data control circuit 214, based on information indicating the destination of the data. For example, the information indicating the destination of the data is information indicating the bit regions allocated for the main band and sideband in the multi-bit transmission data.

[0071] Furthermore, the interface circuit 211 outputs the received data received from the main band's receive data control circuit 213 and the sideband's transmit / receive data control circuit 214 to the communication control unit CNTL as received data rx_int, along with information indicating the data source. The transmit data tx_int and received data rx_int handled by the UCIe_PHY communication unit of UCIe(1) are examples of the fifth type of data.

[0072] The interface circuit 211 outputs the control information control received from the communication control unit CNTL to the transmit data control circuit 212, the receive data control circuit 213, or the transmit / receive data control circuit 214, based on information indicating the signal destination. For example, the information indicating the signal destination is information indicating the bit regions allocated for the main band and sideband in the multi-bit control information.

[0073] Furthermore, the interface circuit 211 outputs a status signal, status, which indicates the transmission and reception status, received from the main band receive data control circuit 213 and the sideband transmit / receive data control circuit 214, to the UCIe controller, along with information indicating the signal source. For example, the information indicating the signal source is information indicating the bit regions allocated for the main band and sideband in the multi-bit status signal.

[0074] The interface circuit 211 outputs the main clock lCLK to the main band transmit data control circuit 212 and the main band receive data control circuit 213, and outputs the sideband clock sb_CLK to the sideband transmit / receive data control circuit 214.

[0075] The main band transmit data control circuit 212 performs a predetermined conversion process on the transmit data received from the interface circuit 211 based on the main clock lCLK, and outputs the converted data to the serializer circuit 221. The transmit data control circuit 212 performs conversion processing on, for example, 16 channels of parallel data. Here, the conversion process is, for example, a scrambling process that rearranges the order of the data. The main band receive data control circuit 213 performs a predetermined conversion process on the receive data received from the deserializer circuit 222 based on the main clock lCLK, and outputs the converted data to the interface circuit 211. The receive data control circuit 214 performs conversion processing on, for example, 16 channels of parallel data. Here, the conversion process is, for example, a descrambling process that returns the order of the data to its original order.

[0076] The sideband transmit / receive data control circuit 214 transmits and receives data between the interface circuit 211 and the sideband transmit / receive buffer circuit 225 based on the sideband clock sb_CLK. For example, a clock switching process is performed between the main clock lCLK and the sideband clock sb_CLK.

[0077] PLL circuits 215 and 226 are included in the digital and analog circuit sections, respectively, and generate a PLL clock pll_clock based on a reference clock refck, which is output to the serializer circuit 221 and the transmit buffer circuit 223 for the main band. The frequency of the PLL clock pll_clock is, for example, 8 GHz. The operating voltage (VDDH) of the PLL circuit 226 is different from the operating voltages of other circuit blocks included in UCIe_PHY, and therefore operates under an independent power supply voltage VDDH.

[0078] The PLL circuit 226 of UCIe_PHY in UCIe(1) is an example of a first clock generation circuit, and the PLL clock pll_ck generated by the PLL circuit 226 of UCIe_PHY in UCIe(1) is an example of a first clock. The PLL circuit 226 of UCIe_PHY in UCIe(2) is an example of a second clock generation circuit, and the PLL clock pll_ck generated by the PLL circuit 226 of UCIe_PHY in UCIe(2) is an example of a second clock.

[0079] The serializer circuit 221 converts parallel data txpdt (e.g., 16-bit data) received from the main band transmit data control circuit 212 into serial data txsdt based on the PLL clock pll_CLK, and outputs it to the main band transmit buffer circuit 223. The serializer circuit 221 has a configuration of, for example, 16:1. The serializer circuit 221 of UCIe_PHY in UCIe(1) is an example of a first serializer circuit.

[0080] The transmit buffer circuit 223 for the main band transmits the serial data received from the serializer circuit 221 as serial transmit data tx_ext_mb along with the transmit clock tx_clock_mb, based on the PLL clock pll_clock. The transmit clock tx_clock_mb is generated, for example, based on the PLL clock pll_clock. Since the transmit buffer circuit 223 is one of the circuit blocks in UCIe_PHY that requires the highest precision, it operates under an independent power supply voltage VCCIO. The transmit buffer circuit 223 of UCIe_PHY in UCIe(1) is an example of a first transmit buffer circuit, and the transmit buffer circuit 223 of UCIe_PHY in UCIe(2) is an example of a second transmit buffer circuit.

[0081] The main band receive buffer circuit 224 receives serial receive data rx_ext_mb along with the receive clock rx_clock_mb from an external source and outputs it as serial data rxsdt to the deserializer circuit 222. The receive clock rx_clock_mb is an example of a clock supplied from outside the chiplet 100. The deserializer circuit 222 converts the serial data rxsdt into parallel data rxpdt (for example, 16-bit data) and outputs the converted parallel data rxpdt to the main band receive data control circuit 213. The configuration of the deserializer circuit 222 is, for example, 1:16. The deserializer circuit 222 performs the conversion process based on the receive clock rx_clock_mb received from the receive buffer circuit 224, for example. Note that the bit width of the parallel signal is not limited to 16 bits, but may be, for example, 8 bits.

[0082] The serial transmission data tx_ext_mb and serial reception data rx_ext_mb handled by UCIe_PHY of UCIe(1) are examples of the first type of data. The serial transmission data tx_ext_mb and serial reception data rx_ext_mb handled by UCIe_PHY of UCIe(2) are examples of the second type of data. The parallel data txpdt and rxpdt handled by UCIe_PHY of UCIe(1) are examples of the first type of parallel data, and the serial data txsdt and rxsdt handled by UCIe_PHY of UCIe(1) are examples of the first type of serial data.

[0083] The sideband transmit / receive buffer circuit 225 outputs the data received from the sideband transmit / receive data control circuit 214 as transmit data tx_ext_sb along with the transmit clock tx_clock_sb, based on the sideband clock sb_clock. The transmit clock tx_clock_sb is generated, for example, based on the sideband clock sb_clock. The transmit / receive buffer circuit 225 also receives the received data rx_ext_sb supplied from the outside along with the receive clock rx_clock_sb, and outputs the received data rx_ext_sb to the sideband transmit / receive data control circuit 214. The transmit data tx_ext_sb and received data rx_ext_sb handled by UCIe_PHY in UCIe(1) are examples of the third type of data. The transmitted data tx_ext_sb and received data rx_ext_sb handled by UCIe_PHY in UCIe(2) are examples of the fourth type of data.

[0084] Alternatively, the channel width processed by the main band transmit data control circuit 212 and the main band receive data control circuit 213 may be set to 8 channels, the serializer circuit 221 may be configured in an 8:1 ratio, and the deserializer circuit 222 may be configured in a 1:8 ratio. In that case, the frequency of the main clock lck can be 2 GHz or 1.5 GHz.

[0085] In the first embodiment, within the chiplet 100, the power supply is electrically isolated between the communication unit UCIe_PHY and the circuit blocks outside the communication unit UCIe_PHY. Furthermore, within the communication unit UCIe_PHY, the power supplies are electrically isolated from each other between the main band transmit buffer circuit 223, which directly affects the signal quality of data transmitted to the outside, the PLL circuit 226 (analog circuit section), which is directly involved in generating the operating clock of the main band transmit buffer circuit 223, and the remaining circuit blocks of the communication unit UCIe_PHY. With this configuration, the effects of power supply quality degradation due to power supply noise and the effects of power supply drop due to power consumption in each circuit can be appropriately controlled in each chiplet 100a, 100b.

[0086] In the first embodiment described above, by electrically appropriately isolating the power lines and power connection terminals connected to each of the 100 circuit blocks of each chiplet, it is possible to suppress the transmission of power noise generated in other circuits to the multiple circuits mounted on the UCIe_PHY communication unit of each UCIe. As a result, a decrease in the operating accuracy of the UCIe_PHY communication unit can be suppressed.

[0087] Furthermore, even when a single PMIC is connected to multiple external power supply terminals, by placing a noise filter circuit FLT between the PMIC and the external power supply terminals, it is possible to suppress the transmission of power supply noise generated by other circuits to the multiple circuits mounted on the communication unit UCIe_PHY of each UCIe. As a result, the cost of the information processing device 300 can be reduced by decreasing the number of high-cost components mounted on the circuit board 310, while suppressing a decrease in the operating accuracy of the communication unit UCIe_PHY. In addition, the cost of the circuit board 310 and the chiplet system 200 can be reduced by decreasing the size of the circuit board 310 and the package board 220, while suppressing a decrease in the operating accuracy of the communication unit UCIe_PHY.

[0088] (Second Embodiment) Figure 8 shows an example of power connection wiring formed on the interposer 210 and package substrate 220 of the chiplet system 200 in the second embodiment. Components similar to those in Figure 3 are denoted by the same reference numerals, and detailed explanations are omitted. The circuits mounted on each chiplet 100a and 100b are the same as in Figure 3.

[0089] In Figure 8, the type and number of power lines connected to each chiplet 100 are the same as in Figure 3. The power connection terminals of chiplet 100a, except for power connection terminal VDD, are connected to the same type of power connection terminals of chiplet 100b via a common power connection wiring formed on the interposer 210. However, the three power connection terminals VDD_UCIe_DIG of each chiplet 100 are connected to the common power connection wiring VDD_UCIe_DIG formed on the interposer 210.

[0090] In chiplets 100a and 100b, the GPIO, three PLL1s, and three PLL2s are connected to a common power supply wiring VDD_UCIe_PLL via a single power supply connection terminal VDD_UCIe_PLL. Also in chiplets 100a and 100b, the three communication control units CNTLs are connected to a common power supply wiring VDD_UCIe_DIG via three power supply connection terminals VDD_UCIe_DIG, and are connected to a common external power supply terminal VDD_UCIe_DIG.

[0091] In Figure 8, PMIC1 generates the power supply voltage VDD to be supplied to each CPU 120 of the chiplet 100a. PMIC2 generates the power supply voltages VDD_UCIe_PLL, VDDDC, VCCIO, VCCAON, and VDD_UCIe_DIG to be supplied to each UCIe of the chiplets 100a and 100b. PMIC3 generates the power supply voltage VDDH to be supplied to each UCIe of the chiplets 100a and 100b. PMIC4 generates the power supply voltage VDD to be supplied to each CPU 120 of the chiplet 100b. Although not particularly limited, PMIC1, PMIC2, and PMIC4 generate, for example, 0.75V, and PMIC3 generates 1.2V.

[0092] In the second embodiment, by commonizing the power connection wirings VDDH, VDDDC, VCCIO, VCCAON, VDD_UCIe_PLL, and VDD_UCIe_DIG between the chiplets 100a and 100b, the number of power connection wirings, PMICs, and noise filter circuits FLTs can be reduced compared to the first embodiment. Furthermore, by commonizing the power connection wiring VDD_UCIe_DIG and the external power terminal VDD_UCIe_DIG to just one for the three power connection terminals VDD_UCIe_DIG of the chiplets 100a and 100b, the number of power connection wirings, PMICs, and noise filter circuits FLTs can be reduced compared to the first embodiment. As a result, in each chiplet 100a and 100b, the cost of the information processing device 300 and the chiplet system 200 can be reduced while appropriately controlling the effects of power quality degradation caused by power supply noise and the effects of power drop due to fluctuations in power consumption during the operation of each circuit.

[0093] Figure 9 shows an example of UCIe(1) in Figure 8. The circuit configuration of UCIe(1) shown in Figure 9 is the same as that of UCIe(1) in Figure 5, except that it has a clock adjustment circuit CRG instead of clock adjustment circuits CRG1 and CRG2.

[0094] The clock adjustment circuit CRG is similar in circuit configuration to the clock adjustment circuits CRG1 and CRG2 in Figure 5, except that one PLL1 is placed instead of PLL10 and PLL11 in the clock adjustment circuit CRG2 in Figure 5. The clock adjustment circuit CRG is controlled by the control logic circuit 115 and generates a main clock lck of 1 GHz or 750 MHz based on the reference clock refck. Unlike UCIe(1) in Figure 5, each circuit provided in the clock adjustment circuit CRG and the main clock control circuit 113 operate under the power supply voltage VDD_UCIe_PLL.

[0095] Figure 10 shows an example of UCIe(2) in Figure 8. The circuit configuration of UCIe(2) shown in Figure 10 is the same as the circuit configuration of UCIe(2) in Figure 6, except that it has a clock adjustment circuit CRG instead of the clock adjustment circuit CRG1 in Figure 6. The clock adjustment circuit CRG generates a main clock lCLK of 1 GHz or 750 MHz based on a reference clock reflc, similar to the clock adjustment circuit CRG in Figure 9. Unlike UCIe(2) in Figure 6, each circuit provided in the clock adjustment circuit CRG and the main clock control circuit 113 operate under a common power supply voltage VDD_UCIe_PLL with UCIe(1).

[0096] As described above, the same effects as in the first embodiment can be obtained in the second embodiment as well. For example, by electrically appropriately isolating the power lines and power connection terminals connected to each of the 100 circuit blocks of each chiplet, it is possible to suppress the transmission of power noise generated in other circuits to the multiple circuits mounted on the UCIe_PHY communication unit of each UCIe. As a result, it is possible to suppress a decrease in the operating accuracy of the UCIe_PHY communication unit.

[0097] Furthermore, in the second embodiment, if the effects of power quality degradation due to power supply noise and the effects of power drop due to fluctuations in power consumption during the operation of each circuit can be appropriately controlled, the same type of power connection wiring can be shared between the chiplets 100a and 100b, and the power supply can be shared between PLL1 and PLL2. As a result, the number of power connection wirings, the number of PMICs, and the number of noise filter circuits FLT can be reduced compared to the first embodiment. As a result, the cost of the information processing device 300 can be reduced by reducing the number of high-cost components mounted on the circuit board 310, and the cost of the circuit board 310 and chiplet system 200 can be reduced by further reducing the size of the circuit board 310 and package board 220, while suppressing a decrease in the operational accuracy of the communication unit UCIe_PHY.

[0098] (Third Embodiment) Figure 11 shows an example of power connection wiring formed on the interposer 210 and package substrate 220 of the chiplet system 200 in the third embodiment. Components similar to those in Figure 3 are denoted by the same reference numerals, and detailed explanations are omitted. The circuits mounted on each chiplet 100a and 100b are the same as in Figure 3.

[0099] In Figure 11, the types and number of power lines connected to each chiplet 100 are the same as in Figure 3, except that the three communication control units (CNTLs) are connected to one power connection terminal. The three communication control units (CNTLs) of each chiplet 100 are connected to the interposer 210 and the external power terminal VDD of the package substrate 220 via one power connection terminal. That is, the three CPUs 120 and three communication control units (CNTLs) of each chiplet 100 operate on a common power supply voltage VDD.

[0100] In Figure 11, in each chiplet 100a and 100b, three identical power lines (VDDH, VCCIO, VCCAON, VCCIO) connected to UCIe(1) and the two UCIe(2) respectively are connected to a single power connection wiring (VDDH, VCCIO, VCCAON, VCCIO) on the interposer 210 and the package substrate 220, respectively. Also, similar to Figure 8, in each chiplet 100a and 100b, the GPIO, the three PLL1 and PLL2 are connected to a common power connection wiring VDD_UCIe_PLL via a single power connection terminal VDD_UCIe_PLL.

[0101] In Figure 11, PMIC1 generates the power supply voltage VDD to be supplied to each CPU 120 and each communication control unit CNTL of the chiplet 100a. PMIC2 generates the power supply voltages VDD_UCIe_PLL, VDDDC, VCCIO, and VCCAON to be supplied to each UCIe of the chiplet 100a. PMIC3 generates the power supply voltage VDDH to be supplied to each UCIe of the chiplet 100a.

[0102] PMIC4 generates the power supply voltage VDD to be supplied to each CPU 120 and each communication control unit CNTL of the chiplet 100b. PMIC5 generates the power supply voltages VDD_UCIe_PLL, VDDDC, VCCIO, and VCCAON to be supplied to each UCIe of the chiplet 100b. PMIC6 generates the power supply voltage VDDDH to be supplied to each UCIe of the chiplet 100b. Although not particularly limited, PMIC1, PMIC2, PMIC4, and PMIC5 generate, for example, 0.75V, and PMIC3 and PMIC6 generate 1.2V.

[0103] In the third embodiment, by making the same type of power connection wiring VDDH, VCCIO, VCCAON, and VCCIO common for each chiplet 100, the number of power connection wirings, the number of external power terminals on the interposer 210 and package substrate 220, and the number of noise filter circuits FLT can be reduced compared to the first and second embodiments. As a result, in each chiplet 100a, 100b, the cost of the information processing device 300 and the chiplet system 200 can be reduced while appropriately controlling the effects of power quality degradation caused by power supply noise and the effects of power drop due to fluctuations in power consumption during the operation of each circuit.

[0104] Figure 12 shows a modified example of the power connection wiring formed on the interposer 210 and package substrate 220 of the chiplet system 200 in Figure 11. Components similar to those in Figures 3 and 11 are denoted by the same reference numerals, and detailed explanations are omitted.

[0105] In Figure 12, similar to Figure 8, the power connection terminals of the chiplet 100a, except for the power connection terminal VDD, are connected to the same type of power connection terminal of the chiplet 100b via common power connection wiring formed on the interposer 210. This eliminates the need for the PMIC 5 and PMIC 6 in Figure 11, the external power terminals of the interposer 210 and package substrate 220 connected to the PMIC 5 and PMIC 6, and the noise filter circuit FLT connected to the PMIC 5 and PMIC 6, thereby reducing the cost of the information processing device 300 and the chiplet system 200.

[0106] Figure 13 shows an example of the interface circuit UCIe(1) shown in Figures 11 and 12. The UCIe(1) shown in Figure 13 is similar in configuration to the UCIe(1) in Figure 9, except that the communication control unit CNTL is connected to the power terminal VDD instead of the power terminal VDD_UCIe_DIG in Figure 9.

[0107] Figure 14 shows an example of the interface circuit UCIe(2) in Figures 11 and 12. The UCIe(2) shown in Figure 14 is similar in configuration to the UCIe(2) in Figure 10, except that the communication control unit CNTL is connected to the power terminal VDD instead of the power terminal VDD_UCIe_DIG in Figure 10.

[0108] As described above, the same effects as in the first and second embodiments can be obtained in the third embodiment as well. For example, by electrically appropriately isolating the power lines and power connection terminals connected to each of the 100 circuit blocks of each chiplet, it is possible to suppress the transmission of power noise generated in other circuits to the multiple circuits mounted on the UCIe_PHY communication unit of each UCIe. As a result, it is possible to suppress a decrease in the operating accuracy of the UCIe_PHY communication unit.

[0109] Furthermore, by standardizing the power connection wiring for each chiplet 100, the number of PMICs, the number of external power terminals on the interposer 210 and package substrate 220, and the number of noise filter circuits FLT can be reduced. This reduces the cost of the information processing device 300 and the chiplet system 200 while suppressing a decrease in the operational accuracy of the communication unit UCIe_PHY.

[0110] Furthermore, by standardizing the power connection wiring between chiplets 100a and 100b, the number of PMICs, the number of power connection wirings, the number of external power terminals on the interposer 210 and package substrate 220, and the number of noise filter circuits FLT can be further reduced. This allows for further reduction of the cost of the information processing device 300 and the chiplet system 200 while suppressing a decrease in the operational accuracy of the communication unit UCIe_PHY.

[0111] (Fourth Embodiment) Figure 15 shows an example of power connection wiring formed on the interposer 210 and package substrate 220 of the chiplet system 200 in the fourth embodiment. Components similar to those in Figures 3 and 11 are denoted by the same reference numerals, and detailed explanations are omitted. The circuits mounted on each chiplet 100a and 100b are the same as in Figure 3.

[0112] Figure 15 is similar to the configuration in Figure 11, except that the three communication control units CNTL are connected to the power supply wiring VDD_UCIe_PLL via the power supply connection terminal VDD_UCIe_PLL, and the power supply wiring VDD_UCIe_PLL, VDDDC, and VCCAON are interconnected near the external power supply terminals of the interposer 210 and the package substrate 220. As a result, each PMIC2 and PMIC5 is connected to the two external power supply terminals of the interposer 210 and the package substrate 220, and one noise filter circuit FLT is connected to each PMIC2 and PMIC5.

[0113] In the fourth embodiment, the external power terminal VCCAON connected to the power supply connection wiring VCCAON is an example of a first external power terminal or a second external power terminal. PMIC3 and PMIC6 are an example of a third power management circuit, and PMIC2 and PMIC5 are an example of a fourth power management circuit. Although not particularly limited, PMIC1, PMIC2, PMIC4 and PMIC5 generate 0.75V, for example, and PMIC3 and PMIC6 generate 1.2V.

[0114] For example, for each chiplet 100, the power connection wiring VDDDC is connected to the power connection wiring VCCAON via connection point CN1, which is located near the external power terminal VCCAON. Also, for each chiplet 100, the power connection wiring VDD_UCIe_PLL is connected to the power connection wiring VCCAON via connection point CN2, which is located near the external power terminal VCCAON. Connection point CN is an example of a first or second connection point. The power connection wiring provided between connection point CN1 or connection point CN2 and the external power terminal VCCAON is an example of a first or second intermediate connection wiring.

[0115] The wiring paths of the power supply wiring VDDDC and VCCAON connected via connection point CN1, the connection paths of the power supply wiring VDDDC and VDD_UCIe_PLL connected via connection points CN1 and CN2, and the connection paths of the power supply wiring VCCAON and VDD_UCIe_PLL connected via connection points CN1 and CN2 are configured to have an impedance capable of reducing power supply noise to a level that prevents each chiplet 100 from malfunctioning. In other words, the connection paths of two or more power supply wirings connected via one or more connection points provided near the external power supply terminal are configured to have an impedance capable of reducing power supply noise to a level that prevents each chiplet 100 from malfunctioning.

[0116] For example, the length of the power connection wiring between connection point CN1 and the external power terminal VCCAON is configured to be shorter than, at least, the length of the power connection wiring between connection point CN1 and the power connection terminal VCCAON, and the length of the power connection wiring between connection point CN1 and the power connection terminal VDDDC. Also, for example, the length of the power connection wiring between connection point CN2 and the external power terminal VCCAON is configured to be shorter than, at least, the length of the power connection wiring between connection point CN2 and the power connection terminal VCCAON, and the length of the power connection wiring between connection point CN2 and the power connection terminal VDD_UCIe_PLL. This is also the case in Figures 16, 19, and 20, which will be described later.

[0117] For example, by connecting the power connection wiring VDDDC and VDD_UCIe_PLL near the external power terminal VCCAON on the power connection wiring VCCAON, the length of the power connection wiring between different types of power connection terminals connected to each UCIe can be made longer compared to when they are connected near different types of power connection terminals on the chiplet 100. This reduces the influence of mutual power supply noise due to the impedance effect of the long-distance power lines, thereby electrically isolating the power supplies.

[0118] The combination of power connection wires connected at the connection point near the external power terminal is not limited to the example shown in Figure 15, as long as the power connection wires have the same voltage values. For example, power connection wires VCCIO and VDDDC may be connected to power connection wire VCCAON at the connection point near the external power terminal VCCAON. Also, power connection wires VCCIO and VDDDC may be connected to power connection wire VCCIO at the connection point near the external power terminal VCCIO. Furthermore, power connection wires VCCIO, VDDDC, and VCCAON may be connected to power connection wire VCCAON at the connection point near the external power terminal VCCAON. In addition, multiple power connection wires connected via the connection point near the external power terminal may be of the same type as well as different types of power connection wires. These are also true for Figures 16, 19, and 20, which will be described later.

[0119] Figure 16 shows a modified example of the power connection wiring formed on the interposer 210 and package substrate 220 of the chiplet system 200 in Figure 15. Components similar to those in Figures 3 and 15 are denoted by the same reference numerals, and detailed explanations are omitted.

[0120] In Figure 16, similar to Figure 11, three identical power connection terminals in each chiplet 100 are interconnected by a common power connection wiring. Furthermore, the identical power connection wirings of chiplets 100a and 100b are interconnected near the external power terminals of the package substrate 220. This reduces the number of PMICs, the number of external power terminals on the interposer 210 and package substrate 220, and the number of noise filter circuits FLT compared to Figure 15. While not particularly limited, PMIC1, PMIC2, and PMIC4 generate, for example, 0.75V, and PMIC3 generates 1.2V.

[0121] In Figure 16, the impedance effect of the long-distance power line described in Figure 15 can be obtained even between chiplets 100a and 100b that are interconnected by the same type of power connection wiring, reducing the influence of power supply noise between chiplets 100a and 100b and enabling the power supply to be electrically isolated.

[0122] Figure 17 shows an example of the interface circuit UCIe(1) shown in Figures 15 and 16. The UCIe(1) shown in Figure 17 is similar in configuration to the UCIe(1) in Figure 13, except that all external circuit blocks of the communication unit UCIe_PHY are connected to the power terminal VDD_UCIe_PLL.

[0123] Figure 18 shows an example of the interface circuit UCIe(2) shown in Figures 15 and 16. The UCIe(2) shown in Figure 18 is similar in configuration to the UCIe(2) in Figure 14, except that all external circuit blocks of the communication unit UCIe_PHY are connected to the power terminals VDD and VDD_UCIe_PLL.

[0124] As described above, the same effects as those of the first to third embodiments can be obtained in the fourth embodiment. For example, by electrically appropriately isolating the power lines and power connection terminals connected to each of the 100 circuit blocks of each chiplet, it is possible to suppress the transmission of power noise generated in other circuits to the multiple circuits mounted on the UCIe_PHY communication unit of each UCIe. As a result, it is possible to suppress a decrease in the operating accuracy of the UCIe_PHY communication unit.

[0125] Furthermore, by standardizing the power connection wiring for each chiplet 100, the number of PMICs, the number of external power terminals on the interposer 210 and package substrate 220, and the number of noise filter circuits FLT can be reduced. This reduces the cost of the information processing device 300 and the chiplet system 200 while suppressing a decrease in the operational accuracy of the communication unit UCIe_PHY.

[0126] Furthermore, by standardizing the power connection wiring between chiplets 100a and 100b, the number of PMICs, the number of power connection wirings, the number of external power terminals on the interposer 210 and package substrate 220, and the number of noise filter circuits FLT can be further reduced. This reduces the cost of the information processing device 300 and the chiplet system 200 while suppressing a decrease in the operational accuracy of the communication unit UCIe_PHY.

[0127] Furthermore, in the fourth embodiment, by connecting multiple different types of power connection wires at connection points near the external power terminals, the length of the power connection wires between different types of power connection terminals can be made longer compared to when they are connected near the different types of power connection terminals of the chiplet 100. This reduces the influence of mutual power noise due to the impedance effect of the long-distance power lines, and allows for the electrical isolation of the power supplies.

[0128] (Fifth Embodiment) Figure 19 shows an example of power connection wiring formed on the interposer 210 and package substrate 220 of the chiplet system 200 in the fifth embodiment. Components similar to those in Figures 3 and 15 are denoted by the same reference numerals, and detailed explanations are omitted. The circuits mounted on each chiplet 100a and 100b are the same as in Figure 3.

[0129] In Figure 19, for each chiplet 100, the GPIO and PLL2 are connected to the power connection wiring VDD_UCIe_PLL on the interposer 210 via the power connection terminal VDD_UCIe_PLL. The power connection wiring VDD_UCIe_PLL is connected to the power connection wiring VCCAON in the vicinity of the external power terminal VCCAON.

[0130] Furthermore, the three PLL1s of each UCIe are connected to three power connection wires VDD_UCIe_LCLK on the interposer 210 via three power connection terminals VDD_UCIe_LCLK. The three power connection wires VDD_UCIe_LCLK are interconnected on the interposer 210 or package substrate 220 and combined into a single power connection wire VDD_UCIe_LCLK, which is connected to the power connection wire VDD_UCIe_PLL near the external power terminal VCCAON. The rest of the configuration of the chiplet system 200 is the same as in Figure 15.

[0131] Figure 20 shows a modified example of the power connection wiring formed on the interposer 210 and package substrate 220 of the chiplet system 200 in Figure 19. In Figure 20, as in Figure 16, three identical power connection terminals in each chiplet 100 are interconnected by a common power connection wiring, and the identical power connection wirings of chiplets 100a and 100b are interconnected near the external power terminals of the interposer 210 and package substrate 220.

[0132] Figure 21 shows an example of the interface circuit UCIe(1) in Figures 19 and 20. The UCIe(1) shown in Figure 21 is similar in configuration to the UCIe(1) in Figure 17, except that a dedicated power supply connection terminal VDD_UCIe_LCLK is formed on PLL1 and the power line VDD_UCIe_LCLK is connected to PLL1.

[0133] Figure 22 shows an example of the interface circuit UCIe(2) in Figures 19 and 20. The UCIe(2) shown in Figure 21 is similar in configuration to the UCIe(2) in Figure 18, except that a dedicated power supply connection terminal VDD_UCIe_LCLK is formed on PLL1 and the power line VDD_UCIe_LCLK is connected to PLL1.

[0134] As described above, the same effects as those of the first to fourth embodiments can be obtained in the fifth embodiment as well. For example, by electrically appropriately isolating the power lines and power connection terminals connected to each of the 100 circuit blocks of each chiplet, it is possible to suppress the transmission of power noise generated in other circuits to the multiple circuits mounted on the UCIe_PHY communication unit of each UCIe. As a result, it is possible to suppress a decrease in the operating accuracy of the UCIe_PHY communication unit.

[0135] Furthermore, by standardizing the power connection wiring for each chiplet 100, the number of PMICs, the number of external power terminals on the interposer 210 and package substrate 220, and the number of noise filter circuits FLT can be reduced. This reduces the cost of the information processing device 300 and the chiplet system 200 while suppressing a decrease in the operational accuracy of the communication unit UCIe_PHY.

[0136] Furthermore, by standardizing the power connection wiring between chiplets 100a and 100b, the number of PMICs, the number of power connection wirings, the number of external power terminals on the interposer 210 and package substrate 220, and the number of noise filter circuits FLT can be further reduced. This reduces the cost of the information processing device 300 and the chiplet system 200 while suppressing a decrease in the operational accuracy of the communication unit UCIe_PHY.

[0137] Furthermore, by connecting multiple different types of power connection wires at connection points near the external power terminals, the length of the power connection wires between different types of power connection terminals can be increased compared to connecting them near the terminals themselves. This reduces the influence of mutual power noise due to the impedance effect of long-distance power lines, and allows for electrical isolation of the power supplies.

[0138] It should be noted that the combinations of power supply isolation configurations for the circuits within each chiplet 100 in the chiplet system 200, power supply isolation configurations for the power supply connection wiring formed on the interposer 210 and circuit board 310, and power supply isolation configurations for the PMIC and noise filter circuit FLT formed on the circuit board 310, as shown in the first to fifth embodiments, are merely examples, and these combinations can be changed as appropriate.

[0139] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application.

[0140] 10a, 10b Transmit / receive circuits 51, 52 Microbumps 53 Bumps 54 BGA balls 100a, 100b Chiplets 110 Transmit / receive circuits 111 Communication main unit 112 Wrapper circuit 113 Main clock control circuit 114 Test circuit 115 Control logic circuit 200 Chiplet system 210 Interposer 211 Interface circuit 212 Transmit data control circuit 213 Receive data control circuit 214 Transmit / receive data control circuit 215 PLL circuit 220 Package board 221 Serializer circuit 222 Deserializer circuit 223 Transmit buffer circuit 224 Receive buffer circuit 225 Transmit / receive buffer circuit 226 PLL circuit 300 Information processing unit 310 Circuit board CLK_IO Clock receiving circuit CN1, CN2 Connection point CNTL Communication control unit CRG, CRG1, CRG2 Clock adjustment circuit dt Data FLT Noise filter circuit lCLK Main clock LSFT Level shifter pll_CLK PLL clock rx_clock_mb, rx_clock_sb Receive clock rx_ext_mb Serial received data rx_ext_sb Received data rx_int Received data rxpdt Parallel data rxsdt Serial data sb_CLK Sideband clock tx_clock_mb, tx_clock_sb Transmit clock tx_ext_mb Serial transmitted data tx_ext_sb Transmitted data tx_int Transmitted data txpdt Parallel data txsdt Serial data UCIe(1), UCIe(2) Interface Circuit UCIE_PHY Communication Section VCCIO Power line, power connection terminal, power connection wiring, external power terminal VDD Power line, power connection terminal, power connection wiring, external power terminal VDD_UCIE_DIG Power line, power connection terminal, power connection wiring, external power terminal VDD_UCIE_LCCLK Power line, power connection terminal, power connection wiring VDD_UCIE_PLL Power line, power connection terminal, power connection wiring, external power terminal VDDDC Power line, power connection terminal, power connection wiring, external power terminalVDDH power line, power connection terminal, power connection wiring, external power terminal

Claims

1. A semiconductor device comprising: first to third power connection terminals that are physically independent of each other; first to third power lines; first to third power lines; a first transmit / receive circuit block connected to the first and second power lines for transmitting and receiving first data; and a first peripheral circuit block connected to the third power line for controlling the first transmit / receive circuit block, wherein the first transmit / receive circuit block comprises: a first clock generation circuit connected to the first power line for generating a first clock; and a first transmit buffer circuit connected to the second power line for transmitting the first data based on the first clock; and the first to third power lines are each connected to the first to third power connection terminals and are electrically isolated from each other.

2. A semiconductor device according to claim 1, comprising: fourth and fifth power connection terminals that are physically independent from and physically independent of each other from any of the first to third power connection terminals; fourth and fifth power lines; and a second transmit / receive circuit block connected to the fourth and fifth power lines for transmitting and receiving second data, wherein the second transmit / receive circuit block comprises: a second clock generation circuit connected to the fourth power line for generating a second clock; and a second transmit buffer circuit connected to the fifth power line for transmitting the second data based on the second clock, wherein the fourth and fifth power lines are connected to the fourth and fifth power connection terminals, respectively, and are electrically isolated from each other.

3. The semiconductor device according to claim 2, further comprising: a sixth power connection terminal physically independent from any of the first to fifth power connection terminals; a sixth power line; and a second peripheral circuit block connected to the sixth power line for controlling the second transmit / receive circuit block, wherein the sixth power line is connected to the sixth power connection terminal and electrically isolated from the fourth and fifth power lines.

4. The semiconductor device according to claim 2, comprising: a seventh power line; and a second peripheral circuit block connected to the seventh power line and controlling the second transmit / receive circuit block, wherein the seventh power line is connected to the third power connection terminal and is electrically isolated from the fourth and fifth power lines.

5. The semiconductor device according to claim 2, wherein the first to third power lines are electrically isolated from each other outside the semiconductor device, and the fourth and fifth power lines are electrically isolated from each other outside the semiconductor device.

6. The semiconductor device according to claim 3 or 4, wherein the first peripheral circuit block includes a first transmit / receive control circuit for controlling the transmit / receive operation in the first transmit / receive circuit block, and the second peripheral circuit block includes a second transmit / receive control circuit for controlling the transmit / receive operation in the second transmit / receive circuit block.

7. The semiconductor device according to claim 3 or 4, wherein the first peripheral circuit block includes a first clock adjustment circuit that supplies a third clock for transmission and reception to the first transmit / receive circuit block, and the second peripheral circuit block includes a second clock adjustment circuit that supplies a fourth clock for transmission and reception to the second transmit / receive circuit block.

8. The semiconductor device according to claim 3 or 4, wherein the first transmit / receive circuit block includes a first mainband transmit / receive circuit and a first sideband transmit / receive circuit, the first peripheral circuit block includes a first clock adjustment circuit that supplies the first mainband transmit / receive circuit a third clock for the transmission and reception of the first data, and the first sideband transmit / receive circuit includes a second mainband transmit / receive circuit and a second sideband transmit / receive circuit, the second peripheral circuit block includes a second clock adjustment circuit that supplies the second mainband transmit / receive circuit a fourth clock for the transmission and reception of the second data, and the second sideband transmit / receive circuit receives the first sideband clock from the third clock adjustment circuit for the transmission and reception of the fourth data.

9. The semiconductor device according to claim 1, further comprising: an eighth power connection terminal physically independent from any of the first to third power connection terminals; and an eighth power line, wherein the first transmit / receive circuit block is connected to the eighth power line and has a first serializer circuit that converts first parallel data into first serial data based on the first clock and outputs the first serial data to the first transmit buffer circuit, and the eighth power line is connected to the eighth power connection terminal and electrically isolated from the first to third power lines.

10. The semiconductor device according to claim 9, further comprising: a ninth power connection terminal physically independent from any of the first to third power connection terminals; and a ninth power line, wherein the first transmit / receive circuit block is connected to the ninth power line and has a data control circuit that transmits and receives fifth data with the first peripheral circuit block and performs conversion processing between the fifth data and the first parallel data, and the ninth power line is connected to the ninth power connection terminal and electrically isolated from the first to third power lines.

11. The semiconductor device according to claim 10, comprising: a first receive buffer circuit connected to the eighth power line and receiving the first serial data based on a clock supplied from outside the semiconductor device; and a deserializer circuit connected to the eighth power line and converting the first serial data into first parallel data, wherein the data control circuit further performs a conversion process between the first parallel data and the fifth data.

12. The semiconductor device according to claim 7, wherein the first clock adjustment circuit and the second clock adjustment circuit each generate at least two clocks with different frequencies, the first peripheral circuit block has a first clock control circuit that outputs one of the at least two clocks output from the first clock adjustment circuit as the third clock, and the second peripheral circuit block has a second clock control circuit that outputs one of the at least two clocks output from the second clock adjustment circuit as the fourth clock.

13. The semiconductor device according to claim 7, comprising a clock receiving circuit that receives a reference clock and supplies the reference clock to the first clock generation circuit, the second clock generation circuit, the first clock adjustment circuit, and the second clock adjustment circuit, wherein the first clock generation circuit, the second clock generation circuit, the first clock adjustment circuit, and the second clock adjustment circuit each generate the first clock, the second clock, the third clock, and the fourth clock, respectively, based on the reference clock.

14. The semiconductor device according to claim 1, further comprising: a tenth power connection terminal physically independent of any of the first to third power connection terminals; a tenth power line; and a processing circuit connected to the tenth power line, which transmits and receives sixth data with the first peripheral circuit block and processes data based on the sixth data, wherein the tenth power line is connected to the tenth power connection terminal and is electrically isolated from the first to third power lines.

15. A semiconductor product having a chiplet architecture, comprising: an interposer including first to third power connection wiring; two semiconductor devices disposed on the interposer, wherein at least one of the two semiconductor devices comprises: first to third power connection terminals that are physically independent of each other; first to third power lines; first to third power lines; a first transmit / receive circuit block connected to the first and second power lines for transmitting and receiving first data; a first peripheral circuit block connected to the third power line for controlling the first transmit / receive circuit block; wherein the first transmit / receive circuit block comprises: a first clock generation circuit connected to the first power line for generating a first clock; a first transmit buffer circuit connected to the second power line for transmitting first data based on the first clock; wherein the first to third power lines are connected to the first to third power connection terminals, respectively. The first to third power connection wirings are connected to the first to third power connection terminals of at least one of the two semiconductor devices, respectively, and the semiconductor product is electrically isolated from each other.

16. The semiconductor product according to claim 15, wherein the first to third power connection wirings are connected to the first to third power connection terminals of both of the two semiconductor devices, respectively.

17. The semiconductor product according to claim 15, wherein the interposer includes fourth and fifth power connection wiring, and at least one of the two semiconductor devices further includes fourth and fifth power connection terminals that are physically independent from and physically independent of any of the first to third power connection terminals, fourth and fifth power lines, and a second transmit / receive circuit block connected to the fourth and fifth power lines for transmitting and receiving second data, the second transmit / receive circuit block includes a second clock generation circuit connected to the fourth power line for generating a second clock, and a second transmit buffer circuit connected to the fifth power line for transmitting the second data based on the second clock, the fourth and fifth power lines are connected to the fourth and fifth power connection terminals, respectively, the fourth and fifth power connection wiring is connected to the fourth and fifth power connection terminals of at least one of the two semiconductor devices, and the first to fifth power connection wiring are electrically isolated from each other.

18. At least one of the two semiconductor devices further includes: fourth and fifth power connection terminals that are physically independent of and physically independent of each other from any of the first to third power connection terminals; fourth and fifth power lines; and a second transmit / receive circuit block connected to the fourth and fifth power lines for transmitting and receiving second data. The second transmit / receive circuit block includes: a second clock generation circuit connected to the fourth power line for generating a second clock; and a second transmit buffer circuit connected to the fifth power line for transmitting the second data based on the second clock. The fourth and fifth power lines are connected to the fourth and fifth power connection terminals, respectively. The first power connection wiring is connected to the first and fourth power connection terminals of at least one of the two semiconductor devices. The second power connection wiring is connected to the second and fifth power connection terminals of at least one of the two semiconductor devices. The third power connection wiring is connected to the third power connection terminal of at least one of the two semiconductor devices. The semiconductor product according to claim 15, wherein the first to third power connection wirings are electrically isolated from each other.

19. The semiconductor product according to claim 18, wherein the first to third power connection wirings are connected to the first to third power connection terminals of both of the two semiconductor devices, respectively.

20. The interposer further includes eighth and ninth power connection wiring, at least one of the two semiconductor devices further includes an eighth power connection terminal physically independent of any of the first to third power connection terminals, a ninth power connection terminal physically independent of any of the first to third power connection terminals, an eighth power line, and a ninth power line, and the first transmit / receive circuit block includes a first serializer circuit connected to the eighth power line, which converts first parallel data into first serial data based on the first clock and outputs the first serial data to the first transmit buffer circuit, and a data control circuit connected to the ninth power line, which transmits and receives fifth data with the first peripheral circuit block and performs conversion processing between the fifth data and the first parallel data, the eighth and ninth power lines are connected to the eighth and ninth power connection terminals, respectively, and the eighth and ninth power connection wiring is connected to the eighth and ninth power connection terminals of at least one of the two semiconductor devices, The semiconductor product according to claim 15, wherein at least two of the third, eighth, and ninth power connection wires are connected at a first connection point near a first external power terminal of the semiconductor product, and the first connection point is connected to the first external power terminal via a first relay connection wire.

21. The semiconductor product according to claim 20, wherein the length of the first relay connection wiring from the first connection point to the first external power terminal is less than the length of the wiring from the first connection point to the power connection terminal among the third, eighth, and ninth power connection terminals that is connected to the first connection point.

22. The semiconductor product according to claim 20, wherein the wiring path between the power connection terminals of the third, eighth, and ninth power connection terminals connected to the first connection point, passing through the first connection point, has an impedance capable of reducing power noise to a level that prevents at least one of the two semiconductor devices from malfunctioning.

23. The semiconductor product according to claim 20, wherein the first to third power connection wirings are connected to the first to third power connection terminals of both of the two semiconductor devices, respectively.

24. The semiconductor product according to claim 15, wherein two of the first to third power supply connection wires are connected at a second connection point near the second external power supply terminal of the semiconductor product, and the second connection point is connected to the second external power supply terminal via a second relay connection wire.

25. An information processing apparatus comprising: a circuit board; a semiconductor product having a chiplet architecture disposed on the circuit board, wherein the semiconductor product comprises: an interposer including first to third power connection wiring; and two semiconductor devices disposed on the interposer, wherein at least one of the two semiconductor devices comprises: first to third power connection terminals that are physically independent of each other; first to third power lines; first to third power lines; a first transmit / receive circuit block connected to the first and second power lines for transmitting and receiving first data; and a first peripheral circuit block connected to the third power line for controlling the first transmit / receive circuit block, wherein the first transmit / receive circuit block comprises: a first clock generation circuit connected to the first power line for generating a first clock; and a first transmit buffer circuit connected to the second power line for transmitting first data based on the first clock, wherein the first to third power lines are each connected to the first to third power connection terminals, The first to third power connection wirings are each connected to the first to third power connection terminals of at least one of the two semiconductor devices and are electrically isolated from each other, and the circuit board includes a power management device that controls the supply of power to the first to third power connection wirings, and at least one filter circuit device provided between the first to third power connection wirings and the power management device, and is an information processing apparatus.

26. The information processing apparatus according to claim 25, wherein the power management device is provided exclusively for one of the first to third power connection wirings and has a first power management circuit that controls the supply of power to the one power connection wiring, and a second power management circuit that is provided in common for the remaining power connection wirings of the first to third power connection wirings and controls the supply of power to the remaining power connection wiring.

27. The information processing apparatus according to claim 26, wherein the filter circuit device is provided between the second power management circuit and the remaining power connection wiring.

28. The semiconductor product includes a first external power terminal connected to the power management device, the interposer further includes eighth and ninth power connection wiring whose power supply is controlled by the power management device, at least one of the two semiconductor devices further includes an eighth power connection terminal physically independent of any of the first to third power connection terminals, a ninth power connection terminal physically independent of any of the first to third power connection terminals, an eighth power line, and a ninth power line, the first transmit / receive circuit block includes a first serializer circuit connected to the eighth power line, which converts first parallel data into first serial data based on the first clock and outputs the first serial data to the first transmit buffer circuit, and a data control circuit connected to the ninth power line, which transmits and receives fifth data with the first peripheral circuit block and performs conversion processing between the fifth data and the first parallel data, the eighth and ninth power lines are connected to the eighth and ninth power connection terminals, respectively. The information processing apparatus according to claim 25, wherein the eighth and ninth power connection wires are connected to the eighth and ninth power connection terminals of at least one of the two semiconductor devices, and at least two of the third, eighth and ninth power connection wires are connected at a first connection point near the first external power terminal, and the first connection point is connected to the first external power terminal via a first relay connection wire.

29. The information processing apparatus according to claim 28, wherein the power management device comprises at least one third power management circuit provided exclusively for one of the first and second power connection wirings and the first relay connection wiring, and for controlling the supply of power to the one connection wiring, and at least one fourth power management circuit provided in common for the first and second power connection wirings and the remaining connection wiring of the first relay connection wiring, and for controlling the supply of power to the remaining connection wiring.

30. The information processing apparatus according to claim 29, wherein the filter circuit device is provided between the fourth power management circuit and the remaining connection wiring.

31. The information processing apparatus according to claim 25, wherein the semiconductor product further includes a second external power terminal, two of the first to third power connection wirings are connected at a second connection point near the second external power terminal, and the second connection point is connected to the second external power terminal via a second relay connection wiring.

32. The information processing apparatus according to claim 31, wherein the power management device is provided exclusively for one of the connection wires among the second relay connection wiring and the first to third power connection wiring that is not connected at the second connection point, and controls the supply of power to the one connection wire; and is provided in common for the second relay connection wiring and the remaining connection wires among the first to third power connection wiring that are not connected at the second connection point, and controls the supply of power to the remaining connection wires.

33. The information processing apparatus according to claim 32, wherein the filter circuit device is provided between the sixth power management circuit and the remaining connection wiring.

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