Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor capable of preventing a crack from reaching a capacitance formation part even when a mounting substrate is bent by external force or heat.　A multilayer ceramic capacitor 1 comprises: a multilayer body 10 having a plurality of dielectric layers 20, a plurality of internal electrode layers 30, a first main surface TS1 and a second main surface TS2, a first side surface WS1 and a second side surface WS2, and a first end surface LS1 and a second end surface LS2; and an external electrode 40. The multilayer body 10 has an inner layer portion 11, and a pair of outer layer portions 14 disposed so as to sandwich the inner layer portion 11. The outer layer portions 14 have a mounting-surface-side outer layer portion 16 disposed on a mounting surface side to a mounting substrate 80. In the mounting-surface-side outer layer portion 16, a plurality of ceramic particles 21 are disposed, and inside the mounting-surface-side outer layer portion 16, short-circuit suppression gaps 70 each having a size of 10-200 nm inclusive are formed between adjacent ceramic particles 21.

Description

Multilayer ceramic capacitor

[0001] This invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, multilayer ceramic capacitors are known as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor comprises a laminate in which a plurality of dielectric layers and internal electrode layers are alternately stacked, and external electrodes provided on both end faces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, wherein the external electrodes include a base electrode layer formed by firing.

[0003] Japanese Patent Publication No. 2003-243249

[0004] However, in multilayer ceramic capacitors like the one described in Patent Document 1, if the mounting substrate on which the capacitor is mounted is deflected due to external impact or the like, cracks will occur inside due to the deflection stress of the mounting substrate. If these cracks reach the capacitance forming area formed by the opposing internal electrode layers, a short circuit failure will occur.

[0005] The purpose of this disclosure is to provide a multilayer ceramic capacitor that can prevent cracks from reaching the capacitance formation area even when the mounting substrate is bent due to external force or heat.

[0006] The multilayer ceramic capacitor according to this disclosure comprises a laminate having a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, and a pair of external electrodes arranged on the first end surface and the second end surface respectively and connected to the internal electrode layer, wherein the laminate has an inner layer portion in which the dielectric layers and the internal electrode layers are alternately stacked, and a pair of outer layer portions arranged to sandwich the inner layer portion from the first main surface side and the second main surface side, the outer layer portion having a mounting surface side outer layer portion arranged on the mounting surface side to the mounting substrate, a plurality of ceramic particles arranged on the mounting surface side outer layer portion, and a gap of 10 nm to 200 nm is formed between adjacent ceramic particles inside the mounting surface side outer layer portion.

[0007] According to this disclosure, it is possible to provide a multilayer ceramic capacitor that can prevent cracks from reaching the capacitance formation portion even when the mounting substrate is bent due to external force or heat.

[0008] This is an external inclined view of a multilayer ceramic capacitor of the first embodiment. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line II-II. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line III-III. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IVA-IVA. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IVB-IVB. This is an enlarged view of the inside of the outer layer on the mounting side. This is a schematic diagram showing cracks that occur inside the outer layer on the mounting side when mounted on a mounting substrate. This is a diagram of a double-gang multilayer ceramic capacitor. This is a diagram of a triple-gang multilayer ceramic capacitor. This is a diagram of a quadruple-gang multilayer ceramic capacitor.

[0009] The following describes a multilayer ceramic capacitor 1 according to the first embodiment of this disclosure. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 1 along the line II-II. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line III-III. Figure 4A is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line IVA-IVA. Figure 4B is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line IVB-IVB.

[0010] Furthermore, the drawings may be schematically simplified to illustrate the content of the invention, and the ratios of the dimensions of the depicted components or between components may not match the ratios of those dimensions described in the specification. In addition, components described in the specification may be omitted in the drawings, or their number may be omitted. For example, the number of internal electrode layers described in Figures 2 and 3 is 10 for the sake of explanation, but this does not represent the actual number of internal electrode layers 30. Furthermore, the terms used in this invention to specify shapes, geometric conditions, and their degree, such as terms like "parallel," "orthogonal," and "identical," as well as values ​​of length and angle, should not be interpreted strictly, but rather as including a range to which similar functionality can be expected.

[0011] The multilayer ceramic capacitor 1 comprises a laminate 10 and an external electrode 40.

[0012] Figures 1 to 4B show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T, which is the height direction of the multilayer ceramic capacitor 1 and the laminate 10, corresponds to the Z direction. Here, the cross section shown in Figure 2 is also called the LT cross section. The cross section shown in Figure 3 is also called the WT cross section. The cross sections shown in Figures 4A and 4B are also called the LW cross section.

[0013] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the lamination direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the lamination direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the lamination direction T and the width direction W.

[0014] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0015] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a pair of outer layers 14, a first main surface-side outer layer 12 and a second main surface-side outer layer 13, which are arranged to sandwich the inner layer 11 in the lamination direction T.

[0016] The inner layer 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0017] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as the above. Alternatively, the dielectric material may have minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components. The dielectric material may have BaTiO as its main component. ３ It is particularly preferable that the material contains [a specific substance].

[0018] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 10 μm or less. The number of dielectric layers 20 to be stacked is preferably 15 or more and 1200 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0019] The plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 are arranged on a plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on a plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are arranged alternately in the height direction T of the laminate 10 via the dielectric layers 20. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0020] The first internal electrode layer 31 has a first opposing portion 31A that faces the second internal electrode layer 32, and a first leading portion 31B that is drawn out from the first opposing portion 31A to the first end face LS1. The first leading portion 31B is exposed to the first end face LS1.

[0021] The second internal electrode layer 32 has a second opposing portion 32A that faces the first internal electrode layer 31, and a second leading portion 32B that is drawn out from the second opposing portion 32A to the second end face LS2. The second leading portion 32B is exposed to the second end face LS2.

[0022] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0023] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0024] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0026] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 1000 or less.

[0027] Multiple ceramic particles 21 are arranged in the outer layer 14, forming a short-circuit suppression gap 70, which will be described later.

[0028] The first main surface-side outer layer 12 is located on the side of the first main surface TS1 of the laminate 10. The first main surface-side outer layer 12 is an aggregate of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface-side outer layer 12 may be the same as the dielectric layers 20 used in the inner layer 11.

[0029] The second main surface-side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 13 is an aggregate of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0030] Thus, the laminate 10 has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20. In other words, the multilayer ceramic capacitor 1 has a laminate 10 in which the dielectric layers 20 and internal electrode layers 30 are stacked alternately.

[0031] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 4A and 4B show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion or capacitance forming portion.

[0032] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3, 4A, and 4B show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0033] Furthermore, the laminate 10 has an end face side outer layer portion. The end face side outer layer portion includes a first end face side outer layer portion LG1 and a second end face side outer layer portion LG2. The first end face side outer layer portion LG1 is a portion including the dielectric layer 20 positioned between the counter electrode portion 11E and the first end face LS1. The second end face side outer layer portion LG2 is a portion including the dielectric layer 20 positioned between the counter electrode portion 11E and the second end face LS2. FIGS. 2, 4A and 4B show the ranges in the length direction L of the first end face side outer layer portion LG1 and the second end face side outer layer portion LG2. Note that the end face side outer layer portion is also referred to as an L-gap or an end gap.

[0034] The external electrodes 40 include a first external electrode 40A disposed on the first end face LS1 side, and a second external electrode 40B disposed on the second end face LS2 side.

[0035] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed extending from the top of the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0036] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed extending from the top of the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0037] As described above, in the multilayer body 10, a capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 opposing each other with the dielectric layer 20 interposed therebetween. Therefore, capacitor characteristics are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0038] The first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A.

[0039] The second external electrode 40B includes a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0040] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. In the present embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1 and a part of the second side surface WS2.

[0041] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1 and a part of the second side surface WS2.

[0042] The first base electrode layer 50A and the second base electrode layer 50B each include at least one layer selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0043] In the present embodiment, the first base electrode layer 50A and the second base electrode layer 50B are baked layers. It is preferable that the baked layer contains either a metal component and one of a glass component or a ceramic component, or contains both of them. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, and the like. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, and the like. For the ceramic component, the same type of ceramic material as that of the dielectric layer 20 may be used, or a different type of ceramic material may be used. The ceramic component is, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ and includes at least one selected from the above.

[0044] The baked layer is formed, for example, by applying a conductive paste containing glass and metal onto a laminate and then baking the same. The baked layer may be obtained by co-firing a multilayer chip having internal electrodes and dielectric layers together with the conductive paste applied onto the multilayer chip, or may be obtained by applying the conductive paste onto the laminate and baking it after obtaining the laminate by firing the multilayer chip having internal electrodes and dielectric layers. When a multilayer chip having internal electrodes and dielectric layers and the conductive paste applied onto the multilayer chip are fired at the same time, it is preferable that the baked layer is formed by baking a material added with a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the ceramic material to be added. The baked layer may be a plurality of layers.

[0045] The thickness in the length direction of the first base electrode layer 50A located on the first end face LS1 is preferably, for example, about 10 µm or more and 150 µm or less at the central portion in the height direction T and the width direction W of the first base electrode layer 50A.

[0046] The thickness of the second base electrode layer 50B located at the second end face LS2 in the longitudinal direction is preferably, for example, 10 μm to 150 μm at the center of the height direction T and width direction W of the second base electrode layer 50B.

[0047] When the first base electrode layer 50A is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A in the height direction T provided in this part is, for example, 10 μm or more and 100 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided in this part.

[0048] When the first base electrode layer 50A is provided on a part of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness of the first base electrode layer 50A in the width direction provided in this portion is, for example, 10 μm or more and 100 μm or less at the center of the length direction L and height direction T of the first base electrode layer 50A provided in this portion.

[0049] When a second base electrode layer 50B is provided on at least one of the surfaces of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the second base electrode layer 50B in the height direction T provided in this portion is, for example, 10 μm or more and 100 μm or less at the center of the length direction L and width direction W of the second base electrode layer 50B provided in this portion.

[0050] When a second base electrode layer 50B is provided on at least one of the surfaces of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness of the second base electrode layer 50B in the width direction provided in this portion is, for example, 10 μm or more and 100 μm or less at the center of the length direction L and height direction T of the second base electrode layer 50B provided in this portion.

[0051] The first base electrode layer 50A and the second base electrode layer 50B are not limited to baked layers. For example, the first base electrode layer 50A and the second base electrode layer 50B may be thin film layers. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer of 10 μm or less in thickness on which metal particles are deposited.

[0052] The first plating layer 60A is positioned to cover the first underlay electrode layer 50A.

[0053] The second plating layer 60B is positioned to cover the second under electrode layer 50B.

[0054] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0055] The first plating layer 60A is arranged to cover the first underlay electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0056] The second plating layer 60B is arranged to cover the second under electrode layer 50B. In this embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0057] The Ni plating layer prevents the first underlay electrode layer 50A and the second underlay electrode layer 50B from being corroded by the solder used when mounting the multilayer ceramic capacitor 1. The Sn plating layer also improves the wettability of the solder used when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably between 1 μm and 15 μm.

[0058] In this embodiment, the first external electrode 40A and the second external electrode 40B may have, for example, a conductive resin layer containing a conductive filler and a thermosetting resin. When a conductive resin layer is provided as a base electrode layer (first base electrode layer 50A, second base electrode layer 50B), the conductive resin layer may be arranged to cover the baking layer, or it may be placed directly on the laminate 10 without providing a baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is placed between the baking layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baking layer, or it may cover a part of the baking layer.

[0059] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0060] The metal constituting the conductive filler may be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. The conductive filler preferably contains Ag. The conductive filler is, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as a conductive filler.

[0061] Furthermore, the conductive filler may be a metal powder with an Ag coating on its surface. When using a metal powder with an Ag coating on its surface, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy of these. It is preferable to use an Ag-coated metal powder in order to maintain the properties of Ag while making the base metal inexpensive.

[0062] Furthermore, the conductive filler may be Cu or Ni that has been treated to prevent oxidation. Alternatively, the conductive filler may be metal powder coated with Sn, Ni, or Cu on its surface. When using metal powder coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0063] The shape of the conductive filler is not particularly limited. Conductive fillers can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0064] The average particle size of the conductive filler is not particularly limited. For example, the average particle size of the conductive filler may be 0.3 μm or more and 10 μm or less.

[0065] Preferably, the conductive filler contained in the conductive resin layer is present in an amount of 35 vol% to 75 vol% relative to the total volume of the conductive resin layer.

[0066] The conductive fillers contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive fillers forms an electrical pathway within the conductive resin layer.

[0067] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0068] The conductive resin layer may be formed from multiple layers. Preferably, the thickness of the thickest part of the conductive resin layer is 10 μm or more and 200 μm or less.

[0069] It is also possible to omit the first base electrode layer 50A and the second base electrode layer 50B, and instead directly arrange the first plating layer 60A and the second plating layer 60B, as described later, on the laminate 10. In other words, the multilayer ceramic capacitor 1 may include a plating layer that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 10 as a pretreatment.

[0070] In this case as well, it is preferable that the plating layer consists of multiple layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder barrier properties. The upper plating layer is more preferably formed using Sn or Au, which has good solder wettability. For example, if the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, it is preferable that the lower plating layer be formed using Cu, which has good bonding properties with Ni. The upper plating layer may be formed as needed, and the external electrode 40 may consist only of the lower plating layer. Furthermore, the upper plating layer may be the outermost layer, or other plating layers may be formed on the surface of the upper plating layer.

[0071] The thickness of each plating layer, when placed without an undercoat electrode layer, is preferably 1 μm to 15 μm. Furthermore, the plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0072] Furthermore, when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, by reducing the thickness of the base electrode layer, the height T dimension of the multilayer ceramic capacitor 1 can be reduced, thereby making the multilayer ceramic capacitor 1 lower profile. Alternatively, by reducing the thickness of the base electrode layer, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased, thereby improving the overall thickness. In this way, by forming the plating layer directly on the laminate 10, the design flexibility of the multilayer ceramic capacitor can be improved.

[0073] Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrode 40, is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. Also, if the heightwise dimension of the multilayer ceramic capacitor 1, is denoted as dimension T, then it is preferable that dimension T is 0.1 mm or more and 5 mm or less. Also, if the widthwise dimension of the multilayer ceramic capacitor 1, is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 10 mm or less.

[0074] Next, the internal structure of the outer layer 14 in which the short-circuit suppression gap 70 is formed will be explained with reference to Figures 2, 3, 5, and 6. Figure 5 is an enlarged view of the inside of the outer layer 16 on the mounting surface side. Figure 6 is a schematic diagram showing cracks C that occur within the laminate 10 when the multilayer ceramic capacitor 1 is mounted on the mounting substrate 80.

[0075] The multilayer ceramic capacitor 1 shown in Figure 6 is joined to the electrode pads 82 of the mounting substrate 80 via solder 81. This provides a mounting structure for a multilayer ceramic capacitor comprising the mounting substrate 80 and the multilayer ceramic capacitor 1.

[0076] Inside the outer layer 14 of the laminate 10, short-circuit suppression gaps 70 are formed as gaps of 10 nm to 200 nm between adjacent ceramic particles 21.

[0077] In this embodiment, the short-circuit suppression gap 70 is formed in the mounting surface side outer layer portion 16 of the outer layer portion 14, which is located on the mounting surface side to the mounting substrate 80. For convenience, in Figures 2, 3, and 6, the dimensions of the ceramic particles 21 and the dimensions of the short-circuit suppression gap 70 are shown in an exaggerated manner compared to their actual dimensions.

[0078] In this embodiment, the second main surface TS2 of the laminate 10 and the first external electrode 40A and the second external electrode 40B arranged on the second main surface TS2 become the mounting surface to the mounting substrate 80. That is, in this embodiment, the outer layer portion 13 on the second main surface side becomes the outer layer portion 16 on the mounting surface side, and a short-circuit suppression gap 70 is formed inside the outer layer portion 13 on the second main surface side.

[0079] In this embodiment, the short-circuit suppression gap 70 is formed inside the second main surface-side outer layer portion 13, which is the mounting surface-side outer layer portion 16. However, it may also be formed inside the first main surface-side outer layer portion 12, not just the second main surface-side outer layer portion 13. In other words, the short-circuit suppression gap 70 may be formed inside both of the pair of outer layer portions 14.

[0080] In this case, when the mounting substrate 80 of the multilayer ceramic capacitor 1 mounted on the mounting substrate 80 is subjected to external impact, heat, or bending tests, bending stress in the mounting substrate 80 causes cracks to form and propagate inside the laminate 10. If these cracks reach the opposing electrode portion 11E, which is a capacitance forming portion formed by the opposing internal electrode layers 30, a short circuit failure occurs. With the multilayer ceramic capacitor 1 of this disclosure, the propagation of cracks to the opposing electrode portion 11E can be suppressed by having a short-circuit suppression gap 70 formed inside the outer layer portion 16 on the mounting surface side.

[0081] The ceramic particles 21 will now be described. The ceramic particles 21 are particles that form the dielectric layer 20 and are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as the above. Alternatively, the dielectric material may have minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components. The dielectric material may have BaTiO as its main component. ３ It is particularly preferable that the material contains [a specific substance].

[0082] The dimensions of the ceramic particles 21 are preferably 20 nm to 300 nm. The shape of the ceramic particles 21 is not particularly limited and may be, for example, polyhedral.

[0083] The configuration of the short-circuit suppression gap 70 will now be explained. The size of the short-circuit suppression gap 70 is between 10 nm and 200 nm. If the gap between adjacent ceramic particles 21 is less than 10 nm, the direction of crack propagation cannot be controlled. On the other hand, if the size of the gap between adjacent ceramic particles 21 exceeds 200 nm, the ceramic particles 21 may detach or long gaps may occur in the lamination direction T. As a result, there is a risk that cracks may reach the counter electrode portion 11E. In addition, moisture may easily enter the laminate 10, potentially worsening its moisture resistance.

[0084] The size of the short-circuit suppression gap 70 is preferably 10 nm or more and 100 nm or less.

[0085] The short-circuit suppression gap 70 has a parallel portion 71 and an inclined portion 72. As shown in Figure 5, the parallel portion 71 is the portion of the short-circuit suppression gap 70 that is parallel to the main surface on the mounting surface side outer layer portion 16, that is, the portion parallel to the second main surface TS2 in this embodiment. In other words, the parallel portion 71 is the portion of the short-circuit suppression gap 70 that is parallel to the length direction L.

[0086] The inclined portion 72 is the portion that is inclined with respect to the main surface on the mounting surface side outer layer portion 16 side of the short-circuit suppression gap 70, that is, the second main surface TS2 in this embodiment. In other words, the inclined portion 72 is the portion that is inclined with respect to the length direction L of the short-circuit suppression gap 70. The inclined portion 72 and the parallel portion 71 may be formed continuously with respect to each other.

[0087] The short-circuit suppression gap 70 may have vertical portions in addition to the parallel portions 71 and inclined portions 72. The vertical portions are the parts of the short-circuit suppression gap 70 that are perpendicular to the first main surface TS1 and the second main surface TS2. In this case, it is preferable that the volume occupied by the parallel portions 71 is larger than the volume occupied by the vertical portions of the short-circuit suppression gap 70. This makes it easier for cracks that occur in the outer layer portion 16 on the mounting surface side to propagate in a direction parallel to the second main surface TS2 rather than in the stacking direction T. Therefore, it is possible to more reliably prevent cracks from reaching the inner layer portion 11.

[0088] Multiple short-circuit suppression gaps 70 may be formed in the stacking direction T from the second main surface TS2, which is the main surface on the mounting surface side outer layer portion 16, to the inner layer portion 11 side by a predetermined thickness. For example, multiple short-circuit suppression gaps 70 may be formed to half the thickness from the second main surface TS2 to the inner electrode layer 30 located closest to the second main surface TS2 in the stacking direction T. In this case, the size of the short-circuit suppression gaps 70 may be configured to decrease as you move from the second main surface TS2 side to the inner layer portion 11 side inside the mounting surface side outer layer portion 16. Also, the number of short-circuit suppression gaps 70 may be configured to decrease as you move from the second main surface TS2 side to the inner layer portion 11 side inside the mounting surface side outer layer portion 16. This makes it possible to more reliably prevent cracks from reaching the opposing electrode portion 11E.

[0089] Here, as shown in Figure 6, cracks C tend to originate relatively frequently from the boundary E between the portion of the main surface on the mounting surface side outer layer portion 16 that is exposed to the outside and the portion covered by the external electrode 40. In this embodiment, the boundary E is, as shown in Figure 2, the boundary E1 between the portion of the second main surface TS where the first external electrode 40A is located and the portion where it is not located, and the boundary E2 between the portion of the second main surface TS where the second external electrode 40B is located and the portion where it is not located.

[0090] It is preferable that the multiple short-circuit suppression gaps 70 are formed in a region where the external electrode 40 and the opposing electrode portion 11E overlap when viewed from the stacking direction T.

[0091] As shown in Figure 2, it is preferable that the multiple short-circuit suppression gaps 70 are formed in the length direction L, at least from boundary E1 to the end of the opposing electrode portion 11E on the first external electrode 40A side, and from boundary E2 to the end of the opposing electrode portion 11E on the second external electrode 40B side. This makes it difficult for cracks C to reach the opposing electrode portion 11E, as they extend in the length direction L inside the outer layer portion 16 on the mounting surface side where the short-circuit suppression gaps 70 are formed. As shown in Figure 3, it is preferable that the multiple short-circuit suppression gaps 70 are formed in the width direction W, at least over the portion where the opposing electrode portion 11E is located. That is, it is preferable that the multiple short-circuit suppression gaps 70 are formed in the width direction W, at least from the end of the opposing electrode portion 11E on the first side surface WS1 side to the end on the second side surface WS2 side.

[0092] The short-circuit suppression gap 70 is preferably formed near the external electrode 40 located on the second main surface TS2 side within the outer layer portion 16 on the mounting surface side. As shown in Figure 6, cracks C are relatively likely to originate from the boundary E between the portion of the second main surface TS, which is the mounting surface, that is exposed to the outside and the portion covered by the external electrode 40. Therefore, the extension of cracks C to the opposing electrode portion 11E can be suppressed more efficiently.

[0093] In this embodiment, multiple short-circuit suppression gaps 70 are formed inside the outer layer portion 16 on the mounting surface side. Preferably, the multiple short-circuit suppression gaps 70 are formed along the entire direction of the LW plane parallel to the length direction L and the width direction W, that is, along the entire plane direction of the first main surface TS1 and the second main surface TS2. This makes it possible to more reliably prevent cracks C from reaching the opposing electrode portion 11E.

[0094] The short-circuit suppression gap 70 may be formed near both the first external electrode 40A and the second external electrode 40B on the second main surface TS2 side within the mounting surface side outer layer 16, or it may be formed near either one of them.

[0095] The mounting surface side outer layer portion 16 has an inner layer side outer layer portion 161 and an outer surface side outer layer portion 162, and the gap between adjacent ceramic particles 21 in the outer surface side outer layer portion 162 may be larger than the gap between adjacent ceramic particles 21 in the inner layer side outer layer portion 161.

[0096] The gaps between adjacent ceramic particles 21 in the outer layer portion 162 on the outer surface side are preferably 10 nm to 200 nm, and the gaps between adjacent ceramic particles 21 in the outer layer portion 161 on the inner layer side are smaller than this.

[0097] The outer surface-side outer layer portion 162 refers to the outer surface side (mounting surface side, second main surface TS2 side) portion of the mounting surface-side outer layer portion 16. When measuring the gap between ceramic particles 21 in the outer surface-side outer layer portion 162, the measurement is taken in the LT cross section at the end side in the longitudinal direction L of the opposing electrode portion 11E and in the region closest to the second main surface TS2. In order to prevent the crack C from extending to the opposing electrode portion 11E, it is important that a short-circuit suppression gap 70 is formed in this region so that the vicinity of this region becomes the crack propagation path.

[0098] The inner layer side outer layer portion 161 refers to the portion of the mounting surface side outer layer portion 16 that is on the inner layer portion 11 side. When measuring the gap between ceramic particles 21 in the inner layer side outer layer portion 161, the measurement is taken in the LT cross-section, at the end side in the longitudinal direction L of the opposing electrode portion 11E, and in the region closest to the inner layer portion 11.

[0099] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described.

[0100] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known substances.

[0101] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0102] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer portion 12 on the first main surface TS1 side. On top of this, dielectric sheets with printed patterns for the first internal electrode layer 31 and dielectric sheets with printed patterns for the second internal electrode layer 32 are sequentially stacked to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer portion 13 on the second main surface TS2 side. This completes the production of the laminated sheet.

[0103] Laminated sheets are pressed in the height direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0104] The laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0105] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0106] When a laser is irradiated onto the outer layer 14 of the laminate 10 after firing, the heat causes the glass components remaining at the grain boundaries to move, creating nano-order gaps between adjacent ceramic particles 21 within the outer layer 14. The size of the gaps is controlled by the laser output.

[0107] A conductive paste, which will form the base electrode layers (first base electrode layer 50A, second base electrode layer 50B), is applied to both end faces of the laminate 10. In this embodiment, the base electrode layers are baked layers. A conductive paste containing glass components and metal is applied to the laminate 10 by methods such as dipping or screen printing. A baking process is then performed to form the base electrode layers. The temperature of this baking process is preferably 700°C to 900°C.

[0108] Furthermore, when firing the laminated chip before firing and the conductive paste applied to the laminated chip simultaneously, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminate 10 with a baked layer.

[0109] Subsequently, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0110] When forming the base electrode layer as a thin film layer, masking or other methods are used to form the thin film layer as the base electrode layer in the area where the external electrode is to be formed. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer of metal particles deposited on it that is 1.0 μm or less in thickness.

[0111] When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be arranged to cover the baking layer, or it may be placed directly on the laminate 10 without providing a baking layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and metal components is applied to the baking layer or the laminate 10, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to heat-cur, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0112] Alternatively, the plating layer may be directly placed on the exposed portion of the internal electrode layer 30 of the laminate 10 without providing a base electrode layer. In this case, the first end face LS1 and the second end face LS2 of the laminate 10 are plated, and the plating layer is formed on the exposed portion of the internal electrode layer 30. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, electrolytic plating is generally preferred. Barrel plating is preferred as the plating method. Furthermore, if necessary, the upper plating layer formed on the surface of the lower plating layer may be formed using the same method as the lower plating layer.

[0113] Through this manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0114] Note that the configuration of the laminated structure 10 of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 6. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 7A, 7B, and 7C.

[0115] The multilayer ceramic capacitor 1 shown in Figure 7A is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 7B is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 7C is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0116] The multilayer ceramic capacitor 1 of this embodiment provides the following effects.

[0117] (1) The multilayer ceramic capacitor 1 according to this embodiment has a plurality of stacked dielectric layers 20 and a plurality of stacked internal electrode layers 30, and a laminate 10 having a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W, and a pair of external electrodes 40 arranged on the first end surface LS1 and the second end surface LS2 respectively and connected to the internal electrode layer 30. A multilayer ceramic capacitor 1 comprises a laminate 10 having an inner layer portion 11 in which dielectric layers 20 and internal electrode layers 30 are alternately laminated, and a pair of outer layer portions 14 arranged to sandwich the inner layer portion 11 from the first main surface TS1 side and the second main surface TS2 side, the outer layer portion 14 having a mounting surface side outer layer portion 16 arranged on the mounting surface side to the mounting substrate 80, a plurality of ceramic particles 21 arranged on the mounting surface side outer layer portion 16, and short-circuit suppression gaps 70 of 10 nm to 200 nm are formed inside the mounting surface side outer layer portion 16 between adjacent ceramic particles 21.

[0118] This creates gaps of 10 nm to 200 nm between adjacent ceramic particles 21 within the outer layer 16 on the mounting surface side, preventing cracks from reaching the capacitance formation area even if the mounting substrate 80 is bent due to external force or heat. Furthermore, since the gaps between adjacent ceramic particles 21 are 200 nm or less, which makes it difficult for moisture to enter, moisture resistance can also be maintained. Thus, it is possible to prevent short-circuit failures while ensuring moisture resistance.

[0119] (2) In the multilayer ceramic capacitor 1 according to this embodiment, the short-circuit suppression gap 70 has a parallel portion 71 which is parallel to at least the main surface on the mounting surface side outer layer portion 16 side of the first main surface TS1 and the second main surface TS2, and an inclined portion 72 which is inclined with respect to at least the main surface on the mounting surface side outer layer portion 16 side of the first main surface TS1 and the second main surface TS2.

[0120] As a result, even if cracks occur and propagate inside the laminate 10 due to the flexural stress of the mounting substrate 80, the propagation of the cracks can be guided in a direction along the inclined portion 72 and parallel portion 71 of the short-circuit suppression gap 70 between the ceramic particles 21. In other words, the propagation of cracks can be controlled in a direction parallel to and inclined to the first main surface TS1 and the second main surface TS2 on the mounting surface side outer layer portion 16. Therefore, it is possible to more reliably prevent cracks from reaching the volume-forming portion.

[0121] (3) In the multilayer ceramic capacitor 1 according to this embodiment, the external electrodes 40 are also arranged on a part of the first main surface TS1 and a part of the second main surface TS2, and the short-circuit suppression gap 70 is formed near the external electrodes 40 arranged on the main surface of the first main surface TS1 and the second main surface TS2 on the mounting surface side outer layer portion 16.

[0122] As a result, cracks are relatively likely to originate from the boundary between the portion of the main surface on the mounting surface side outer layer portion 16 that is exposed to the outside and the portion that is covered by the external electrode 40, thus more efficiently suppressing the arrival of cracks in the capacitance forming portion.

[0123] (4) In the multilayer ceramic capacitor 1 according to this embodiment, the external electrode 40 includes a first external electrode 40A having a first base electrode layer 50A disposed on at least a first end face LS1 and a first plating layer 60A disposed on the outer surface side of the first base electrode layer 50A, and a second external electrode 40B having a second base electrode layer 50B disposed on at least a second end face LS2 and a second plating layer 60B disposed on the outer surface side of the second base electrode layer 50B.

[0124] As a result, the effects of this disclosure can be obtained even with such a multilayer ceramic capacitor 1.

[0125] <Experimental Examples> Next, we will describe experimental examples performed on the multilayer ceramic capacitor 1 according to this embodiment. In these experimental examples, deflection tests and moisture resistance tests were conducted.

[0126] According to the manufacturing method described in the above embodiment, samples were manufactured in lots as the samples for Examples 1 to 4 and Comparative Examples 1 and 2, with the manufacturing conditions adjusted so that the size of the gap between adjacent ceramic particles 21 inside the outer layer 16 on the mounting surface differed. The samples within each lot were manufactured under the same manufacturing conditions. The dimensions of the multilayer ceramic capacitors in Examples 1 to 4 and Comparative Examples 1 and 2 are L dimension 3.41 mm, W dimension 2.58 mm, and T dimension 2.52 mm. The dielectric material is BaTiO ３ The following was used. Each sample had a capacitance of 22 μF, and the internal electrode was Ni. The sample for Comparative Example 1 was one that had not undergone laser treatment after firing. The sample for Comparative Example 2 was prepared by increasing the laser output after firing.

[0127] For each example and comparative example, five samples (n=5) for measuring the gaps between adjacent ceramic particles 21, fifty samples (n=50) for deflection testing, and fifty samples (n=50) for moisture resistance testing were prepared from the same lot. For measuring the gaps between adjacent ceramic particles 21, the average value of the measurement results was used for evaluation. The specific test results for each example and comparative example are described in Table 1 below.

[0128] <Deflection Test> Multilayer ceramic capacitors 1, which were samples from Examples 1 to 4 and Comparative Examples 1 and 2, were mounted on a mounting substrate using solder paste. However, for samples with resin electrodes, the side with the resin electrodes was defined as the mounting surface. The thickness of the mounting substrate 80 was 1.6 mm. Then, a push rod with a diameter of 5 μm was pressed against the side of the mounting substrate opposite to the mounting surface to bend the substrate. The substrate was held in the bent state for 5 seconds. The amount of bending of the mounting substrate was 8.0 mm.

[0129] <Short Circuit Failure Determination> After the deflection test, 2.5V was applied to the sample using a tester, and a reading of 100Ω or less was determined to be a short circuit. Samples with zero short circuits were judged as "○", and samples with even one short circuit were judged as "×".

[0130] <Method for Measuring Gap> The multilayer ceramic capacitors used as samples in Examples 1 to 4 and Comparative Examples 1 and 2 were polished in a cross-section parallel to the length direction L and the stacking direction T, up to the center in the width direction W. The cross-section of the outer layer 16 on the mounting surface side, exposed by polishing, was observed using an SEM (Scanning Electron Microscope). Specifically, an SEM image of the outer layer 16 on the mounting surface side was taken at a magnification of 5000x and an acceleration voltage of 5kV. The average value of the gap between adjacent ceramic particles 21 in the captured SEM image was taken as the gap between ceramic particles 21 in that sample.

[0131] More specifically, the average value of the gap between adjacent ceramic particles 21 is calculated as follows.

[0132] First, the contour of each ceramic particle 21 is extracted by image processing, and the cross-section of each ceramic particle 21 is defined. Then, the centroid position of the cross-section of each ceramic particle 21 is determined, and a straight line (for example, the straight line D1 shown in Figure 5) is drawn connecting the centroids of adjacent ceramic particles 21. The distance between the contours of adjacent ceramic particles 21 on this straight line is defined as the gap between the ceramic particles 21 (for example, the gap D2 shown in Figure 5). The same process is performed between all adjacent ceramic particles 21 observed in the SEM image, and the average value of the resulting gaps between ceramic particles 21 is defined as the gap of the sample. As the gap between adjacent ceramic particles 21 inside the outer layer portion 16 on the mounting surface side, the region closest to the second main surface TS2 (for example, region A shown by the dashed line in Figure 2) is measured in the LT cross-section, which is on the end side in the length direction L of the opposing electrode portion 11E.

[0133] <Method of Humidity Resistance Test and Criteria for Judging Humidity Resistance Failure> Humidity resistance tests were conducted on samples from Examples 1 to 4 and Comparative Examples 1 and 2 based on the PCBT test method. More specifically, each sample was mounted on a wiring board using eutectic solder, placed in a high-temperature, high-humidity chamber at a temperature of 125°C and a relative humidity of 95%RH, and a DC current of 8V was applied between a pair of external electrodes. This condition was maintained for 72 hours. Samples whose insulation resistance value did not decrease by two orders of magnitude or more before and after the test were judged as "○", and samples whose insulation resistance value decreased by two orders of magnitude or more before and after the test were judged as "×". Samples with zero humidity resistance failures were judged as "○", and samples with even one humidity resistance failure were judged as "×".

[0134]

[0135] Table 1 shows the gap measurement results, short-circuit failure judgment results, moisture resistance failure judgment results, and overall judgment results for Examples 1 to 4 and Comparative Examples 1 and 2. In the overall judgment, if both the short-circuit failure judgment and moisture resistance failure judgment results were "○", the result was "○", and if either the short-circuit failure judgment or moisture resistance failure judgment was "×", the result was "×".

[0136] According to Table 1, in the case of samples from Examples 1 to 4, where the gap between adjacent ceramic particles 21 was between 10 nm and 200 nm, no short-circuit failures or moisture resistance failures occurred. On the other hand, in the case of Comparative Example 1, where the gap between adjacent ceramic particles 21 was less than 10 nm (5 nm), short-circuits occurred in 13 out of 50 samples, and moisture resistance failures were also confirmed. The moisture resistance failures are thought to be due to cracks occurring in the laminate when the samples were mounted on the substrate and placed in a high-temperature, high-humidity layer. Furthermore, when the gap between adjacent ceramic particles 21 was greater than 200 nm (500 nm), no short-circuit failures occurred, but moisture resistance failures occurred in all 50 samples.

[0137] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0138] 1 Multilayer ceramic capacitor 10 Laminate 11 Inner layer 12 First main surface side outer layer 13 Second main surface side outer layer 14 Outer layer 16 Mounting surface side outer layer 20 Dielectric layer 21 Ceramic particles 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 40 External electrode 40A First external electrode 40B Second external electrode 70 Short circuit suppression gap 80 Mounting substrate L Length direction LS1 First end face LS2 Second end face T Lamination direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface

Claims

1. A multilayer ceramic capacitor comprising: a laminate having a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction; and a pair of external electrodes arranged on the first end surface and the second end surface and connected to the internal electrode layer, wherein the laminate has an inner layer portion in which the dielectric layers and the internal electrode layers are alternately stacked, and a pair of outer layer portions arranged to sandwich the inner layer portion from the first main surface side and the second main surface side, the outer layer portion having a mounting surface side outer layer portion arranged on the mounting surface side to the mounting substrate, a plurality of ceramic particles arranged on the mounting surface side outer layer portion, and gaps of 10 nm to 200 nm between adjacent ceramic particles formed inside the mounting surface side outer layer portion.

2. The multilayer ceramic capacitor according to claim 1, wherein the gap has a parallel portion parallel to at least the main surface on the mounting surface side of the first main surface and the second main surface, and an inclined portion inclined with respect to at least the main surface on the mounting surface side of the first main surface and the second main surface.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the external electrodes are also arranged on a part of the first main surface and a part of the second main surface, and the gap is formed near the external electrodes arranged on the main surface on the mounting surface side of the first main surface and the second main surface.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the external electrode comprises: a first external electrode having a first base electrode layer disposed on at least the first end face and a first plating layer disposed on the outer surface side of the first base electrode layer; and a second external electrode having a second base electrode layer disposed on at least the second end face and a second plating layer disposed on the outer surface side of the second base electrode layer.

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