Semiconductor device

Abstract

This semiconductor device includes: a semiconductor substrate; a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film; a second layer formed on a layer above the first layer and including a second insulating film and a channel formed of an oxide semiconductor; and a third layer formed on a layer above the second layer and including a third insulating film. The oxide semiconductor has a bixbyite structure.

Description

semiconductor devices

[0001] This invention relates to a semiconductor device. Specifically, this invention relates to a semiconductor device that has excellent operational stability and a high degree of freedom in its manufacturing process.

[0002] A semiconductor device has been proposed (Patent Document 1) comprising a semiconductor substrate, a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film, a second layer formed above the first layer and including a channel formed from an oxide semiconductor and a second insulating film, and a third layer formed above the second layer and including an electrode formed on the channel and a third insulating film. Here, as the oxide semiconductor, an oxide (IGZO) containing indium (In), gallium (Ga), and zinc (Zn) is used, and the third insulating film has a film density smaller than at least one of the film density of the first insulating film and the film density of the second insulating film. This promotes the supply of oxygen to the second layer oxide semiconductor (IGZO) which requires oxygen, and suppresses the supply of oxygen to the first layer semiconductor element which does not require oxygen.

[0003] Japanese Patent Publication No. 2024-25325

[0004] However, in the technology described in Patent Document 1, by reducing the film density of the third insulating film, not only oxygen but also hydrogen becomes more permeable through the third insulating film, and there is a concern that hydrogen will be supplied to the second layer oxide semiconductor (IGZO), making transistors equipped with the oxide semiconductor more prone to malfunction. Furthermore, forming the first to third insulating films to satisfy predetermined film density conditions impairs the freedom of the semiconductor device manufacturing method.

[0005] One of the objectives of the present invention is to provide a semiconductor device that exhibits excellent operational stability and high flexibility in its manufacturing process.

[0006] As a result of intensive studies, the present inventors have found that by forming an oxide semiconductor having a bixbyite structure as the oxide semiconductor, a semiconductor device excellent in operational stability and having a high degree of freedom in manufacturing method can be provided, and have completed the present invention. According to the present invention, the following semiconductor device can be provided. 1. A semiconductor device comprising: a semiconductor substrate; a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film; a second layer formed above the first layer and including a channel formed of an oxide semiconductor and a second insulating film; and a third layer formed above the second layer and including a third insulating film, wherein the oxide semiconductor has a bixbyite structure. 2. The semiconductor device according to 1, wherein when the hydrogen concentration of the insulating film having a higher hydrogen concentration among the second insulating film and the first insulating film is C ｍａｘ , and the hydrogen concentration of the insulating film having a lower hydrogen concentration is C ｍｉｎ , C ｍａｘ is 1.1 times or more that of C ｍｉｎ . 3. The semiconductor device according to 1 or 2, wherein when the hydrogen concentration of the insulating film having a higher hydrogen concentration among the second insulating film and the first insulating film is C ｍａｘ , and the hydrogen concentration of the insulating film having a lower hydrogen concentration is C ｍｉｎ , C ｍａｘ is 100 times or less that of C ｍｉｎ . 4. The semiconductor device according to any one of 1 to 3, wherein when the hydrogen concentration of the insulating film having a higher hydrogen concentration among the second insulating film and the third insulating film is C ｍａｘ , and the hydrogen concentration of the insulating film having a lower hydrogen concentration is C ｍｉｎ , C ｍａｘ is 1.1 times or more that of C ｍｉｎ . 5. When the hydrogen concentration of the insulating film having a higher hydrogen concentration among the second insulating film and the third insulating film is C ｍａｘ , and the hydrogen concentration of the insulating film having a lower hydrogen concentration is C ｍｉｎ , C ｍａｘ is C ｍｉｎA semiconductor device according to any one of 1 to 4, wherein the hydrogen concentration is 100 times or less. 6. A semiconductor device according to any one of 1 to 5, further comprising a fourth layer formed between the first layer and the second layer, the fourth layer including a capacitor and a fourth insulating film. 7. The hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the fourth insulating film is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ A semiconductor device as described in 6, which is 1.1 times or more. 8. The hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the fourth insulating film is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ A semiconductor device according to 6 or 7, wherein the hydrogen concentration of the second insulating film is 1 × 10⁻⁶. １８ atoms / cm ３ ~1 x 10 ２２ toms / cm ３A semiconductor device according to any one of 1 to 8. 10. A semiconductor device according to any one of 1 to 9, wherein the third insulating film has the highest film density among the first insulating film, the second insulating film, and the third insulating film. 11. A semiconductor device according to any one of 6 to 8, wherein the third insulating film has the highest film density among the first insulating film, the second insulating film, the third insulating film, and the fourth insulating film. 12. A semiconductor device according to any one of 1 to 11, wherein the transistor having the channel comprises: a first electrode, and a second electrode; the oxide semiconductor connecting the first electrode and the second electrode; and a third electrode adjacent to the oxide semiconductor without contact with it. 13. A semiconductor device according to 12, wherein one of the first electrode and the second electrode is arranged on the first layer side and the other is arranged on the third layer side. 14. A semiconductor device according to 12 or 13, wherein the oxide semiconductor connects the first electrode and the second electrode by at least partially penetrating the second insulating film. 15. A semiconductor device according to any one of 12 to 14, further comprising a third electrode-oxide semiconductor insulating film provided between the third electrode and the oxide semiconductor. 16. A semiconductor device according to any one of 12 to 14, wherein the oxide semiconductor is provided in a columnar shape penetrating the second insulating film and the third electrode, and further comprising a third electrode-oxide semiconductor insulating film provided between the third electrode and the oxide semiconductor, wherein the third electrode-oxide semiconductor insulating film is provided so as to surround at least a part of the columnar oxide semiconductor. 17. A semiconductor device according to any one of 12 to 14, wherein the first electrode and the second electrode are stacked via the second insulating film, the oxide semiconductor has a tubular portion provided penetrating the second insulating film, and further comprising a third electrode-oxide semiconductor insulating film provided between the third electrode and the oxide semiconductor, wherein the third electrode-oxide semiconductor insulating film has a tubular portion provided on the inner wall of the tubular portion of the oxide semiconductor, and the third electrode has a portion provided inside the tubular portion of the third electrode-oxide semiconductor insulating film.18. A semiconductor device according to any one of 1 to 17, wherein the channel length of the oxide semiconductor is 1 to 1000 nm. 19. A semiconductor device according to any one of 1 to 18, wherein the oxide semiconductor is mainly composed of indium oxide. 20. A semiconductor device according to any one of 1 to 19, wherein the ratio of indium atoms to all metal atoms contained in the oxide semiconductor is 80 atomic% or more. 21. A semiconductor device according to any one of 1 to 20, wherein the indium oxide content in the oxide semiconductor is 55 mass% or more. 22. A semiconductor device according to any one of 18 to 21, wherein the oxide semiconductor further comprises Ga or Al. 23. A semiconductor device according to any one of 18 to 21, wherein the oxide semiconductor further comprises Ga. 24. A semiconductor device according to any one of 18 to 21, wherein the oxide semiconductor further comprises Ga and Al. 25. A semiconductor device according to any one of 1 to 24, wherein the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) is 0.5 to 25 at%. 26. A semiconductor device according to any one of 1 to 25, wherein the atomic ratio of Zn to all metal elements contained in the oxide semiconductor ([Zn] / ([Zn] + [all metal elements other than Zn]) × 100) is 0 to 3 at%. 27. A semiconductor device according to any one of 1 to 26, wherein the oxide semiconductor substantially does not contain Zn. 28. A semiconductor device according to any one of 1 to 27, wherein the oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition. 29. A semiconductor device according to any one of 1 to 28, which is a semiconductor memory device. 30. The device comprises: a semiconductor substrate; a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film; a second layer formed above the first layer and including a channel and a second insulating film made of an oxide semiconductor; and a third layer formed above the second layer and including a third insulating film, wherein the hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the first insulating film is C. ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎThe hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the third insulating film is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ A semiconductor device having a channel of 1.1 times or more and 100 times or less, wherein the transistor comprising the channel comprises a first electrode and a second electrode, an oxide semiconductor connecting the first electrode and the second electrode, and a third electrode adjacent to the oxide semiconductor without contact, wherein one of the first electrode and the second electrode is arranged on the first layer side and the other is arranged on the third layer side, the oxide semiconductor is mainly composed of indium oxide and has a bigx-byte structure, and the atomic ratio of Zn to all metal elements contained in the oxide semiconductor ([Zn] / ([Zn] + [all metal elements other than Zn]) × 100) is 0 to 3 at%.

[0007] According to the present invention, it is possible to provide a semiconductor device that has excellent operational stability and a high degree of freedom in its manufacturing process.

[0008] This is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to one embodiment. This is a schematic perspective view showing a cross-section of a transistor according to the first embodiment. This is a schematic cross-sectional view of a transistor according to the first embodiment. This is a diagram illustrating an example of a method for manufacturing a transistor according to the first embodiment. This is a schematic perspective view showing a cross-section of a transistor according to the second embodiment. This is a schematic cross-sectional view of a transistor according to the second embodiment. This is a schematic perspective view showing a cross-section of a transistor according to the third embodiment. This is a diagram showing an example of the circuit configuration of a semiconductor memory device. This is a graph showing the hydrogen concentration of each insulating layer in the examples and comparative examples.

[0009] The transistors and semiconductor devices of the present invention will be described in detail below. In this specification, "x to y" represents a numerical range of "x or more, and y or less". The upper and lower limits described for the numerical range can be combined in any way. Furthermore, it is possible to combine two or more non-conflicting embodiments of the embodiments of the present invention described below, and an embodiment that combines two or more embodiments is also an embodiment of the embodiments of the present invention.

[0010] A semiconductor device according to one aspect of the present invention comprises: a semiconductor substrate; a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film; a second layer formed above the first layer and including a channel formed from an oxide semiconductor and a second insulating film; and a third layer formed above the second layer and including a third insulating film, wherein the oxide semiconductor has a Bix-byte structure. The semiconductor device according to this aspect provides excellent operational stability and a high degree of freedom in the manufacturing process. More specifically, the semiconductor device according to this aspect has a Bix-byte structure in the oxide semiconductor. Because the hydrogen diffusion rate of an oxide semiconductor having a Bix-byte structure is slow, the channel formed from the oxide semiconductor is less susceptible to the influence of hydrogen. Therefore, even if there is a large variation in the hydrogen concentration of the first to third insulating films, the operation of the semiconductor device can be stabilized. Furthermore, since variation in the hydrogen concentration of the first to third insulating films is permissible, it is not necessarily required to control the film density of the insulating films as described in Patent Document 1 during the manufacturing process. Therefore, the semiconductor device according to this aspect has a high degree of freedom in the manufacturing process. Furthermore, since oxide semiconductors having a bixbite structure are less prone to oxygen desorption, oxygen supply to the oxide semiconductor, as described in Patent Document 1, is not necessarily required during the manufacturing process.

[0011] In one embodiment, the semiconductor device is a semiconductor memory device, specifically a DRAM (Dynamic Random Access Memory). The DRAM is configured to include a memory cell array consisting of a plurality of memory cells. Each memory cell comprises a field-effect transistor (hereinafter also simply referred to as "transistor") and a capacitor. The memory cells are arranged in a matrix direction to form a memory cell array. However, multiple memory cells may be arranged not only in the matrix direction but also in the vertical direction. The gate electrodes of the transistors constituting the memory cells are connected to the corresponding word lines, and one of the source electrode or drain electrode is connected to one electrode of the capacitor, while the other is connected to the corresponding bit line. One electrode of the capacitor may be configured to supply charge by being connected to one electrode of the transistor as described above. The other electrode of the capacitor may be connected to a power line that supplies a predetermined potential. The memory cell is configured to hold data by accumulating charge from the bit line to the capacitor through switching of the transistor via the word line.

[0012] Figure 1 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to one embodiment. Here, the case where the semiconductor device is a DRAM is shown. The semiconductor device 100 comprises a semiconductor substrate 101, a first layer 1 formed on the semiconductor substrate 101, a second layer 2 formed above the first layer 1, and a third layer 3 formed above the second layer 2. The semiconductor device 100 also further comprises a fourth layer between the first layer 1 and the second layer.

[0013] (Semiconductor substrate 101) The semiconductor substrate 101 is a substrate formed from, for example, single-crystal silicon.

[0014] (First Layer 1) The first layer 1 includes a semiconductor element 11 and a first insulating film 10. The first layer 1 further includes a lower capacitor electrode 12. The semiconductor element 11 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) formed on a semiconductor substrate 101, but it may be any other semiconductor element. Unlike the transistor 21, the semiconductor element 11 may have a channel made of silicon, for example. The semiconductor element 11 constitutes a semiconductor integrated circuit made of CMOS (Complementary Metal-Oxide-Semiconductor) for controlling a memory cell array. The first insulating film 10 is an insulator formed in layers on the semiconductor substrate 101. By being formed in the same layer as the semiconductor element 11, the first insulating film 10 electrically insulates the semiconductor element 11 and the wiring (conductors, etc.) connecting them.

[0015] (Fourth Layer 4) The fourth layer 4 includes a capacitor 41 and a fourth insulating film 40. The capacitor 41 in this embodiment is a three-dimensional capacitor such as a so-called pillar-type capacitor or a cylinder-type capacitor. The capacitor 41 comprises a capacitor structure 42 included in the fourth layer 4 and a lower capacitor electrode 12 included in the first layer 1, and is configured to store charge between the lower electrode (source electrode or drain electrode) of the transistor 21 and the lower capacitor electrode 12. The capacitor structure 42 may be a known configuration that includes a dielectric and is capable of storing electricity and functions as a capacitor. The fourth insulating film 40 is an insulator that electrically insulates the capacitors 41 from each other in the fourth layer where the capacitor 41 is formed.

[0016] (Second Layer 2) The second layer 2 includes a channel formed from an oxide semiconductor (in Figure 2, the transistor 21 having the channel is schematically shown as a rectangle) and a second insulating film 20. The oxide semiconductor has a bigx-byte structure. The second layer 2 also further includes wiring 22. The transistor 21 comprises an oxide semiconductor, a first electrode, a second electrode, and a third electrode (all not shown in Figure 2). One of the first and second electrodes functions as a source electrode, and the other functions as a drain electrode. The third electrode functions as a gate electrode. One of the first and second electrodes may be located on the first layer 1 side, and the other on the third layer 3 side. The transistor 21 may further include a third electrode-oxide semiconductor insulating film (not shown in Figure 2) provided between the third electrode and the oxide semiconductor. The transistor 21 is a component of the memory cell. In the example in Figure 2, four transistors 21 are shown. The number of transistors 21 can be arbitrarily changed according to the number of capacitors 41. One of the first and second electrodes of the transistor 21 may be positioned as a lower electrode at the bottom of the transistor 21 (above the capacitor structure 42) and electrically connected to the capacitor structure 42. The other of the first and second electrodes, or the third electrode, may be positioned as an upper electrode at the top of the transistor 21. All of the first, second, and third electrodes of the transistor 21 may be formed in the second layer 2, or one or more of these electrodes may be formed in a layer other than the second layer 2 (for example, the fourth layer 4 and / or the third layer 3). For example, the lower electrode of the transistor 21 may be formed in the second layer 2 or the fourth layer 4. Also, the upper electrode of the transistor 21 may be formed in the second layer 2 or the third layer 3. At least a portion of the oxide semiconductor is included in the second layer 2 and is formed to connect the first electrode and the second electrode, forming the channel of the transistor 21. The second insulating film 20 is an insulator provided in the second layer 2 of the transistor 21, which includes the oxide semiconductor. The oxide semiconductor may connect the first electrode and the second electrode by at least partially penetrating the second insulating film 20.

[0017] (Third Layer 3) The third layer 3 includes a third insulating film 30. The third layer 3 further includes wiring 31. The third insulating film 30 is an insulator that electrically insulates the wiring 31 from each other. One of the wirings 22 and 31 is connected to the gate electrode of the transistor 21 (the third electrode described later) and functions as a word line in the memory cell, while the other is connected to the source electrode or drain electrode of the transistor 21 (the first electrode or second electrode described later) and functions as a bit line. Each of the wirings 22 and 31 may be made of a conductor such as tungsten (W), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and tungsten (W). The word line may also serve as the gate electrode. Furthermore, a metal layer serving as a landing pad (for example, tungsten (W), ruthenium (Ru), molybdenum (Mo), or a laminated structure of multiple metals including these) may be formed between the source electrode or drain electrode and the bit wire to facilitate connection between them, or a metal layer serving as a barrier metal (for example, a conductor such as tantalum (Ta) or tantalum nitride (TaN)) may be formed between the source electrode or drain electrode and the landing pad.

[0018] As described above, in this embodiment, the oxide semiconductor forming the channel of the transistor 21 has a Bix-byte structure. Because oxide semiconductors having a Bix-byte structure have a slow hydrogen diffusion rate, the channel formed from the oxide semiconductor is less susceptible to hydrogen influence. Therefore, even if there is a large variation in the hydrogen concentration of the first to third insulating films 10, 20, 30 (first to fourth insulating films 10, 20, 30, 40 in the example of Figure 2), the operation of the semiconductor device 100 can be stabilized. Furthermore, since variations in the hydrogen concentration of the first to third insulating films 10, 20, 30 (first to fourth insulating films 10, 20, 30, 40 in the example of Figure 2) are permissible, it is not necessarily required to control the film density of the insulating films as described in Patent Document 1 during the manufacturing process. Therefore, the semiconductor device 100 of this embodiment offers a high degree of freedom in its manufacturing method.

[0019] In one embodiment, the hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film 20 and the first insulating film 10 is set to C ｍａｘThe hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ It is 1.1 times or more, and may be 1.2 times or more, 1.3 times or more, or even 1.4 times or more. In this way, even when there is a large variation in hydrogen concentration, the operation of the semiconductor device 100 can be stabilized, which has the effect of increasing the degree of freedom in the manufacturing method of the semiconductor device 100. In one embodiment, the hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film 20 and the first insulating film 10 is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ It is less than 100 times, and may be less than 50 times, less than 30 times, less than 10 times, less than 3 times, less than 2 times, or even less than 1.5 times. Such variations in hydrogen concentration can further stabilize the operation of the semiconductor device 100.

[0020] In one embodiment, the hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film 20 and the third insulating film 30 is set to C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ It is 1.1 times or more, and may be 1.2 times or more, 1.3 times or more, or even 1.4 times or more. In this way, even when there is a large variation in hydrogen concentration, the operation of the semiconductor device 100 can be stabilized, which has the effect of increasing the degree of freedom in the manufacturing method of the semiconductor device 100. In one embodiment, the hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film 20 and the third insulating film 30 is set to C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ It is less than 100 times, and may be less than 50 times, less than 30 times, less than 10 times, less than 3 times, less than 2 times, or even less than 1.5 times. Such variations in hydrogen concentration can further stabilize the operation of the semiconductor device 100.

[0021] In one embodiment, the hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film 20 and the fourth insulating film 40 is set to C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ It is 1.1 times or more, and may be 1.2 times or more, 1.3 times or more, or even 1.4 times or more. In this way, even when there is a large variation in hydrogen concentration, the operation of the semiconductor device 100 can be stabilized, which has the effect of increasing the degree of freedom in the manufacturing method of the semiconductor device 100. In one embodiment, the hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film 20 and the fourth insulating film 40 is set to C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ It is less than 100 times, and may be less than 50 times, less than 30 times, less than 10 times, less than 3 times, less than 2 times, or even less than 1.5 times. Such variations in hydrogen concentration can further stabilize the operation of the semiconductor device 100.

[0022] In one embodiment, the hydrogen concentration of the first insulating film 10 is C １ The hydrogen concentration of the second insulating film 20 is set to C ２ When that happens, C １ / C ２ It is between 0.01 and 100, and may be between 0.1 and 10, between 0.3 and 3, between 0.5 and 2, and even between 0.7 and 1.5.

[0023] In one embodiment, the hydrogen concentration of the second insulating film 20 is set to C ２ The hydrogen concentration of the third insulating film 30 is C ３ When that happens, C ３ / C ２ It is between 0.01 and 100, and may be between 0.1 and 10, between 0.3 and 3, between 0.5 and 2, and even between 0.7 and 1.5.

[0024] In one embodiment, the hydrogen concentration of the second insulating film 20 is set to C ２ The hydrogen concentration of the fourth insulating film 40 is C ４ When that happens, C ４ / C２ It is between 0.01 and 100, and may be between 0.1 and 10, between 0.3 and 3, between 0.5 and 2, and even between 0.7 and 1.5.

[0025] In one embodiment, the hydrogen concentration of the second insulating film 20 is 1 × 10 １８ atoms / cm ３ ~1 x 10 ２２ toms / cm ３ Preferably 1 × 10 １９ atoms / cm ３ ~2 x 10 ２１ atoms / cm ３ And more preferably 1 × 10 ２０ atoms / cm ３ ~5 x 10 ２０ atoms / cm ３ Therefore, even with such a high hydrogen concentration in the second insulating film 20, the oxide semiconductor having a bigxbyte structure functions well as a channel in the transistor 21, and the operation of the semiconductor device 100 can be stabilized.

[0026] The hydrogen concentration in insulating films can be measured by secondary ion mass spectrometry (SIMS). The hydrogen concentration is calculated as the arithmetic mean of the measured values ​​(hydrogen concentrations) at five measurement points within each insulating film. Specifically, for measurement, each insulating film is divided into five equal parts along the film thickness direction, and each of these points serves as a SIMS measurement point.

[0027] In this embodiment, the film densities of the first insulating film 10, the second insulating film 20, the third insulating film 30, and the fourth insulating film 40 are not particularly limited. For example, among the first insulating film 10, the second insulating film 20, and the third insulating film 30, the third insulating film 30 may have the highest film density.

[0028] Each of the first insulating film 10, the second insulating film 20, the third insulating film 30, and the fourth insulating film 40 may be a film containing an insulator or consisting of an insulator. Examples of the insulator include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Each of the first insulating film 10, the second insulating film 20, the third insulating film 30, and the fourth insulating film 40 may be a laminated film of the above materials. The insulating film may contain La, N, Zr, or the like. The insulators contained in the first insulating film 10, the second insulating film 20, the third insulating film 30, and the fourth insulating film 40 may be the same as or different from each other. According to this aspect, for each of the first insulating film 10, the second insulating film 20, the third insulating film 30, and the fourth insulating film 40, an effect of a high degree of freedom in selecting an insulator can also be obtained. For example, each of the first insulating film 10, the second insulating film 20, and the fourth insulating film 40 may be provided with SiO ２ , and Si may be used for the third insulating film ３ N ４ can be applied. Si ３ N ４ has a higher density (film density) than SiO ２ and is less permeable to oxygen. With this configuration, desorption of oxygen from the oxide semiconductor 55 is suppressed particularly during high-temperature operation, and threshold shift and leakage current can be suppressed.

[0029] The method for forming each of the first insulating film 10, the second insulating film 20, the third insulating film 30, and the fourth insulating film 40 is not particularly limited, and known methods may be used. Configurations other than the insulating film described above may also be manufactured using known methods. For the method of forming the transistor 21, the method described below may be used.

[0030] Hereinafter, the transistor 21 included in the semiconductor device 100 will be described in further detail with reference to several examples (embodiments).

[0031] (First Embodiment) Figure 2 is a schematic perspective view showing a cross-section of a transistor according to the first embodiment. Figure 3 is a schematic cross-sectional view of the transistor. In this embodiment, the transistor 21 includes a first electrode 51, a second electrode 52, a third electrode 53, an oxide semiconductor 55, and a third electrode-oxide semiconductor interfacial insulating film 56. Of the first electrode 51 and the second electrode 52, the second electrode 52 is located on the first layer 1 side, and the first electrode 51 is located on the third layer 3 side. The second electrode 52 may be included in the second layer 2, or it may be included in the first layer 1. The first electrode 51 may be included in the second layer 2, or it may be included in the third layer 3. The third electrode may be included in the second layer 2. The first electrode 51 and the second electrode 52 are stacked via at least a second insulating film 20 (here, a second insulating film 20a located below the third electrode 53, and a second insulating film 20b located above the third electrode 53). The transistor 21 having such a structure (vertical structure) allows multiple transistors to be arranged at high density in a semiconductor memory device, for example, which also contributes to the miniaturization of the semiconductor memory device. When multiple transistors are arranged at high density, hydrogen diffusion from adjacent transistors tends to occur, but in this embodiment, the oxide semiconductor 55 has a bigx-byte structure, which reduces the hydrogen concentration of the oxide semiconductor 55. As a result, even when multiple transistors are arranged at high density, variations in the operation of the transistors can be suppressed. The term "stacked" here may mean that at least a part of the first electrode 51 and at least a part of the second electrode 52 are arranged along a direction perpendicular to the plane direction of the substrate supporting the transistor 21 (which may be the semiconductor substrate 101 shown in Figure 2), or, although not shown, when multiple transistors 21 are connected in a planar manner (in the X-Y direction) (when multiple transistors 21 form a transistor array), at least a part of the first electrode 51 and at least a part of the second electrode 52 are arranged along a direction perpendicular to the plane direction (Z direction). The second insulating film 20 (here, the second insulating films 20a and 20b) may have at least a portion interposed between the first electrode 51 and the second electrode 52. The third electrode 53 is located between the first electrode 51 and the second electrode 52.

[0032] Of the second insulating film 20a and the second insulating film 20b, the second insulating film 20a is located between the first electrode 51 and the third electrode 53. As a result, the first electrode 51 and the third electrode 53 are electrically insulated by the second insulating film 20a. The second insulating film 20b is located between the second electrode 52 and the third electrode 53. As a result, the second electrode 52 and the third electrode 53 are electrically insulated by the second insulating film 20b.

[0033] In the region shown in Figure 3, the third electrode 53 is positioned between the second insulating film 20a and the second insulating film 20b. However, outside the region shown in Figure 3, the second insulating film 20a and the second insulating film 20b are in contact with each other, forming a single layer (the second insulating film 20). In this case, the third electrode 53 (or the wiring 22 connected to the third electrode 53) does not need to be positioned between the second insulating film 20a and the second insulating film 20b in that region.

[0034] The oxide semiconductor 55 penetrates at least the second insulating film 20a and is provided to connect the first electrode 51 and the second electrode 52. The oxide semiconductor 55 may also penetrate the third electrode 53 in addition to the second insulating film 20a and the second insulating film 20b. Here, the oxide semiconductor 55 is provided in a columnar shape, penetrating the second insulating film 20a, the third electrode 53, and the second insulating film 20b in this order. In this case, it is preferable that the third electrode 53 surrounds the entire circumference of the oxide semiconductor 55 (around the periphery in the direction perpendicular to the length direction) in a portion of the oxide semiconductor 55 in the longitudinal direction (the central portion in the example of Figure 3) via the third electrode-oxide semiconductor inter-insulating film 56 described later. This makes it easier to prevent leakage current even if the channel length of the oxide semiconductor 55 described later is shortened. At the same time, it is also advantageous in terms of miniaturization. Furthermore, the length direction of the oxide semiconductor 55 as referred to here may be the vertical direction in Figure 3 (the direction connecting the first electrode and the second electrode), the direction along the channel length described later, the thickness direction of the laminate in which the second insulating film 20a, the third electrode 53, and the second insulating film 20b are stacked in this order, and, if the oxide semiconductor 55 is columnar, the height direction of the columnar structure.

[0035] The third electrode-oxide semiconductor insulating film 56 is provided between the third electrode 53 and the oxide semiconductor 55. The oxide semiconductor 55, the third electrode-oxide semiconductor insulating film 56, and the third electrode 53 are arranged in this order. The third electrode-oxide semiconductor insulating film 56 may insulate the third electrode 53 from the oxide semiconductor 55 by being provided between the third electrode 53 and the oxide semiconductor 55. In addition to being provided between the third electrode 53 and the oxide semiconductor 55, the third electrode-oxide semiconductor insulating film 56 may also be provided, for example, between the second insulating film 20a and / or the second insulating film 20b and the oxide semiconductor 55. The third electrode-oxide semiconductor insulating film 56 is provided so as to surround the entire circumference of the side surface of the columnar oxide semiconductor 55.

[0036] From one perspective, the transistor 21 can be described as having a laminate in which a second insulating film 20a, a third electrode 53, and the second insulating film 20b are stacked in this order, with a through-hole penetrating the laminate in the thickness direction (vertical direction in Figures 2 and 3), the inner circumferential surface of the through-hole being covered with a cylindrical third electrode-oxide semiconductor insulating film 56, and the inside of the cylindrical third electrode-oxide semiconductor insulating film 56 being filled with an oxide semiconductor 55.

[0037] When the semiconductor device 100 includes the transistor 21 according to the first embodiment, the wiring 22 of the second layer 2 shown in Figure 1 may be a word line connected to and / or formed by the third electrode 53. Also, the wiring 31 of the third layer 3 shown in Figure 1 may be a bit line connected to and / or formed by the first electrode 51. Furthermore, the capacitor structure 42 of the capacitor 41 shown in Figure 1 may be connected to the second electrode 52.

[0038] The dimensions of the transistor 21 may be designed as appropriate depending on its application. The channel length of the oxide semiconductor 55 is, for example, 1 nm to 10 μm, preferably 2 to 1000 nm, more preferably 3 to 100 nm, even more preferably 4 to 50 nm, even more preferably 5 to 30 nm, and even more preferably 6 to 20 nm. The channel length of the oxide semiconductor 55 is the length of the oxide semiconductor 55 along the thickness direction (vertical direction in Figures 2 and 3) of the laminate in which the second insulating film 20a, the third electrode 53, and the second insulating film 20b are stacked in this order, and may coincide with the distance between the first electrode 51 and the second electrode 52. If the oxide semiconductor 55 is columnar, the channel length of the oxide semiconductor 55 corresponds to the height of the columnar structure. The channel length of the oxide semiconductor 55 can be measured by processing the relevant area with a focused ion beam (FIB) to expose it and observing the cross-section with a transmission electron microscope (TEM).

[0039] The channel length of the oxide semiconductor 55 is not particularly limited, but is preferably 1 to 1000 nm, more preferably 1 to 500 nm, and more preferably 2 to 500 nm. By having such a fine channel length, the number of grain boundaries in the oxide semiconductor 55 can be reduced (or made zero). Since grain boundaries can become diffusion pathways for hydrogen, reducing them effectively suppresses hydrogen diffusion. The "channel length" of the oxide semiconductor 55 is the distance (length) between the first electrode 51 and the second electrode 52 connected by the oxide semiconductor 55, which is the channel.

[0040] The channel width of the oxide semiconductor 55 is, for example, 1 nm to 1000 nm, preferably 2 nm to 500 nm. The channel width of the oxide semiconductor 55 is the length of the oxide semiconductor 55 along the direction perpendicular to the thickness direction (for example, the left-right direction in Figure 3) of the laminate in which the second insulating film 20a, the third electrode 53, and the second insulating film 20b are stacked in this order. As shown in Figures 2 and 3, if the channel width of the oxide semiconductor 55 is not constant with respect to the channel length direction, the channel width of the oxide semiconductor 55 may be the average width along the channel length direction. The average width along the channel length direction is the average value obtained when the channel width is measured at 10 or more locations along the channel length direction. If the oxide semiconductor 55 is columnar, the channel width of the oxide semiconductor 55 corresponds to the width of the columnar structure. Furthermore, if the channel width of the oxide semiconductor 55 differs depending on the observation direction (for example, if the channel width differs when observed from a direction perpendicular to the plane of Figure 3 and when observed from the left or right direction in Figure 3), the channel width when observed from at least one direction may be within the above range.

[0041] The thickness of the third electrode-oxide semiconductor insulating film 56 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the third electrode-oxide semiconductor insulating film 56 from becoming a parasitic component, the thickness of the third electrode-oxide semiconductor insulating film 56 may be 50 nm or less, 10 nm or less, or 2 nm or less within the above range. The channel width of the oxide semiconductor 55 and the thickness of the third electrode-oxide semiconductor insulating film 56 can be measured in the same way as the channel length of the oxide semiconductor 55.

[0042] In transistor 21, the first electrode 51 can function as a source electrode, and the second electrode 52 can function as a drain electrode. In other examples, the first electrode 51 can function as a drain electrode, and the second electrode 52 can function as a source electrode. The third electrode 53 can function as a gate electrode. The oxide semiconductor 55 can function as a channel (current path) of transistor 21. For example, when a gate voltage is applied to the third electrode 53, which is the gate electrode, the first electrode 51 and the second electrode 52 are electrically connected by the oxide semiconductor 55, and transistor 21 is in the ON state. When no gate voltage is applied, the electrical connection between the first electrode 51 and the second electrode 52 by the oxide semiconductor 55 is released, and transistor 21 is in the OFF state.

[0043] Furthermore, in this specification, "electrically connected" includes cases where a connection is made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects.

[0044] In the transistor 21, the oxide semiconductor 55 is provided to connect the first electrode 51 and the second electrode 52. "Provided to connect the first electrode 51 and the second electrode 52" means that it is provided in a state in which the first electrode 51 and the second electrode 52 can be electrically connected. Therefore, the oxide semiconductor 55 does not need to be in physical contact with the first electrode 51 and the second electrode 52. For example, a conductive material (conductor) may be provided between the oxide semiconductor 55 and the first electrode 51 and / or the second electrode 52, or an insulating material (insulator) may be provided to the extent that conductivity (electrical connection) is ensured.

[0045] As described above, the oxide semiconductor 55 has a Bixbite structure. The presence or absence of a Bixbite structure can be determined based on the X-ray diffraction pattern in X-ray diffraction (XRD) or the electron diffraction spots in electron diffraction (particularly the TEM-ED described above).

[0046] In one embodiment, the oxide semiconductor 55 is mainly composed of indium oxide. "Mainly composed of indium oxide" means that more than 50% by mass of the material constituting the oxide semiconductor 55 is indium oxide.

[0047] In one embodiment, the ratio of indium atoms to the total metal atoms contained in the oxide semiconductor 55 is 80 atomic% or more, 90 atomic% or more, or 95 atomic% or more. The content (atomic ratio) of each metal element in the oxide semiconductor 55 can be analyzed by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope.

[0048] In one embodiment, the oxide semiconductor 55 has a bixbite structure mainly composed of indium oxide and may contain other metal atoms. For example, in addition to indium oxide (IO), the oxide semiconductor 55 may contain indium gallium oxide (IGO), in which gallium is dissolved in the main component indium oxide, or indium gallium aluminum oxide (IGAO), in which gallium and aluminum are dissolved in the main component indium oxide. In one embodiment, the oxide semiconductor 55 may have an indium oxide content of 55% by mass or more, 60% by mass or more, 70% by mass or more, 80% by mass or more, 90% by mass or more, 95% by mass or more, 97% by mass or more, 98% by mass or more, or 99% by mass, and may be substantially 100% by mass. In the case of "substantially 100% by mass", it may contain unavoidable impurities.

[0049] In one embodiment, the oxide semiconductor 55 contains indium oxide and further contains a trivalent metal. The trivalent metal is preferably Ga and Al, with Ga being more preferred. In one embodiment, the crystalline oxide semiconductor further contains Ga or Al, may contain Ga, may contain Al, or may contain both Ga and Al. In one embodiment, the atomic ratio of the trivalent metal to all metal elements contained in the oxide semiconductor 55 ([trivalent metal] / ([trivalent metal] + [all metal elements other than the trivalent metal]) × 100) may be 0 to 30 at%, 0.5 to 25 at%, 1.0 to 22 at%, 1.5 to 20 at%, 2.0 to 15 at%, or 3.0 to 10 at%. Here, "trivalent metal" may be read as Ga and Al. In one embodiment, the atomic ratio of Ga to all metal elements contained in the oxide semiconductor 55 ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) may be 0 to 30 at%, 0.5 to 25 at%, 1.0 to 22 at%, 1.5 to 20 at%, 2.0 to 15 at%, or 3.0 to 10 at%. In one embodiment, the atomic ratio of Al to all metal elements contained in the oxide semiconductor 55 ([Al] / ([Al] + [all metal elements other than Al]) × 100) may be 0 to 30 at%, 0.5 to 25 at%, 1.0 to 22 at%, 1.5 to 20 at%, 2.0 to 15 at%, or 3.0 to 10 at%.

[0050] When the oxide semiconductor 55 contains Ga, it is preferable because it tends to enlarge the crystal grains of the oxide semiconductor 55 and reduce the number of crystal grain boundaries in the oxide semiconductor 55. This is because crystal grain boundaries can serve as pathways for hydrogen diffusion.

[0051] In one embodiment, the oxide semiconductor 55 further contains one or more additive elements selected from B, Si, Sc, Zn, Ce, Y, Zr, Sn, Sm, Hf, Ta, and Yb. In one embodiment, the atomic ratio of the total amount of additive elements to the total amount of metal elements contained in the oxide semiconductor 55 ([total amount of additive elements] / ([total amount of additive elements] + [total metal elements other than additive elements]) × 100) is 0 to 10 at%, and may be 0.1 to 8 at%, 0.5 to 5 at%, or 1 to 3 at%.

[0052] In one embodiment, the oxide semiconductor 55 does not need to contain Zn. The atomic ratio of Zn to all metal elements contained in the oxide semiconductor 55 ([amount of Zn] / ([amount of Zn] + [amount of all metal elements other than Zn]) × 100) is 0 to 3 at%, and may be 0 to 1 at%, 0 to 0.1 at%, 0 to 0.01 at%, or substantially 0 at%. In the case of "substantially 0 at%," the oxide semiconductor 55 may contain Zn as an unavoidable impurity. Since Zn has the property of absorbing water molecules (including hydrogen and oxygen atoms), a low Zn content in the oxide semiconductor 55, and especially the absence of Zn in the oxide semiconductor 55, can reduce the hydrogen and oxygen concentrations in the oxide semiconductor 55 and suppress the diffusion of hydrogen and oxygen into the oxide semiconductor 55. This makes it possible to provide transistors with even less variation.

[0053] Each of the first electrode 51, the second electrode 52, and the third electrode 53 is not particularly limited as long as they are conductors. Examples of conductors include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N).

[0054] The third electrode-oxide semiconductor insulating film 56 is not particularly limited as long as it contains an insulator or is a film made of an insulator, and the materials exemplified for the second insulating film 20 may be applied.

[0055] An example of a manufacturing method for the transistor 21 according to this embodiment is described below, but the manufacturing method is not limited to this example.

[0056] Figure 4 illustrates an example of a method for manufacturing the transistor 21 according to this embodiment. Figure 4(a) shows the oxide semiconductor 55, the second electrode 52, and the insulating film supporting the second electrode 52 (in this example, the fourth insulating film 40) formed in Figures 2 and 3. Although not shown in Figure 4(a), the second electrode 52 and the insulating film 40 may be formed on another substrate. The second electrode 52 may also be connected to an element outside the transistor (for example, a capacitor 41). The insulating film 40 and the second electrode 52 can be formed by known methods.

[0057] Next, as shown in Figure 4(b), the second insulating film 20b, the third electrode 53, and the second insulating film 20a are formed in this order. At this time, as will be described later, the third electrode 53 may be formed to be connected to the word line. Alternatively, the third electrode 53 itself may be used as the word line.

[0058] The second insulating film 20a and the second insulating film 20b are formed by, for example, depositing a film containing the above-mentioned insulator by various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method, or by depositing a film containing the above-mentioned insulator by various methods such as plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0059] The third electrode 53 is formed by depositing a conductive material such as tungsten, as described above. The third electrode 53 may be patterned into any shape. The pattern of the third electrode 53 may be formed during film deposition, or it may be formed by etching after film deposition.

[0060] Next, as shown in Figure 4(c), through-holes H are formed by etching, penetrating the second insulating film 20a, the third electrode 53, and the second insulating film 20b. Various etching methods, such as dry etching and wet etching, may be used to form the through-holes H. Alternatively, a resist may be deposited on the second insulating film 20a before etching to define the region where the through-holes H will be formed.

[0061] Next, as shown in Figure 4(d), a third electrode-oxide semiconductor insulating film 56 containing the above-described insulator is formed by various methods such as chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method.

[0062] Next, as shown in Figure 4(e), an oxide semiconductor 55 is formed in the through-hole H where the third electrode-oxide semiconductor insulating film 56 is formed. Methods for forming the oxide semiconductor 55 include chemical vapor deposition (CVD), plasma CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, and coating method. Note that CVD methods include metalloorganic CVD (MO-CVD), inductively coupled plasma CVD (ICP-CVD), and mist CVD. PVD methods include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, and ion plating. The oxide semiconductor 55 may also be formed as a crystalline oxide semiconductor by first forming an amorphous oxide semiconductor and then performing post-annealing as described later. A crystalline oxide semiconductor may be formed by performing post-annealing after the formation of an amorphous oxide semiconductor, or post-annealing may be performed after the oxide semiconductor has crystallized and a crystalline oxide semiconductor has been formed. Alternatively, a crystalline oxide semiconductor may be formed without post-annealing, or post-annealing may be performed after the formation of the crystalline oxide semiconductor to adjust the crystallinity of the crystalline oxide semiconductor.

[0063] It is preferable to post-anneal the oxide semiconductor 55 formed in the process shown in Figure 4(e). Post-annealing can be performed after the deposition of the oxide semiconductor film, for example, after or before the formation of the first electrode 51 in the subsequent step. The state of the oxide semiconductor before post-annealing may be amorphous or crystalline. The annealing atmosphere may contain nitrogen or oxygen and may be under vacuum or air. The annealing temperature is preferably 250°C to 600°C, more preferably 300°C to 500°C, and even more preferably 350°C to 450°C. The annealing time is 5 minutes to 2 hours, preferably 30 minutes to 1 hour. The oxide semiconductor 55 can be formed by atomic layer deposition (ALD), which will be described later.

[0064] Next, as shown in Figure 4(f), a first electrode 51 is formed on the upper layer of the oxide semiconductor 55. The first electrode 51 may be patterned into any shape. The first electrode 51 may have a pattern formed during film deposition, or it may have a pattern formed by etching after film deposition.

[0065] As described above, a transistor 21 as shown in Figures 2 and 3 can be obtained.

[0066] In the first embodiment, the third electrode-oxide semiconductor insulating film 56 is shown to completely surround the side surface of the columnar oxide semiconductor 55, but it is not necessarily limited to this, and for example, the third electrode-oxide semiconductor insulating film 56 may surround at least a part of the columnar oxide semiconductor 55.

[0067] In the manufacturing method described above, the oxide semiconductor 55 is formed in the through-hole H where the third electrode-oxide semiconductor insulating film 56 is formed. Therefore, atomic layer deposition (ALD) is preferred as the method for forming the oxide semiconductor 55. Atomic layer deposition (ALD) is a thin film formation method in which a process of alternately exposing a raw material (sometimes called a precursor) containing a metal element constituting the film to be deposited (in this case, the oxide semiconductor 55) and an oxidizing agent to the substrate surface constitutes one cycle, forming one atomic layer in one cycle, and repeating this cycle until the desired film thickness is achieved. Therefore, by using ALD, a dense oxide semiconductor 55 can be formed even in the region near the second electrode 52, which is far from the opening, in the through-hole H where the third electrode-oxide semiconductor insulating film 56 is formed.

[0068] A single atomic layer deposition cycle of ALD may include the following four steps: (1) The precursor, which is the raw material, is vaporized in a container and introduced into the chamber. A predetermined system pressure is applied and the precursor is reacted with the OH groups on the substrate surface or film surface for a predetermined time to adsorb single molecules. If the vapor pressure of the precursor is low, the container containing the precursor may be heated to promote vaporization, and if the vapor pressure of the precursor is high, the container containing the precursor may be cooled to suppress vaporization and adjust the process. (2) Unreacted raw materials and by-product gases are removed from the chamber by purging with an inert gas, and one atomic layer is deposited. (3) A reactive gas is introduced into the chamber, and the metal of the precursor is oxidized using heat, plasma, etc. (4) Unreacted oxidizing agents and by-product gases are removed by purging with an inert gas. After step (4), the process returns to step (1), and steps (1) to (4) may be repeated until the desired film thickness is achieved.

[0069] When performing ALD, various ALD devices can be used. Specifically, examples include devices that can supply a precursor by bubbling, and devices that have a vaporization chamber. Also, devices that can perform plasma treatment on the reactive gas (oxidizer) can be used. Furthermore, not only single-wafer devices equipped with a film deposition chamber, but also devices that can process multiple sheets simultaneously using a batch furnace may be used.

[0070] Types of ALD precursors include organometallics (e.g., AlMe ３ ), metal hydrides (e.g., AsH ３ ), metal alkoxides (e.g., Ti(OCHMe ２ ) ４ ), metal amides (e.g., Ti(NMe ２ ) ４ ), β-diketonates (e.g., Co(acac) ２ ), metallocenes (e.g., MgCp ２ ), metal amidinates, etc. Various metal compounds used as ALD precursors are commercially available, and a precursor and an oxidant that can form a target film to be deposited may be selected.

[0071] Examples of precursors include compounds of one or more types selected from the group consisting of compounds used as organic ligands, such as alkyl compounds, alcohol compounds, glycol compounds, β-diketone compounds, cyclopentadiene compounds, and organic amine compounds, with silicon or a metal.

[0072] Examples of metal species of the precursor include lithium, sodium, potassium, magnesium, calcium, strontium, barium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, iron, ruthenium, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, zinc, boron, aluminum, silicon, indium, gallium, germanium, tin, lead, antimony, bismuth, scandium, ruthenium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0073] If the oxide semiconductor 55 contains indium atoms (In), an In-containing precursor may be used. If the oxide semiconductor 55 contains other metals, a precursor containing those metals may be used. When forming an oxide semiconductor using two or more metals, there are two methods: vaporizing and supplying each component independently (sometimes referred to as the "single-source method") and vaporizing and supplying a mixed raw material in which multi-component raw materials are pre-mixed to a desired composition (sometimes referred to as the "cocktail-source method"). In the single-source method, it is preferable that each precursor used has similar thermal and / or oxidative decomposition behavior. In the cocktail-source method, in addition to having similar thermal and / or oxidative decomposition behavior, it is preferable that each precursor is a compound that does not undergo alteration due to chemical reactions, etc., when mixed.

[0074] The following are examples of compounds that can be used as organic ligands for precursors. Furthermore, depending on the valency of the central metal, multiple ligands from the following list may coordinate. In a precursor, when multiple ligands coordinate to the central metal, these ligands may be identical to each other, or two or more ligands may be combined.

[0075] Alkyl compounds used as organic ligands for precursors include methyl, ethyl, propyl, isopropyl, butyl, 2-butyl, isobutyl, 3-butyl, pentyl, isopentyl, and 3-pentyl.

[0076] Alcohol compounds used as organic ligands for precursors include alkyl alcohols such as methanol, ethanol, propanol, isopropyl alcohol, butanol, 2-butyl alcohol, isobutyl alcohol, 3-butyl alcohol, pentyl alcohol, isopentyl alcohol, and 3-pentyl alcohol; 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, 2-(2-methoxyethoxy)ethanol, 2-methoxy-1-methylethanol, 2-methoxy-1,1-dimethylethanol, 2-ethoxy-1,1-dimethylethanol, 2-isopropoxy-1,1-dimethylethanol, and 2-butoxy Examples include ether alcohols such as -1,1-dimethylethanol, 2-(2-methoxyethoxy)-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-s-butoxy-1,1-diethylethanol, and 3-methoxy-1,1-dimethylpropanol; and dialkylamino alcohols such as dimethylaminoethanol, ethylmethylaminoethanol, diethylaminoethanol, dimethylamino-2-pentanol, ethylmethylamino-2-pentanol, dimethylamino-2-methyl-2-pentanol, ethylmethylamino-2-methyl-2-pentanol, and diethylamino-2-methyl-2-pentanol.

[0077] Examples of glycol compounds used as organic ligands for precursors include 1,2-ethanediol, 1,2-propanediol, 1,3-propanediol, 2,4-hexanediol, 2,2-dimethyl-1,3-propanediol, 2,2-diethyl-1,3-propanediol, 1,3-butanediol, 2,4-butanediol, 2,2-diethyl-1,3-butanediol, 2-ethyl-2-butyl-1,3-propanediol, 2,4-pentanediol, 2-methyl-1,3-propanediol, 2-methyl-2,4-pentanediol, 2,4-hexanediol, and 2,4-dimethyl-2,4-pentanediol.

[0078] Examples of β-diketone compounds used as organic ligands for precursors include acetylacetone, hexane-2,4-dione, 5-methylhexane-2,4-dione, heptane-2,4-dione, 2-methylheptane-3,5-dione, 5-methylheptane-2,4-dione, 6-methylheptane-2,4-dione, 2,2-dimethylheptane-3,5-dione, 2,6-dimethylheptane-3,5-dione, 2,2,6-trimethylheptane-3,5-dione, 2,2,6,6-tetramethylheptane-3,5-dione, octane-2,4-dione, 2,2,6-trimethyloctane-3,5-dione, 2,6-dimethyloctane-3,5-dione, 2,9-dimethylnonane-4,6-dione, and 2-methyl-6-ethyl Examples include alkyl-substituted β-diketones such as decane-3,5-dione and 2,2-dimethyl-6-ethyldecane-3,5-dione; fluorine-substituted alkyl β-diketones such as 1,1,1-trifluoropentane-2,4-dione, 1,1,1-trifluoro-5,5-dimethylhexane-2,4-dione, 1,1,1,5,5,5-hexafluoropentane-2,4-dione, and 1,3-diperfluorohexylpropane-1,3-dione; and ether-substituted β-diketones such as 1,1,5,5-tetramethyl-1-methoxyhexane-2,4-dione, 2,2,6,6-tetramethyl-1-methoxyheptane-3,5-dione, and 2,2,6,6-tetramethyl-1-(2-methoxyethoxy)heptane-3,5-dione.

[0079] Examples of cyclopentadiene compounds used as organic ligands for precursors include cyclopentadiene, methylcyclopentadiene, ethylcyclopentadiene, propylcyclopentadiene, isopropylcyclopentadiene, butylcyclopentadiene, 2-butylcyclopentadiene, isobutylcyclopentadiene, 3-butylcyclopentadiene, dimethylcyclopentadiene, and tetramethylcyclopentadiene.

[0080] Examples of organic amine compounds used as organic ligands for precursors include methylamine, ethylamine, propylamine, isopropylamine, butylamine, 2-butylamine, 3-butylamine, isobutylamine, dimethylamine, diethylamine, dipropylamine, diisopropylamine, ethylmethylamine, propylmethylamine, and isopropylmethylamine.

[0081] In addition, metal halogen compounds (e.g., InCl ３ InBr ３ InF ３ (etc.) may be used as precursors. When multiple halogens coordinate to a metal, these halogens may be identical to each other, or two or more halogens may be combined. In addition, some of the halogens may be replaced with hydrogen.

[0082] Examples of indium-containing precursors include InCl ３ , TMIn (trimethyl indium), TEIn (triethyl indium), InCp (cyclopentadienyl indium (I)), InEtCp (ethylcyclopentadienyl indium(I)), In(acac) ３ (indium acetylacetonate), In(tmhd) ３ (indium 2,2,6,6-tetramethyl-3,5-heptanedionate), In[( ｉ PrN) ２ CNR ２ ] ３ (R=Me) (indium-tris-guanidinates), Et ２ InN (TMS) ２ (diethyl[bis-(trimethylsilyl)amido]indium), INCA(diethyl[1,1,1-trimethyl-N- (trimethylsilyl)silanaminato]indium), DADI([3-(dimethylamino)propyl]dimethyl indium), In(dmamp) ３((1-dimethylamino-2-methyl-2-propoxy)indium), Me ２ Examples include In(EDPA)(dimethyl(N-ethoxy-2,2-dimethylpropanamido)indium) and tris(N,N'-disosopropylacetamidinato)indium(III).

[0083] These ALD precursors may be used individually or in combination of two or more types.

[0084] The precursors described above can be manufactured according to known manufacturing methods. For example, when an alcohol compound is used as an organic ligand, the precursor can be manufactured by reacting the inorganic salt or hydrate of the aforementioned metal with an alkali metal alkoxide of the alcohol compound. Examples of the inorganic salt or hydrate of the metal include metal halides and nitrates. Examples of alkali metal alkoxides include sodium alkoxide, lithium alkoxide, and potassium alkoxide.

[0085] As an oxidizing agent used in ALD, H ２ O, O ２ , O ３ , O ２ Plasma, H ２ O plasma, hydrogen peroxide (H ２ O ２ Examples include the following. These oxidizing agents may be used individually or in combination of two or more.

[0086] When using two or more oxidizing agents, they may be used simultaneously, or they may be used individually while changing between them. For example, as an oxidizing agent, O ２ Plasma and H ２ By using two types of O plasma, ２ High mobility obtained when using plasma, and H ２By using O plasma, it is possible to take advantage of both the reduction in carbon concentration and the improved stability of mobility during heat treatment. By using two or more oxidizing agents, high mobility and low carbon concentration can be adjusted. Depending on the desired effect, O ２ Plasma and H ２ The proportion of O-plasma used, the order of use, the number of cycles, etc., should be selected as appropriate.

[0087] The pressure in the system (inside the film deposition chamber) in step (1) can be set appropriately according to the type of precursor, substrate temperature, etc. For example, 1 to 10,000 Pa is preferred, 10 to 1,000 Pa is more preferred, 50 to 500 Pa is even more preferred, and 80 to 120 Pa is particularly preferred.

[0088] In one embodiment, in the film formation process, H is used as the oxidizing agent. ２ O plasma is used. In one embodiment, in the film formation process, O is used as the oxidizing agent. ２ Plasma is used. In one embodiment, in the film deposition process, O is used as the oxidizing agent. ３ These oxidizing agents are used. By using these oxidizing agents, it is possible to control the electrical properties of the oxide semiconductor film to a favorable state.

[0089] To vaporize the precursor, the container containing the precursor may be heated to a temperature at which the precursor is sufficiently vaporized, as needed. If a precursor with a high vapor pressure is used, the container containing the precursor may be cooled as needed. In one embodiment, the container containing the indium-containing precursor (e.g., triethylindium) is heated to a temperature in the range of 25 to 150°C. The above temperature is preferably in the range of 50 to 150°C, and more preferably in the range of 75 to 125°C.

[0090] In the manufacturing method described above, the substrate temperature during film formation is usually in the range of 50 to 600°C, preferably 85 to 500°C, more preferably 80 to 350°C, and even more preferably 100 to 250°C.

[0091] Furthermore, the amount of oxide semiconductor film grown per ALD process cycle varies depending on the type of precursor and reactive gas used during film formation, as well as the substrate temperature during film formation.

[0092] The growth rate per ALD process cycle is called Growth per Cycle (GPC), and can be calculated, for example, by measuring the film thickness of the oxide semiconductor after repeating 30 ALD cycles. Here, GPC changes depending on the combination of precursor, oxidizer, and substrate temperature, and also changes depending on the type of substrate. Therefore, the number of cycles can be set appropriately by taking these factors into consideration, as it depends on numerous factors such as the type and combination of precursor and oxidizer used, the type of substrate, the substrate temperature during film formation, and the desired film thickness.

[0093] Also, as an oxidizing agent, O ３ When using, the substrate temperature during film formation is preferably above 100°C, more preferably 110-250°C, 120-230°C, or 130-220°C. H is used as the oxidizing agent. ２ O plasma and O ２ When using plasma, the substrate temperature during film deposition is preferably 100 to 150°C.

[0094] Examples of inert gases used to purge unreacted raw materials and unreacted oxidizing agents include argon and nitrogen, and in the method of this embodiment, argon or nitrogen is preferred.

[0095] In step (3) above, it is preferable to generate a plasma of the reactive gas (oxidizer).

[0096] (Second Embodiment) Next, another example of the transistor (second embodiment) will be described with reference to Figures 5 and 6. Figure 5 is a schematic perspective view showing a cross-section of the transistor according to the second embodiment. Figure 6 is a schematic cross-sectional view of the same transistor. In Figures 5 and 6, the same reference numerals as in Figures 2 and 3 indicate the same components, and unless otherwise specified, the descriptions given for Figures 2 and 3 will be incorporated by reference.

[0097] In the second embodiment, the transistor 21 includes a first electrode 51, a second electrode 52, a third electrode 53, an oxide semiconductor 55, and a third electrode-oxide semiconductor interfacial insulating film 56. Of the first electrode 51 and the second electrode 52, the second electrode 52 is located on the first layer 1 side, and the first electrode 51 is located on the third layer 3 side. The second electrode 52 may be included in the second layer 2, or it may be included in the first layer 1. The first electrode 51 may be included in the second layer 2, or it may be included in the third layer 3. The third electrode may be included in the second layer 2, or (particularly its upper part) it may be included in the third layer 3. At least a portion of the third electrode 53 is located between the first electrode 51 and the second electrode 52. At least a portion of the third electrode 53 may be located on the opposite side of the first electrode 51 from the second electrode 52, or on the opposite side of the second electrode 52 from the first electrode 51. The second insulating film 20 is located between the first electrode 51 and the second electrode 52. Here, the first electrode 51 and the second electrode 52 are stacked with a second insulating film 20 in between. As a result, the first electrode 51 and the second electrode 52 are electrically insulated by the second insulating film 20. The third electrode 53 is provided adjacent to the oxide semiconductor 55 without contacting it. Specifically, the third electrode 53 is adjacent to the oxide semiconductor 55 via a third electrode-oxide semiconductor insulating film 56. The third electrode-oxide semiconductor insulating film 56 may be provided between the third electrode 53 and the oxide semiconductor 55 to insulate the third electrode 53 from the oxide semiconductor 55.

[0098] The oxide semiconductor 55 is provided to penetrate at least the second insulating film 20 and connect the first electrode 51 and the second electrode 52. Here, the oxide semiconductor 55 is provided in a columnar shape, penetrating the first electrode 51 and the second insulating film 20 in that order. A recess is formed in the columnar oxide semiconductor 55 from one end (upper side in Figures 5 and 6) to the other end (lower side in Figures 5 and 6), and a third electrode-oxide semiconductor insulating film 56 is formed on the inner circumferential surface and bottom surface of the recess. The third electrode 53 is provided to fill the recess in which the third electrode-oxide semiconductor insulating film 56 is formed. From one viewpoint, it can also be said that the oxide semiconductor 55 has a cylindrical portion provided penetrating the second insulating film 20, the third electrode-oxide semiconductor insulating film 56 has a cylindrical portion provided on the inner wall of the cylindrical portion of the oxide semiconductor 55, and the third electrode 53 has a portion provided inside the cylindrical portion of the third electrode-oxide semiconductor insulating film 56.

[0099] When the semiconductor device 100 includes the transistor 21 according to the second embodiment, the wiring 22 of the second layer 2 shown in Figure 1 may be a bit line connected to and / or formed by the first electrode 51. Also, the wiring 31 of the third layer 3 shown in Figure 1 may be a word line connected to and / or formed by the third electrode 53. Furthermore, the capacitor structure 42 of the capacitor 41 shown in Figure 1 may be connected to the second electrode 52.

[0100] The dimensions of the transistor 21 may be designed as appropriate depending on its application. The channel length of the oxide semiconductor 55 is, for example, 1 nm to 10 μm, preferably 2 nm to 1000 nm. The channel length of the oxide semiconductor 55 is the length of the oxide semiconductor 55 along the thickness direction (vertical direction in Figures 5 and 6) of the laminate in which the first electrode 51, the second insulating film 20, and the second electrode 52 are stacked in this order, and may coincide with the depth of the recess in the oxide semiconductor 55.

[0101] The thickness of the oxide semiconductor 55 is, for example, 1 nm to 500 nm, preferably 1 nm to 100 nm. The thickness of the oxide semiconductor 55 may be the average thickness along the channel length. The average thickness along the channel length is the average value obtained when the thickness is measured at 10 or more locations along the channel length.

[0102] The thickness of the third electrode-oxide semiconductor insulating film 56 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the third electrode-oxide semiconductor insulating film 56 from becoming a parasitic component, the thickness of the third electrode-oxide semiconductor insulating film 56 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0103] The channel length and thickness of the oxide semiconductor 55, and the thickness of the third electrode-oxide semiconductor insulating film 56, can be measured in the same manner as in the first embodiment.

[0104] The first electrode 51, the second electrode 52, the third electrode 53, the second insulating film 20, the third electrode-oxide semiconductor insulating film 56, and the oxide semiconductor 55 may be described by reference to the first embodiment.

[0105] The method for manufacturing the transistor 21 according to the second embodiment is not particularly limited and can be manufactured by known methods with reference to the manufacturing method according to the first embodiment. For example, the transistor 21 according to the second embodiment may be manufactured as follows: After forming a laminate of the second electrode 52, the second insulating film 20, and the first electrode 51, through holes are formed so as to penetrate the first electrode 51 and the second insulating film 20. After forming the oxide semiconductor 55, the third electrode-oxide semiconductor insulating film 56 and the third electrode 53 are formed.

[0106] (Third Embodiment) Next, another further example of the transistor according to this embodiment (third embodiment) will be described with reference to Figures 7 and 8. Figure 7 is a schematic perspective view showing a cross-section of the transistor according to the third embodiment. Figure 8 is a schematic cross-sectional view of the same transistor. In Figures 7 and 8, the same reference numerals as in Figures 2 and 3 indicate the same components, and unless otherwise specified, the descriptions given for Figures 2 and 3 will be incorporated by reference.

[0107] In the third embodiment, the transistor 21 comprises a first electrode 51, a second electrode 52, a third electrode 53, oxide semiconductors 55, 55', and a third electrode-oxide semiconductor insulating film 56. Of the first electrode 51 and the second electrode 52, the second electrode 52 is located on the first layer 1 side, and the first electrode 51 is located on the third layer 3 side. The second electrode 52 may be included in the second layer 2, or it may be included in the first layer 1. Similarly, the first electrode 51 may be included in the second layer 2, or it may be included in the third layer 3. The third electrode may be included in the second layer 2. The third electrode 53 is located between the first electrode 51 and the second electrode 52. The third electrode-oxide semiconductor insulating film 56 is located between the first electrode 51 and the third electrode 53. Here, the first electrode 51 and the second electrode 52 are stacked via the third electrode-oxide semiconductor insulating film 56. As a result, the first electrode 51 and the second electrode 52 are electrically insulated by the third electrode-oxide semiconductor insulating film 56. The third electrode 53 is provided so as to be adjacent to the oxide semiconductors 55 and 55' without contacting them. Specifically, the third electrode 53 is adjacent to the oxide semiconductors 55 and 55' via the third electrode-oxide semiconductor insulating film 56 located between the third electrode 53 and the oxide semiconductors 55 and 55'.

[0108] The oxide semiconductors 55 and 55' connect the first electrode 51 and the second electrode 52, respectively.

[0109] When multiple transistors 21 are connected in parallel, a second insulating film 20 (not shown in Figures 7 and 8) may be interposed in at least a portion of the region between the transistors 21. Although not shown, for example, when considering two adjacent transistors 21, the second insulating film 20 may be interposed between the oxide semiconductor 55' of one transistor 21 and the oxide semiconductor 55 of the other transistor 21.

[0110] When the semiconductor device 100 includes the transistor 21 according to the third embodiment, the wiring 22 of the second layer 2 shown in Figure 1 may be a word line connected to and / or formed by the third electrode 53. Also, the wiring 31 of the third layer 3 shown in Figure 1 may be a bit line connected to and / or formed by the first electrode 51. Furthermore, the capacitor structure 42 of the capacitor 41 shown in Figure 1 may be connected to the second electrode 52.

[0111] The dimensions of the transistor 21 may be designed as appropriate depending on its application. The channel lengths of the oxide semiconductors 55 and 55' are, for example, 1 nm to 10 μm, preferably 2 nm to 1000 nm. The channel length of the oxide semiconductor 55 is the length of the oxide semiconductors 55 and 55' along the thickness direction (vertical direction in Figures 7 and 8) of the laminate in which the first electrode 51, the third electrode-oxide semiconductor insulating film 56, and the second electrode 52 are stacked in this order, and may coincide with the distance between the first electrode 51 and the second electrode 52.

[0112] The thickness of the oxide semiconductors 55 and 55' is, for example, 1 nm to 500 nm, preferably 1 nm to 100 nm. The thickness of the oxide semiconductor 55 may be the average thickness along the channel length. The average thickness along the channel length is the average value obtained when the thickness is measured at 10 or more locations along the channel length.

[0113] The thickness of the third electrode-oxide semiconductor insulating film 56 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to suppress the capacitance of the second insulating film 20 from becoming a parasitic component, the thickness of the third electrode-oxide semiconductor insulating film 56 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0114] The channel length and thickness of the oxide semiconductors 55 and 55', as well as the thickness of the third electrode-oxide semiconductor insulating film 56, can be measured in the same manner as in the first embodiment.

[0115] The descriptions in the first and second embodiments may be applied to the first electrode 51, the second electrode 52, the third electrode 53, the third electrode-oxide semiconductor insulating film 56, and the oxide semiconductor 55.

[0116] The method for manufacturing the transistor 21 according to the third embodiment is not particularly limited and can be manufactured by referring to known methods (for example, the method described in International Publication No. 2020 / 076850, etc.) while referring to the manufacturing method according to the first embodiment. The methods for forming the first electrode 51, the second electrode 52, the third electrode 53, the third electrode-oxide semiconductor insulating film 56, and the oxide semiconductor 55 can be adapted from the descriptions in the first and second embodiments.

[0117] The semiconductor device 100 according to this embodiment can reduce the hydrogen concentration in the oxide semiconductor in the transistor 21, thereby suitably achieving normally-off operation and high reliability. The type of semiconductor device 100 is not particularly limited, but from the viewpoint of demonstrating the above-mentioned effects significantly, it is preferable to use semiconductor memory devices such as volatile memories like DRAM (Dynamic Random Access Memory) and SRAM (Static RAM); and non-volatile memories like mask ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory (NOR type flash memory, NAND type flash memory), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), and ReRAM (Resistive RAM). Alternatively, the semiconductor device according to this embodiment may be a logic device such as TTL (Transistor-Transistor Logic), CMOS (Complementary Metal-Oxide-Semiconductor), BiCMOS, PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), or MPU (Microprocessor Unit). Furthermore, since the transistor 21 can be fitted with a vertical structure as shown in each embodiment, it is suitable for densely arranging multiple transistors 21 in a semiconductor memory device, and contributes to the miniaturization of the semiconductor memory device. In addition, since the transistor 21 uses an oxide semiconductor having a bigx-byte structure as its channel, it tends to have a small leakage current. Therefore, by using it in a semiconductor memory device, the capacitance of the capacitor can be reduced or the capacitor can be omitted. As a result, the semiconductor memory device can be miniaturized by using the transistor 21.

[0118] A semiconductor device may contain a large number of transistors 21. For example, a DRAM contains hundreds of millions of memory cells, and the number of transistors 21 constituting these memory cells is also in the hundreds of millions. In addition, DRAM uses multiple transistors other than memory cells. According to this embodiment, variations in the performance of each transistor can be suppressed, and variations in the operation of the semiconductor device can also be effectively suppressed.

[0119] Figure 9 shows an example of the circuit configuration of a semiconductor memory device according to one embodiment of the present invention. As shown in Figure 9, the semiconductor memory device 60 includes a transistor 21, a capacitor 41, a word line WL, and a bit line BL. The source electrode of the transistor 21 is connected to the bit line BL. The drain electrode of the transistor 21 is connected to one end of the capacitor 41. The gate electrode of the transistor 21 is connected to the word line WL. The other end of the capacitor 41 is grounded. The bit line BL may be connected to the first electrode 51 of the transistor 21 or to the second electrode 52. The word line WL may be connected to the third electrode 53 of the transistor 21. One end of the capacitor 41 may be connected to the first electrode 51 of the transistor 21 or to the second electrode 52.

[0120] In the example shown in Figure 9, a single memory cell 61 is formed by a transistor 21 and a capacitor 41. The memory cell 61 can store data based on the charge held by the capacitor 41. Note that the configuration of the memory cell 61 is not limited to this example, and in other examples, the capacitor 41 may be omitted (in this case, the fourth layer 4 described above may be omitted). When the capacitor 41 is omitted, data can be stored based on the charge held by the transistor 21 itself. In addition, two or more transistors may be combined to form the memory cell 61. When the transistor 21 itself is to have the function of holding charge, for example, one or more of the configurations described below can be applied. (1) In the third electrode-oxide semiconductor insulating film, hafnium oxide (HfO ２ ), zirconium oxide (ZrO ２(2) Use a high dielectric constant insulator such as (Pb,La)(Zr,Ti)O in the third electrode-oxide semiconductor insulating film. ３ (PLZT), SrTiO ３ (STO), yttria-stabilized zirconia (YSZ), and other ferroelectric materials are used. (3) Hysteresis is utilized by adding an element that forms an energy level within the gap of the oxide semiconductor to the oxide semiconductor. (4) Parasitic capacitance is utilized by arranging a part of the source electrode and / or drain electrode and a part of the gate electrode so that they face each other across an insulating film. In (4) above, for example, parasitic capacitance can be utilized by arranging a part of one of the source electrode and drain electrode and a part of the gate electrode so that they face each other across an insulating film. In this case, the other of the source electrode and drain electrode may be arranged away from the gate electrode (for example, the distance between the other of the source electrode and drain electrode and the gate electrode may be longer than the distance between one of the source electrode and drain electrode and the gate electrode).

[0121] The semiconductor memory device 60 can read data stored in the memory cell 61 to the bit line BL by controlling the word line WL, and can also write data transferred to the bit line BL to the memory cell 61. The semiconductor memory device 50 is configured to include a memory cell array (not shown) consisting of a plurality of memory cells 61.

[0122] The following describes embodiments of the present invention, but the present invention is not limited to these embodiments.

[0123] (Examples 1-3 and Comparative Examples 1-3) Examples and comparative examples are assumed for a semiconductor device 100 similar to that shown in Figure 1. The examples and comparative examples can be manufactured by the methods described below. The following description will focus on the processes characteristic of the present invention. Processes other than those described below can be manufactured using known semiconductor device manufacturing methods, so their description will be omitted.

[0124] First, a semiconductor element 11 is formed on the semiconductor substrate 101 using a known method. Next, a first insulating film 10 is deposited. In this way, the first layer 1 is formed.

[0125] Next, a fourth insulating film 40 is formed on the first layer 1. Then, patterning, etching, and film deposition of the fourth insulating film 40 are repeatedly performed to form a capacitor 41. In this way, the fourth layer 4 is formed.

[0126] Next, a second insulating film 20 and wiring (word lines) 22 are formed on the fourth layer 4. Then, etching and film deposition of the second insulating film 20 and wiring 22 are repeatedly performed to form a transistor 21 containing an oxide semiconductor as a channel. The second layer 2 is formed in this way. The oxide semiconductor of the transistor 21 is formed from the materials shown in Table 1. The structure of the transistor 21 is the same as that shown in Figure 2.

[0127] Next, an upper electrode and wiring (bit lines) 31 are formed on the upper part of the oxide semiconductor of the transistor 21. Then, a third insulating film 30 is deposited on the second layer 2. In this way, the third layer 3 is formed.

[0128] The first insulating film 10 of the first layer 1, the fourth insulating film 40 of the fourth layer 4, the second insulating film 20 of the second layer 2, and the third insulating film 30 of the third layer 3 are each formed from the materials shown in Table 1.

[0129] The hydrogen concentrations of each insulating film in the examples and comparative examples are shown in Table 1 and Figure 10 (note that the hydrogen concentration of the fourth insulating film is omitted in the graph of Figure 10). Also, the hydrogen concentration of the first insulating film 10 is C １ The hydrogen concentration of the second insulating film 20 is set to C ２ The hydrogen concentration of the third insulating film 30 is C ３ The hydrogen concentration of the fourth insulating film 40 is C ４ The hydrogen concentration ratio "C" in this case １ / C ２ "C ３ / C ２ " and "C ４ / C ２The results are shown in Table 1. The hydrogen concentration of the insulating film can be measured by secondary ion mass spectrometry (SIMS). The hydrogen concentration is determined as the arithmetic mean of the measured values ​​(hydrogen concentration) at five measurement points in each insulating film. That is, for measurement, each insulating film is divided into five equal parts in the film thickness direction, and each part is used as a SIMS measurement point.

[0130] The operational stability of the semiconductor devices (transistors) of the example and comparative example will be evaluated by a positive bias stress test at 25°C with Vg = +20V applied, according to the following evaluation criteria, and the results shown in Table 1 are expected to be obtained. <Evaluation Criteria> A: When the threshold voltage (Vth) after 10,000 seconds is compared with the threshold voltage before the test and the difference between the two is denoted as ΔVth, ΔVth is less than 1V. The threshold voltage is defined as the gate voltage value at which the current value Id is 1nA. B: When the threshold voltage (Vth) after 10,000 seconds is compared with the threshold voltage before the test and the difference between the two is denoted as ΔVth, ΔVth is 1V or more. The threshold voltage is defined as the gate voltage value at which the current value Id is 1nA.

[0131]

[0132] The details of the materials in Table 1 are as follows: <Oxide Semiconductors> ・NC-IGO: Gallium-doped indium oxide (nanocrystal) with a bixbite structure ・NC-IGSO: Indium gallium tin oxide with a bixbite structure ・NC-IO: Indium oxide (nanocrystal) with a bixbite structure ・Amo-IGZO: Indium gallium zinc oxide with an amorphous structure ・CAAC-IGZO: Indium gallium zinc oxide with a hexagonal structure when viewed from the c-axis direction and a layered structure when viewed from a direction perpendicular to the c-axis <Insulating Films> ・SiO ２ : TEOS-SiO2, an insulating film formed using silane (SiH4) and N2O (nitrous oxide). ２ : Tetraethyl orthosilicate (TEOS, Si(OC) ２ H ５ ) ４ Insulating film formed using ) SiN:silane (SiH ４ ) and NH ３Insulating film formed using (ammonia) Note that in Table 1 and Figure 1, m"E+"n is m × 10 ｎ It can be reinterpreted as follows.

[0133] From Evaluation Table 1, it can be seen that Examples 1 to 3 exhibit excellent operational stability of semiconductor devices (transistors). For example, SiN with a high hydrogen content and SiO with a low hydrogen content ２ Even when these materials are present together, the use of an oxide semiconductor with a bigx-byte structure that is less susceptible to the effects of hydrogen ensures that operational stability is well maintained.

[0134] 100: Semiconductor device 101: Semiconductor substrate 1: First layer 10: First insulating film 11: Semiconductor element 2: Second layer 20, 20a, 20b: Second insulating film 21: Transistor 51: First electrode 52: Second electrode 53: Third electrode 55, 55': Oxide semiconductor 56: Insulating film between third electrode and oxide semiconductor 22: Wiring 3: Third layer 30: Third insulating film 31: Wiring 4: Fourth layer 40: Fourth insulating film 41: Capacitor 12: Lower capacitor electrode 42: Capacitor structure 60: Semiconductor memory device 61: Memory cell WL: Word line BL: Bit line

Claims

1. A semiconductor device comprising: a semiconductor substrate; a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film; a second layer formed above the first layer and including a channel and a second insulating film made of an oxide semiconductor; and a third layer formed above the second layer and including a third insulating film, wherein the oxide semiconductor has a bigx-byte structure.

2. The hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the first insulating film is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ The semiconductor device according to claim 1, which is 1.1 times or more.

3. The hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the first insulating film is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ A semiconductor device according to claim 1 or 2, wherein the ratio is 100 times or less.

4. Where, letting C ｍａｘ be the hydrogen concentration of the one of the second insulating film and the third insulating film having a higher hydrogen concentration, and C ｍｉｎ be the hydrogen concentration of the one of the second insulating film and the third insulating film having a lower hydrogen concentration, C ｍａｘ is at least 1.1 times C ｍｉｎ , the semiconductor device according to any one of claims 1 to 3.

5. The hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the third insulating film is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ A semiconductor device according to any one of claims 1 to 4, wherein the ratio is 100 times or less.

6. The semiconductor device according to any one of claims 1 to 5, further comprising a fourth layer formed between the first layer and the second layer, the fourth layer including a capacitor and a fourth insulating film.

7. The hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the fourth insulating film is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ The semiconductor device according to claim 6, which is 1.1 times or more.

8. The hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the fourth insulating film is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ The semiconductor device according to claim 6 or 7, wherein the ratio is 100 times or less.

9. The hydrogen concentration of the second insulating film is 1 × 10⁻⁶ １８ atoms / cm ３ ~1 x 10 ２２ toms / cm ３ The semiconductor device according to any one of claims 1 to 8.

10. The semiconductor device according to any one of claims 1 to 9, wherein the third insulating film has the highest film density among the first insulating film, the second insulating film, and the third insulating film.

11. The semiconductor device according to any one of claims 6 to 8, wherein, among the first insulating film, the second insulating film, the third insulating film, and the fourth insulating film, the third insulating film has the highest film density.

12. The semiconductor device according to any one of claims 1 to 11, wherein the transistor having the channel comprises a first electrode and a second electrode, an oxide semiconductor connecting the first electrode and the second electrode, and a third electrode adjacent to the oxide semiconductor without contact.

13. The semiconductor device according to claim 12, wherein one of the first electrode and the second electrode is arranged on the first layer side and the other is arranged on the third layer side.

14. The semiconductor device according to claim 12 or 13, wherein the oxide semiconductor connects the first electrode and the second electrode by at least partially penetrating the second insulating film.

15. The semiconductor device according to any one of claims 12 to 14, further comprising a third electrode-oxide semiconductor insulating film provided between the third electrode and the oxide semiconductor.

16. The semiconductor device according to any one of claims 12 to 14, wherein the oxide semiconductor is provided in a columnar shape penetrating the second insulating film and the third electrode, and further comprises a third electrode-oxide semiconductor insulating film provided between the third electrode and the oxide semiconductor, wherein the third electrode-oxide semiconductor insulating film is provided so as to surround at least a portion of the columnar oxide semiconductor.

17. The semiconductor device according to any one of claims 12 to 14, wherein the first electrode and the second electrode are stacked with the second insulating film in between, the oxide semiconductor has a tubular portion provided through the second insulating film, and further comprises a third electrode-oxide semiconductor insulating film provided between the third electrode and the oxide semiconductor, the third electrode-oxide semiconductor insulating film having a tubular portion provided on the inner wall of the tubular portion of the oxide semiconductor, and the third electrode having a portion provided inside the tubular portion of the third electrode-oxide semiconductor insulating film.

18. The semiconductor device according to any one of claims 1 to 17, wherein the channel length of the oxide semiconductor is 1 to 1000 nm.

19. The semiconductor device according to any one of claims 1 to 18, wherein the oxide semiconductor mainly comprises indium oxide.

20. The semiconductor device according to any one of claims 1 to 19, wherein the ratio of indium atoms to all metal atoms contained in the oxide semiconductor is 80 atomic percent or more.

21. The semiconductor device according to any one of claims 1 to 20, wherein the indium oxide content in the oxide semiconductor is 55% by mass or more.

22. The semiconductor device according to any one of claims 18 to 21, wherein the oxide semiconductor further comprises Ga or Al.

23. The semiconductor device according to any one of claims 18 to 21, wherein the oxide semiconductor further comprises Ga.

24. The semiconductor device according to any one of claims 18 to 21, wherein the oxide semiconductor further comprises Ga and Al.

25. The semiconductor device according to any one of claims 1 to 24, wherein the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) is 0.5 to 25 at%.

26. The semiconductor device according to any one of claims 1 to 25, wherein the atomic ratio of Zn to all metal elements contained in the oxide semiconductor ([Zn] / ([Zn] + [all metal elements other than Zn]) × 100) is 0 to 3 at%.

27. The semiconductor device according to any one of claims 1 to 26, wherein the oxide semiconductor substantially does not contain Zn.

28. The semiconductor device according to any one of claims 1 to 27, wherein the oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition.

29. A semiconductor device according to any one of claims 1 to 28, which is a semiconductor memory device.

30. A semiconductor substrate, a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film, a second layer formed above the first layer and including a channel and a second insulating film made of an oxide semiconductor, and a third layer formed above the second layer and including a third insulating film, wherein the hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the first insulating film is set to C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ The hydrogen concentration of the insulating film with the higher hydrogen concentration among the second insulating film and the third insulating film is C ｍａｘ The hydrogen concentration of the insulating film with the lower hydrogen concentration is C ｍｉｎ When that happens, C ｍａｘ C ｍｉｎ A semiconductor device having a channel of 1.1 times or more and 100 times or less, wherein the transistor comprising the channel comprises a first electrode and a second electrode, an oxide semiconductor connecting the first electrode and the second electrode, and a third electrode adjacent to the oxide semiconductor without contact, wherein one of the first electrode and the second electrode is arranged on the first layer side and the other is arranged on the third layer side, the oxide semiconductor is mainly composed of indium oxide and has a bigx-byte structure, and the atomic ratio of Zn to all metal elements contained in the oxide semiconductor ([Zn] / ([Zn] + [all metal elements other than Zn]) × 100) is 0 to 3 at%.

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