Semiconductor capacitor

Abstract

This semiconductor capacitor includes a first trench capacitor and a second trench capacitor connected in series. The first trench capacitor has a first conductive film and a first dielectric film laminated on the inner surfaces of a plurality of first grooves formed in the main surface of a semiconductor substrate. The second trench capacitor has a second conductive film and a second dielectric film laminated on the inner surfaces of a plurality of second grooves formed in the main surface of the semiconductor substrate. The first grooves and the second grooves are alternately arranged in a first direction parallel to the main surface of the semiconductor substrate.

Description

Semiconductor Capacitor

[0001] The present invention relates to a semiconductor capacitor.

[0002] A laminated trench capacitor is known, in which a plurality of dielectric films and conductive films are alternately laminated on a surface of a substrate and inside a groove formed on the surface of the substrate, odd-numbered conductive films counted from the substrate are electrically connected to each other, and the substrate and even-numbered conductive films counted from the substrate are electrically connected to each other.

[0003] Japanese Patent Application Laid-Open No. 2022-80628

[0004] Since a laminated trench capacitor has a structure in which a plurality of thin films made of different materials are laminated inside a groove, warpage or cracking of the substrate is likely to occur due to stress caused by the difference in thermal expansion coefficient between the respective materials.

[0005] On the other hand, when attempting to increase the breakdown voltage of a laminated trench capacitor, increasing the thickness of the dielectric film is conceivable. However, the increase in the thickness of the dielectric film further increases the influence of the aforementioned stress.

[0006] Therefore, by connecting a plurality of capacitors in series, the voltage is divided among the plurality of capacitors, so the voltage applied to each capacitor can be reduced. Accordingly, the breakdown voltage of the laminated trench capacitor can be increased without increasing the thickness of the dielectric film.

[0007] When a plurality of capacitors are connected in series to achieve higher breakdown voltage, it is desirable that the capacitance imbalance between the capacitors is small. If there is variation in capacitance values, the voltages applied to the respective capacitors will not be equal, so each capacitor needs to have a breakdown voltage that accommodates the imbalance. Therefore, the capacitance imbalance of the capacitors hinders the increase in the breakdown voltage of the entire laminated trench capacitor.

[0008] The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor capacitor capable of increasing breakdown voltage by suppressing capacitance imbalance between capacitors connected in series.

[0009] A semiconductor capacitor according to one aspect of the present invention has a first trench capacitor and a second trench capacitor connected in series. The first trench capacitor has a first dielectric film and a first conductive film laminated on the inner surfaces of a plurality of first grooves formed on the main surface of a semiconductor substrate. The second trench capacitor has a second dielectric film and a second conductive film laminated on the inner surfaces of a plurality of second grooves formed on the main surface of a semiconductor substrate. The first grooves and the second grooves are arranged alternately in a first direction parallel to the main surface of the semiconductor substrate.

[0010] According to the present invention, it is possible to provide a semiconductor capacitor that can withstand high voltage by suppressing the imbalance in capacitance values ​​between capacitors connected in series.

[0011] Figure 1 is a circuit diagram of a semiconductor capacitor 100 according to the first embodiment. Figure 2 is a plan view of the semiconductor capacitor 100. Figure 3A is a cross-sectional view of the semiconductor capacitor 100 along A1-A1" and A3"-A3 in Figure 2. Figure 3B is a cross-sectional view of the semiconductor capacitor 100 along A2-A2" in Figure 2. Figure 3C is a cross-sectional view of the semiconductor capacitor 100 along B1-B1" and B2"-B2 in Figure 2. Figure 4 is a plan view of a semiconductor capacitor 100A according to the second embodiment. Figure 5A is a cross-sectional view of the semiconductor capacitor 100A along A1-A1" in Figure 4. Figure 5B is a cross-sectional view of the semiconductor capacitor 100A along A2-A2" in Figure 4. Figure 5C is a cross-sectional view of the semiconductor capacitor 100A along A3-A3" in Figure 4. Figure 5D is a cross-sectional view of semiconductor capacitor 100A along B1-B1'' in Figure 4. Figure 5E is a cross-sectional view of semiconductor capacitor 100A along B2-B2'' in Figure 4. Figure 5F is a cross-sectional view of semiconductor capacitor 100A along B3-B3'' in Figure 4. Figure 6 is a circuit diagram of semiconductor capacitor 101 according to the third embodiment. Figure 7 is a plan view of semiconductor capacitor 101. Figure 8A is a cross-sectional view of semiconductor capacitor 101 along A1-A1'' in Figure 7. Figure 8B is a cross-sectional view of semiconductor capacitor 101 along A2-A2'' in Figure 7. Figure 8C is a cross-sectional view of semiconductor capacitor 101 along A3-A3'' in Figure 7. Figure 8D is a cross-sectional view of semiconductor capacitor 101 along B1-B1'' in Figure 7. Figure 9 is a plan view of semiconductor capacitor 101A according to the fourth embodiment. Figure 10A is a cross-sectional view of semiconductor capacitor 101A along A1-A1'' in Figure 9. Figure 10B is a cross-sectional view of the semiconductor capacitor 101A along A2-A2'' in Figure 9. Figure 10C is a cross-sectional view of the semiconductor capacitor 101A along A3-A3'' in Figure 9. Figure 10D is a cross-sectional view of the semiconductor capacitor 101A along B1-B1'' in Figure 9.

[0012] The embodiments will be described with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the ratios of the thicknesses of each part may differ from those of reality. Furthermore, it is also true that there are parts in the drawings where the dimensional relationships and ratios differ from those of other parts. The embodiments shown below are illustrative examples of devices and methods for realizing the technical idea of ​​this invention, and the embodiments of this invention do not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0013] (First Embodiment) [Semiconductor Capacitor 100] The configuration of the semiconductor capacitor 100 according to the first embodiment will be described with reference to Figures 1 to 3C. Figure 1 is a circuit diagram of the semiconductor capacitor 100. Figure 2 is a plan view of the semiconductor capacitor 100. Figure 3A is a cross-sectional view of the semiconductor capacitor 100 along A1-A1" and A3"-A3 in Figure 2. Figure 3B is a cross-sectional view of the semiconductor capacitor 100 along A2-A2" in Figure 2. Figure 3C is a cross-sectional view of the semiconductor capacitor 100 along B1-B1" and B2"-B2 in Figure 2.

[0014] In Figure 3A, the symbols for the cross-section along A1-A1" are shown, and the symbols for the cross-section along A3"-A3 are shown in parentheses. Coordinate axis AX1 indicates the coordinate axis of the cross-section along A1-A1", and coordinate axis AX2 indicates the coordinate axis of the cross-section along A3"-A3. In Figure 3C, the symbols for the cross-section along B1-B1" are shown, and the symbols for the cross-section along B2"-B2 are shown in parentheses. Coordinate axis AX3 indicates the coordinate axis of the cross-section along B1-B1", and coordinate axis AX4 indicates the coordinate axis of the cross-section along B2"-B2.

[0015] As shown in Figure 1, the semiconductor capacitor 100 according to the first embodiment has a first trench capacitor TC1 and a second trench capacitor TC2 connected in series. By connecting multiple trench capacitors TC1 and TC2 in series, the voltage applied between the first external terminal TR1 and the second external terminal TR2 is divided among the multiple trench capacitors TC1 and TC2, so that the voltage applied to each trench capacitor TC1 and TC2 can be reduced, and thus the breakdown voltage of the semiconductor capacitor 100 is improved.

[0016] A first external terminal TR1 is electrically connected to one electrode of the first trench capacitor TC1, and a second external terminal TR2 is electrically connected to one electrode of the second trench capacitor TC2. The semiconductor capacitor 100 can be electrically connected to external electronic components via the first external terminal TR1 and the second external terminal TR2.

[0017] When connecting multiple capacitors in series to achieve high voltage resistance, it is desirable to minimize the capacitance imbalance between the capacitors. The structure of a semiconductor capacitor 100 that reduces the capacitance imbalance between the first trench capacitor TC1 and the second trench capacitor TC2 will be described below with reference to Figures 2 and 3A to 3C.

[0018] As shown in Figures 2 and 3B, a plurality of first grooves 11 and a plurality of second grooves 15 are formed on the main surface 10A of the semiconductor substrate 10. Here, an example is shown in which three first grooves 11 and three second grooves 15 are formed, but the number of grooves is not limited. Each of the first grooves 11 and second grooves 15 has a concave shape that does not penetrate the semiconductor substrate 10 and is defined by its side and bottom surfaces.

[0019] In this embodiment, the XYZ coordinate system will be used for explanation. The plane parallel to the main surface 10A of the semiconductor substrate 10 is defined as the XY plane, and the direction perpendicular to the XY plane is defined as the Z direction. The area below the bottom surfaces of the first groove 11 and the second groove 15 is referred to as "downward," and the area above the bottom surfaces of the first groove 11 and the second groove 15 is referred to as "upward." Of the surfaces of each component constituting the semiconductor capacitor 100, the surface facing upward is referred to as the "upper surface," and the surface facing downward is referred to as the "lower surface."

[0020] As shown in Figure 2, the multiple first grooves 11 and the multiple second grooves 15 have the same planar shape. The three first grooves 11 and the three second grooves 15 are arranged alternately in the X direction. In this embodiment, the case where they are arranged alternately one by one in the X direction is shown, but they may be arranged alternately two or more at a time in the X direction. Each of the first grooves 11 and the second grooves 15 has a planar shape that extends in the Y direction perpendicular to the X direction. Therefore, the multiple first grooves 11 and the multiple second grooves 15 as a whole form a stripe shape. The first grooves 11 and the second grooves 15 are formed simultaneously in the same manufacturing process. By reducing the manufacturing error in the dimensions of the multiple first grooves 11 and the multiple second grooves 15, the imbalance in the capacitance value of the trench capacitor can be reduced.

[0021] The diagram shows the case where the sides of the first groove 11 and the second groove 15 are substantially perpendicular to the main surface 10A, but it is not limited to this, and the sides of the first groove 11 and the second groove 15 may be inclined. Also, the diagram shows the case where the cross-sectional area of ​​the first groove 11 and the second groove 15 along the XY plane is constant in the Z direction, but it is not limited to this, and it may vary. For example, the shape of the first groove 11 and the second groove 15 on the main surface 10A shown in Figure 2 may be a tapered shape that narrows from the main surface 10A toward the depth direction of the groove (downward: negative Z direction), or an inverse tapered shape that widens from the main surface 10A toward the depth direction of the groove (downward: negative Z direction).

[0022] As shown in Figure 3B, the first trench capacitor TC1 has a first dielectric film 12 and a first conductive film 13 laminated on the inner surface of the first groove 11. Multiple first dielectric films 12 and multiple first conductive films 13 are alternately laminated one layer at a time on the inner surface of the first groove 11. The film structure in which multiple first dielectric films 12 and multiple first conductive films 13 are alternately laminated is called the "first laminated film 14". As an example, the case in which five layers of the first dielectric film 12 and five layers of the first conductive film 13 are formed will be described. As shown in Figure 2, the first laminated film 14 is arranged not only on the inner surface of the first groove 11 but also on the main surface 10A of the semiconductor substrate 10 surrounding the first groove 11.

[0023] As shown in Figure 3B, the second trench capacitor TC2 has a second dielectric film 16 and a second conductive film 17 laminated on the inner surface of the second groove 15. Multiple second dielectric films 16 and multiple second conductive films 17 are alternately laminated on the inner surface of the second groove 15. The film structure in which multiple second dielectric films 16 and multiple second conductive films 17 are alternately laminated is called the "second laminated film 18". As an example, the case in which five layers of the first dielectric film 12 and five layers of the first conductive film 13 are formed will be described. As shown in Figure 2, the second laminated film 18 is arranged not only on the inner surface of the second groove 15 but also on the main surface 10A of the semiconductor substrate 10 surrounding the second groove 15.

[0024] As shown in Figure 2, the first laminated film 14 has a comb-like planar shape. Specifically, the first laminated film 14 has a plurality of comb teeth (three in Figure 2) extending in the Y direction along the first groove 11 and a connecting portion that connects one end of the plurality of comb teeth (the negative end in the Y direction). Similarly, the second laminated film 18 has a comb-like planar shape. Specifically, the second laminated film 18 has a plurality of comb teeth (three in Figure 2) extending in the Y direction along the second groove 15 and a connecting portion that connects one end of the plurality of comb teeth (the positive end in the Y direction). The comb teeth of the first laminated film 14 and the comb teeth of the second laminated film 18 interlock with each other at a predetermined interval. In this way, the first laminated film 14 and the second laminated film 18 have a comb-like planar shape that interlocks with each other.

[0025] The materials for the first conductive film 13 and the second conductive film 17 include, for example, n-type impurities or p-type impurities in a quantity of 10E18 to 10E21 cm. －３ Examples include polycrystalline silicon (Poly-Si), metals, and metal nitrides added at high concentrations. The conductivity of polycrystalline silicon is improved by doping it to the p-type or n-type. Examples of metals and metal nitrides include tantalum nitride (TaN) or titanium nitride (TiN), and molybdenum (Mo). Examples of the first dielectric film 12 and the second dielectric film 16 include silicon oxide film and silicon nitride film.

[0026] As shown in Figures 3A to 3C, an insulating film 71 is placed on the upper and side surfaces of the first laminated film 14 and the second laminated film 18, and on the main surface 10A of the semiconductor substrate 10 where the first laminated film 14 and the second laminated film 18 are not formed. The insulating film 71 electrically insulates the first laminated film 14, the second laminated film 18, and the first to fourth wirings 31 to 34, which will be described later. The insulating film 71 is, for example, a silicon oxide film, a silicon nitride film, or a combination thereof.

[0027] The thickness of the first dielectric film 12 and the second dielectric film 16 is uniform. This makes it possible to make the capacitance and breakdown voltage of the capacitor structure uniform. The uppermost layer (fifth layer), the first conductive film 13 and the second conductive film 17, may be formed thicker than the other conductive films in order to fill the first groove 11 or the second groove 15.

[0028] As shown in Figures 3A and 3C, the first laminated film 14 and the insulating film 71 have a plurality of contact holes 411, 413, 415, 420, 422, and 424 of different depths. At the bottom of each of the contact holes 411, 413, 415, 420, 422, and 424, the first conductive film 13 of each layer constituting the first laminated film 14 or the main surface 10A of the semiconductor substrate 10 is exposed.

[0029] As shown in Figure 3A, the odd-numbered layers of the first conductive film 13, counted from the inner surface of the first groove 11, are exposed on the bottom surface of each of the contact holes 411, 413, and 415, i.e., the 1st, 3rd, and 5th layers of the first conductive film 13. As shown in Figure 3C, the even-numbered layers of the first conductive film 13, counted from the inner surface of the first groove 11, are exposed on the bottom surface of each of the contact holes 420, 422, and 424, i.e., the 2nd and 4th layers of the first conductive film, counted from the main surface 10A of the semiconductor substrate 10, and the inner surface of the first groove 11. The insulating film 71 is also arranged on the sides of the contact holes 411, 413, 420, 422, and 424.

[0030] As shown in Figure 2, the contact holes 411, 413, and 415 (hereinafter sometimes referred to as "contact holes 41") are arranged in the X direction at the connecting portion of the first laminated film 14. For example, the contact holes 411, 413, and 415 are formed in the order of 411, 413, and 415, and this is repeated three times. On the other hand, the contact holes 420, 422, and 424 (hereinafter sometimes referred to as "contact holes 42") are arranged in the Y direction at one of the comb teeth of the first laminated film 14. For example, the contact holes 420, 422, and 424 are formed in the order of 420, 422, and 424, and this is repeated four times.

[0031] As shown in Figures 2, 3A, and 3C, the semiconductor capacitor 100 further includes a first wiring 31 and a second wiring 32. The first wiring 31 and the second wiring 32 are positioned above the first and second laminated films 14 and 18 and on the upper surface of the insulating film 71.

[0032] A portion of the first wiring 31 is embedded in each of the contact holes 41 via an insulating film 71. A portion of the second wiring 32 is embedded in each of the contact holes 42 via an insulating film 71. A portion of the first wiring 31 (first connection portion) is electrically connected to the odd-numbered layers of the first conductive film 13 exposed on the bottom surface of each contact hole 41, but is electrically insulated from other first conductive films 13 exposed on the sides of each contact hole 41 by the insulating film 71. A portion of the second wiring 32 (second connection portion) is electrically connected to the main surface 10A of the semiconductor substrate 10 or the even-numbered layers of the first conductive film 13 exposed on the bottom surface of each contact hole 42, but is electrically insulated from other first conductive films 13 exposed on the sides of each contact hole 42 by the insulating film 71.

[0033] Therefore, the first wiring 31 electrically connects the odd-numbered layers of the first conductive film 13. The second wiring 32 electrically connects the semiconductor substrate 10 and the even-numbered layers of the first conductive film 13. Thus, the first wiring 31 and the second wiring 32 can connect in parallel multiple capacitor structures formed by the first dielectric film 12 and the first conductive film 13 alternately stacked on the inner surface of the semiconductor substrate 10 and the first groove 11, thereby forming the first trench capacitor TC1 shown in Figure 1.

[0034] As shown in Figures 3A and 3C, the second laminated film 18 and the insulating film 71 have a plurality of contact holes 431, 433, 435, 440, 442, and 444 of different depths. At the bottom of each of the contact holes 431, 433, 435, 440, 442, and 444, the second conductive film 17 of each layer constituting the second laminated film 18 or the main surface 10A of the semiconductor substrate 10 is exposed.

[0035] As shown in Figure 3A, the odd-numbered layers of the second conductive film 17, counting from the inner surface of the second groove 15, are exposed on the bottom surface of each of the contact holes 431, 433, and 435, i.e., the 1st, 3rd, and 5th layers of the second conductive film 17. As shown in Figure 3C, the even-numbered layers of the first conductive film 17, counting from the inner surface of the second groove 15, are exposed on the bottom surface of each of the contact holes 440, 442, and 444, i.e., the 2nd and 4th layers of the first conductive film, i.e., the 2nd and 4th layers of the first conductive film, are exposed on the main surface 10A of the semiconductor substrate 10. The insulating film 71 is also arranged on the sides of the contact holes 431, 433, 440, 442, and 444.

[0036] As shown in Figure 2, the contact holes 431, 433, and 435 (hereinafter sometimes referred to as "contact holes 43") are arranged in the X direction at the connecting portion of the second laminated film 18. For example, the contact holes 431, 433, and 435 are formed in the order of 431, 433, and 435, and this is repeated three times. On the other hand, the contact holes 440, 442, and 444 (hereinafter sometimes referred to as "contact holes 44") are arranged in the Y direction at one of the comb teeth of the second laminated film 18. For example, the contact holes 440, 442, and 444 are formed in the order of 440, 442, and 444, and this is repeated four times.

[0037] As shown in Figures 2, 3A, and 3C, the semiconductor capacitor 100 further includes a third wiring 33 and a fourth wiring 34. The third wiring 33 and the fourth wiring 34 are positioned above the first and second laminated films 14 and 18 and on the upper surface of the insulating film 71.

[0038] A portion of the third wiring 33 is embedded in each of the contact holes 43 via an insulating film 71. A portion of the fourth wiring 34 is embedded in each of the contact holes 44 via an insulating film 71. A portion of the third wiring 33 (third connection portion) is electrically connected to the odd-numbered layers of the second conductive film 17 exposed on the bottom surface of each contact hole 43, but is electrically insulated from the other second conductive films 17 exposed on the sides of each contact hole 43 by the insulating film 71. A portion of the fourth wiring 34 (fourth connection portion) is electrically connected to the main surface 10A of the semiconductor substrate 10 or the even-numbered layers of the second conductive film 17 exposed on the bottom surface of each contact hole 44, but is electrically insulated from the other second conductive films 17 exposed on the sides of each contact hole 44 by the insulating film 71.

[0039] Therefore, the third wiring 33 electrically connects the odd-numbered layers of the second conductive film 17. The fourth wiring 34 electrically connects the semiconductor substrate 10 and the even-numbered layers of the first conductive film 17. Thus, the third wiring 33 and the fourth wiring 34 can connect in parallel multiple capacitor structures formed by the second dielectric film 16 and the second conductive film 17 alternately stacked on the inner surface of the semiconductor substrate 10 and the second groove 15, thereby forming the second trench capacitor TC2 shown in Figure 1.

[0040] As shown in Figure 2, the first wiring 31 and the third wiring have shapes symmetrical with respect to the center of the semiconductor capacitor 100. Similarly, the second wiring 32 and the fourth wiring 34 have shapes symmetrical with respect to the center of the semiconductor capacitor 100.

[0041] The first to fourth wirings 31 to 34 are, for example, single-layer films or multilayer films of two or more materials selected from the group consisting of aluminum (Al), titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W), silver (Ag), and copper (Cu).

[0042] The semiconductor substrate 10 is a conductive substrate containing a semiconductor such as silicon with a high concentration of impurities added. For example, n-type impurities or p-type impurities are added in a concentration of 10E18 to 10E21 cm. －３This is a silicon substrate added with a high concentration of the dopant. The entire semiconductor substrate 10 may have conductivity, or a conductive layer may be provided in an upper layer portion including the main surface 10A of the semiconductor substrate 10. For example, an SOI (Silicon on Insulator) substrate in which a single crystal silicon layer is formed on an oxide film may be used. In this case, the above-described high-concentration impurity may be added to the single crystal silicon layer.

[0043] A capacitor structure constituting the first trench capacitor TC1 is also formed between the main surface 10A of the semiconductor substrate 10 including the inner surface of the first trench 11 and the first conductive film 13 of the first layer. A capacitor structure constituting the second trench capacitor TC2 is also formed between the main surface 10A of the semiconductor substrate 10 including the inner surface of the second trench 15 and the second conductive film 17 of the first layer. Therefore, the first trench capacitor TC1 and the second trench capacitor TC2 are connected in series via the conductive semiconductor substrate 10. As described above, the circuit configuration shown in FIG. 1 can be obtained with the structure of the semiconductor capacitor 100 shown in FIG. 2 and FIGS. 3A to 3C.

[0044] The basic operation of the semiconductor capacitor 100 will be described.

[0045] A negative voltage with respect to the first external terminal TR1 is applied to the second external terminal TR2, or a positive voltage with respect to the second external terminal TR2 is applied to the first external terminal TR1. The applied voltage is divided between the first trench capacitor TC1 and the second trench capacitor TC2.

[0046] Positive charges are charged in the first conductive films 13 of odd layers of the first trench capacitor TC1 connected to the first external terminal TR1, and negative charges are charged on the inner surface of the first trench 11 facing the first conductive films 13 of even layers and the first conductive film 13 of the first layer, and the main surface 10A of the semiconductor substrate 10. At this time, polarization occurs inside the first dielectric film 12, generating capacitance.

[0047] Positive charges are accumulated on the even-numbered layers of the second conductive film 17 of the second trench capacitor TC2, on the inner surface of the second groove 15 facing the first layer of the second conductive film 17, and on the main surface 10A of the semiconductor substrate 10, while negative charges are accumulated on the odd-numbered layers of the second conductive film 17 connected to the second external terminal TR2. At this time, polarization occurs inside the second dielectric film 16, and capacitance is generated.

[0048] Next, an example of a method for manufacturing the semiconductor capacitor 100 will be described.

[0049] First, a first groove 11 and a second groove 15 are simultaneously formed on the semiconductor substrate 10. For example, an etching mask can be formed by photolithography, and the semiconductor substrate 10 exposed through the openings of the etching mask can be selectively etched using reactive ion etching (RIE). The etching gas for RIE is, for example, methane tetrafluoride (CF4). ４ ) or sulfur hexafluoride (SF ６ ) and the like can be used. This makes it possible to form fine patterns of first grooves 11 and second grooves 15. Alternatively, ion beam etching, which physically removes the main surface 10A of the semiconductor substrate 10 by irradiating it with a high-energy ion beam, or laser ablation, which locally heats the semiconductor substrate 10 using a high-power laser and removes a part of the semiconductor substrate 10 may be used. By forming the first grooves 11 and second grooves 15 simultaneously in the same process, variations in the planar shape and depth of the first grooves 11 and second grooves 15 can be suppressed.

[0050] Next, the first laminated film 14 and the second laminated film 18 are formed simultaneously.

[0051] First, silicon oxide films, which are examples of the first dielectric film 12 and the second dielectric film 16, are deposited on the inner surfaces of the first groove 11 and the second groove 15 and on the main surface 10A of the semiconductor substrate 10 using atomic layer deposition (ALD) or thermal CVD (chemical vapor deposition). When using the ALD or thermal CVD method, the silicon oxide film can be deposited with good coverage even when the first groove 11 and the second groove 15 are deep by reducing the pressure.

[0052] Next, a polycrystalline silicon film, such as the first conductive film 13 and the second conductive film 17, is deposited on the inner surfaces of the first groove 11 and the second groove 15 and on the main surface 10A of the semiconductor substrate 10, for example, using a CVD method such as low-pressure CVD (LPCVD) or plasma-enhanced CVD (PECVD), or a sputtering method. The LPCVD method allows for uniform control of the film thickness and provides high-quality crystallinity. On the other hand, the sputtering method allows for film formation at low temperatures. Atomic layer deposition (ALD) may also be used. Subsequently, n-type or p-type impurities are implanted into the polycrystalline silicon using an ion implantation method, and heat treatment (annealing) is performed to activate the impurities in the crystal.

[0053] As described above, a laminated film is formed by alternately stacking silicon oxide films and polycrystalline silicon films. The laminated film is patterned into the planar shape shown in Figure 2 using photolithography. This separates the laminated film, and the first laminated film 14 and the second laminated film 18 are formed simultaneously.

[0054] Contact holes 41 to 44 are formed in the first laminated film 14 and the second laminated film 18 using photolithography and dry etching. Specifically, contact holes 41 and 43 are formed simultaneously in the first laminated film 14 and the second laminated film 18, respectively. Contact holes 42 and 44 are formed simultaneously in the first laminated film 14 and the second laminated film 18, respectively. More specifically, contact holes 41 and 43 of the same depth are formed simultaneously, and contact holes 42 and 44 of the same depth are formed simultaneously. By forming them simultaneously, process variations can be suppressed. As etching methods for silicon oxide and polycrystalline silicon, for example, highly anisotropic dry etching such as reactive ion etching (RIE) or ICP etching (Inductively Coupled Plasma Etching) can be used.

[0055] An insulating film 71 is deposited on the upper and side surfaces of the first laminated film 14 and the second laminated film 18, and on the side surfaces of the contact holes 41 to 43. An aluminum film (AL film), which is an example of the first to fourth wirings 31 to 34, is formed on the insulating film 71 and embedded in the contact holes 41 to 43. The Al film is patterned using lithography and etching to form the first to fourth wirings 31 to 44 shown in Figure 2. As a method for forming the Al film, for example, ALD method, CVD method, sputtering method, or vapor deposition method can be used. By the above steps, a semiconductor capacitor 100 can be manufactured.

[0056] According to the first embodiment, the following effects and advantages can be obtained.

[0057] When processing a semiconductor wafer using a semiconductor process, variations in process characteristics may occur at different locations on the semiconductor wafer (main surface 10A of the semiconductor substrate 10). Examples include (1) non-uniformity of film deposition such as non-uniformity of film thickness due to CVD and angle dependence of sputtering, (2) variations in lithography such as uneven coating of photoresist, distortion of the optical system and edge effects, and (3) variations in etching such as non-uniform distribution of reaction gas and uneven distribution of plasma. Variations in process characteristics within the XY plane are an important factor that affects the performance of semiconductor devices.

[0058] For example, to realize a semiconductor capacitor 100 with a voltage rating of 100V, it can be achieved by connecting a first trench capacitor TC1 with a voltage rating of 50V and a second trench capacitor TC2 with a voltage rating of 50V in series. However, if an imbalance in capacitance values ​​occurs between the first trench capacitor TC1 and the second trench capacitor TC2, it becomes necessary to set the voltage rating by adding a margin to account for this imbalance to 50V. Thus, an imbalance in capacitance values ​​between the first trench capacitor TC1 and the second trench capacitor TC2 hinders the overall increase in the voltage rating of the semiconductor capacitor 100.

[0059] In this embodiment, as shown in Figure 2, a plurality of first grooves 11 and a plurality of second grooves 15 are formed alternately in the X direction (a first direction parallel to the main surface 10A). Therefore, even if fluctuations (variations) in process characteristics occur in the X direction, an imbalance in capacitance values ​​between the first trench capacitor TC1 formed in the first groove 11 and the second trench capacitor TC2 formed in the second groove 15 can be suppressed. Thus, according to this embodiment, a semiconductor capacitor 100 that can achieve high voltage resistance can be provided by suppressing an imbalance in capacitance values ​​between capacitors connected in series. Furthermore, by suppressing the variation in capacitance values ​​of capacitors connected in series, it becomes unnecessary to increase the thickness of the dielectric film to provide a voltage resistance margin, and the resulting decrease in capacitance value can be prevented.

[0060] As shown in Figure 2, the planar shapes of the first groove 11 and the second groove 15 are the same when viewed from the direction normal to the main surface 10A. This makes it possible to suppress an imbalance in capacitance values ​​between the first trench capacitor TC1 formed in the first groove 11 and the second trench capacitor TC2 formed in the second groove 15.

[0061] The first groove 11 and the second groove 15 extend in a second direction (Y direction) that is parallel to the main surface 10A of the semiconductor substrate 10 and perpendicular to the first direction (X direction). In other words, the first groove 11 and the second groove 15 have a planar shape with the Y direction as the longitudinal direction and the X direction as the short direction. As a result, the first groove 11 and the second groove 15 as a whole can form a stripe shape.

[0062] The semiconductor substrate 10 is a conductive substrate, and the first trench capacitor TC1 and the second trench capacitor TC2 are connected in series by the semiconductor substrate 10. This allows the first trench capacitor TC1 and the second trench capacitor TC2 to be connected with low resistance.

[0063] The first wiring 31 connects the odd-numbered layers of the first conductive film 13, counting from the inner surface of the first groove 11. The second wiring 32 connects the even-numbered layers of the first conductive film 13, counting from the inner surface of the first groove 11. The third wiring 33 connects the odd-numbered layers of the second conductive film 17, counting from the inner surface of the second groove 15. The fourth wiring 34 connects the even-numbered layers of the second conductive film 17, counting from the inner surface of the second groove 15. In this way, the first trench capacitor TC1 and the second trench capacitor TC2 can be formed from the first multilayer film 14 and the second multilayer film 18, respectively.

[0064] As shown in Figure 2, at least one of the first wiring 31 and the third wiring, and the second wiring 32 and the fourth wiring 34, has a shape symmetrical with respect to the center of the semiconductor capacitor 100. This suppresses the imbalance in capacitance values ​​between the first trench capacitor TC1 and the second trench capacitor TC2 due to variations in process characteristics. Not only in capacitance values, but also in parasitic resistance ESR and parasitic inductance ESL, variations between the first trench capacitor TC1 and the second trench capacitor TC2 can be suppressed. In this embodiment, the case is shown where both the first wiring 31 and the third wiring, and the second wiring 32 and the fourth wiring 34 have shapes symmetrical with respect to the center of the semiconductor capacitor 100.

[0065] At least one of the first and third connection parts and the second and fourth connection parts has a shape symmetrical with respect to the center of the semiconductor capacitor 100. This makes it possible to suppress an imbalance in capacitance values ​​between the first trench capacitor TC1 and the second trench capacitor TC2 due to variations in process characteristics. Not only in capacitance values, but also in parasitic resistance ESR and parasitic inductance ESL, variations between the first trench capacitor TC1 and the second trench capacitor TC2 can be suppressed. The first connection part is part of the first wiring 31 embedded in the contact hole 41. The second connection part is part of the second wiring 32 embedded in the contact hole 42. The third connection part is part of the third wiring 33 embedded in the contact hole 43. The fourth connection part is part of the fourth wiring 34 embedded in the contact hole 44.

[0066] The first laminated film 14 and the second laminated film 18 have a comb-like planar shape that interlocks with each other. This allows for electrical insulation between the first trench capacitor TC1 and the second trench capacitor TC2, while electrically connecting conductive films embedded in grooves to which the same capacitor belongs.

[0067] The first groove 11 and the second groove 15, the first laminated film 14 and the second laminated film 18, contact holes 41 and 43, contact holes 42 and 44 are formed simultaneously. This suppresses process variations that can cause variations in capacity values.

[0068] (Second Embodiment) In the second embodiment, a semiconductor capacitor 100A having two trench capacitors (TC1, TC2) connected in series will be described, similar to the first embodiment. The equivalent circuit of semiconductor capacitor 100A is the same as the equivalent circuit of semiconductor capacitor 100 shown in Figure 1.

[0069] Figure 4 is a plan view of a semiconductor capacitor 100A according to the second embodiment. Figure 5A is a cross-sectional view of the semiconductor capacitor 100A along A1-A1'' in Figure 4. Figure 5B is a cross-sectional view of the semiconductor capacitor 100A along A2-A2'' in Figure 4. Figure 5C is a cross-sectional view of the semiconductor capacitor 100A along A3-A3'' in Figure 2. Figure 5D is a cross-sectional view of the semiconductor capacitor 100A along B1-B1'' in Figure 4. Figure 5E is a cross-sectional view of the semiconductor capacitor 100A along B2-B2'' in Figure 4. Figure 5F is a cross-sectional view of the semiconductor capacitor 100A along B3-B3'' in Figure 2.

[0070] The first trench capacitor TC1 has a first dielectric film 12 and a first conductive film 13 laminated on the inner surfaces of a plurality of first grooves 61 formed on the main surface 10A of the semiconductor substrate 10. The second trench capacitor TC2 has a second dielectric film 16 and a second conductive film 17 laminated on the inner surfaces of a plurality of second grooves 65 formed on the main surface 10A of the semiconductor substrate 10. As shown in Figure 4, the first grooves 61 and the second grooves 65 are arranged alternately in a first direction (X direction) parallel to the main surface 10A.

[0071] Furthermore, the first groove 61 and the second groove 65 are arranged alternately in a second direction (Y direction) that is parallel to the main surface 10A of the semiconductor substrate 10 and perpendicular to the first direction (X direction). In other words, the first groove 61 and the second groove 65 do not have a stripe-like planar shape extending in the Y direction as shown in Figure 2, but rather have a dot-like planar shape in which the length in the X direction and the length in the Y direction are approximately equal.

[0072] The planar shapes of the first groove 61 and the second groove 65 are not particularly limited and can be rectangular, circular, elliptical, etc. Figure 4 shows the case where the spacing in the X and Y directions of adjacent first grooves 61 and second grooves 65 is equal, but the spacing in the X direction and the spacing in the Y direction may be different. Similar to the first embodiment, each of the first groove 61 and the second groove 65 has a concave shape that does not penetrate the semiconductor substrate 10 and is a groove defined by its side and bottom surfaces. From the viewpoint of reducing variations in capacitance values, the first groove 61 and the second groove 65 are formed simultaneously in the same manufacturing process, and the planar shapes and depths of the first groove 61 and the second groove 65 are equal to each other. The cross-sectional shapes of the first groove 61 and the second groove 65 may be tapered or inversely tapered.

[0073] As shown in Figures 4, 5B, and 5E, the first laminated film 14 is arranged not only on the inner surface of the first groove 61 but also on the main surface 10A of the semiconductor substrate 10 surrounding the first groove 61. The second laminated film 18 is arranged not only on the inner surface of the second groove 65 but also on the main surface 10A of the semiconductor substrate 10 surrounding the second groove 65. The planar shapes of the first laminated film 14 and the second laminated film 18 are not comb-shaped as shown in Figure 2, but have independent shapes corresponding to the first groove 61 and the second groove 65, respectively. In detail, the first laminated film 14 and the first groove 61 correspond one-to-one, and the second laminated film 18 and the second groove 65 correspond one-to-one. In the example shown in Figure 4, the planar shapes of the first laminated film 14 and the second laminated film 18 are square, but they may be rectangular, circular, elliptical, etc.

[0074] As shown in Figures 5A and 5C, the first laminated film 14 and the insulating film 71 have a plurality of contact holes 411, 413, 415, 420, 422, and 424 of different depths. At the bottom surface of each of the contact holes 411, 413, 415, 420, 422, and 424, the first conductive film 13 of each layer constituting the first laminated film 14 or the main surface 10A of the semiconductor substrate 10 is exposed. The contact holes 411, 413, and 415, through which the odd-numbered layers of the first conductive film 13 are exposed, are arranged in the X direction. The contact holes 420, 422, and 424, through which the even-numbered layers of the first conductive film 13 or the main surface 10A of the semiconductor substrate 10 are exposed, are arranged in the X direction.

[0075] Multiple contact holes 431, 433, 435, 440, 442, and 444 of different depths are formed in the second laminated film 18 and the insulating film 71. The bottom surface of each of the contact holes 431, 433, 435, 440, 442, and 444 exposes the second conductive film 17 of each layer constituting the second laminated film 18 or the main surface 10A of the semiconductor substrate 10. The contact holes 431, 433, and 435, through which the odd-numbered layers of the second conductive film 17 are exposed, are arranged in the X direction. The contact holes 420, 422, and 424, through which the even-numbered layers of the second conductive film 17 or the main surface 10A of the semiconductor substrate 10 are exposed, are arranged in the X direction.

[0076] The first wiring 31 and the second wiring 32 are positioned above the first laminated film 14 and on the upper surface of the insulating film 71. The third wiring 33 and the fourth wiring 34 are positioned above the second laminated film 18 and on the upper surface of the insulating film 71. A portion of the first wiring 31 is embedded in contact holes 411, 413, and 415. The first wiring 31 electrically connects the odd-numbered first conductive films of the first conductive film 13. A portion of the second wiring 32 is embedded in contact holes 420, 422, and 424. The second wiring 32 electrically connects the even-numbered first conductive films of the first conductive film 13 and the semiconductor substrate 10. A portion of the third wiring 33 is embedded in contact holes 431, 433, and 435. The third wiring 33 electrically connects the odd-numbered second conductive films of the second conductive film 17. A portion of the fourth wiring 34 is embedded in contact holes 440, 442, and 444. The fourth wiring 34 electrically connects the even-numbered layers of the second conductive film 17 to each other and to the semiconductor substrate 10.

[0077] The first wiring 31 is arranged in each of the first grooves 61. One end of each of the multiple first wirings 31 arranged along the Y direction is electrically connected by a connecting portion 31b that extends along the Y direction. Multiple connecting portions 31b are arranged along the X direction. One end of each connecting portion 31b (the negative end in the Y direction in Figure 4) is connected to the first extraction electrode 31c. This allows for the electrical connection of the odd-numbered layers of the first conductive film 13 to the first extraction electrode 31c.

[0078] The third wiring 33 is arranged in each second groove 65. One end of each of the multiple third wirings 33 arranged along the Y direction is electrically connected by a connecting portion 33b that extends in the Y direction. Multiple connecting portions 33b are arranged along the X direction. One end of each connecting portion 33b (the end on the positive Y side in Figure 4) is connected to the second extraction electrode 33c. This allows for the electrical connection of the odd-numbered layers of the second conductive film 17 to the second extraction electrode 33c.

[0079] The second wiring 32 and the fourth wiring 34 are positioned adjacent to each other, and are electrically connected. As shown in Figure 2, one second wiring 32 and one fourth wiring 34 adjacent to each other in the Y direction form a single electrode. This allows the semiconductor substrate 10, the even-numbered first conductive film 13, and the even-numbered second conductive film 17 to be electrically connected.

[0080] In this way, the semiconductor capacitor 100A can obtain the circuit configuration shown in Figure 1.

[0081] The basic operation and manufacturing method of the semiconductor capacitor 100A are the same as those described in the first embodiment, and therefore a further explanation is omitted.

[0082] According to the second embodiment, the following effects and advantages can be obtained.

[0083] The first groove 61 and the second groove 65 are arranged alternately in the first direction (X direction), and also alternately in the second direction (Y direction), which is parallel to the main surface 10A of the semiconductor substrate 10 and perpendicular to the first direction (X direction). This makes it possible to realize a two-dimensional repeating groove structure. Therefore, even if fluctuations (variations) in process characteristics occur in both the X and Y directions, it is possible to suppress the imbalance in capacitance values ​​between the first trench capacitor TC1 formed in the first groove 61 and the second trench capacitor TC2 formed in the second groove 65. Thus, according to this embodiment, it is possible to provide a semiconductor capacitor 100A that can withstand high voltage by suppressing the imbalance in capacitance values ​​between capacitors connected in series.

[0084] Furthermore, it goes without saying that since the semiconductor capacitor 100A has the same configuration as the semiconductor capacitor 100 described in the first embodiment, similar effects and benefits can be obtained.

[0085] (Third Embodiment) In the third embodiment, the case in which there are three trench capacitors connected in series will be described. As shown in Figure 6, the semiconductor capacitor 101 according to the third embodiment has a first trench capacitor TC1, a second trench capacitor TC2, and a third trench capacitor TC3 connected in series. By connecting the multiple trench capacitors TC1, TC2, and TC3 in series, the voltage applied between the first external terminal TR1 and the second external terminal TR2 is divided among the multiple trench capacitors TC1, TC2, and TC3, so that the voltage applied to each trench capacitor TC1, TC2, and TC3 can be reduced, and the breakdown voltage of the semiconductor capacitor 101 is improved.

[0086] Referring to Figures 7 and 8A to 8D, the structure of the semiconductor capacitor 101 that reduces the capacitance imbalance between the first trench capacitor TC1 to the third trench capacitor TC3 will be described. Components identical to those of the semiconductor capacitor 100 in the first embodiment are denoted by the same reference numerals and their further explanation is omitted.

[0087] Multiple first grooves 11, multiple second grooves 15, and multiple third grooves 19 are formed on the main surface 10A of the semiconductor substrate 10. Here, we show the case in which two first grooves 11, two second grooves 15, and two third grooves 19 are formed, but the number of grooves is not limited. The third grooves 19 have a concave shape that does not penetrate the semiconductor substrate 10 and are defined by the side surface and the bottom surface.

[0088] As shown in Figure 7, the multiple first grooves 11, multiple second grooves 15, and multiple third grooves 19 have the same planar shape. The multiple first grooves 11, multiple second grooves 15, and multiple third grooves 19 are arranged alternately in the X direction. In this embodiment, the case where they are arranged alternately one by one in the X direction is shown, but they may also be arranged alternately in the X direction in groups of two or more.

[0089] Each of the first groove 11, second groove 15, and third groove 19 has a planar shape that extends in the Y direction perpendicular to the X direction. Therefore, the entirety of the multiple first grooves 11, multiple second grooves 15, and multiple third grooves 19 forms a stripe shape. The first grooves 11, second grooves 15, and third grooves 19 are formed simultaneously in the same manufacturing process. By reducing the manufacturing error in the dimensions of the multiple first grooves 11, multiple second grooves 15, and multiple third grooves 19, the imbalance in the capacitance value of the trench capacitor can be reduced. Variations in parasitic resistance ESR and parasitic inductance ESL, other than capacitance value, among the characteristics of the trench capacitor can also be suppressed.

[0090] The sides of the first groove 11, the second groove 15, and the third groove 19 may be inclined with respect to the main surface 10A. The first groove 11, the second groove 15, and the third groove 19 may be tapered or reverse tapered.

[0091] As shown in Figures 8A to 8C, the third trench capacitor TC3 has a third dielectric film 20 and a third conductive film 21 laminated on the inner surface of the third groove 19. Multiple third dielectric films 20 and multiple third conductive films 21 are alternately laminated on the inner surface of the third groove 19. The film structure in which multiple third dielectric films 20 and multiple third conductive films 21 are alternately laminated is called the "third laminated film 22". As an example, the case in which five layers of the third dielectric film 20 and five layers of the third conductive film 21 are formed will be described. As shown in Figure 7, the third laminated film 22 is arranged not only on the inner surface of the third groove 19 but also on the main surface 10A of the semiconductor substrate 10 surrounding the third groove 19.

[0092] As shown in Figure 7, the first laminated film 14, the second laminated film 18, and the third laminated film 22 do not have a comb-like shape as shown in Figure 2, but rather have independent shapes corresponding to the first groove 11, the second groove 15, and the third groove 19, respectively. Specifically, the first laminated film 14 corresponds one-to-one with the first groove 61, the second laminated film 18 corresponds one-to-one with the second groove 65, and the third laminated film 22 corresponds one-to-one with the third groove 19.

[0093] As shown in Figures 7, 8A, and 8C, the first laminated film 14 and the insulating film 71 have a plurality of contact holes 411, 413, 415, 422, and 424 of different depths. At the bottom of each of the contact holes 411, 413, 415, 422, and 424, the first conductive film 13 of each layer constituting the first laminated film 14 is exposed. Unlike semiconductor capacitors 100 and 100A, no contact holes are formed that expose the main surface 10A of the semiconductor substrate 10. This is because, when a conductive semiconductor substrate 10 is used as the electrode for a capacitor, it becomes difficult to connect three trench capacitors formed on a common semiconductor substrate 10 in series.

[0094] Similarly, the second laminated film 18 and the insulating film 71 have multiple contact holes 431, 433, 435, 442, and 444 of different depths. The third laminated film 22 and the insulating film 71 also have multiple contact holes 451, 453, 455, 462, and 464 of different depths.

[0095] Contact holes 411, 413, and 415, through which the odd-numbered first conductive film 13 is exposed, are arranged in the X direction. Contact holes 422 and 424, through which the even-numbered first conductive film 13 is exposed, are arranged in the X direction. Contact holes 431, 433, and 435, through which the odd-numbered second conductive film 17 is exposed, are arranged in the X direction. Contact holes 442 and 444, through which the even-numbered second conductive film 17 is exposed, are arranged in the X direction. Contact holes 451, 453, and 455, through which the odd-numbered third conductive film 21 is exposed, are arranged in the X direction. Contact holes 462 and 464, through which the even-numbered third conductive film 21 is exposed, are arranged in the X direction. Contact holes 451, 453, and 455 are sometimes referred to as "contact holes 45," and contact holes 462 and 464 are sometimes referred to as "contact holes 46."

[0096] As shown in Figure 7, contact holes 41, 43, and 45 are arranged alternately along the X direction. Contact holes 42, 44, and 46 are also arranged alternately along the X direction. Even if variations (variations) in process characteristics occur in the X direction, an imbalance in capacitance values ​​between the first trench capacitor TC1 to the third trench capacitor TC3 can be suppressed. Variations in parasitic resistance ESR and parasitic inductance ESL, other than capacitance values, among the characteristics of the trench capacitors can be suppressed.

[0097] The semiconductor capacitor 101 further includes a fifth wiring 35 and a sixth wiring 36. The fifth wiring 35 and the sixth wiring 36 are located above the third laminated film 22 and on the upper surface of the insulating film 71.

[0098] A portion of the fifth wiring 35 is embedded in each of the contact holes 45 via an insulating film 71. A portion of the sixth wiring 36 is embedded in each of the contact holes 46 via an insulating film 71. A portion of the fifth wiring 35 (fifth connection portion) is electrically connected to the odd-numbered layers of the third conductive film 21 that are exposed on the bottom surface of each contact hole 45, but is electrically insulated from the other third conductive films 21 that are exposed on the sides of each contact hole 45 by the insulating film 71. A portion of the sixth wiring 36 (sixth connection portion) is electrically connected to the even-numbered layers of the third conductive film 21 that are exposed on the bottom surface of each contact hole 46, but is electrically insulated from the other third conductive films 21 that are exposed on the sides of each contact hole 46 by the insulating film 71.

[0099] Therefore, the fifth wiring 35 electrically connects the odd-numbered layers of the third conductive film 21. The sixth wiring 36 electrically connects the even-numbered layers of the third conductive film 21. Thus, the fifth wiring 35 and the sixth wiring 36 can connect in parallel multiple capacitor structures formed by the third dielectric film 20 and the third conductive film 21 alternately stacked on the inner surface of the third groove 19 to constitute the third trench capacitor TC3 shown in Figure 6.

[0100] The first wiring 31 is positioned adjacent to one end of the first groove 11 on the negative side in the Y direction. One end of the first wiring 31 on the negative side in the Y direction is electrically connected to the first extraction electrode 31c which extends in the X direction. This allows for the electrical connection of the odd-numbered layers of the first conductive film 13 to the first extraction electrode 31c.

[0101] The sixth wiring 36 is positioned adjacent to one end of the third groove 19 on the positive side in the Y direction. One end of the sixth wiring 36 on the positive side in the Y direction is electrically connected to the second extraction electrode 36c which extends in the Y direction. This allows for the electrical connection of the even-numbered layers of the third conductive film 21 to the second extraction electrode 36c.

[0102] The second wiring 32 and the fourth wiring 34 are positioned adjacent to each other, and are electrically connected. As shown in Figure 7, one second wiring 32 and one fourth wiring 34 adjacent to each other in the X direction form a single electrode. This allows for the electrical connection of the even-numbered first conductive film 13 and the even-numbered second conductive film 17.

[0103] The third wiring 33 and the fifth wiring 35 are positioned adjacent to each other, and are electrically connected. As shown in Figure 7, one third wiring 33 and one fifth wiring 35 adjacent to each other in the X direction form a single electrode. This allows for the electrical connection of the odd-numbered second conductive film 17 and the odd-numbered third conductive film 21.

[0104] In this way, the semiconductor capacitor 101 can obtain the circuit configuration shown in Figure 6.

[0105] Furthermore, the basic operation and manufacturing method of the semiconductor capacitor 101 are the same as those described in the first embodiment, and therefore a further explanation is omitted.

[0106] According to the third embodiment, the following effects can be obtained. Multiple first grooves 11 to multiple third grooves 19 are formed alternately in the X direction (first direction parallel to the main surface 10A). Therefore, even if fluctuations (variations) in process characteristics occur in the X direction, an imbalance in capacitance values ​​between the first trench capacitor TC1 formed in the first groove 11, the second trench capacitor TC2 formed in the second groove 15, and the third trench capacitor TC3 formed in the third groove 19 can be suppressed. Thus, according to this embodiment, a semiconductor capacitor 101 that can withstand high voltage can be provided by suppressing an imbalance in capacitance values ​​between capacitors connected in series.

[0107] As shown in Figure 7, the planar shapes of the first groove 11 to the third groove 19 are the same when viewed from the direction normal to the main surface 10A. This makes it possible to suppress an imbalance in capacitance values ​​between the first trench capacitor TC1 formed in the first groove 11, the second trench capacitor TC2 formed in the second groove 15, and the third trench capacitor TC3 formed in the third groove 19.

[0108] The first grooves 11 to the third grooves 19 extend in a second direction (Y direction) that is parallel to the main surface 10A of the semiconductor substrate 10 and perpendicular to the first direction (X direction). In other words, the first grooves 11 to the third grooves 19 have a planar shape with the Y direction as the longitudinal direction and the X direction as the short direction. As a result, the first grooves 11 to the third grooves 19 as a whole can form a stripe shape.

[0109] Furthermore, it goes without saying that since the semiconductor capacitor 101 has the same configuration as the semiconductor capacitor 100 described in the first embodiment, similar effects and benefits can be obtained.

[0110] (Fourth Embodiment) In the fourth embodiment, a semiconductor capacitor 101A having three trench capacitors (TC1, TC2, TC3) connected in series will be described, similar to the third embodiment. The equivalent circuit of semiconductor capacitor 101A is the same as the equivalent circuit of semiconductor capacitor 101 shown in Figure 6.

[0111] Figure 9 is a plan view of the semiconductor capacitor 101A according to the fourth embodiment. Figure 10A is a cross-sectional view of the semiconductor capacitor 101A along A1-A1'' in Figure 9. Figure 10B is a cross-sectional view of the semiconductor capacitor 101A along A2-A2'' in Figure 9. Figure 10C is a cross-sectional view of the semiconductor capacitor 101A along A3-A3'' in Figure 9. Figure 10D is a cross-sectional view of the semiconductor capacitor 101A along B1-B1'' in Figure 9. Components identical to those of the semiconductor capacitor 100A in the second embodiment are denoted by the same reference numerals and their further explanation is omitted.

[0112] The semiconductor capacitor 101A differs from the other semiconductor capacitors 100, 100A, and 101 in that its first to sixth wirings 31 to 36 are arranged in multiple layers (two layers in this case). Specifically, as shown in Figures 10A to 10D, the second wiring 32, third wiring 33, fourth wiring 34, and fifth wiring 35 are arranged in the wiring layer (first wiring layer) closer to the semiconductor substrate 10, while the first wiring 31 and sixth wiring 36 are arranged in the wiring layer (second wiring layer) further away from the semiconductor substrate 10.

[0113] As shown in Figure 9, the first grooves 61 to the third grooves 69 are alternately arranged in a first direction (X direction) parallel to the main surface 10A. Furthermore, the first grooves 61 to the third grooves 69 are also alternately arranged in a second direction (Y direction) parallel to the main surface 10A of the semiconductor substrate 10 and perpendicular to the first direction (X direction). In other words, the first grooves 61 to the third grooves 69 do not have a stripe-like planar shape extending in the Y direction as shown in Figure 7, but rather have a dot-like planar shape with approximately equal lengths in the X direction and Y direction, similar to Figure 4. From the viewpoint of reducing variations in capacitance values, the first grooves 61 to the third grooves 69 are formed simultaneously in the same manufacturing process, and the planar shapes and depths of the first grooves 61 to the third grooves 69 are equal to each other.

[0114] As shown in Figures 9, 10B, and 10D, the third laminated film 22 is arranged not only on the inner surface of the third groove 69, but also on the main surface 10A of the semiconductor substrate 10 surrounding the third groove 69. The planar shape of the third laminated film 22 is not comb-like as shown in Figure 7, but has an independent shape corresponding to each of the third grooves 69. In detail, there is a one-to-one correspondence between the third laminated film 22 and the third groove 69.

[0115] As shown in Figure 9, contact holes 41, 43, and 45 are arranged alternately along the X direction. Contact holes 42, 44, and 46 are also arranged alternately along the X direction. Even if fluctuations (variations) in process characteristics occur in the X direction, an imbalance in capacitance values ​​between the first trench capacitor TC1 to the third trench capacitor TC3 can be suppressed.

[0116] The first wiring 31 is positioned adjacent to the negative side in the Y direction of the first groove 61 and along the X direction. One end of the first wiring 31 on the negative side in the X direction is electrically connected to a connecting portion 31b that extends in the Y direction. One end of the connecting portion 31b on the negative side in the Y direction is electrically connected to the first extraction electrode 31c. This allows for the electrical connection of the odd-numbered layers of the first conductive film 13 to the first extraction electrode 31c.

[0117] The sixth wiring 36 is positioned adjacent to the positive side in the Y direction of the third groove 69 and along the X direction. One end of the sixth wiring 36 on the positive side in the X direction is electrically connected to a connecting portion 36b that extends in the Y direction. One end of the connecting portion 36b on the positive side in the Y direction is electrically connected to the second extraction electrode 36c. This allows for the electrical connection of the odd-numbered layers of the third conductive film 21 to the second extraction electrode 36c.

[0118] The second wiring 32 and the third wiring 33 are arranged adjacent to each other and are electrically connected. As shown in Figure 9, one second wiring 32 and one third wiring 33 adjacent to each other in the Y direction form a single electrode. This allows the even-numbered first conductive film 13 and the odd-numbered second conductive film 17 to be electrically connected. One end of the multiple second wirings 32 arranged along the Y direction on the negative side in the X direction is electrically connected to a first connecting portion 32b extending in the Y direction. One end of the first connecting portion 32b on the negative side in the Y direction is electrically connected to a second connecting portion 32c extending in the X direction.

[0119] The fourth wiring 34 and the fifth wiring 35 are arranged adjacent to each other, and the fourth wiring 34 and the fifth wiring 35 are electrically connected. As shown in Figure 9, one fourth wiring 34 and one fifth wiring 35 adjacent to each other in the Y direction form a single electrode. This allows the even-numbered second conductive film 17 and the odd-numbered third conductive film 21 to be electrically connected. One end of the multiple fourth wirings 34 arranged along the Y direction, on the positive side in the X direction, is electrically connected to the first connecting portion 34b extending in the Y direction. One end of the first connecting portion 34b, on the positive side in the Y direction, is electrically connected to the second connecting portion 34c extending in the X direction.

[0120] In this way, the semiconductor capacitor 101A can obtain the circuit configuration shown in Figure 6.

[0121] The basic operation and manufacturing method of the semiconductor capacitor 101A are the same as those described in the first embodiment, and therefore a further explanation is omitted.

[0122] According to the fourth embodiment, the following effects can be obtained. The first grooves 61 to the third grooves 69 are arranged alternately in the first direction (X direction), and also alternately in the second direction (Y direction) which is parallel to the main surface 10A of the semiconductor substrate 10 and perpendicular to the first direction (X direction). This makes it possible to realize a two-dimensional repeating groove structure. Therefore, even if fluctuations (variations) in process characteristics occur in both the X and Y directions, it is possible to suppress the imbalance in capacitance values ​​between the first trench capacitor TC1 to the third trench capacitor TC3. Thus, according to this embodiment, it is possible to provide a semiconductor capacitor 101A that can withstand high voltage by suppressing the imbalance in capacitance values ​​between capacitors connected in series.

[0123] As described above, embodiments of the present invention have been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting the invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0124] For example, in the embodiment, the first conductive film 13 to the third conductive film 21 are shown to be conductive polycrystalline silicon. However, the conductive film 20 may be made of other conductive materials, such as conductive polysilicon carbide (poly-SiC), silicon germanium (SiGe), or aluminum (Al).

[0125] 10 Semiconductor substrate 10A Main surface 11, 61 First groove 12 First dielectric film 13 First conductive film 14 First multilayer film 15, 65 Second groove 16 Second dielectric film 17 Second conductive film 18 Second multilayer film 19, 69 Third groove 20 Third dielectric film 21 Third conductive film 22 Third multilayer film 31 First wiring 32 Second wiring 33 Third wiring 34 Fourth wiring 35 Fifth wiring 36 Sixth wiring 41-46 Contact holes 71 Insulating film 100, 100A, 101, 101A Semiconductor capacitor 411, 413, 415, 420, 422, 424, 431, 433, 435, 440, 442, 444, 451, 453, 455, 462, 464 Contact holes TC1 First trench capacitor TC2 Second trench capacitor TC3 Third trench capacitor TR1 First external terminal TR2 Second external terminal

Claims

1. A semiconductor capacitor having a first trench capacitor and a second trench capacitor connected in series, wherein the first trench capacitor has a first dielectric film and a first conductive film laminated on the inner surface of a plurality of first grooves formed on the main surface of a semiconductor substrate, and the second trench capacitor has a second dielectric film and a second conductive film laminated on the inner surface of a plurality of second grooves formed on the main surface, and the first grooves and the second grooves are alternately arranged in a first direction parallel to the main surface.

2. The semiconductor capacitor according to claim 1, wherein the planar shapes of the first groove and the second groove are the same when viewed from the direction normal to the main surface.

3. The semiconductor capacitor according to claim 1 or 2, wherein the first groove and the second groove extend in a second direction parallel to the main surface of the semiconductor substrate and perpendicular to the first direction.

4. The semiconductor capacitor according to claim 1 or 2, wherein the first groove and the second groove are alternately arranged in a second direction parallel to the main surface of the semiconductor substrate and perpendicular to the first direction.

5. The semiconductor capacitor according to any one of claims 1 to 4, wherein the semiconductor substrate is a conductive substrate, and the first trench capacitor and the second trench capacitor are connected in series by the semiconductor substrate.

6. A semiconductor capacitor according to any one of claims 1 to 4, further comprising: a first wiring that connects odd-numbered layers of the first conductive film, counted from the inner surface of the first groove; a second wiring that connects even-numbered layers of the first conductive film, counted from the inner surface of the first groove; a third wiring that connects odd-numbered layers of the second conductive film, counted from the inner surface of the second groove; and a fourth wiring that connects even-numbered layers of the second conductive film, counted from the inner surface of the second groove, wherein the first wiring or the second wiring is electrically connected to the third wiring or the fourth wiring.

7. The semiconductor capacitor according to claim 6, wherein, when viewed from the direction normal to the main surface, at least one of the first and third wirings and the second and fourth wirings has a shape symmetrical with respect to the center of the semiconductor capacitor.

8. A semiconductor capacitor according to claim 6 or 7, further comprising: a plurality of first connection portions for electrically connecting the first wiring and the odd-numbered first conductive films; a plurality of second connection portions for electrically connecting the second wiring and the even-numbered first conductive films; a plurality of third connection portions for electrically connecting the third wiring and the odd-numbered second conductive films; and a plurality of fourth connection portions for electrically connecting the fourth wiring and the even-numbered second conductive films, wherein, when viewed from the direction normal to the main surface, at least one of the first connection portions and the third connection portions and the second connection portions and the fourth connection portions have a shape symmetrical with respect to the center of the semiconductor capacitor.

9. The semiconductor capacitor according to any one of claims 1 to 8, wherein the first laminated film having the first dielectric film and the first conductive film, and the second laminated film having the second dielectric film and the second conductive film, have a comb-like planar shape that interlocks with each other.

10. The semiconductor capacitor according to claim 1, further comprising a third trench capacitor connected in series with the first trench capacitor or the second trench capacitor, wherein the third trench capacitor has a third dielectric film and a third conductive film laminated on the inner surfaces of a plurality of third grooves formed on the main surface, and the first to third grooves are arranged alternately in the first direction.

11. The semiconductor capacitor according to claim 10, wherein the planar shapes of the first to third grooves are the same when viewed from the direction normal to the main surface.

12. The semiconductor capacitor according to claim 10 or 11, wherein the first to third grooves extend in a second direction parallel to the main surface and perpendicular to the first direction.

13. The semiconductor capacitor according to claim 10 or 11, wherein the first to third grooves are alternately arranged in a second direction parallel to the main surface of the semiconductor substrate and perpendicular to the first direction.

14. The first conductive film further comprises: a first wiring that connects odd-numbered layers of the first conductive film counted from the inner surface of the first groove; a second wiring that connects even-numbered layers of the first conductive film counted from the inner surface of the first groove; a third wiring that connects odd-numbered layers of the second conductive film counted from the inner surface of the second groove; a fourth wiring that connects even-numbered layers of the second conductive film counted from the inner surface of the second groove; a fifth wiring that connects odd-numbered layers of the third conductive film counted from the inner surface of the third groove; and a sixth wiring that connects even-numbered layers of the third conductive film counted from the inner surface of the third groove, wherein the first or second wiring is electrically connected to the third or fourth wiring. The semiconductor capacitor according to any one of claims 10 to 13, wherein the third or fourth wiring, which is not electrically connected to the first or second wiring, is electrically connected to the fifth or sixth wiring.

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