Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of suppressing the occurrence of cracks in a laminate.　A first main surface-side external electrode portion 502 and a second main surface-side external electrode portion in this multilayer ceramic capacitor 1 include a main surface-side base electrode layer 502 disposed on a first main surface TS1 and a second main surface TS2, a main surface-side conductive resin layer 602 disposed on the main surface-side base electrode layer 502, and a main surface-side plating layer 702 disposed on the main surface-side conductive resin layer 602. The main surface-side base electrode layer 502 has: a main surface-side discontinuous portion DCT which is a discontinuous portion where no electrode exists; and a main surface inner base electrode layer 5021 disposed on the center side of a laminate 10 in a length direction L, and a main surface outer base electrode layer 5022 disposed on an end surface LS side of the laminate 10 in the length direction L, with the main surface-side discontinuous portion DCT interposed therebetween.

Description

Multilayer ceramic capacitor

[0001] This invention relates to a multilayer ceramic capacitor.

[0002] In conventional multilayer ceramic capacitors using resin electrodes as external electrodes (for example, Patent Document 1), the configuration is such that a resin electrode, Ni, and Sn plating are arranged in that order on top of a base electrode. In the above configuration, the resin electrode uses Ag as a conductive filler and epoxy resin in the resin part, and conductivity of the terminal electrodes is ensured by contact of the conductive filler.

[0003] Japanese Patent Application Publication No. 11-162771

[0004] Incidentally, tensile stress can occur in the underlying electrode layer during thermal shock cycles, etc. It was anticipated that the tensile stress generated in the underlying electrode layer on the end face side could be transmitted to the tip of the underlying electrode layer on the main face side, potentially causing cracks in the laminate, and countermeasures were needed.

[0005] The present invention aims to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks in the laminate.

[0006] The multilayer ceramic capacitor of the present invention comprises a laminated body having a plurality of laminated dielectric layers and a plurality of internal electrode layers, a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, wherein the first external electrode comprises a first end surface side external electrode portion disposed on the first end surface, and a first main surface side external electrode portion connected to the first end surface side external electrode portion and disposed on a part of the first end surface side of the first main surface and the second main surface, and the second external electrode comprises a second end surface side external electrode portion disposed on the second end surface, and a second end surface side external electrode portion connected to the second end surface side external electrode portion and disposed on a part of the second end surface side of the first main surface and the second main surface The first end face side external electrode portion and the second end face side external electrode portion are arranged on the first end face and the second end face, and each comprises an end face side base electrode layer arranged on the first end face and the second end face, an end face side conductive resin layer arranged on the end face side base electrode layer, and an end face side plating layer arranged on the end face side conductive resin layer, and the first main face side external electrode portion and the second main face side external electrode portion are arranged on the first main face and the second main face The laminate comprises a main surface-side base electrode layer, a main surface-side conductive resin layer disposed on the main surface-side base electrode layer, and a main surface-side plating layer disposed on the main surface-side conductive resin layer, wherein the main surface-side base electrode layer has a main surface-side discontinuous portion which is a discontinuous portion where no electrodes are present, a first main surface-inside base electrode layer disposed on the central side of the laminate in the longitudinal direction, sandwiching the main surface-side discontinuous portion, and a second main surface-outside base electrode layer disposed on the end face side of the laminate in the longitudinal direction.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks in the laminate.

[0008] This is an external perspective view of the multilayer ceramic capacitor of this embodiment. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line II-II. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line III-III. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IV-IV. This is a cross-sectional view corresponding to Figure 4A in a modified example. This is a schematic diagram showing the laminate after a part of the base electrode has been removed. This is a schematic diagram showing an example of the configuration of a two-gang multilayer ceramic capacitor. This is a schematic diagram showing an example of the configuration of a three-gang multilayer ceramic capacitor. This is a schematic diagram showing an example of the configuration of a four-gang multilayer ceramic capacitor.

[0009] <Embodiment> Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to the first embodiment of this disclosure will be described with reference to Figures 1 to 5. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 1 along the line II-II. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line III-III. Figure 4A is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IV-IV. Figure 4B is a cross-sectional view corresponding to Figure 4A in a modified example. Figure 5 is a schematic diagram showing the laminate after a part of the base electrode has been removed.

[0010] The multilayer ceramic capacitor 1 comprises a laminate 10 and an external electrode 40.

[0011] Figures 1 to 5 show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T, which is the height direction of the multilayer ceramic capacitor 1 and the laminate 10, corresponds to the Z direction. Here, the cross section shown in Figure 2 is also called the LT cross section. The cross section shown in Figure 3 is also called the WT cross section. The cross sections shown in Figures 4A and 4B are also called the LW cross section.

[0012] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the lamination direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the lamination direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the lamination direction T and the width direction W.

[0013] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0014] The dimensions of the laminate 10 are not particularly limited, but if the dimension in the length direction L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. If the dimension in the stacking direction T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.1 mm or more and 10 mm or less. If the dimension in the width direction W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 10 mm or less.

[0015] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12A and a second main surface-side outer layer 12B, which are arranged to sandwich the inner layer 11 in the lamination direction T.

[0016] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0017] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as those mentioned above. Furthermore, the dielectric material may be obtained by adding minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components.

[0018] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 10 or more and 700 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0019] The plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The plurality of first internal electrode layers 31 are arranged on a plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on a plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10 via the dielectric layers 20. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0020] The first internal electrode layer 31 has a first opposing portion 31A that faces the second internal electrode layer 32, and a first leading portion 31B that is drawn out from the first opposing portion 31A to the first end face LS1. The first leading portion 31B is exposed to the first end face LS1.

[0021] The second internal electrode layer 32 has a second opposing portion 32A that faces the first internal electrode layer 31, and a second leading portion 32B that is drawn out from the second opposing portion 32A to the second end face LS2. The second leading portion 32B is exposed to the second end face LS2.

[0022] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0023] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0024] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0026] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 700 or less.

[0027] The first main surface-side outer layer 12A is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12A is an aggregate of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface-side outer layer 12A may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0028] The second main surface-side outer layer 12B is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 12B is an aggregate of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface-side outer layer 12B may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 4A and 4B show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0030] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3, 4A, and 4B show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0031] The laminate 10 has an end-face outer layer. The end-face outer layer has a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end-face outer layer LG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figures 2, 4A, and 4B show the range L in the longitudinal direction of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called an L gap or end gap.

[0032] The external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side and a second external electrode 40B positioned on the second end face LS2 side.

[0033] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A is also positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2. The first external electrode 40A may also be positioned on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0034] In this embodiment, the first external electrode 40A has a first end face side external electrode portion 40A1, a first main face side external electrode portion 40A2, and a first side side external electrode portion 40A3. The first end face side external electrode portion 40A1 is positioned on the first end face LS1. The first main face side external electrode portion 40A2 is connected to the first end face side external electrode portion 40A1 and is positioned on a part of the first main face TS1 and the second main face TS2 on the side of the first end face LS1. The first side side external electrode portion 40A3 is connected to the first end face side external electrode portion 40A1 and is positioned on a part of the first side WS1 and the second side WS2 on the side of the first end face LS1.

[0035] Thus, the first external electrode 40A is formed extending from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0036] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B is also disposed on a part of the first main surface TS1 and a part of the second main surface TS2. The first external electrode 40A may also be disposed on a part of the first side surface WS1 and a part of the second side surface WS2.

[0037] In the present embodiment, the second external electrode 40B includes a second end-face-side external electrode portion 40B1, a second main-surface-side external electrode portion 40B2, and a second side-surface-side external electrode portion 40B3. The second end-face-side external electrode portion 40B1 is disposed on the second end face LS2. The second main-surface-side external electrode portion 40B2 is connected to the second end-face-side external electrode portion 40B1, and is disposed on a part of the second end face LS2 side on the first main surface TS1 and the second main surface TS2. The second side-surface-side external electrode portion 40B3 is connected to the second end-face-side external electrode portion 40B1, and is disposed on a part of the first end face LS1 side on the first side surface WS1 and the second side surface WS2.

[0038] As described above, the second external electrode 40B is formed to extend from above the second end face LS2 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0039] As described above, in the multilayer body 10, capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 opposing the second opposing portion 32A of the second internal electrode layer 32 with the dielectric layer 20 interposed therebetween. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0040] The first external electrode 40A includes a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. The first plating layer 70A includes a first Ni plating layer 71A serving as a lower plating layer and a first Sn plating layer 72A serving as an upper plating layer.

[0041] The first base electrode layer 50A includes a first end surface side base electrode layer 50A1, a first main surface side base electrode layer 50A2, and a first side surface side base electrode layer 50A3.

[0042] The first conductive resin layer 60A includes a first end surface side conductive resin layer 60A1, a first main surface side conductive resin layer 60A2, and a first side surface side conductive resin layer 60A3.

[0043] The first plating layer 70A includes a first end surface side plating layer 70A1, a first main surface side plating layer 70A2, and a first side surface side plating layer 70A3.

[0044] The first Ni plating layer 71A includes a first end surface side Ni plating layer 71A1, a first main surface side Ni plating layer 71A2, and a first side surface side Ni plating layer 71A3.

[0045] The first Sn plating layer 72A includes a first end surface side Sn plating layer 72A1, a first main surface side Sn plating layer 72A2, and a first side surface side Sn plating layer 72A3.

[0046] The second external electrode 40B includes a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. The second plating layer 70B includes a second Ni plating layer 71B as a lower plating layer and a second Sn plating layer 72B as an upper plating layer.

[0047] The second base electrode layer 50B includes a second end surface side base electrode layer 50B1, a second main surface side base electrode layer 50B2, and a second side surface side base electrode layer 50B3.

[0048] The second conductive resin layer 60B includes a second end surface side conductive resin layer 60B1, a second main surface side conductive resin layer 60B2, and a second side surface side conductive resin layer 60B3.

[0049] The second plating layer 70B includes a second end surface side plating layer 70B1, a second main surface side plating layer 70B2, and a second side surface side plating layer 70B3.

[0050] The second Ni plating layer 71B includes a second end-face Ni plating layer 71B1, a second main-face Ni plating layer 71B2, and a second side-side Ni plating layer 71B3.

[0051] The second Sn plating layer 72B comprises a second end face side Sn plating layer 72B1, a second main face side Sn plating layer 72B2, and a second side side Sn plating layer 72B3.

[0052] Here, the basic configuration of each layer constituting the first external electrode 40A and the second external electrode 40B is the same. Furthermore, the first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to the cross-section LW at the center of the length L of the multilayer ceramic capacitor 1. Therefore, when there is no need to specifically distinguish between the first external electrode 40A and the second external electrode 40B, they may be collectively referred to as the external electrode 40.

[0053] Furthermore, if there is no need to specifically distinguish between the first end-face side external electrode portion 40A1 and the second end-face side external electrode portion 40B1, the first end-face side external electrode portion 40A1 and the second end-face side external electrode portion 40B1 may be collectively referred to as the end-face side external electrode portion 401. Also, if there is no need to specifically distinguish between the first main-face side external electrode portion 40A2 and the second main-face side external electrode portion 40B2, the first main-face side external electrode portion 40A2 and the second main-face side external electrode portion 40B2 may be collectively referred to as the main-face side external electrode portion 402. Also, if there is no need to specifically distinguish between the first side-side external electrode portion 40A3 and the second side-side external electrode portion 40B3, the first side-side external electrode portion 40A3 and the second side-side external electrode portion 40B3 may be collectively referred to as the side-side external electrode portion 403.

[0054] Furthermore, if there is no need to distinguish between the first end-face-side base electrode layer 50A1 and the second end-face-side base electrode layer 50B1, the first end-face-side base electrode layer 50A1 and the second end-face-side base electrode layer 50B1 may be collectively referred to as the end-face-side base electrode layer 501. Also, if there is no need to distinguish between the first main-face-side base electrode layer 50A2 and the second main-face-side base electrode layer 50B2, the first main-face-side base electrode layer 50A2 and the second main-face-side base electrode layer 50B2 may be collectively referred to as the main-face-side base electrode layer 502. Furthermore, when there is no need to specifically distinguish between the first side-side base electrode layer 50A3 and the second side-side base electrode layer 50B3, the first side-side base electrode layer 50A3 and the second side-side base electrode layer 50B3 may be collectively referred to as the side-side base electrode layer 503.

[0055] Furthermore, when there is no need to specifically distinguish between the first main surface inner substrate electrode layer 50A21 and the second main surface inner substrate electrode layer 50B21, which will be described later, the first main surface inner substrate electrode layer 50A21 and the second main surface inner substrate electrode layer 50B21 may be collectively referred to as the main surface inner substrate electrode layer 5021.

[0056] Furthermore, when there is no need to specifically distinguish between the first main surface outer substrate electrode layer 50A22 and the second main surface outer substrate electrode layer 50B22, which will be described later, the first main surface outer substrate electrode layer 50A22 and the second main surface outer substrate electrode layer 50B22 may be collectively referred to as the main surface outer substrate electrode layer 5022.

[0057] Furthermore, when there is no need to specifically distinguish between the first side inner substrate electrode layer 50A31 and the second side inner substrate electrode layer 50B31, which will be described later, the first side inner substrate electrode layer 50A31 and the second side inner substrate electrode layer 50B31 may be collectively referred to as the side inner substrate electrode layer 5031.

[0058] Furthermore, when there is no need to specifically distinguish between the first side outer substrate electrode layer 50A32 and the second side outer substrate electrode layer 50B32, which will be described later, the first side outer substrate electrode layer 50A32 and the second side outer substrate electrode layer 50B32 may be collectively referred to as the side outer substrate electrode layer 5032.

[0059] Furthermore, if there is no need to specifically distinguish between the first end-face side conductive resin layer 60A1 and the second end-face side conductive resin layer 60B1, the first end-face side conductive resin layer 60A1 and the second end-face side conductive resin layer 60B1 may be collectively referred to as the end-face side conductive resin layer 601. Also, if there is no need to specifically distinguish between the first main surface side conductive resin layer 60A2 and the second main surface side conductive resin layer 60B2, the first main surface side conductive resin layer 60A2 and the second main surface side conductive resin layer 60B2 may be collectively referred to as the main surface side conductive resin layer 602. Furthermore, if there is no need to specifically distinguish between the first side-side conductive resin layer 60A3 and the second side-side conductive resin layer 60B3, the first side-side conductive resin layer 60A3 and the second side-side conductive resin layer 60B3 may be collectively referred to as the side-side conductive resin layer 603.

[0060] Furthermore, if there is no need to distinguish between the first end-face plating layer 70A1 and the second end-face plating layer 70B1, the first end-face plating layer 70A1 and the second end-face plating layer 70B1 may be collectively referred to as the end-face plating layer 701. Also, if there is no need to distinguish between the first main surface plating layer 70A2 and the second main surface plating layer 70B2, the first main surface plating layer 70A2 and the second main surface plating layer 70B2 may be collectively referred to as the main surface plating layer 702. Furthermore, if there is no need to distinguish between the first side-side plating layer 70A3 and the second side-side plating layer 70B3, the first side-side plating layer 70A3 and the second side-side plating layer 70B3 may be collectively referred to as the side-side plating layer 703.

[0061] The base electrode layer 50 has a first base electrode layer 50A and a second base electrode layer 50B.

[0062] The first base electrode layer 50A is positioned on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. The first base electrode layer 50A is also positioned on a part of the first main surface TS1 and a part of the second main surface TS2. The first base electrode layer 50A may also be positioned on a part of the first side surface WS1 and a part of the second side surface WS2. In this embodiment, the first base electrode layer 50A is formed extending from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0063] More specifically, the first base electrode layer 50A is configured such that the first end face base electrode layer 50A1 described above is placed on the first end face LS1, the first main surface base electrode layer 50A2 described above extends from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, and the first side surface base electrode layer 50A3 described above extends from the first end face LS1 to a part of the first side surface WS1 and a part of the second side surface WS2.

[0064] The second base electrode layer 50B is located on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. The second base electrode layer 50B is also located on a portion of the first main surface TS1 and a portion of the second main surface TS2. The second base electrode layer 50B may also be located on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second base electrode layer 50B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0065] More specifically, the second base electrode layer 50B is configured such that the second end face base electrode layer 50B1 described above is placed on the second end face LS2, the second main face base electrode layer 50B2 described above extends from the second end face LS2 to a part of the first main face TS1 and a part of the second main face TS2, and the second side base electrode layer 50B3 described above extends from the second end face LS2 to a part of the first side surface WS1 and a part of the second side surface WS2.

[0066] The main surface-side base electrode layer 502 comprises a main surface-inside base electrode layer 5021, a main surface-outside base electrode layer 5022, and a main surface-side discontinuity DCT. The main surface-outside base electrode layer 5022 is positioned on the end face LS side of the laminate 10. The main surface-inside base electrode layer 5021 is positioned on the central side of the laminate 10, with the main surface-side discontinuity DCT in between. In this specification, when describing the arrangement of the configuration of the multilayer ceramic capacitor 1, when comparing the distance between the center of the laminate 10 and the configuration in the length direction L, and the distance between the end face LS of the laminate 10 and the configuration in question, the configuration is positioned on the central side of the laminate 10 when it is closer to the center of the laminate 10, and the configuration is positioned on the end face LS side of the laminate 10 when it is closer to the end face LS of the laminate 10.

[0067] Furthermore, if the base electrode layer 50 is also arranged on the first side surface WS1 and the second side surface WS2, as shown in Figure 4A, the side base electrode layer 503 may have a side inner base electrode layer 5031, a side outer base electrode layer 5032, and a side discontinuity DCW. The side outer base electrode layer 5032 is arranged on the end face LS side of the laminate 10 in the length direction L. The side inner base electrode layer 5031 is arranged on the central side of the laminate 10 in the length direction L, with the side discontinuity DCW in between. However, it is not limited to this, and for example, as shown in Figure 4B, the side base electrode layer 503 does not have to have a side inner base electrode layer 5031, a side outer base electrode layer 5032, and a side discontinuity DCW. However, it is preferable that the side-side base electrode layer 503 has a side-inner base electrode layer 5031, a side-outer base electrode layer 5032, and a side-side discontinuity portion DCW.

[0068] The first main surface-side base electrode layer 50A2 comprises a first main surface-inner base electrode layer 50A21, a first main surface-outer base electrode layer 50A22, and a main surface-side discontinuity DCT. The second main surface-side base electrode layer 50B2 comprises a second main surface-inner base electrode layer 50B21, a second main surface-outer base electrode layer 50B22, and a main surface-side discontinuity DCT. The main surface-side discontinuity DCT is a discontinuous portion in the main surface-side base electrode layer 502 where no electrodes exist. In this embodiment, a portion of the main surface-side conductive resin layer 602 is arranged in the main surface-side discontinuity DCT.

[0069] Furthermore, if the base electrode layer 50 is also arranged on the first side surface WS1 and the second side surface WS2, the first side surface base electrode layer 50A3 may have a first side inner base electrode layer 50A31, a first side outer base electrode layer 50A32, and a side discontinuity DCW. Also, the second side surface base electrode layer 50B3 may have a second side inner base electrode layer 50B31, a second side outer base electrode layer 50B32, and a side discontinuity DCW. In this case, the side discontinuity DCW is a discontinuous portion of the side surface base electrode layer 503 where no electrodes exist. In this embodiment, a part of the side conductive resin layer 603 is arranged in the side discontinuity DCW.

[0070] The main surface discontinuity DCT is positioned on the central side of the laminate 10, beyond the ridge between the end face LS and the main surface TS of the laminate 10. Therefore, the main surface outer base electrode layer 5022 is positioned on the plane of the main surface TS of the laminate 10. Because the main surface outer base electrode layer 5022 is positioned beyond the ridge of the laminate 10 and on the plane of the main surface TS, a longer distance can be secured at the interface between the surface of the laminate 10 and the base electrode layer 50, connecting the end of the internal electrode layer 30 exposed on the end face LS of the laminate 10 and the main surface discontinuity DCT. Thus, it is possible to provide a multilayer ceramic capacitor 1 that can suppress crack generation in the laminate 10 while ensuring moisture resistance by suppressing liquid penetration to the end of the internal electrode layer 30.

[0071] Furthermore, if a side discontinuity DCW is also provided in the side base electrode layer 503, the side discontinuity DCW is positioned on the central side of the laminate 10, beyond the ridge between the end face LS and the side WS of the laminate 10. Therefore, the side outer base electrode layer 5032 is positioned on the plane of the main surface TS of the laminate 10. Because the side outer base electrode layer 5032 extends beyond the ridge of the laminate 10 to the plane of the side WS, a longer distance can be secured at the interface between the surface of the laminate 10 and the base electrode layer 50, connecting the end of the internal electrode layer 30 exposed on the end face LS of the laminate 10 and the side discontinuity DCW. Thus, it is possible to provide a multilayer ceramic capacitor 1 that can suppress crack generation in the laminate 10 while ensuring moisture resistance by suppressing liquid penetration to the end of the internal electrode layer 30.

[0072] Furthermore, if a side discontinuity DCW is also provided in the side base electrode layer 503, it is preferable that the main surface discontinuity DCT and the side discontinuity DCW are connected at the ridge of the laminate 10. It is preferable that the main inner base electrode layer 5021 and the side inner base electrode layer 5031 are connected at the ridge of the laminate 10. It is preferable that the main outer base electrode layer 5022 and the side outer base electrode layer 5032 are connected at the ridge of the laminate 10. In other words, the connected main inner base electrode layer 5021 and side inner base electrode layer 5031 are separated from the main outer base electrode layer 5022 and the side outer base electrode layer 5032 by the main surface discontinuity DCT and the side discontinuity DCW. Furthermore, since the main surface outer base electrode layer 5022 and the side surface outer base electrode layer 5032 are connected to the end surface base electrode layer 501, it can also be said that the connected main surface inner base electrode layer 5021 and the side surface inner base electrode layer 5031 are separated from the end surface base electrode layer 501 by the main surface discontinuity DCT and the side surface discontinuity DCW.

[0073] In the present embodiment, the first base electrode layer 50A and the second base electrode layer 50B are baked layers. The baked layer preferably contains a metal component and either one of a glass component or a ceramic component, or contains both of them. This can improve the adhesion between the laminate 10 and the base electrode layer. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, and the like. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, and the like. When the glass component is present, it can assist and promote the sintering of the metal component in the base electrode layer. For the ceramic component, the same type of ceramic material as that of the dielectric layer 20 may be used, or a different type of ceramic material may be used. The ceramic component is, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ includes at least one selected from the group consisting of the above and the like.

[0074] The baked layer is obtained, for example, by applying a conductive paste containing glass and metal onto a laminate and then baking the same. The baked layer may be obtained by co-firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied onto the laminated chip, or may be obtained by firing a laminated chip having internal electrodes and a dielectric layer to obtain a laminate, and then applying the conductive paste onto the laminate and baking the same. In the case where a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied onto the laminated chip are fired at the same time, it is preferable that the baked layer is formed by baking a material added with a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the ceramic material to be added. The baked layer may be a plurality of layers.

[0075] The maximum value of the thickness in the length direction L of the end face side base electrode layer 501 is preferably, for example, about 2 μm or more and 220 μm or less.

[0076] The maximum thickness of the inner main surface base electrode layer 5021 and the outer main surface base electrode layer 5022 in the lamination direction T is preferably, for example, 4 μm or more and 40 μm or less.

[0077] The maximum thickness in the width direction W of the inner side base electrode layer 5031 and the outer side base electrode layer 5032 is preferably, for example, 4 μm or more and 40 μm or less.

[0078] In this embodiment, the length of the inner main surface base electrode layer 5021 in the longitudinal direction L is preferably about 20 μm to 1000 μm, and more preferably about 40 μm to 1000 μm. The length of the outer main surface base electrode layer 5022 in the longitudinal direction L is preferably about 10 μm to 500 μm, and more preferably about 20 μm to 500 μm. Furthermore, the length of the discontinuous portion DCT on the main surface in the longitudinal direction L is preferably about 50 μm to 1000 μm, and more preferably about 100 μm to 1000 μm.

[0079] In this embodiment, the length L of the inner side substrate electrode layer 5031 is preferably about 20 μm to 1000 μm, and more preferably about 40 μm to 1000 μm. The length L of the outer side substrate electrode layer 5032 is preferably about 10 μm to 500 μm, and more preferably about 20 μm to 500 μm. Furthermore, the length L of the discontinuous portion DCW on the side is preferably about 50 μm to 1000 μm, and more preferably about 100 μm to 1000 μm.

[0080] The external electrode 40 has a conductive resin layer 60 containing a resin component and a metal component. The external electrode 40 is placed on the base electrode layer 50. The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0081] The first conductive resin layer 60A is arranged to cover the first base electrode layer 50A. In this embodiment, the first conductive resin layer 60A is arranged such that the first end face side conductive resin layer 60A1 described above is placed on the first end face LS1, the first main surface side conductive resin layer 60A2 described above extends from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, and the first side side conductive resin layer 60A3 described above extends from the first end face LS1 to a part of the first side surface WS1 and a part of the second side surface WS2.

[0082] The second conductive resin layer 60B is arranged to cover the second base electrode layer 50B. In this embodiment, the second conductive resin layer 60B is arranged such that the second end face side conductive resin layer 60B1 described above is placed on the second end face LS2, the second main surface side conductive resin layer 60B2 described above extends from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, and the second side side conductive resin layer 60B3 described above extends from the second end face LS2 to a part of the first side surface WS1 and a part of the second side surface WS2.

[0083] The maximum thickness of the conductive resin layer 601 on the end face side in the longitudinal direction L is preferably, for example, 10 μm or more and 200 μm or less.

[0084] The maximum thickness of the main surface conductive resin layer 602 in the lamination direction T is preferably, for example, 10 μm or more and 200 μm or less.

[0085] The maximum thickness of the side conductive resin layer 603 in the width direction W is preferably, for example, 10 μm or more and 200 μm or less.

[0086] Furthermore, the main surface side conductive resin layer 602 is formed on a portion of the main surface inner base electrode layer 5021 and on the main surface outer base electrode layer 5022. Specifically, the first main surface side conductive resin layer 60A2 is formed on the portion of the first main surface inner base electrode layer 50A21 on the end face LS side of the laminate 10 and on the first main surface outer base electrode layer 50A22. Furthermore, the second main surface side conductive resin layer 60B2 is formed on the portion of the second main surface inner base electrode layer 50B21 on the end face LS side of the laminate 10 and on the second main surface outer base electrode layer 50B22.

[0087] Furthermore, if a discontinuous DCW is also provided in the side-side base electrode layer 503, the side-side conductive resin layer 603 is formed on a portion of the side-inner base electrode layer 5031 and on the side-outer base electrode layer 5032. Specifically, the first side-side conductive resin layer 60A3 is formed on the portion of the first side-inner base electrode layer 50A31 on the end face LS side of the laminate 10 and on the first side-outer base electrode layer 50A32. The second side-side conductive resin layer 60B3 is formed on the portion of the second side-inner base electrode layer 50B31 on the end face LS side of the laminate 10 and on the second side-outer base electrode layer 50B32.

[0088] Therefore, the main surface side discontinuity DCT is positioned on the end face LS side of the laminate 10 rather than the central end of the laminate 10 in the longitudinal direction L of the main surface side conductive resin layer 602. Specifically, the main surface side discontinuity DCT is positioned on the end face LS side of the laminate 10 rather than the central end 602E of the laminate 10 in the longitudinal direction L of the first main surface side conductive resin layer 60A2. Also, the main surface side discontinuity DCT is positioned on the end face LS side of the laminate 10 rather than the central end 602E of the laminate 10 in the longitudinal direction L of the second main surface side conductive resin layer 60B2.

[0089] Furthermore, the side discontinuity portion DCW is positioned on the end face LS side of the laminate 10, rather than on the central end of the laminate 10 in the longitudinal direction L of the side conductive resin layer 603. Specifically, the side discontinuity portion DCW is positioned on the end face LS side of the laminate 10, rather than on the central end 603E of the laminate 10 in the longitudinal direction L of the first side conductive resin layer 60A3. Also, the side discontinuity portion DCW is positioned on the end face LS side of the laminate 10, rather than on the central end 603E of the laminate 10 in the longitudinal direction L of the second side conductive resin layer 60B3.

[0090] Furthermore, at the central end 602E of the laminate 10 in the longitudinal direction L of the main surface conductive resin layer 602, a step equal to the thickness of the main surface conductive resin layer 602 is formed. Also, if a side discontinuity DCW is provided in the side base electrode layer 503, a step equal to the thickness of the side conductive resin layer 603 is formed at the central end 603E of the laminate 10 in the longitudinal direction L of the side conductive resin layer 603.

[0091] Furthermore, the main surface side conductive resin layer 602 is formed to fill the space of the main surface side discontinuity DCT in the region of the main surface side discontinuity DCT. Therefore, the thickness of the main surface side conductive resin layer 602 in the lamination direction T in the region of the main surface side discontinuity DCT is greater than the thickness of the main surface side conductive resin layer 602 in the lamination direction T outside the region of the main surface side discontinuity DCT.

[0092] Specifically, the first main surface-side conductive resin layer 60A2 is formed to fill the space of the main surface-side discontinuity DCT in the region of the main surface-side discontinuity DCT. Therefore, the thickness of the first main surface-side conductive resin layer 60A2 in the lamination direction T in the region of the main surface-side discontinuity DCT is greater than the thickness of the first main surface-side conductive resin layer 60A2 in the lamination direction T outside the region of the main surface-side discontinuity DCT.

[0093] Furthermore, the second main surface side conductive resin layer 60B2 is formed to fill the space of the main surface side discontinuity DCT in the region of the main surface side discontinuity DCT. Therefore, the thickness of the second main surface side conductive resin layer 60B2 in the lamination direction T in the region of the main surface side discontinuity DCT is greater than the thickness of the second main surface side conductive resin layer 60B2 in the lamination direction T outside the region of the main surface side discontinuity DCT.

[0094] Furthermore, the main surface-side conductive resin layer 602 is formed on the main surface of the laminate 10 in the region of the main surface-side discontinuity DCT. Specifically, the first main surface-side conductive resin layer 60A2 is formed on the main surface of the laminate 10 in the region of the main surface-side discontinuity DCT. The second main surface-side conductive resin layer 60B2 is formed on the main surface of the laminate 10 in the region of the main surface-side discontinuity DCT.

[0095] The conductive resin layer 60 is placed on the underlying electrode layer 50. The plating layer 70 is then placed so as to cover the conductive resin layer 60. The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72.

[0096] The conductive resin layer 60 has a resin portion and a conductive filler dispersed within the resin portion.

[0097] The resin portion of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin portion of the conductive resin layer 60 contains a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0098] Because the conductive resin layer 60 includes such resin components, it is more flexible than, for example, the base electrode layer 50 which consists of a plated film or a fired product of metal and glass components. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer 60 functions as a buffer layer. Thus, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0099] The conductive filler is dispersed within the resin portion in a substantially uniform distribution. The conductive filler is primarily responsible for the conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer 60, and electrical conductivity is established between the base electrode layer 50 and the plating layer 70.

[0100] Conductive fillers contain metallic components. Preferably, conductive fillers contain Ag (silver). The metal constituting the conductive filler may be pure Ag, or it may be an alloy containing Ag, or a metal powder with an Ag coating on its surface. Ag has the lowest resistivity among metals, making it suitable for electrode materials. Furthermore, as a noble metal, Ag is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as a conductive filler. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu, Ni, Sn, Bi, or alloy powders containing these as the metal powder.

[0101] Furthermore, the conductive filler may be Cu or Ni that has been treated to prevent oxidation. Alternatively, the conductive filler may be metal powder coated with Sn, Ni, or Cu on its surface. When using metal powder coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0102] The shape of the conductive filler is not particularly limited. Conductive fillers can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0103] The average particle size of the conductive filler may be, for example, 0.3 μm or more and 10 μm or less.

[0104] The average particle size of the conductive filler contained in the conductive resin layer 60 is calculated using the laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0105] The plating layer 70 has a first plating layer 70A and a second plating layer 70B.

[0106] The first plating layer 70A is arranged to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2. The first plating layer 70A may also be arranged to extend to a part of the first side surface WS1 and a part of the second side surface WS2. More specifically, the first plating layer 70A is arranged such that the first end face Ni plating layer 71A1 described above is arranged on the first end face LS1, the first main surface Ni plating layer 71A2 described above extends from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, and the first side surface Ni plating layer 71A3 described above extends to a part of the first side surface WS1 and a part of the second side surface WS2.

[0107] The second plating layer 70B is arranged to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2. The second plating layer 70B may also be arranged to extend to a part of the first side surface WS1 and a part of the second side surface WS2. More specifically, the second plating layer 70B is arranged such that the second end face Ni plating layer 71B1 described above is arranged on the second end face LS2, the second main surface Ni plating layer 71B2 described above extends from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, and the second side surface Ni plating layer 71B3 described above extends to a part of the first side surface WS1 and a part of the second side surface WS2.

[0108] Furthermore, since the plating layer 70 is formed with a constant thickness on the surface on which the base electrode layer 50 and the conductive resin layer 60 are formed, the step that occurred at the edge 602E of the main surface side conductive resin layer 602 during the formation of the conductive resin layer 60 remains as is. Therefore, the main surface side external electrode portion 402 has a step on the edge 602E of the main surface side conductive resin layer 602.

[0109] Furthermore, if a discontinuous portion DCW is also provided on the side-side base electrode layer 503, the step created at the edge 603E of the side-side conductive resin layer 603 during the formation of the conductive resin layer 60 remains as is. Therefore, the side-side external electrode portion 403 has a step on the edge 603E of the side-side conductive resin layer 603.

[0110] The plating layer 70 preferably has a two-layer structure consisting of a Ni plating layer 71 and a Sn plating layer 72. Preferably, the first Sn plating layer 72A is arranged on the first Ni plating layer 71A, and preferably, the second Sn plating layer 72B is arranged on the second Ni plating layer 71B.

[0111] In this embodiment, the first end face Ni plating layer 71A1 and the first end face Sn plating layer 72A1 are arranged on the first end face LS1, the first main surface Ni plating layer 71A2 and the first main surface Sn plating layer 72A2 are arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, and the first side surface Ni plating layer 71A3 and the first side surface Sn plating layer 72A3 are arranged to extend from the first end face LS1 to a part of the first side surface WS1 and a part of the second side surface WS2.

[0112] Similarly, the second end face Ni plating layer 71B1 and the second end face Sn plating layer 72B1 are arranged on the second end face LS2, the second main surface Ni plating layer 71B2 and the second main surface Sn plating layer 72B2 are arranged to extend from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, and the second side surface Ni plating layer 71B3 and the second side surface Sn plating layer 72B3 are arranged to extend from the second end face LS2 to a part of the first side surface WS1 and a part of the second side surface WS2.

[0113] The Ni plating layer 71 prevents the underlying electrode layer 50 and the conductive resin layer 60 from being corroded by the solder used when mounting the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder used when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1.

[0114] The thickness of the first Ni plating layer 71A and the first Sn plating layer 72A are preferably 1 μm or more and 15 μm or less.

[0115] The thickness of the second Ni plating layer 71B and the second Sn plating layer 72B are preferably 1 μm or more and 15 μm or less.

[0116] Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 10 mm. Also, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.1 mm and 10 mm. Furthermore, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 10 mm.

[0117] <Manufacturing Method> Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0118] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known substances.

[0119] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0120] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer portion 12A on the first main surface TS1 side. On top of this, dielectric sheets with printed patterns for the first internal electrode layer 31 and dielectric sheets with printed patterns for the second internal electrode layer 32 are sequentially stacked to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer portion 12B on the second main surface TS2 side. This completes the production of the laminated sheet.

[0121] Laminated sheets are pressed in the lamination direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0122] The laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or the like.

[0123] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0124] A conductive paste, which will serve as the base electrode layer 50, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked-on layer. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. After that, the conductive paste applied to the laminate 10 is dried, and the dried coating of the base electrode layer 50 is partially removed using a pulsed laser or the like, as shown in Figure 5.

[0125] More specifically, the dried coating of the main surface-side base electrode layer 502 is partially removed using a pulsed laser or the like. Immediately after removal with the pulsed laser or the like, the discontinuous DCT on the main surface side becomes a groove-shaped space. As a result, the main surface-side base electrode layer 502 has a main surface inner base electrode layer 5021, a main surface outer base electrode layer 5022, and a main surface-side discontinuous DCT.

[0126] Specifically, the first main surface-side base electrode layer 50A2 includes a first main surface-inside base electrode layer 50A21, a first main surface-outside base electrode layer 50A22, and a main surface-side discontinuity DCT. The second main surface-side base electrode layer 50B2 includes a second main surface-inside base electrode layer 50B21, a second main surface-outside base electrode layer 50B22, and a main surface-side discontinuity DCT.

[0127] Furthermore, if the base electrode layer 50 is also placed on the first side surface WS1 and the second side surface WS2, the dried coating of the side base electrode layer 503 may be partially removed by a pulsed laser or the like, as shown in Figure 5. In this case, the side base electrode layer 503 has a side inner base electrode layer 5031, a side outer base electrode layer 5032, and a side discontinuity DCW.

[0128] Specifically, the first side-side base electrode layer 50A3 comprises a first side-inner base electrode layer 50A31, a first side-outer base electrode layer 50A32, and a side-side discontinuity DCW. The second side-side base electrode layer 50B3 comprises a second side-inner base electrode layer 50B31, a second side-outer base electrode layer 50B32, and a side-side discontinuity DCW. Preferably, the side-side discontinuity DCW is formed so as to be connected to the main surface discontinuity DCT at the ridge of the laminate 10.

[0129] Subsequently, a baking process is performed to form the base electrode layer 50. The temperature of this baking process is preferably between 700°C and 950°C.

[0130] Next, a conductive resin layer 60 is formed. The conductive resin layer 60 may be formed on the surface of the underlying electrode layer 50, or it may be formed directly on the laminate 10. In this embodiment, the conductive resin layer 60 is formed on the surface of the underlying electrode layer 50.

[0131] First, a conductive resin paste is prepared by dispersing a conductive filler in a thermosetting resin, which serves as the base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive filler. Therefore, the conductive filler is uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, a silver (Ag) metal powder.

[0132] Subsequently, a conductive resin paste is applied to the base electrode layer 50 using a dipping method, and heat treatment is performed at a temperature of 150°C to 550°C. This causes the resin to heat-cur, forming a conductive resin layer 60. The atmosphere during this heat treatment is N ２ It is preferable that the atmosphere is such that the oxygen concentration is kept below 100 ppm in order to prevent the scattering of resin and to prevent oxidation of various metal components.

[0133] Furthermore, the conductive resin paste is applied to the base electrode layer 50 by a dipping method such that the wetted area of ​​the applied conductive resin paste exposes the central tip portion of the laminate 10 within the base electrode layer 50.

[0134] In this way, the inner main surface base electrode layer 5021 is positioned closer to the center of the laminate 10 than the main surface side conductive resin layer 602. Furthermore, the central end 5021E of the inner main surface base electrode layer 5021 in the longitudinal direction L is positioned closer to the center of the laminate 10 than the central end 602E of the main surface side conductive resin layer 602 in the longitudinal direction L.

[0135] Furthermore, if a discontinuous DCW is also provided in the side-side base electrode layer 503, the side-inner base electrode layer 5031 is positioned closer to the center of the laminate 10 than the side-side conductive resin layer 603. Also, the end 5031E of the side-inner base electrode layer 5031 that is closer to the center of the laminate 10 in the longitudinal direction L is positioned closer to the center of the laminate 10 than the end 603E of the side-side conductive resin layer 603 that is closer to the center of the laminate 10 in the longitudinal direction L.

[0136] Furthermore, in this state, a step equal to the thickness of the main surface conductive resin layer 602 is formed at the central end 602E of the laminate 10 in the longitudinal direction L of the main surface conductive resin layer 602. Also, if a side discontinuity DCW is provided in the side base electrode layer 503, a step equal to the thickness of the side conductive resin layer 603 is formed at the central end 603E of the laminate 10 in the longitudinal direction L of the side conductive resin layer 603 in this state.

[0137] In this state, the surface of the portion that becomes the external electrode is composed of the central surface of the laminate 10 among the surface of the main surface inner base electrode layer 5021 and the surface of the main surface side conductive resin layer 602. Specifically, in this state, the surface of the portion that becomes the first external electrode 40A is composed of the central surface of the laminate 10 among the surface of the first main surface inner base electrode layer 50A21 and the surface of the first main surface side conductive resin layer 60A2. In addition, in this state, the surface of the portion that becomes the second external electrode 40B is composed of the central surface of the laminate 10 among the surface of the second main surface inner base electrode layer 50B21 and the surface of the second main surface side conductive resin layer 60B2.

[0138] Furthermore, the discontinuous DCT on the main surface side, which had become a space after the dried conductive paste was removed by a pulsed laser or the like, is filled with conductive resin paste at the time the conductive resin paste is applied. Therefore, the conductive resin layer 602 on the main surface side is formed to fill the space in the discontinuous DCT on the main surface side in that region.

[0139] Furthermore, if a side discontinuity DCW is also provided in the side base electrode layer 503, the side discontinuity DCW, which was previously a space created when the dried conductive paste was removed by a pulsed laser or the like, is also filled with conductive resin paste at the time the conductive resin paste is applied. Therefore, the side conductive resin layer 603 is formed in the region of the side discontinuity DCW to fill the space of the side discontinuity DCW.

[0140] Subsequently, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electroplating method. For example, barrel plating is preferred as the plating method.

[0141] Furthermore, since the plating layer 70 is formed with a constant thickness on the surface of the portion that will become the external electrode 40 after the conductive resin layer 60 is formed, the step that occurred at the edge 602E of the main surface side conductive resin layer 602 during the formation of the conductive resin layer 60 remains as is. Also, if a side discontinuity DCW is provided in the side base electrode layer 503, the step that occurred at the edge 603E of the side conductive resin layer 603 during the formation of the conductive resin layer 60 remains as is.

[0142] Through the above manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0143] (1) The multilayer ceramic capacitor 1 according to this embodiment includes a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30, and comprises a laminate 10 having a first main surface TS1 and a second main surface TS2 facing the height direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the height direction T and the width direction W, a first external electrode 40A disposed on the first end surface LS1, and a second external electrode 40B disposed on the second end surface LS2 A multilayer ceramic capacitor 1 having the following: The first external electrode 40A comprises a first end face side external electrode portion 40A1 disposed on the first end face LS1, and a first main surface side external electrode portion 40A2 connected to the first end face side external electrode portion 40A1 and disposed on a part of the first end face LS1 side of the first main surface TS1 and the second main surface TS2, and the second external electrode 40B comprises a second end face side external electrode portion 40B1 disposed on the second end face LS2, and connected to the second end face side external electrode portion 40B1 and on the first main surface TS1 and the second main surface TS2 The first end face side external electrode portion 40A1 and the second end face side external electrode portion 40B2 are located on a part of the second end face LS2 side of the first end face LS1 and the second end face side external electrode portion 40B1, and each of the first end face side external electrode portion 40A1 and the second end face side external electrode portion 40B1 comprises an end face side base electrode layer 501 located on the first end face LS1 and the second end face LS2, an end face side conductive resin layer 601 located on the end face side base electrode layer 501, and an end face side plating layer 701 located on the end face side conductive resin layer 601, and the first main face side external electrode portion 40A2 and the second main face side external electrode portion 40B2 are located on a part of the first main face TS1 and the second main The laminate comprises a main surface-side base electrode layer 502 arranged on the surface TS2, a main surface-side conductive resin layer 602 arranged on the main surface-side base electrode layer 502, and a main surface-side plating layer 702 arranged on the main surface-side conductive resin layer 602. The main surface-side base electrode layer 502 has a main surface-side discontinuous portion DCT which is a discontinuous portion where no electrodes are present, a main surface-inner base electrode layer 5021 arranged on the central side of the laminate 10 in the length direction L, sandwiching the main surface-side discontinuous portion DCT, and a main surface-outer base electrode layer 5022 arranged on the end face side of the laminate 10 in the length direction L.

[0144] This makes it possible to suppress the occurrence of cracks in the laminate.

[0145] Specifically, with the above configuration, the large stress applied from the end face side of the laminate to the underlying electrode layer is interrupted at the main surface side, preventing it from being transmitted to the main surface tip. As a result, the strong tensile stress generated at the end face side of the underlying electrode layer is not transmitted to the main surface tip. This makes the maximum stress during deflection smaller than that of a typical multilayer ceramic capacitor with baked electrodes. Furthermore, the conductive resin layer is formed thicker on the mounting surface side in the thickness direction than the underlying electrode layer, which provides a stress-relieving effect during deflection. In addition, similar effects are obtained against cracks that occur directly beneath the external electrode at the main surface tip due to the shrinkage stress of the external electrode during thermal shock cycling, just as with the effect on stress during deflection.

[0146] (2) In the multilayer ceramic capacitor 1 of this embodiment, the main surface side conductive resin layer 602 has a conductive filler having a metal component and a resin portion having a resin component, the conductive filler contains at least Ag, and the main surface inner base electrode layer 5021 is positioned closer to the center of the laminate 10 than the main surface side conductive resin layer 602.

[0147] The most commonly used conductive filler is silver (Ag), and in the case of Ag conductive fillers, Ag migration can be a problem. Ag migration occurs when an electric field is generated on the main surface side of the external electrode, where the potentials are different. In particular, the presence of Ag at the tip of the main surface, where the electric field tends to concentrate, has been a problem as Ag migration is more likely to occur.

[0148] However, by configuring the external electrode so that the base electrode is interrupted at the main surface side portion and does not connect from the end face side to the main surface tip, and further by positioning the main surface inner base electrode layer inside the laminate relative to the conductive resin layer, a configuration that is less prone to migration is achieved. In addition, the conductive resin layer containing Ag, which is prone to migration, is formed in a position where an electric field is less likely to be applied, thus making the configuration less prone to migration. Therefore, in an external electrode with such a configuration, migration is structurally less likely to occur.

[0149] (3) In the multilayer ceramic capacitor 1 of this embodiment, the central end of the main surface inner base electrode layer 5021 in the longitudinal direction L of the laminate 10 is located closer to the center of the laminate 10 than the central end of the main surface side conductive resin layer 602 in the longitudinal direction L of the laminate 10.

[0150] As a result, the conductive resin layer containing metals prone to migration is not formed at the main surface tip of the external electrode, resulting in a configuration that is less susceptible to migration. Furthermore, the conductive resin layer containing metals prone to migration is formed in a location where no electric field is applied, further reducing the likelihood of migration. Therefore, in an external electrode with this configuration, migration is structurally less likely to occur.

[0151] (4) In the multilayer ceramic capacitor 1 of this embodiment, a main surface side conductive resin layer 602 is arranged directly above the main surface inner base electrode layer 5021.

[0152] This suppresses the occurrence of cracks in the laminate while further reducing the increase in ESR due to the increased resistance of the resin layer.

[0153] (5) The multilayer ceramic capacitor 1 of this embodiment has a first external electrode 40A which is connected to a first end face side external electrode portion 40A1 and has a first side side external electrode portion 40A3 which is located on a part of the first end face LS1 side of the first side surface WS1 and the second side surface WS2, and a second external electrode 40B which is connected to a second end face side external electrode portion 40B1 and has a second side side external electrode portion 40B3 which is located on a part of the second end face LS2 side of the first side surface WS1 and the second side surface WS2, and the first side side external electrode portion 40A3 and the second side side external electrode portion 40B3 are located on the first side surface W The laminate comprises a side-side base electrode layer 503 disposed on S1 and a second side surface WS2, a side-side conductive resin layer 603 disposed on the side-side base electrode layer 503, and a side-side plating layer 703 disposed on the side-side conductive resin layer 603. The side-side base electrode layer 503 has a side-side discontinuous portion DCW which is a discontinuous portion where no electrodes are present, a side-side inner base electrode layer 5031 disposed on the central side of the laminate 10 in the length direction L, sandwiching the side-side discontinuous portion DCW, and a side-side outer base electrode layer 5032 disposed on the outer side of the laminate 10 in the length direction L.

[0154] This further suppresses the occurrence of cracks in the laminate.

[0155] 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 40A First external electrode 40A1 First end-face side external electrode portion 40A2 First main surface side external electrode portion 40B Second external electrode 40B1 Second end-face side external electrode portion 40B2 Second main surface side external electrode portion 501 End-face side base electrode layer 502 Main surface side base electrode layer 5021 Main surface inner base electrode layer 601 End-face side conductive resin layer 602 Main surface side conductive resin layer 701 End-face side plating layer 702 Main surface side plating layer DCT Main surface side discontinuity T Height direction TS End face TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface L Length direction LS1 First end face LS2 Second end face

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of stacked dielectric layers and a plurality of internal electrode layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the first external electrode comprises a first end surface side external electrode portion disposed on the first end surface, and a first main surface side external electrode portion connected to the first end surface side external electrode portion and disposed on a part of the first end surface side of the first main surface and the second main surface, and the second external electrode comprises a second end surface side external electrode portion disposed on the second end surface, The first and second end-face side external electrode portion is connected to the second end-face side external electrode portion and is located on the first main surface and a part of the second end-face side of the second main surface, and the first and second end-face side external electrode portions each comprise an end-face side base electrode layer located on the first and second end surfaces, an end-face side conductive resin layer located on the end-face side base electrode layer, and an end-face side plating layer located on the end-face side conductive resin layer, and the first and second main-face side external electrode portions each comprise a main-face side base electrode layer located on the first and second main surfaces, a main-face side conductive resin layer located on the main-face side base electrode layer, and a main-face side plating layer located on the main-face side conductive resin layer, and the main-face side base electrode layer comprises a main-face side discontinuous portion which is a discontinuous portion where no electrodes are present, A multilayer ceramic capacitor comprising: an inner main surface under electrode layer located on the central side of the laminate in the longitudinal direction, and an outer main surface under electrode layer located on the end face side of the laminate in the longitudinal direction, with the discontinuity on the main surface side in between.

2. The multilayer ceramic capacitor according to claim 1, wherein the main surface side conductive resin layer comprises a conductive filler having a metal component and a resin portion having a resin component, the conductive filler contains at least Ag, and the main surface inner base electrode layer is positioned closer to the center of the laminate than the main surface side conductive resin layer.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the end of the inner main surface base electrode layer on the central side of the laminate in the longitudinal direction is located closer to the center of the laminate than the end of the main surface side conductive resin layer on the central side of the laminate in the longitudinal direction.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the main surface side conductive resin layer is disposed directly above the main surface inner base electrode layer.

5. The first external electrode is connected to the first end-face side external electrode portion and comprises a first side-side external electrode portion located on the first side surface and a part of the first end-face side of the second side surface; the second external electrode is connected to the second end-face side external electrode portion and comprises a second side-side external electrode portion located on the first side surface and a part of the second end-face side of the second side surface; the first side-side external electrode portion and the second side-side external electrode portion each comprise a side-side base electrode layer located on the first side surface and the second side surface, a side-side conductive resin layer located on the side-side base electrode layer, and a side-side plating layer located on the side-side conductive resin layer; the side-side base electrode layer comprises a side-side discontinuous portion which is a discontinuous portion where no electrodes are present, and a side-side inner base electrode layer located on the central side of the laminate in the longitudinal direction, sandwiching the side-side discontinuous portion. A multilayer ceramic capacitor according to any one of claims 1 to 4, comprising a side outer under electrode layer disposed on the outer side of the laminate in the longitudinal direction.

Images