Multilayer ceramic electronic component

Abstract

The present invention provides a multilayer ceramic electronic component capable of suppressing the occurrence of cracks in a laminate when a substrate is bent, and also suppressing the occurrence of cracks in the laminate in the vicinity of an edge in the width direction of an insulation layer.　An insulation layer (71) of the invention is formed so as to cover at least a portion of a first main surface (TS1) of a laminate (10), at least a portion of a first covering part (91A), and at least a portion of a second covering part (91B). The insulation layer (71) has a plurality of connection portions (77) that extend in the length direction (L) on the first main surface (TS1) so as to connect a first external electrode (40A) and a second external electrode (40B), and that are disposed at intervals in the width direction (W). Exposed surfaces (78) that are exposed portions of the first main surface (TS1) of the laminate (10) are each provided between the plurality of connection portions (77) in the width direction (W).

Description

Multilayer Ceramic Electronic Component

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] A multilayer ceramic capacitor as a conventional multilayer ceramic electronic component comprises outer layers formed of ceramic on both main surface sides of a multilayer body. External electrodes are disposed on both end faces of the multilayer body so as to cover the outer layers. When such a multilayer ceramic capacitor is mounted on a mounting substrate using a bonding material such as solder, when a thermal cycle is applied to the multilayer ceramic capacitor, or when the substrate bends due to voltage application or the like, cracks may occur in the multilayer body starting from the tips of the external electrodes.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor for addressing such cracks. In this multilayer ceramic capacitor, an insulating layer is formed so as to cover the main surface of the multilayer body and the external electrode exposed on the main surface side of the multilayer body.

[0004] Japanese Patent Application Laid-Open No. 2020-188144

[0005] The multilayer ceramic capacitor of Patent Document 1 can suppress the occurrence of cracks in the multilayer body when the substrate bends. On the other hand, in recent years, multilayer ceramic capacitors have been required to be used in severe high-temperature environments. In the technique described in Patent Document 1, although the crack resistance of the multilayer body when the substrate bends is improved, for example, under an environment with excessive temperature changes, cracks may occur in the multilayer body near the edges in the width direction of the electrical insulating layer coated on the multilayer body due to the tensile stress in the width direction of the electrical insulating layer.

[0006] Therefore, an object of the present invention is to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the multilayer body when the substrate bends, and can also suppress the occurrence of cracks in the multilayer body near the edges in the width direction of the insulating layer.

[0007] A multilayer ceramic electronic component according to one aspect of the present invention comprises: a laminate including a plurality of dielectric layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction; a first external electrode disposed on the first end surface side and having a first covering portion that covers a part of the first end surface side of the first main surface; a second external electrode disposed on the second end surface side and having a second covering portion that covers a part of the second end surface side of the first main surface; and an insulating layer formed to cover at least a part of the first main surface of the laminate, at least a part of the first covering portion and at least a part of the second covering portion, wherein the insulating layer has a plurality of connecting portions that extend in the length direction on the first main surface and are spaced apart in the width direction so as to connect the first external electrode and the second external electrode. Between the plurality of connecting portions in the width direction, exposed surfaces are provided on which the first main surface of the laminate is exposed.

[0008] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate when the substrate is deflected, as well as suppress the occurrence of cracks in the laminate near the edges in the width direction of the insulating layer.

[0009] This is a first external perspective view of a multilayer ceramic capacitor according to the first embodiment. This is a second external perspective view of a multilayer ceramic capacitor according to the first embodiment. This is a cross-sectional view taken along line III-III in Figure 1. This is a cross-sectional view taken along line IV-IV in Figure 3. This is a cross-sectional view taken along line VA-VA in Figure 3. This is a cross-sectional view taken along line VB-VB in Figure 3. This is a bottom view of a multilayer ceramic capacitor. This is an external perspective view of the mounting structure of a multilayer ceramic capacitor. This is a cross-sectional view of a multilayer ceramic capacitor according to a first modified example of the first embodiment. This is a bottom view of a multilayer ceramic capacitor according to a first modified example of the first embodiment. This is a bottom view of a multilayer ceramic capacitor according to a second modified example of the first embodiment. This is a bottom view of a multilayer ceramic capacitor according to a third modified example of the first embodiment. This is a cross-sectional view of a multilayer ceramic capacitor according to a second embodiment. This is a bottom view of a multilayer ceramic capacitor according to a modified example of the second embodiment. This is a diagram showing a double-gang multilayer ceramic capacitor. This is a diagram showing a triple-gang multilayer ceramic capacitor. This is a diagram showing a quadruple-gang multilayer ceramic capacitor.

[0010] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to the present disclosure will be described with reference to the drawings. Figure 1 is a first external perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. Figure 2 is a second external perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. Figure 3 is a cross-sectional view taken along line III-III of Figure 1. Figure 4 is a cross-sectional view taken along line IV-IV of Figure 3. Figure 5A is a cross-sectional view taken along line VA-VA of Figure 3. Figure 5B is a cross-sectional view taken along line VB-VB of Figure 3.

[0011] As shown in Figures 1 and 2, the multilayer ceramic capacitor 1 according to this embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 comprises a laminate 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 40 arranged spaced apart from each other at both ends of the laminate 10.

[0012] In Figures 1 and 2, arrow T indicates the height direction of the multilayer ceramic capacitor 1 and the laminate 10. This height direction T is also the thickness direction and stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. In Figures 1 and 2, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the height direction T. In Figures 1 and 2, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the height direction T and the length direction L. A pair of external electrodes 40 are arranged at one end and the other end of the laminate 10 in the length direction L, respectively.

[0013] Figures 1 to 5B show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The height direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in Figure 3 is also called the LT cross section. The cross section shown in Figure 4 is also called the WT cross section. The cross sections shown in Figures 5A and 5B are also called the LW cross section.

[0014] As shown in Figures 1 to 5B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that are opposite to the height direction T, a first end surface LS1 and a second end surface LS2 that are opposite to the length direction L which is perpendicular to the height direction T, and a first side surface WS1 and a second side surface WS2 that are opposite to the width direction W which is perpendicular to the height direction T and the length direction L.

[0015] The mounting surface of the multilayer ceramic capacitor 1 is the first main surface TS1. The mounting surface is the surface that faces the wiring board when the multilayer ceramic capacitor 1 is mounted on a wiring board or the like.

[0016] As shown in Figures 1 and 2, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0017] The dimensions of the laminate 10 are not particularly limited, but if the length L of the laminate 10 is denoted as dimension L, then dimension L is preferably 0.1 mm or more and 10 mm or less, and more preferably 0.2 mm or more and 10 mm or less. If the height T of the laminate 10 is denoted as dimension T, then dimension T is preferably 0.05 mm or more and 10 mm or less. If the width W of the laminate 10 is denoted as dimension W, then dimension W is preferably 0.05 mm or more and 10 mm or less, and more preferably 0.1 mm or more and 10 mm or less.

[0018] As shown in Figures 3 and 4, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12 and a second main surface-side outer layer 13 arranged to sandwich the inner layer 11 in the height direction T.

[0019] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers, which are alternately stacked in the height direction T. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the height direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0020] The multiple dielectric layers 20 are composed of a dielectric material. The dielectric material may be a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, the dielectric material may be a material in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to these main components. It is particularly preferable that the dielectric material contains BaTiO3 as its main component.

[0021] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 15 or more and 1200 or less. This number of dielectric layers 20 is the sum of the number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0022] The multiple internal electrode layers 30 include a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the height direction T with a dielectric layer 20 in between them. The first internal electrode layers 31 are led out to the second end face LS2. The second internal electrode layers 32 are led out to the first end face LS1. In the following, when it is not necessary to explain the first internal electrode layers 31 and the second internal electrode layers 32 separately, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layer 30.

[0023] As shown in Figure 5A, the first internal electrode layer 31 has a first opposing portion 31A and a first leading portion 31B. The first opposing portion 31A is a region that faces the second internal electrode layer 32 with the dielectric layer 20 in between, and is located inside the laminate 10. The first leading portion 31B is a portion that is drawn out from the first opposing portion 31A to the second end face LS2, and is exposed to the second end face LS2.

[0024] As shown in Figure 5B, the second internal electrode layer 32 has a second opposing portion 32A and a second leading portion 32B. The second opposing portion 32A is a region that faces the first internal electrode layer 31 with the dielectric layer 20 in between, and is located inside the laminate 10. The second leading portion 32B is a portion that is drawn out from the second opposing portion 32A to the first end face LS1, and is exposed to the first end face LS1.

[0025] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0026] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first drawer portion 31B and the second drawer portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0027] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0028] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0029] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 1000 or less.

[0030] As shown in Figures 3 and 4, the first main surface-side outer layer 12 is located on the second main surface TS2 side of the laminate 10. The first main surface-side outer layer 12 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. On the other hand, the second main surface-side outer layer 13 is located on the first main surface TS1 side of the laminate 10. The second main surface-side outer layer 13 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface-side outer layer 12 and the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0031] The portion where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other is the opposing electrode portion, and is configured as part of the inner layer 11.

[0032] As shown in Figures 1, 2, and 3, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10, and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0033] The basic configurations of the first external electrode 40A and the second external electrode 40B are the same. Furthermore, the first external electrode 40A and the second external electrode 40B have shapes that are generally symmetrical with respect to the WT cross-section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to explain the first external electrode 40A and the second external electrode 40B separately, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0034] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is in contact with the second lead-out portion 32B of each of the multiple second internal electrode layers 32 exposed on the first end face LS1. As a result, the first external electrode 40A is electrically connected to the multiple second internal electrode layers 32. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is in contact with the first lead-out portion 31B of each of the multiple first internal electrode layers 31 exposed on the second end face LS2. As a result, the second external electrode 40B is electrically connected to the multiple first internal electrode layers 31. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, within the laminate 10, capacitance is formed when the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the second internal electrode layer 32 is connected and the second external electrode 40B to which the first internal electrode layer 31 is connected.

[0037] As shown in Figures 3, 5A, and 5B, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0038] The first base electrode layer 50A is positioned on the first end face LS1. The first base electrode layer 50A is connected to the second lead-out portions 32B of each of the multiple second internal electrode layers 32 that are exposed on the first end face LS1. In this embodiment, the first base electrode layer 50A is formed extending from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0039] The second base electrode layer 50B is positioned on the second end face LS2. The second base electrode layer 50B is in contact with the first pull-out portions 31B of each of the multiple first internal electrode layers 31 that are exposed on the second end face LS2. In this embodiment, the second base electrode layer 50B is formed extending from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0040] The first base electrode layer 50A and the second base electrode layer 50B in this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material may be used. The ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0041] The baked layer is formed, for example, by applying a conductive paste containing glass and metal onto the multilayer body 10 and baking the paste. The baked layer can be formed by co-firing an unfired multilayer chip, which is a raw material of the multilayer body 10 including a plurality of internal electrodes and dielectric layers, and the conductive paste applied to the multilayer chip. Alternatively, after firing the multilayer chip to obtain the multilayer body 10, the baked layer may also be formed by applying the conductive paste onto the multilayer body 10 and baking the paste. In the case of the above cofiring, the baked layer is preferably formed by baking a material added with a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layers 20 as the ceramic material to be added. The baked layer may be a plurality of layers.

[0042] The thickness corresponding to the length direction L of the first base electrode layer 50A located on the first end face LS1 is preferably, for example, approximately 2 µm or more and 220 µm or less at the central portion of the first base electrode layer 50A in the height direction T and the width direction W.

[0043] The thickness corresponding to the length direction L of the second base electrode layer 50B located on the second end face LS2 is preferably, for example, approximately 2 µm or more and 220 µm or less at the central portion of the second base electrode layer 50B in the height direction T and the width direction W.

[0044] When the first base electrode layer 50A is also provided on a part of at least one of the first main surface TS1 and the second main surface TS2, the thickness corresponding to the height direction T of the first base electrode layer 50A provided in this part is preferably, for example, approximately 3 µm or more and 40 µm or less at the central portion of the first base electrode layer 50A provided in this part in the length direction L and the width direction W.

[0045] When the first base electrode layer 50A is also provided on a part of at least one of the first side surface WS1 and the second side surface WS2, the thickness corresponding to the width direction W of the first base electrode layer 50A provided in this part is preferably, for example, approximately 3 µm or more and 40 µm or less at the central portion of the first base electrode layer 50A provided in this part in the length direction L and the height direction T.

[0046] When the second base electrode layer 50B is also provided on a part of at least one of the first main surface TS1 and the second main surface TS2, the thickness corresponding to the height direction T of the second base electrode layer 50B provided in this part is preferably, for example, about 3 µm or more and 40 µm or less at the center in the length direction L and the width direction W of the second base electrode layer 50B provided in this part.

[0047] When the second base electrode layer 50B is also provided on a part of at least one of the first side surface WS1 and the second side surface WS2, the thickness corresponding to the width direction W of the second base electrode layer 50B provided in this part is preferably, for example, about 3 µm or more and 40 µm or less at the center in the length direction L and the height direction T of the second base electrode layer 50B provided in this part.

[0048] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0049] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0050] The first plating layer 60A and the second plating layer 60B may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, and the like. Each of the first plating layer 60A and the second plating layer 60B may be formed of a plurality of layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0051] The first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0052] The second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0053] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B and the second Sn plating layer 62B is preferably between 2 μm and 15 μm.

[0054] The external electrode 40 in this embodiment may, for example, have a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be arranged to cover the baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is placed between the baking layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baking layer or cover a part of the baking layer.

[0055] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0056] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or alloys containing these. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0057] Furthermore, the conductive particles may be metal powders with an Ag coating on their surface. When using metal powders with an Ag coating on their surface, the metal powders are preferably Cu, Ni, Sn, Bi, or alloys thereof. It is preferable to use Ag-coated metal powders in order to maintain the properties of Ag while making the base metal less expensive.

[0058] Furthermore, the conductive particles may be Cu or Ni that have been treated to prevent oxidation. Alternatively, the conductive particles may be metal powder coated with Sn, Ni, or Cu on the surface of the metal powder. When using metal powder coated with Sn, Ni, or Cu on the surface, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0059] The shape of the conductive particles is not particularly limited. Conductive particles can have shapes such as spherical or flattened, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0060] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive particles forms an electrical pathway within the conductive resin layer.

[0061] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0062] The conductive resin layer may be formed from multiple layers. Preferably, the thickness of the thickest part of the conductive resin layer is 10 μm or more and 150 μm or less.

[0063] The above describes the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the length L dimension of the multilayer ceramic capacitor 1, including the laminate 10 and the external electrode 40, is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 6 mm or less. If the height T dimension of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is 0.05 mm or more and 5 mm or less. Furthermore, if the width W dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 5 mm or less.

[0064] Figure 7 shows the mounting structure 100 of the multilayer ceramic capacitor 1. Figure 7 is an external perspective view of the mounting structure of the multilayer ceramic capacitor. The mounting structure 100 is a structure in which the multilayer ceramic capacitor 1 is mounted on a mounting substrate 80, which will be described in detail later.

[0065] The first external electrode 40A has a first covering portion 91A that covers a part of the first end face LS1 side of the first main surface TS1. The first covering portion 91A is also called the main surface side external electrode. Specifically, the first covering portion 91A extends continuously from the portion formed on the first end face LS1 of the first external electrode 40A. More specifically, the first covering portion 91A is formed over the entire width W of the first main surface TS1. The second external electrode 40B has a second covering portion 91B that covers a part of the second end face LS2 side of the first main surface TS1. The second covering portion 91B is also called the main surface side external electrode. Specifically, the second covering portion 91B extends continuously from the portion formed on the second end face LS2 of the second external electrode 40B. More specifically, the second covering portion 91B is formed over the entire width W of the first main surface TS1.

[0066] The multilayer ceramic capacitor 1 further includes an insulating layer 71.

[0067] In conventional multilayer ceramic capacitors, stress is relieved, and the occurrence of cracks in the laminate can be suppressed. However, in conventional technology, the shape and arrangement of the insulating layer have not been sufficiently considered, so the stress relief effect does not function properly, and in some cases, sufficient crack resistance of the laminate against substrate deflection cannot be obtained.

[0068] Considering the above, the inventors of the present invention diligently studied arrangements of the insulating layer that can enhance crack resistance. As a result, the inventors of the present invention found that, according to the configuration of this embodiment, it is possible to suppress both bending cracks and cracks caused by tensile stress in the width direction. Specifically, the inventors of the present invention found that bending crack resistance can be enhanced by appropriately adjusting the stress generated near both ends of the insulating layer in the length direction and the stress generated near both ends of the insulating layer in the width direction.

[0069] The configuration of the insulating layer 71 in this embodiment will be described in detail below.

[0070] As shown in Figures 1 to 4 and Figure 6, the insulating layer 71 is formed to cover at least a portion of the first main surface TS1 of the laminate 10 and at least a portion of the first external electrode 40A and the second external electrode 40B which are arranged on the side of the first main surface TS1.

[0071] Specifically, the insulating layer 71 is formed on the first main surface TS1 of the laminate 10, and includes a first external electrode 40A and a second external electrode 40B that are exposed on the first main surface TS1 side.

[0072] In other words, the insulating layer 71 is formed across the surface of the first external electrode 40A, specifically the surface of the laminate 10 on the side of the first main surface TS1, the first main surface TS1 located between the first external electrode 40A and the second external electrode 40B, and the surface of the second external electrode 40B, specifically the surface of the laminate 10 on the side of the first main surface TS1.

[0073] More specifically, the insulating layer 71 has a first portion 72 formed on the first main surface TS1, a second portion 73 extending from the first portion 72 in the longitudinal direction L to reach a part of the first covering portion 91A of the first external electrode 40A, and a third portion 74 extending from the first portion 72 in the longitudinal direction L to reach a part of the second covering portion 91B of the second external electrode 40B. If the insulating layer 71 is an organic layer, the insulating layer 71, which has a higher coefficient of linear expansion than the laminate 10, connects the first external electrode 40A and the second external electrode 40B, so that in an environment with a temperature lower than the curing temperature of the insulating layer 71 during manufacturing, the force in the direction of contraction of the insulating layer 71 pulls the first external electrode 40A and the second external electrode 40B toward each other. This tensile force is in the opposite direction to the force acting on the first external electrode 40A and the second external electrode 40B when the substrate is deflected, so the two forces cancel each other out. As a result, the stress value acting on the laminate 10 can be kept sufficiently low. Therefore, sufficient crack resistance of the laminate 10 against substrate deflection can be obtained, and as a result, the occurrence of cracks in the laminate 10 can be suppressed. As a result, a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate can be provided.

[0074] Furthermore, the insulating layer 71 has a wetted area 75 and an edge 76 where the resin has spread in the portions of the first side surface WS1 and the second side surface WS2 of the laminate 10 where the first external electrode 40A and the second external electrode 40B are not formed. The edge 76 is the edge of the insulating layer 71 in the width direction W. The edge 76 is the wetted boundary where the resin has spread.

[0075] The insulating layer 71 is preferably an organic layer mainly composed of organic matter. More specifically, the insulating layer 71 is preferably a resin layer mainly composed of resin. The insulating layer 71 is, for example, an epoxy resin. However, the composition constituting the insulating layer 71 is not limited to this. For example, the insulating layer 71 may contain one or more of the following: epoxy resin, silicone resin, fluororesin, phenolic resin, urea resin, melamine resin, and unsaturated polyester resin. The insulating layer 71 is a layer having a low-wettability surface with lower solder wettability than the surface of the external electrode 40. The insulating layer 71 may contain a filler. The insulating layer 71 may also be composed of a material other than resin, and in that case, it is also preferable that it has a surface with lower solder wettability than the external electrode 40.

[0076] (Plan view of the insulating layer 71) The plan view of the insulating layer 71 will be explained using Figures 4 and 6. Figure 6 is a bottom view of the multilayer ceramic capacitor 1.

[0077] The insulating layer 71 extends in the longitudinal direction L on the first main surface TS1 so as to connect the first external electrode 40A and the second external electrode 40B. The thickness of the insulating layer 71 is, for example, 5 μm or more.

[0078] The insulating layer 71 is spaced apart in the width direction W and has a plurality of connecting portions 77 that connect the first external electrode 40A and the second external electrode 40B. The plurality of connecting portions 77 are formed linearly along the length direction L. The plurality of connecting portions 77 are arranged in four rows in the width direction W, and preferably there are three or more. The plurality of connecting portions 77 are formed in the first portion 72, a part of the second portion 73, and a part of the third portion 74 of the insulating layer 71. The longitudinal ends of the plurality of connecting portions 77 extend to a part of the second portion 73 and a part of the third portion 74.

[0079] Between the multiple connecting portions 77 in the width direction W, there are exposed surfaces 78 on which the first main surface TS1 of the laminate is exposed. The exposed surfaces 78 can also be described as dividing portions that divide the multiple connecting portions 77 in the width direction W. The multiple exposed surfaces 78 are formed in a straight line along the length direction L. Multiple exposed surfaces 78 are arranged side by side in the width direction W. Specifically, there are three rows of exposed surfaces 78.

[0080] As a modification of the first embodiment, the connecting portion and the exposed surface do not have to be straight. For example, the connecting portion and the exposed surface may be curved in part or in whole, meandering in part or in whole, or zigzag in part or in whole.

[0081] Due to the shape described above, the resin of the insulating layer 71 is continuous in the longitudinal direction L, linearly connecting the first external electrode 40A and the second external electrode 40B. As a result, a tensile force acts on the longitudinal ends of the first external electrode 40A and the second external electrode 40B toward the center of the laminate 10. This tensile force is in the opposite direction to the force acting on the first external electrode 40A and the second external electrode 40B when the substrate is bent, so the two forces cancel each other out. This makes it possible to sufficiently reduce the stress acting on the laminate 10 near the longitudinal ends of the first external electrode 40A and the second external electrode 40B.

[0082] Furthermore, due to the above shape, the resin of the insulating layer 71 is discontinuous in the width direction W, so the tensile stress of the wetted portion 75 of the resin of the insulating layer 71 in the width direction W is reduced. As a result, the occurrence of cracks in the laminate 10 when the substrate is deflected is suppressed, and the occurrence of cracks in the laminate 10 near the edge 76 in the width direction W of the insulating layer 71 is also suppressed. Conventionally, when a temperature cycle load was applied, there was a risk of cracks forming in the laminate 10 near the edge 76 of the insulating layer 71.

[0083] As shown in Figure 7, the mounting structure 100 for the multilayer ceramic capacitor includes a multilayer ceramic capacitor 1 and a mounting substrate 80. The mounting substrate 80 includes a substrate body 81. The substrate body 81 is formed of, for example, a resin such as glass epoxy, or glass or ceramic. The substrate body 81 may be formed of, for example, a plurality of stacked insulating layers. One main surface of the substrate body 81 (the upper surface in the figure) is the mounting surface, and a land electrode 82 with a rectangular shape in plan view is provided on the mounting surface. The multilayer ceramic capacitor 1 is mounted by connecting and fixing the land electrode 82 to the portions of the first external electrode 40A and the second external electrode 40B of the multilayer ceramic capacitor 1 that are exposed from the insulating layer 71 via solder 83. As a result, the area of ​​the first external electrode 40A and the second external electrode 40B that is joined with the solder 83 is reduced, making the joint structure between the multilayer ceramic capacitor 1 and the mounting substrate 80 more flexible and suppressing the occurrence of cracks in the laminate when the substrate is flexed. Furthermore, a portion of the external electrode 40 near its longitudinal end may be exposed from the insulating layer 71 between the multiple connecting portions 77 of the insulating layer 71. That is, a portion of the external electrode 40 near its longitudinal end may be exposed on the exposed surface 78. This ensures the initial bonding strength between the multilayer ceramic capacitor 1 and the mounting substrate 80 while suppressing the occurrence of cracks in the laminate when the substrate flexes. Furthermore, the external electrode 40 does not have to be exposed from the insulating layer 71 between the multiple connecting portions 77 of the insulating layer 71. That is, the external electrode 40 may not be exposed on the exposed surface 78, and only the surface of the laminate 10 may be exposed. This more effectively suppresses the occurrence of cracks in the laminate when the substrate flexes.

[0084] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0085] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known materials. The paste made of a conductive material is, for example, a metal powder to which an organic binder and an organic solvent are added.

[0086] A conductive paste for the internal electrode layer 30 is printed onto the dielectric sheet using a printing plate designed to form the shape of the internal electrode layer 30 in this embodiment, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer 31 formed on it and a dielectric sheet with the pattern of the second internal electrode layer 32 formed on it.

[0087] A predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the first main surface outer layer portion 12 on the first main surface TS1 side. On top of this, dielectric sheets with the pattern of the first internal electrode layer 31 printed on them and dielectric sheets with the pattern of the second internal electrode layer 32 printed on them are stacked alternately in sequence to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the second main surface outer layer portion 13 on the second main surface TS2 side. This results in a laminated sheet.

[0088] Next, the laminated sheets are pressed in the height direction by means of a hydrostatic press or other means to produce a laminated block.

[0089] Next, the laminated block is cut into predetermined sizes to form individual pieces, thereby obtaining multiple laminated chips. After this, the laminated chips may be polished by barrel polishing or other methods to round off the corners and edges.

[0090] Next, the laminated chips are fired to obtain the laminated body 10. The firing temperature at this time depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably, for example, 900°C to 1400°C.

[0091] A conductive paste, which will serve as the base electrode layer 50, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer can be formed by applying a conductive paste containing glass components and metal to the laminate 10, for example by dipping, and then performing a baking treatment. The temperature of the baking treatment at this time is preferably 700°C to 900°C.

[0092] Alternatively, the laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, it is preferable to form the baked layer by baking a material with a ceramic component added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminated body 10 with a baked layer.

[0093] Subsequently, a plating layer is formed on the surface of the base electrode layer 50, which consists of a baked layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating treatment, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like in order to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0094] The multilayer ceramic capacitor body is manufactured through the above process.

[0095] Next, an insulating layer 71 is formed on the multilayer ceramic capacitor body. Specifically, the insulating layer 71 is formed by applying a resin paste to the ceramic capacitor body using methods such as inkjet printing, screen printing, metal mask printing, dispenser, roller transfer, dipping, or spray coating. At this time, by partially forming layers using masking or the like, multiple connecting portions 77 and multiple exposed surfaces 78 are formed. The exposed surfaces 78 may also be formed by trimming the resin film after it has been formed using a laser or the like.

[0096] Subsequently, the resin is cured by heat treatment in an oven at 100-200°C for a predetermined time. In this manner, the multilayer ceramic capacitor 1 is manufactured.

[0097] In the process described above, the amount of overlap between the resin paste and the external electrode on the main surface, and the thickness of the resin, can be controlled by controlling the dispensing position, paste dispensing amount, paste viscosity, number of dispensing cycles, and temperature during application.

[0098] Next, as shown in Figure 7, the manufactured multilayer ceramic capacitor 1 is positioned so that its first main surface TS1 side faces the mounting substrate 80 on which the land electrodes 82 are provided, and the multilayer ceramic capacitor 1 is mounted on the mounting substrate 80 via solder 83.

[0099] In the multilayer ceramic capacitor 1 described in this embodiment, the occurrence of cracks in the laminate 10 when the substrate is deflected can be suppressed, as can the occurrence of cracks in the laminate 10 near the edge 76 in the width direction W of the insulating layer 71.

[0100] (First Modification of the First Embodiment) A modification of the insulating layer 71 will be described using Figures 8 and 9. Figure 8 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first modification of the first embodiment. Figure 9 is a bottom view of the multilayer ceramic capacitor 1 according to the first modification of the first embodiment.

[0101] The wetted portion 75A and edge 76A of the insulating layer 71 are located on the first main surface TS1 of the laminate 10. This reduces the stress generated near the edge 76A in the width direction W of the resin of the insulating layer 71. Alternatively, the wetted portion 75A and edge 76A of the insulating layer 71 may be located on the ridge line between the first main surface TS1 and the first side surface WS1, and on the ridge line between the first main surface TS1 and the second side surface WS2.

[0102] (Second Modification of the First Embodiment) Using Figure 10, a modification of the connecting portion and exposed surface in the insulating layer will be explained. Figure 10 is a bottom view of a multilayer ceramic capacitor 1 according to the second modification of the first embodiment.

[0103] The insulating layer 71 is spaced apart in the width direction W and has connecting portions 77A that connect the first external electrode 40A and the second external electrode 40B. The connecting portions 77A are formed in the first portion 72 of the insulating layer 71. The connecting portions 77A have a first connecting portion 77Aa and a second connecting portion 77Ab. The first connecting portion 77Aa and the second connecting portion 77Ab are formed linearly along the length direction L. A first connecting portion 77Ac is provided that connects the first connecting portion 77Aa and the second connecting portion 77Ab on the first external electrode 40A. A second connecting portion 77Ad is provided that connects the first connecting portion 77Aa and the second connecting portion 77Ab on the second external electrode 40B. Furthermore, the first connecting portion 77Ac is the same portion as the second portion 73, and the second connecting portion 77Ad is the same portion as the third portion 74. As a result, the connecting portion 77A, the first connecting portion 77Aa, and the second connecting portion 77Ab form an annular ring overall.

[0104] Between the first connecting portion 77Aa and the second connecting portion 77Ab in the width direction W, there is an exposed surface 78A in which the first main surface TS1 of the laminate is exposed. The exposed surface 78A is formed in a generally oval shape and extends long in the length direction L.

[0105] The connecting parts and exposed surfaces do not have to be straight. For example, the connecting parts and exposed surfaces may be curved in part or in whole, meandering in part or in whole, or zigzag in part or in whole.

[0106] The wetting spread portion 75A and edge 76A of the insulating layer 71 are located on the first main surface TS1 of the laminate 10. Alternatively, the wetting spread portion 75A and edge 76A of the insulating layer 71 may be located on the first side surface WS1 and the second side surface WS2, or on the ridge line between the first main surface TS1 and the first side surface WS1 and the ridge line between the first main surface TS1 and the second side surface WS2.

[0107] Due to the shape described above, the resin of the insulating layer 71A is continuous in the longitudinal direction L, linearly connecting the first external electrode 40A and the second external electrode 40B. As a result, a tensile force acts on the longitudinal ends of the first external electrode 40A and the second external electrode 40B toward the center of the laminate 10. This tensile force is in the opposite direction to the force acting on the first external electrode 40A and the second external electrode 40B when the substrate is bent, so the two forces cancel each other out. This makes it possible to sufficiently reduce the stress acting on the laminate 10 near the longitudinal ends of the first external electrode 40A and the second external electrode 40B.

[0108] Furthermore, due to the above shape, the resin of the insulating layer 71A is discontinuous in the width direction W, so the stress in the wetted portion 75A of the resin of the insulating layer 71A in the width direction W is reduced. As a result, cracks are less likely to occur in the laminate 10 near the edge 76A.

[0109] (Third Modification of the First Embodiment) Using Figure 11, a modification of the connecting portion and exposed surface in the insulating layer will be explained. Figure 11 is a bottom view of a multilayer ceramic capacitor 1 according to the third modification of the first embodiment.

[0110] The insulating layer 71 is arranged with gaps in the width direction W and has a plurality of connecting portions 77B that connect the first external electrode 40A and the second external electrode 40B. The connecting portions 77B have a plurality of X-shaped portions defined by 78B on the exposed surface, which will be described later. The connecting portions 77B are the same portions as the first portion 72 of the insulating layer 71.

[0111] Between the multiple connecting portions 77B in the width direction W, exposed surfaces 78B are provided, on which the first main surface TS1 of the laminate is exposed. The multiple exposed surfaces 78B are rhombic in shape and are arranged so that their sides face each other.

[0112] The wetting spread portion 75B and edge 76B of the insulating layer 71B are located on the first main surface TS1 of the laminate 10. Alternatively, the wetting spread portion 75B and edge 76B of the insulating layer 71 may be located on the first side surface WS1 and the second side surface WS2, or on the ridge line between the first main surface TS1 and the first side surface WS1 and the ridge line between the first main surface TS1 and the second side surface WS2.

[0113] Due to the shape described above, the resin of the insulating layer 71B is continuous in the longitudinal direction L, connecting the first external electrode 40A and the second external electrode 40B in the longitudinal direction L. Therefore, a tensile force acts on the longitudinal ends of the first external electrode 40A and the second external electrode 40B toward the longitudinal center of the laminate 10. Since this tensile force is in the opposite direction to the force acting on the first external electrode 40A and the second external electrode 40B when the substrate is bent, the two forces cancel each other out. As a result, the stress acting on the laminate 10 near the longitudinal ends of the first external electrode 40A and the second external electrode 40B can be sufficiently reduced.

[0114] Furthermore, due to the above shape, the resin of the insulating layer 71B is discontinuous in the width direction W, so the stress in the wetted portion 75B of the resin of the insulating layer 71B in the width direction W is reduced. As a result, cracks are less likely to occur in the laminate 10 near the edge 76B.

[0115] (Second Embodiment) The multilayer ceramic capacitor 1 according to the second embodiment will be described with reference to Figure 12. Figure 12 is a cross-sectional view of the multilayer ceramic capacitor according to the second embodiment. Since the multilayer ceramic capacitor 1 according to the second embodiment has the same basic configuration as that according to the first embodiment, only the differences will be described below.

[0116] The insulating layer 71C is formed to cover at least a portion of the first main surface TS1 of the laminate 10, at least a portion of the first covering portion 91A, and at least a portion of the second covering portion 91B.

[0117] The insulating layer 71C is arranged at intervals in the width direction W and has a plurality of thick film connecting portions 77C that connect the first external electrode 40A and the second external electrode 40B. The plurality of thick film connecting portions 77C are formed in a straight line along the length direction L. The plurality of thick film connecting portions 77C are arranged in four rows in the width direction W, and it is preferable that there be three or more. The plan view shape of the plurality of thick film connecting portions 77C is the same as that of the connecting portion 77 in the first embodiment.

[0118] The insulating layer 71C has thin film connecting portions 78C that are thinner than the thick film connecting portions 77C and are provided between the multiple thick film connecting portions 77C in the width direction W. The thin film connecting portions 78C can also be described as thin film portions that divide the multiple thick film connecting portions 77C in the width direction W. The thin film connecting portions 78C are formed in a straight line along the length direction L. There are three rows of thin film connecting portions 78C. There may also be two rows of thin film connecting portions 78C. The plan view shape of the multiple thin film connecting portions 78C is the same as the exposed surface 78 of the first embodiment.

[0119] The thickness of the thick film connecting portion 77C is, for example, 10 μm to 200 μm. The thickness of the thin film connecting portion 78C is thinner than the thickness of the thick film connecting portion 77C, for example, 5 μm to 50 μm.

[0120] The wetting spread portion 75C and edge 76C of the insulating layer 71C are located on the first main surface TS1 of the laminate 10. Alternatively, the wetting spread portion 75C and edge 76C of the insulating layer 71 may be located on the first side surface WS1 and the second side surface WS2, or on the ridge line between the first main surface TS1 and the first side surface WS1 and the ridge line between the first main surface TS1 and the second side surface WS2.

[0121] Due to the above shape, the thick film connecting portion 77C of the insulating layer 71 is continuous in the longitudinal direction L, linearly connecting the first external electrode 40A and the second external electrode 40B. Therefore, a tensile force acts on the longitudinal ends of the first external electrode 40A and the second external electrode 40B toward the center of the laminate 10. Since this tensile force is in the opposite direction to the force acting on the first external electrode 40A and the second external electrode 40B when the substrate is bent, the two forces cancel each other out. As a result, the stress acting on the laminate 10 near the longitudinal ends of the first external electrode 40A and the second external electrode 40B can be sufficiently reduced.

[0122] Furthermore, due to the above shape, the thick film connecting portion 77C of the insulating layer 71C is discontinuous in the width direction W, so the stress on the wetted portion 75C of the resin of the insulating layer 71C in the width direction W is reduced. As a result, cracks are less likely to occur in the laminate 10 near the edge 76C.

[0123] As a variation of the second embodiment, the thick film connecting portion and the thin film connecting portion do not have to be linear. For example, the thick film connecting portion and the thin film connecting portion may be curved in part or in whole, meandering in part or in whole, or zigzag in part or in whole.

[0124] In the multilayer ceramic capacitor 1 according to this embodiment, the occurrence of cracks in the laminate 10 when the substrate is deflected can be suppressed, as can the occurrence of cracks in the laminate 10 near the edge 76C in the width direction W of the insulating layer 71C.

[0125] (Modified Version of the Second Embodiment) A modified version of the second embodiment of the multilayer ceramic capacitor 1 will be described using Figure 13. Figure 13 is a cross-sectional view of the modified version of the second embodiment of the multilayer ceramic capacitor 1.

[0126] The insulating layer 71D has a plurality of thick film connecting portions 77D that extend in the longitudinal direction L on the first main surface TS1 and are spaced apart in the width direction W, connecting the first external electrode 40A and the second external electrode 40B. The plurality of thick film connecting portions 77D are formed linearly along the longitudinal direction L. The plurality of thick film connecting portions 77D are arranged in four rows in the width direction W, and it is preferable that there be three or more rows. The plan view shape of the plurality of thick film connecting portions 77D is the same as that of the connecting portion 77 in the first embodiment.

[0127] The insulating layer 71D has thin film connecting portions 78D that are thinner than the thick film connecting portions 77D and are provided between the multiple thick film connecting portions 77D in the width direction W. The multiple thin film connecting portions 78D are formed in a straight line along the length direction L. The plan view shape of the multiple thin film connecting portions 78C is the same as the exposed surface 78 of the first embodiment. The cross-sectional shape of the thin film connecting portion 78C is curved, and the bottom apex is closest to the first main surface TS1.

[0128] The thickness of the thick film connecting portion 77D is, for example, 10 μm to 200 μm. The thickness of the thin film connecting portion 78D is, for example, 5 μm to 50 μm.

[0129] The thin film connecting portion 78D is even thinner than the thin film connecting portion 78C of the second embodiment. In other words, the thin film connecting portion 78D is formed to be as thin as possible so that the first main surface TS1 is not exposed.

[0130] The wetting spread portion 75D and edge 76D of the insulating layer 71D are located on the first main surface TS1 of the laminate 10. Alternatively, the wetting spread portion 75D and edge 76D of the insulating layer 71 may be located on the first side surface WS1 and the second side surface WS2, or on the ridge line between the first main surface TS1 and the first side surface WS1 and the ridge line between the first main surface TS1 and the second side surface WS2.

[0131] Due to the above shape, the thick film connecting portion 77D of the insulating layer 71D is discontinuous in the width direction W, so the stress on the wetted spreading portion 75D of the resin of the insulating layer 71D in the width direction W is reduced. As a result, cracks in the laminate 10 are less likely to occur near the edge 76C.

[0132] (Other Embodiments) The configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 13. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 14A, 14B, and 14C.

[0133] The multilayer ceramic capacitor 1 shown in Figure 14A is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not drawn out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 14B is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 14C is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is reduced, and the voltage withstand capability of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0134] In the embodiments described above, a multilayer ceramic capacitor was given as an example of a multilayer ceramic electronic component in which a dielectric layer 20 made of dielectric ceramic is used as the ceramic layer. However, the multilayer ceramic electronic components of this disclosure are not limited to this. For example, the ceramic electronic components of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer, and thermistors using semiconductor ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, and examples of semiconductor ceramics include spinel ceramics.

[0135] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0136] 1: Multilayer ceramic capacitor (multilayer ceramic electronic component) 10: Laminate 20: Dielectric layer 30: Internal electrode layer 40: External electrode 40A: First external electrode 40B: Second external electrode 71: Insulating layer 71A: Insulating layer 71B: Insulating layer 71C: Insulating layer 71D: Insulating layer 76: Edge 76A: Edge 76B: Edge 76C: Edge 76D: Edge 77: Connecting part 77A: Connecting part 77Aa: First connecting part 77Ab: Second connecting part 77B: Connecting part 77C: Thick film connecting part 77D: Thick film connecting part 78: Exposed surface 78A: Exposed surface 78B: Exposed surface 78C: Thin film connecting part 78D: Thin film connecting part 91A: First covering part 91B: Second covering part 91A: First covering part 91B: Second covering part

Claims

1. A laminate comprising a plurality of dielectric layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction; a first external electrode disposed on the first end surface side and having a first covering portion that covers a part of the first end surface side of the first main surface; a second external electrode disposed on the second end surface side and having a second covering portion that covers a part of the second end surface side of the first main surface; and an insulating layer formed to cover at least a part of the first main surface of the laminate, at least a part of the first covering portion, and at least a part of the second covering portion, wherein the insulating layer has a plurality of connecting portions that extend in the length direction on the first main surface and are spaced apart in the width direction to connect the first external electrode and the second external electrode. A multilayer ceramic electronic component, wherein exposed surfaces are provided between the plurality of connecting portions in the width direction, on which the first main surface of the laminate is exposed.

2. The multilayer ceramic electronic component according to claim 1, wherein the exposed surfaces are arranged in a plurality in the width direction.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein the plurality of connecting portions are arranged in a line in the width direction, with three or more of them aligned.

4. A laminate comprising a plurality of dielectric layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction; a first external electrode disposed on the first end surface side and having a first covering portion that covers a portion of the first main surface on the first end surface side; a second external electrode disposed on the second end surface side and having a second covering portion that covers a portion of the second main surface on the first main surface; and an insulating layer formed to cover at least a portion of the first main surface of the laminate, at least a portion of the first covering portion, and at least a portion of the second covering portion. The insulating layer comprises a plurality of thick film connecting portions extending in the longitudinal direction on the first main surface and spaced apart in the width direction so as to connect the first external electrode and the second external electrode, and thin film connecting portions that are thinner than the thick film connecting portions and provided between the plurality of thick film connecting portions in the width direction.

5. The multilayer ceramic electronic component according to claim 4, wherein the thin film connecting portions are arranged in a plurality in the width direction.

6. The multilayer ceramic electronic component according to claim 4 or 5, wherein three or more of the thick film connecting portions are arranged in the width direction.

Images