Semiconductor storage device and information processing system

Abstract

Provided is a semiconductor storage device that is capable of stably reading and writing data at high speed. The semiconductor storage device comprises a memory cell array in which a plurality of memory cells 40 are arranged in a matrix. A pair of first and second magnetic tunnel junction elements MTJ11 and MTJ12 are provided for holding the potential of a first storage node and the potential of a second storage node of a data holding mechanism of each memory cell at a first potential and a second potential, respectively, in a complementary and non-volatile manner according to storage data, and are set to a high resistance and a low resistance, respectively, in a complementary manner according to the storage data. The data holding mechanism further includes a first read drive transistor RTr0 which is controlled by the potential of one of the first storage node and the second storage node to drive the potential of the first read node to the first potential in the conductive state.

Description

Semiconductor memory devices and information processing systems

[0001] This invention relates to a semiconductor memory device using a magnetic tunnel junction element and an information processing system using a semiconductor memory device.

[0002] (Background of magnetic random access memory)

[0003] Non-volatile memory devices that utilize magnetoresistive elements (MRAM: Magnetic Random Access Memory or Magnetoresistive Random Access Memory) are attracting attention as next-generation logic integrated circuits.

[0004] One example of such an MRAM configuration is spin-transfer torque (STT) MRAM. However, in STT-MRAM, a large voltage is applied to the device's tunnel oxide during writing, resulting in a continuous trade-off between data retention, write durability, and write speed. In other words, despite the maturation of STT-MRAM technology, it still has limitations in meeting the requirements of high-speed RAM applications that demand a combination of high speed, unlimited durability, and sufficient data retention.

[0005] As an MRAM configuration that can solve such problems, the three-terminal SOT (Spin Orbit Torque)-MRAM (Spin Orbit Torque-Magnetic Random Access Memory) is known to be suitable for non-volatile memory where high speed of writing is required. For example, Patent Documents 1 and 2 disclose a three-terminal SOT-MRAM composed of a laminate of a channel layer, a recording layer, a barrier layer, and a reference layer.

[0006] For example, the memory cell of the SOT-MRAM disclosed in Patent Document 1 is composed of a stack of a channel layer, a recording layer, a barrier layer, and a reference layer from the bottom layer, and is equipped with three terminals.

[0007] The channel layer is a conductive layer composed of heavy metals, etc., and when a writing current flows through this layer, it is a region that generates spin-orbit torque. The recording layer is composed of a magnetic material, and its magnetization M is variable between the + axis and - axis depending on the spin-orbit torque generated by the writing current flowing through the channel layer. The barrier layer is a non-magnetic layer composed of a tunnel insulating layer.

[0008] The reference layer is composed of a magnetic material, and the direction of its magnetization M is fixed.

[0009] When writing data to SOT-MRAM, a voltage corresponding to the data to be written is applied between the second and third terminals, and a write current flows through the channel layer. This causes a spin-orbit torque to act, and the direction of the magnetization M of the recording layer changes according to the direction of the write current. At this time, no current flows through the tunnel insulating layer.

[0010] When the magnetization direction M of the recording layer and the magnetization direction of the reference layer are the same (parallel state), the resistance between the reference layer and the recording layer is small. On the other hand, when the magnetization directions of the recording layer and the reference layer are opposite (antiparallel state), the resistance between the reference layer and the recording layer becomes relatively large. Data is assigned to the changing resistance value.

[0011] When reading data from the SOT-MRAM, a read voltage is applied between the first terminal and the second or third terminal, and data corresponding to the magnitude of the read current flowing through the magnetic tunnel junction (MTJ), which consists of a recording layer, a barrier layer, and a reference layer, is output.

[0012] Due to the configuration described above, SOT-MRAM makes it possible to eliminate the high voltage applied to the device's tunnel oxide film during writing.

[0013] The configuration disclosed in Patent Document 2 provides a configuration that suppresses the decrease in read speed while suppressing the write current, even when the integration density is increased.

[0014] On the other hand, SOT-MRAM is a non-volatile memory technology that uses pure spin current due to the spin Hall effect as described above to perform high-speed writing. As one configuration for this, the use of a topological insulator with a strong spin Hall effect is being considered in order to reduce the writing current and power (for example, Non-Patent Document 1).

[0015] On the other hand, with expectations for further enhanced device functionality, the use of "topological antiferromagnets" as a substitute for ferromagnets is attracting attention. The advantages of so-called antiferromagnets include: (i) they do not create leakage magnetic fields, enabling high-density and simple device structures; (ii) their spin resonance frequency is higher than that of ferromagnets (GHz), allowing for higher speeds; and (iii) they offer greater freedom in material selection.

[0016] However, since antiferromagnets do not possess spontaneous magnetization, detecting and controlling spontaneous responses originating from their spin structure is generally difficult.

[0017] In contrast, Mn is a topological antiferromagnetic metal. ３ Sn is being actively researched as a candidate material for non-volatile memory, which could lead to the realization of terahertz electronic devices.

[0018] Mn ３ Sn is an antiferromagnetic material in which a noncollinear spin structure called the inverse 120-degree structure appears from a high temperature of 430 K. This antiferromagnetic spin structure achieves a macroscopically time-reversal symmetry-broken state, similar to that of ferromagnetic order, even in the zero-magnetization state. This is due to the strong order of the spin structure (cluster magnetic octupoles), in which six spins, each consisting of three sublattices, are arranged in a two-layer kagome lattice.

[0019] Here, a "topological antiferromagnet" is a Weyl semimetal that exhibits a topological semimetallic state, where the interior is in a semimetallic state and the surface state is in a metallic state.

[0020] For example, the spin Hall effect, which converts electric current into spin current, has been studied mainly in transition metals with large spin-orbit interactions, but in antiferromagnetic materials such as Mn ３Regarding Sn, an anomalous Hall effect was also observed, and furthermore, due to an effect called the "magnetic spin Hall effect," Mn stacked with ferromagnetic materials was also observed. ３ It has been reported that surface spin accumulation occurs on the surface of Sn, generating a spin torque in the magnetization of adjacent ferromagnetic materials (for example, Non-Patent Documents 2 and 3).

[0021] On the other hand, applying MRAM to last-level caches (LLCs) such as L3 and L4 caches in large-scale microprocessors is promising.

[0022] This is because MRAM has characteristics such as data not being lost even when the power is turned off (non-volatile) and enabling high-speed rewriting.

[0023] Conventional cache memory sometimes uses, for example, SRAM (Static Random Access Memory) to prioritize high operating speed. However, because SRAM is volatile memory, information is lost when the power is turned off.

[0024] To address these challenges, a cache memory configuration has been proposed that uses on-chip memory capable of recording data non-volatilely.

[0025] For example, Patent Document 3 discloses a hybrid SRAM cell that combines a standard 6T SRAM memory cell with two non-volatile memory elements (nonvolatile resistive RAM) connected to its output.

[0026] Here, before powering down the cache memory, the data stored in the cache memory (e.g., SRAM) is written to non-volatile storage. Subsequently, the data written to the non-volatile storage is read out as part of the process of exiting the low-power state and returning to the active state, and stored in the cache memory.

[0027] Japanese Patent Publication No. 2018-157108, Japanese Patent Publication No. 2023-35644, U.S. Patent No. 10748602

[0028] https: / / www.titech.ac.jp / news / 2021 / 062339 https: / / www.jst.go.jp / pr / announce / 20190117-2 / index.html https: / / www.jst.go.jp / pr / announce / 20151029-2 / index.html

[0029] As mentioned above, MRAM is a random-access memory that possesses excellent characteristics such as non-volatility, high-speed operation, and high durability. For this reason, it is considered a leading candidate for a technology suitable for the integration of non-volatile memory and integrated circuits.

[0030] Furthermore, SOT-MRAM allows for the suppression of energy consumption during writing.

[0031] On the other hand, when SRAM is used as cache memory, SRAM memory cells typically do not need to be refreshed (i.e., rewritten) to maintain the state in which data has been written, but SRAM memory cells consume energy while maintaining that state. Therefore, in computing systems such as battery-powered systems, embedded systems, or systems-on-a-chip (SOCs), it is necessary to put processing blocks and cache memory into a low-power "sleep" state to reduce power consumption when the processor or processing unit is idle. Thus, when considering applications such as cache memory, SRAM memory cells have the problem of being volatile, although they are excellent in terms of speed, and it is also necessary to stably reproduce the stored data when the power is turned on again after being turned off.

[0032] One possible solution is a hybrid SRAM cell combined with a non-volatile memory cell, as described in Patent Document 3. However, to meet the recent demand for faster computational processing, even faster memory operation is required.

[0033] Currently, sufficient consideration has not been given to circuit configurations that enable stable and high-speed data writing and reading under these conditions.

[0034] The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor memory device capable of stable high-speed data reading and writing in an SOT-MRAM.

[0035] Another object of the present invention is to provide a semiconductor memory device capable of stably reproducing stored data when power is turned on again.

[0036] (Item 1)

[0037] According to one aspect of this invention, a semiconductor memory device comprises a memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell having a first storage node and a second storage node, and includes a data holding mechanism for storing storage data, the data holding mechanism includes a pair of first and second magnetic tunnel junction elements for non-volatilely holding the potentials of the first and second storage nodes to a first potential and a second potential, respectively, complementaryly according to the storage data, the first and second magnetic tunnel junction elements are supplied with a write current according to the storage data, and are supplied with a write current to change complementaryly to high resistance and low resistance, respectively, and are controlled by the potential of either the first or second storage node to be either a conducting state or a non-conducting state, and in the conducting state, the potential of the first read node is driven to the first potential The first and second magnetic tunnel junction elements further include a read drive element, wherein the side of the first and second storage nodes set to the first potential according to the stored data is connected to a potential source of the first potential via the low-resistance side of the first and second magnetic tunnel junction elements, and is provided in the column direction of the memory cell array so as to be shared by the memory cells and connected to the first read node of each of the data holding mechanisms, and further includes a plurality of first read bit lines provided between the first read bit lines and the plurality of first read nodes, respectively, and a read control circuit that, in a read operation, selectively controls the first read switching element that reads data and reads the potential of the first read node of the selected memory cell as read data via the first read bit line. (Item 2)

[0038] Preferably, the semiconductor memory device of item 1 further comprises a plurality of write bit line pairs provided in the column direction of the memory cell array, wherein each write bit line pair includes a first write bit line provided in common to the first storage node of the corresponding data holding mechanism and a second write bit line provided in common to the second storage node of the corresponding data holding mechanism, and comprises a pair of first write switching elements provided between the first and second storage nodes and the first and second write bit lines, respectively, and a write control circuit that, in a write operation to the data holding mechanism, supplies the write current to the first magnetic tunnel junction element and the second magnetic tunnel junction element via the write bit line so that the potentials of the first storage node and the second storage node are complementary to the stored data, and so that their resistance states become low resistance and high resistance, respectively. (Item 3)

[0039] Preferably, in the semiconductor memory device of item 2, each of the first and second magnetic tunnel junction elements has a first node and an internal node, and each data holding mechanism includes a cross-coupled inverter cell having a first inverter and a second inverter with input nodes and output nodes cross-connected to each other, the first storage node and the second storage node each correspond to the cross-connected nodes, and each of the first and second magnetic tunnel junction elements has a second node and a third node for conducting the write current, which are provided to be connected to the internal node. The first electrode of the first and second magnetic tunnel junction elements is connected to the first memory node, which is the output node of the first inverter, and to the second memory node, which is the output node of the second inverter, respectively. The first node of the first and second magnetic tunnel junction elements is connected to the ground potential, which is the first potential, for a predetermined period after power-on. The third node of each of the magnetic tunnel junction elements in the plurality of memory cells is connected to the plurality of write bit line pairs via the pair of first write switching elements. (Item 4)

[0040] Preferably, in the semiconductor memory device according to item 1, each of said data holding mechanisms further comprises a second read drive element controlled by the potential of the other one of said first storage node and said second storage node to drive the potential of a second read node to said first potential in a conductive state, further comprising: a plurality of second read bit lines provided to be shared by said memory cells in the column direction of said memory cell array and provided so as to be connectable to said second read node of each of said data holding mechanisms; and a plurality of second read switching elements respectively provided between said second read bit lines and said plurality of second read nodes, wherein said read control circuit selectively controls said first and second read switching elements that read data in said read operation, and reads the potentials of said first and second read nodes of the selected memory cell via said first and second read bit lines. (Item 5)

[0041] Preferably, in the semiconductor memory device of item 2, each of the first and second magnetic tunnel junction elements has a first node and an internal node, and each data holding mechanism includes a first PMOS transistor whose gate potential is controlled by the potential of the second memory node and is provided between the power supply potential and the first memory node, a second PMOS transistor whose gate potential is controlled by the potential of the first memory node and is provided between the power supply potential and the second memory node, a first NMOS transistor whose gate potential is controlled by the potential of the second memory node and whose source is connected to ground potential, and a second NMOS transistor whose gate potential is controlled by the potential of the first memory node and whose source is connected to ground potential. The transistors include, and each of the first and second magnetic tunnel junction elements has a first electrode having a second node and a third node for conducting the write current, which are provided to connect to the internal node, the second node of the first electrode of the first and second magnetic tunnel junction elements is connected to the first memory node and the second memory node, respectively, the first node of the first and second magnetic tunnel junction elements is connected to the drains of the first and second NMOS transistors, respectively, and the third node of the first and second magnetic tunnel junction elements is provided to be connectable to the first and second write bit lines via the first write switching element, respectively. (Item 6)

[0042] Preferably, in the semiconductor memory device of item 5, each data retention mechanism further includes a second read drive element controlled by the potential of the other of the first and second storage nodes to drive the potential of a second read node to the first potential in a conductive state; a plurality of second read bit lines provided in the column direction of the memory cell array so as to be shared by the memory cells and so as to be connectable to the second read node of each data retention mechanism; and a plurality of second read switching elements provided between the second read bit lines and the plurality of second read nodes, respectively, wherein the read control circuit selectively controls the first and second read switching elements that read data in the read operation and reads the potentials of the first and second read nodes of the selected memory cell via the first and second read bit lines. (Item 7)

[0043] Preferably, in the semiconductor memory device of item 2, each data holding mechanism further includes a third magnetic tunnel junction element and a fourth magnetic tunnel junction element provided corresponding to the first magnetic tunnel junction element and the second magnetic tunnel junction element, respectively, wherein the first and third magnetic tunnel junction elements are supplied with a write current according to the stored data and change to high resistance and low resistance, respectively, and the second and fourth magnetic tunnel junction elements are supplied with the write current according to the stored data and change to low resistance and high resistance, respectively. The first to fourth magnetic tunnel junction elements are modified, and each of the first to fourth magnetic tunnel junction elements has a first node and an internal node, and each data holding mechanism has a first PMOS transistor whose gate potential is controlled by the potential of the second storage node, and is provided between the power supply potential and the first storage node, with its drain connected to the power supply potential, and a second PMOS transistor whose gate potential is controlled by the potential of the first storage node, and is provided between the power supply potential and the second storage node, with its drain connected to the power supply potential, and the gate potential is controlled by the potential of the second storage node The magnetic tunnel junction further includes a first NMOS transistor whose gate potential is controlled and whose source is connected to ground potential, and a second NMOS transistor whose gate potential is controlled by the potential of the first memory node and whose source is connected to the ground potential, wherein each of the first and second magnetic tunnel junction elements has a first electrode provided to connect to the internal node, the first electrode has a second node and a third node for conducting the write current, and each of the third and fourth magnetic tunnel junction elements has the write current flowing between the second node and the third node. When writing, the internal node is connected to the first electrode so that the writing current flows in the opposite direction to that of the first and second magnetic tunnel junction elements, the second node of the first electrode of the first and second magnetic tunnel junction elements is connected to the first memory node and the second memory node, respectively, the first node of the first and second magnetic tunnel junction elements is connected to the drains of the first and second NMOS transistors, respectively, and the first node of the third and fourth magnetic tunnel junction elements is connected to, respectively,The third nodes of the first and second magnetic tunnel junction elements are connected to the sources of the first and second PMOS transistors, and are each connectable to the first and second write bit lines via the first write switching element. (Item 8)

[0044] Preferably, in the semiconductor memory device of item 2, each data holding mechanism further includes a third magnetic tunnel junction element and a fourth magnetic tunnel junction element provided corresponding to the first magnetic tunnel junction element and the second magnetic tunnel junction element, respectively, wherein the first and third magnetic tunnel junction elements are supplied with a write current according to the stored data and change to high resistance and low resistance, respectively, and the second and fourth magnetic tunnel junction elements are supplied with the write current according to the stored data and change to low resistance and high resistance, respectively, wherein each of the first to fourth magnetic tunnel junction elements has a first node and an internal node, and each data holding mechanism includes a first NMOS transistor whose gate potential is controlled by the potential of the second storage node and whose source is connected to ground potential, and a second NMOS transistor whose gate potential is controlled by the potential of the first storage node and whose source is connected to ground potential, and each of the first and second magnetic tunnel junction elements has the internal node and Each of the third and fourth magnetic tunnel junction elements has a first electrode provided for connection, the first electrode having a second node and a third node for conducting the write current, and each of the third and fourth magnetic tunnel junction elements is provided such that the internal node is connected to the first electrode such that the write current flows in the opposite direction to that of the first and second magnetic tunnel junction elements when the write current flows between the second node and the third node, the second node of the first electrode of the first and second magnetic tunnel junction elements is connected to the first memory node and the second memory node, respectively, the first node of the first and second magnetic tunnel junction elements is connected to the drains of the first and second NMOS transistors, respectively, the third node of the first and second magnetic tunnel junction elements is connectable to the first and second write bit lines via the first write switching element, respectively, and the first node of the third and fourth magnetic tunnel junction elements is connected to the power supply potential, respectively. (Item 9)

[0045] Preferably, in the semiconductor memory device of item 8, each data retention mechanism further includes a second read drive element controlled by the potential of the other of the first and second storage nodes to drive the potential of a second read node to the first potential in a conductive state; a plurality of second read bit lines provided in the column direction of the memory cell array so as to be shared by the memory cells and so as to be connectable to the second read node of each data retention mechanism; and a plurality of second read switching elements provided between the second read bit lines and the plurality of second read nodes, respectively, wherein the read control circuit selectively controls the first and second read switching elements that read data in the read operation and reads the potentials of the first and second read nodes of the selected memory cell via the first and second read bit lines. (Item 10)

[0046] According to another aspect of this invention, a semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell having a first storage node and a second storage node, and including a data holding mechanism for storing storage data, the data holding mechanism including a pair of first and second magnetic tunnel junction elements for non-volatilely holding the potentials of the first storage node and the second storage node complementaryly to a first potential and a second potential, respectively, according to the storage data, the first and second magnetic tunnel junction elements are supplied with a write current according to the storage data and change complementaryly to high resistance and low resistance, respectively, each of the first and second magnetic tunnel junction elements has a first node and an internal node, a first PMOS transistor whose gate potential is controlled by the potential of the second storage node and provided between the power supply potential and the first storage node, and a second PMOS transistor whose gate potential is controlled by the potential of the first storage node and provided between the power supply potential and the second storage node The magnetic tunnel junction includes a first NMOS transistor whose gate potential is controlled by the potential of the second memory node and whose source is connected to ground potential, and a second NMOS transistor whose gate potential is controlled by the potential of the first memory node and whose source is connected to ground potential, wherein each of the first and second magnetic tunnel junction elements has a first electrode having a second node and a third node for conducting the write current, which are provided to connect to the internal node, and the second node of the first electrode of the first and second magnetic tunnel junction elements is Each of the first and second magnetic tunnel junction elements is connected to the first and second memory nodes, and the first node of each magnetic tunnel junction element is connected to the drains of the first and second NMOS transistors, and further comprises a plurality of write bit line pairs provided in the column direction of the memory cell array, each write bit line pair including a first write bit line provided in common to the first memory node of the corresponding data holding mechanism and a second write bit line provided in common to the second memory node of the corresponding data holding mechanism.The system comprises a pair of first write-switching elements provided between the first and second storage nodes and the first and second write-bit lines, respectively, and a write-control circuit that, in a write operation to the data holding mechanism, supplies write current to the first magnetic tunnel junction element and the second magnetic tunnel junction element via the write-bit lines such that their relative resistance states become low resistance and high resistance, respectively, and the third nodes of the first and second magnetic tunnel junction elements are each connectable to the first and second write-bit lines via the first write-switching element. (Item 11)

[0047] According to yet another aspect of this invention, a semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell having a first storage node and a second storage node, and including a data holding mechanism for storing storage data, the data holding mechanism including a pair of first magnetic tunnel junction elements and second magnetic tunnel junction elements for non-volatilely holding the potential of the first storage node and the potential of the second storage node to a first potential and a second potential, respectively, in a complementary manner according to the storage data, and the first magnetic tunnel The first and third magnetic tunnel junction elements are provided corresponding to the first and second magnetic tunnel junction elements, respectively, and the second and fourth magnetic tunnel junction elements are supplied with a write current according to the stored data, causing them to change to high resistance and low resistance respectively, and the second and fourth magnetic tunnel junction elements are supplied with a write current according to the stored data, causing them to change to low resistance and high resistance respectively, and each of the first to fourth magnetic tunnel junction elements has a first node and an internal node, A first PMOS transistor whose gate potential is controlled by the potential of the second memory node, provided between the power supply potential and the first memory node, with its drain connected to the power supply potential; a second PMOS transistor whose gate potential is controlled by the potential of the first memory node, provided between the power supply potential and the second memory node, with its drain connected to the power supply potential; a first NMOS transistor whose gate potential is controlled by the potential of the second memory node, with its source connected to ground potential; and a first NMOS transistor whose gate potential is controlled by the potential of the first memory node, with its source connected to ground potential. The first and second magnetic tunnel junction elements include a second NMOS transistor connected to ground potential, each of the first and second magnetic tunnel junction elements has a first electrode provided to connect to the internal node, the first electrode has a second node and a third node for conducting the write current, and each of the third and fourth magnetic tunnel junction elements has the internal node connected to the first electrode such that when the write current flows between the second node and the third node, the write current flows in the opposite direction to that of the first and second magnetic tunnel junction elements.The second nodes of the first electrodes of the first and second magnetic tunnel junction elements are connected to the first and second storage nodes, respectively; the first nodes of the first and second magnetic tunnel junction elements are connected to the drains of the first and second NMOS transistors, respectively; the first nodes of the third and fourth magnetic tunnel junction elements are connected to the sources of the first and second PMOS transistors, respectively; and the memory cell array further comprises a plurality of write bit line pairs provided in the column direction, wherein the write bit line pairs include a first write bit line provided in common to the first storage node of the corresponding data holding mechanism and the corresponding data holding mechanism The system includes a second write bit line provided in common to the second storage node, a pair of first write switching elements provided between the first and second storage nodes and the first and second write bit lines, and a write control circuit that, in a write operation to the data holding mechanism, supplies write current to the first magnetic tunnel junction element and the second magnetic tunnel junction element via the write bit line such that their resistance states become low resistance and high resistance, respectively, and the third nodes of the first and second magnetic tunnel junction elements are provided so as to be connectable to the first and second write bit lines via the first write switching element. (Item 11)

[0048] According to another aspect of this invention, an information processing system is provided which incorporates a semiconductor memory device described in any one of items 1 to 10. (Item 12)

[0049] According to another aspect of this invention, an information processing system is provided which a semiconductor memory device described in any one of items 1 to 10 is used as a cache memory.

[0050] According to the configuration of the semiconductor memory device of the present invention, stable and high-speed data reading and writing are possible in SOT-MRAM.

[0051] According to the configuration of the semiconductor memory device of the present invention, it becomes possible to have a semiconductor memory device that can stably reproduce stored data when the power is turned on again, and a method for writing such data.

[0052] This is a conceptual diagram showing the configuration of magnetic tunnel junction elements constituting a memory cell. This is a diagram showing an example of the configuration of a memory cell 40 in a comparative example using MTJ elements. This is a diagram showing the planar shape of the lower electrode corresponding to the MTJ element in the SOT-MRAM structure of the comparative example. This is a diagram showing an example of the cross-sectional structure when the MRAM circuit configuration shown in Figure 2 is formed on a silicon substrate. Figure 5 is a conceptual diagram showing an example of data read control of a memory cell 40 in a comparative example. This is a conceptual diagram for explaining the configuration of the memory cell array 40 and the circuit for controlling read and write in the semiconductor memory device 1000.0 of the comparative example. This is a functional block diagram for explaining the configuration of an arithmetic system 10 that includes the semiconductor memory device 1000.0 as a cache memory. This is a diagram showing an example of the configuration of a memory cell 40 in Embodiment 1 using MTJ elements. This is a conceptual diagram for explaining the configuration of the memory cell array 40 and the circuit for controlling read and write in the semiconductor memory device 1000 of Embodiment 1. This is a timing chart for explaining the data writing and reading operations to the semiconductor memory device 1000 of Embodiment 1. This is a diagram showing an example of the configuration of a memory cell 40 in Embodiment 2 using MTJ elements. This is a timing chart for explaining the data writing and reading operations to the semiconductor memory device of Embodiment 2. This figure shows an example of the configuration of the memory cell 40 of Embodiment 3 using an MTJ element. This figure shows an example of the configuration of the memory cell 40 of Embodiment 4 using an MTJ element. This figure shows an example of the configuration of the memory cell 40 of Embodiment 5 using an MTJ element. This figure shows an example of the configuration of the memory cell 40 of Embodiment 6 using an MTJ element. This is the first figure showing the cross-sectional structure of the memory cell 40 of Embodiment 6 including the transistor WLTR01 and the third node CTN103 of the lower electrode. This figure shows an example of the planar structure and cross-sectional structure of the lower electrode of the first magnetic tunnel junction element MTJ11 of the memory cell 40 of Embodiment 6. This figure shows an example of the configuration of the memory cell 40 of Embodiment 7 using an MTJ element. This figure shows an example of the configuration of the memory cell 40 of Embodiment 8 using an MTJ element. This figure shows an example of the configuration of the memory cell 40 of Embodiment 9 using an MTJ element.

[0053] The configuration of a semiconductor memory device according to an embodiment of the present invention will be described below. In the following embodiments, components and processing steps denoted by the same reference numerals are identical or equivalent, and their descriptions will not be repeated unless necessary. [Embodiment] (Comparative example of MRAM circuit configuration)

[0054] Preferred embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0055] Figure 1 is a conceptual diagram showing the configuration of a magnetic tunnel junction element (hereinafter referred to as "MTJ element") that constitutes a memory cell.

[0056] In this embodiment, in the schematic diagram of the MTJ element shown in Figure 1, the rectangle between node T2 and node T3 represents the lower electrode LEL, node T1 is the upper electrode, node T2 is one end of the lower electrode, and node T3 is the other end of the lower electrode. Here, the "lower electrode" is an example of a "first electrode" that flows the write current along the electrode during the write operation of the SOT-MRAM. When the upper and lower structure of the MTJ element is inverted as described below, the upper electrode provided on top of the internal node corresponds to the "first electrode".

[0057] Then, an MTJ element is formed on the lower electrode LEL via an internal node Tint.

[0058] In Figure 1, the MTJ element is simplified and represented as a variable resistor. [Comparative example of circuits]

[0059] Figure 2 shows an example of the configuration of a memory cell 40 in a comparative example using an MTJ element. Figure 2 shows an example of data writing control for the memory cell 40 in the comparative example.

[0060] Furthermore, as will be described later, Figure 5 is a conceptual diagram showing an example of data read control for the memory cell 40 in a comparative example.

[0061] When operating as a memory circuit, the memory cell 40 becomes a memory cell array arranged in a matrix. Therefore, although in reality there are more memory cells and corresponding signal lines arranged in both the row and column directions, these are omitted from the illustration in Figure 2.

[0062] As shown in Figure 2, in the comparative example memory cell 40, in a cross-coupled CMOS inverter SRCEL which is a data retention mechanism, one end (second node CTN002) of the lower electrode LEL11 of the MTJ element MTJ11 and the lower electrode LEL12 of the MTJ element MTJ12 are connected to the output nodes of the first and second inverters, respectively. The node on the upper electrode side of the MTJ element (first node CTN001) is connected to ground potential via transistors MRTR11 and MRTR12, whose opening and closing is controlled by a POR (Power On Rest) signal. Here, the "POR signal" is a signal transmitted from a reset circuit (not shown) when power is turned on in order to start the memory circuit in a stable state, and it is a signal that keeps the circuit in a reset state for a predetermined period until the power supply voltage stabilizes, and then releases the reset state.

[0063] More specifically, the memory cell 40 includes a pair of MTJ elements MTJ11 and MTJ12 and a cross-coupled inverter cell SRCEL, and has the following configuration.

[0064] The cross-coupled inverter cell SRCEL has a first inverter and a second inverter, the input node and the output node of which are cross-connected to each other. The first inverter has a PMOS transistor TP2 and an NMOS transistor TN2 connected in series between the power supply potential and the ground potential, and the second inverter has a PMOS transistor TP1 and an NMOS transistor TN1 connected in series between the power supply potential and the ground potential.

[0065] The connection node between PMOS transistor TP2 and NMOS transistor TN2 is the first memory node, and the connection node between PMOS transistor TP1 and NMOS transistor TN1 is the second memory node, and in the active state, the first and second memory nodes are at complementary potential levels (e.g., power supply potential and ground potential).

[0066] The second node (one end) CTN002 of the lower electrode LEL11 of the MTJ element MTJ11 and the second node (one end) of the lower electrode LEL12 of MTJ12 are connected to the output node of the first inverter and the output node of the second inverter, respectively.

[0067] The comparative example memory circuit includes a plurality of bit line pairs BL, / BL that are provided so as to be commonly connectable to the third node CTN003 of each MTJ element in the plurality of memory cells. The memory cell 40 further includes a pair of first selection transistors (write transistors) SRTR01, SRTR02, respectively, provided between each output node of the cross-coupled inverter cell SRCEL and the bit line pair. Hereinafter, elements that switch the connection between the bit line and the node in the memory cell by controlling the word line potential, such as write transistors or read transistors, will be referred to as "switching elements". Typically, "NMOS transistors" can be used as switching elements. However, they are not limited to NMOS transistors as long as they have a switching function. The same applies to the following embodiments.

[0068] A pair of second selection transistors, MRTR01 and MRTR02, are provided between the pair of third nodes (other ends) CTN003 of the pair of MTJ elements and the bit line pair BL, / BL, respectively.

[0069] Furthermore, the memory cell 40 includes a pair of reset transistors MRTR11 and MRTR12, each provided between a pair of first nodes of a pair of MTJ elements and ground potential, which become conductive for a predetermined period after power-on in response to a POR signal to maintain the first nodes of the pair of MTJ elements at ground potential. The comparative example memory circuit further includes a plurality of word lines WL for controlling the opening and closing of the first selection transistors SRTR01 and SRTR02 and the second selection transistors MRTR01 and MRTR02 according to signals from a write control circuit (not shown) and a read control circuit (not shown).

[0070] Figure 3 shows the planar shape of the lower electrode corresponding to the MTJ element in the comparative example SOT-MRAM structure.

[0071] As shown in Figure 3, through-holes are positioned at both ends of the lower electrode LEL so that current flows directly beneath the MTJ element MTJ11. These through-holes at both ends correspond to the second node CTN002 and the third node CTN003, respectively.

[0072] Furthermore, Figure 3 shows an example of the planar shape of the lower electrode LEL corresponding to the MTJ element MTJ11 in the memory cell structure of the SOT-MRAM shown in Figure 2, the position of the through-holes for connecting to the lower electrode LEL from the lower surface side of the lower electrode LEL (the parts that connect to the second and third nodes of the lower electrode via the through-holes are called "contact parts"), and the position of the lower surface of the MTJ element on the upper surface side of the lower electrode LEL.Therefore, Figure 3 virtually shows the state as seen from the lower surface side of the lower electrode LEL, looking through the lower electrode LEL to the lower surface of the MTJ element MTJ11.

[0073] In this specification, "MTJ element (magnetic tunnel junction element)" refers to an element having a structure in which a tunnel insulating film is sandwiched between two ferromagnetic layers. The resistance to current flowing through this ferromagnetic layer / tunnel insulating film / ferromagnetic layer is small if the magnetic field directions of the two ferromagnetic layers are parallel, and large if they are antiparallel, due to the tunnel magnetoresistance effect.

[0074] In an MTJ element, the direction of one of the two magnetic layers sandwiching the tunnel insulating film is fixed. This magnetic layer is called the "pinned layer." The direction of the other magnetic layer is changed so that it is parallel or antiparallel to the magnetic field direction of the pinned layer, allowing for selective settings of low and high resistance in the MTJ element. This magnetic layer is called the "free layer."

[0075] The stacked structure of the MTJ element shown in Figures 1 to 3 is not particularly limited, but in each embodiment described later, for example, a stacked structure of CoFeB / MgO / CoFeB is formed as the conventional ferromagnetic layer / tunnel insulating film / ferromagnetic layer, and furthermore, Mn is placed below the CoFeB on the free layer side. ３ The configuration includes Sn. Below the CoFeB on the free layer side is Mn. ３Like Sn, it is preferably a non-collinear antiferromagnet and an alloy having a chiral spin structure.

[0076] As described above, Mn stacked with a ferromagnetic material due to the "magnetic spin Hall effect" ３ Surface spin accumulation occurs on the surface of Sn, and spin torque is generated in the magnetization of the adjacent ferromagnetic material, so Mn ３ Sn has a structure that assists the spin reversal of CoFeB in the free layer. As a result, the current density required for spin reversal can be reduced. This makes it possible to further utilize the advantages of the structures of the memory cell and the memory array according to each embodiment.

[0077] For the lower electrode of the MTJ element, for example, tungsten (W) can be used. However, the metal for the electrode is not limited thereto. Further, as the antiferromagnet, if it is a (non-)collinear antiferromagnet that exhibits an anomalous Hall effect, Mn ３ It is not limited to Sn. For example, the antiferromagnet is Mn ３ Ga or Mn ３ It may be Ga, or may be an alloy in which a plurality of Sn, Ga and Ge are mixed. The ferromagnetic layer is not limited to CoFeB either, and may be, for example, CoFe or Co. Further, the tunnel insulating film (barrier layer) may also be AlO in addition to MgO ｘ , TiO ｘ or the like may be used.

[0078] Furthermore, the structure of the MTJ element is not particularly limited to the above configuration. For example, it may be an MTJ element structure using a non-collinear antiferromagnet (e.g., Mn ３ Sn) as a free layer and / or a pinned layer.

[0079] FIG. 4 is a diagram showing an example of a cross-sectional structure when the circuit configuration of the MRAM shown in FIG. 2 is formed on a silicon substrate.

[0080] Referring to FIG. 4, a transistor MRTR01 and a transistor MRTR11 are formed on a silicon substrate.

[0081] Here, the transistor formation process is called the "front-end process." The multilayer wiring process that follows the front-end process is called the "back-end process."

[0082] Although not shown in the diagram, a multilayer wiring consisting of n layers is formed on the silicon substrate. For example, in the diagram, the ground wiring is formed by the nth layer wiring in the uppermost layer. Note that the ground potential wiring may be formed by wiring in other layers, for example.

[0083] The source side of transistor MRTR01 is connected to the third node CTN003 of the lower electrode LEL via via holes VH, multilayer wiring, and contact CL, while the drain side of transistor MRTR01 is connected to the bit line BL. Here, although not particularly limited, the bit line BL is shown as being formed by, for example, the first layer wiring ML1. However, the bit line BL may also be formed by upper layer wiring. As will be described later, the potential of the bit line BL is selectively driven according to the data to be written.

[0084] The source side of transistor MRTR11 is connected to the ground potential wiring (GND) via contact CL, via hole VH, or multilayer wiring.

[0085] Furthermore, the drain side of transistor MRTR11 is connected to the wiring up to the nth layer via contact CL and multiple via holes VH, and is connected to the upper electrode UEL via via holes on the wiring of the nth layer, and is connected to the first node CTN001 of MTJ element MTJ11.

[0086] Furthermore, the word line for driving the gate potential of transistor MRTR01 is formed in the silicon semiconductor front-end / under-layer wiring process by either the second-layer wiring or the (n-1) wiring.

[0087] In other words, the process from the formation of transistors on a silicon semiconductor substrate to the wiring process just before the formation of MTJ elements is called the "front-end / under-layer wiring process."

[0088] In the front-end and underlayer wiring process, the surface of the lower insulating layer is preferably flattened by a polishing process such as CMP (Chemical Mechanical Polishing).

[0089] Furthermore, in multilayer wiring during the front-end and lower-layer wiring process, connections to the transistor's source and drain are made by forming plugs using contact embedding techniques such as tungsten. For example, for the first layer wiring, an aluminum alloy (AlSiCu, AlCu, etc.) may be deposited using PVD (Physical Vapor Deposition) or the like, and then the wiring may be formed by dry etching.

[0090] Furthermore, as a multilayer wiring technology, the so-called "damascene technology" may be used. That is, after forming wiring grooves on an insulating film, wiring metal (for example, Cu) may be deposited by a plating method, and then the wiring metal may be left only in the grooves by polishing using CMP (Chemical Mechanical Planarization) technology, etc., to form multilayer wiring.

[0091] For the damascene process, either single damascene or dual damascene can be used. When multilayer wiring is formed using the damascene process, a flat wiring structure can be obtained without the need for interlayer planarization, as the wiring metal is polished, thus facilitating the multilayering of fine wiring.

[0092] MTJ elements are formed on a silicon semiconductor substrate that has undergone a front-end and lower-layer wiring process, in a separate upper-layer wiring process.

[0093] Specifically, the lower electrode LEL is formed in the upper layer of the via hole VH for connecting one node CTN002 of the lower electrode LEL and the via hole VH for connecting the other node CTN003 of the lower electrode LEL.

[0094] Furthermore, on the lower electrode, as an MTJ element, Mn is added in order from the lower electrode side. ３After forming the Sn layer, the free layer CoFeB layer, the barrier layer MgO layer, the pin layer CoFeB layer, the Ta layer, and the contact layer, and etching them into the shape of an MTJ element, the upper electrode UEL is formed and connected to the drain side of the transistor MRTR11 via the contact in the upper wiring process and the multilayer wiring layer in the front-end / lower wiring process.

[0095] Not particularly limited, Mn ３ Regarding the formation method of the Sn layer, the following publicly available document discloses the sputtering method: Publicly available document: https: / / www.issp.u-tokyo.ac.jp / maincontents / docs / tayori59-1_Part4.pdf

[0096] Furthermore, MTJ elements consisting of a free layer (CoFeB layer), a barrier layer (MgO layer), and a pinned layer (CoFeB layer) have been conventionally used as MTJ elements in MRAM.

[0097] In order to achieve the configuration shown in Figure 2, not only transistors MRTR01 and MRTR11, but also transistors MRTR02, SRTR01, SRTR02, and MRTR12 are provided on the semiconductor substrate.

[0098] Figure 6 is a conceptual diagram illustrating the configuration of the memory cell array 40 and the circuit for controlling reading and writing in the comparative example semiconductor memory device 1000.0.

[0099] Figure 6 shows only a portion of the memory cells; in reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are omitted from the illustration in Figure 6.

[0100] Referring to Figures 2 and 6, the semiconductor memory device 1000.0 includes a row decoder 1010.1 and a row driver 1020.1 for row selection for each memory cell 40.0.0 to 40.1.1 in the memory cell array. The row decoder 1010.1 determines the row to be selected according to the input address signal Add. w, and the row driver 1020.1 sets the word line corresponding to the selected row to an active potential (e.g., power supply potential Vdd).

[0101] Furthermore, the semiconductor memory device 1000.0 includes a column decoder 1110.1 and a column driver 1120.1 for performing column selection for each memory cell 40.0.0 to 40.1.1 in the memory cell array. (Data writing operation)

[0102] During data writing, the column decoder 1110.1 determines the column to select according to the input address signal Add.c, and the column driver 1120.1 complementaryly drives the potential of the bit line pair corresponding to the selected column according to the write data Din input to the write circuit 1150. Since the memory cell selection transistors MRTR01, MRTR02, SRTR01, and SRTR02 corresponding to the selected row and selected column are in a conductive state, data is written to the first and second memory nodes of the cross-coupled inverter cell SRCEL from the driven bit line pair.

[0103] Figure 2 illustrates the case where the bit line BL is driven to an "L" level (e.g., ground potential) and the bit line / BL is driven to an "H" level (e.g., power supply potential). As a result, the first memory node of the cross-coupled inverter cell SRCEL becomes "H" level, and the second memory node becomes "L" level.

[0104] On the other hand, a write current flows from the bit line / BL through the first memory node to the second node CTN002 of the lower electrode LEL11 of the MTJ element MTJ11, and further, a write current is supplied from the third node CTN003 to the bit line BL. As a result, the MTJ element MTJ11 enters an antiparallel state (RH state) with a high resistance value.

[0105] On the other hand, a write current flows from the bit line BL through the second memory node to the second node of the lower electrode LEL12 of the MTJ element MTJ12, and a write current is supplied from the third node to the bit line / BL. As a result, the MTJ element MTJ12 enters a low-resistance parallel state (RL state).

[0106] While not particularly limited, for example, the data written to the cross-coupled inverter cell SRCEL as described above is assumed to correspond to "0".

[0107] When the data written to the cross-coupled inverter cell SRCEL corresponds to "1", the potentials of the bit line BL and the bit line / BL are reversed, the first memory node becomes "L" level, and the second memory node becomes "H" level. In addition, the writing currents flowing to the lower electrode LEL11 of MTJ element MTJ11 and the lower electrode LEL12 of MTJ element MTJ12 are reversed. As a result, MTJ element MTJ11 becomes a low-resistance state RL, and MTJ element MTJ12 becomes a high-resistance state RH.

[0108] In the active state, the potential levels of the first and second memory nodes are complementary. Meanwhile, the resistance values ​​of MTJ elements MTJ11 and MTJ12 are maintained in a complementary state even when the power is off. (Operation upon power-on)

[0109] Next, we will explain how to restore data to the cross-coupled inverter cell SRCEL after it has been powered off and then powered on again.

[0110] When the power is restored, the power supply potential (Vdd) level gradually rises from the ground potential (GND) level. At this time, the output nodes of the cross-coupled inverter cell SRCEL start up in an unstable state. However, the resistance values ​​recorded in the MTJ element are non-volatile and represent the resistance values ​​for the RH state and the RL state, respectively. For a predetermined period when the power is restored, the POR signal is activated to activate the current path to the ground potential (GND) level through the resistance of the MTJ element. As a result, the node that was the H-level node of the inverter (the first memory node in Figure 2) has a high resistance value in the RH state in the current path to the ground potential (GND) level. On the other hand, the node that was the L-level node of the inverter (the second memory node in Figure 2) has a low resistance value in the RL state in the current path to the ground potential (GND) level. As a result, the node that was the L-level node of the inverter is strongly attracted to the ground potential (GND) level, and the node that was the L-level node of the inverter starts up at the L level. This operation allows the memory cell to reconstruct the recorded information from before the power was cut off. (Data read operation)

[0111] Referring to Figures 5 and 6, when reading data, the row decoder 1010.1 determines the row to select according to the input address signal Add. w, and the row driver 1020.1 sets the word line corresponding to the selected row to an active potential (for example, the power supply potential Vdd).

[0112] The column decoder 1110.1 determines the column to select according to the input address signal Add. c, and the column driver 1120.1 precharges the potential of the bit line pair corresponding to the selected column. The memory cell selection transistors MRTR01, MRTR02, SRTR01, and SRTR02 corresponding to the selected row and selected column are in a conductive state. On the other hand, as shown in Figure 2, the first memory node of the cross-coupled inverter cell SRCEL is at the "H" level, and the second memory node is at the "L" level.

[0113] During data retrieval, the MTJ element does not contribute to the readout process, as long as the state-holding capacity of the cross-coupled inverter cell SRCEL is sufficient, no current path is generated that would change its state.

[0114] Data is read from the bit line pairs to the first and second memory nodes of the cross-coupled inverter cell SRCEL, and after the read data is stored in the multiplexer 1130.1, the amplified data is output as read data Dot by the amplifier 1160.

[0115] Therefore, in the above read operation, the potential of the bit line pair is driven by the first and second inverters of the cross-coupled inverter cell SRCEL. (Configuration as a cache memory)

[0116] Figure 7 is a functional block diagram illustrating the configuration of a computing system 10 that includes a CPU (Central Processing Unit), main memory, and the semiconductor memory device 1000.0 shown in Figure 6 as cache memory.

[0117] Referring to Figure 7, the CPU 100 includes a control unit 110 and an arithmetic unit 150.

[0118] The program counter 114 in register 112 is a register that stores the memory address where the next instruction to be executed is stored, indicating which memory address the next instruction to be executed is stored at, while the base register 116 stores the starting address when the program was loaded into memory.

[0119] The index register 118 in register 112 is a register used for retrieving consecutive data and stores the relative position from the beginning. It is used when repeatedly applying the same instruction to consecutive data such as arrays. The instruction register 120 in register 112 is a register for temporarily storing the retrieved instruction.

[0120] The control unit 110 uses these registers to read instructions and data from memory, or to write data, and to perform other operations.

[0121] The arithmetic unit 150 performs predetermined bitwise operations on the read data according to the command. The accumulator 154 in register 112 is a register for temporarily storing the calculation result, and the general-purpose register 156 is a register with no particular role limited and can be used for various purposes depending on the situation.

[0122] Although the arithmetic unit 152 is shown as a single unit in Figure 7, it may have multiple cores.

[0123] The CPU 100 further includes multiple levels of cache memories 102, 104, and 106. For example, cache memory 102 is a Level 1 (L1) primary cache memory, cache memory 104 is a Level 2 (L2) secondary cache memory, and cache memory 106 is a Level 3 (L3) tertiary cache memory. Although not particularly limited, for example, cache memories 102, 104, and 106 are implemented as SRAM (Static Random Access Memory) on the same die as the arithmetic unit 152. The number of levels of SRAM cache on the same die is not limited to this configuration.

[0124] The CPU 100 also has an external interface 108 for exchanging data with the outside world.

[0125] The CPU 100 is connected to a semiconductor memory device 1000.0 that is stacked three-dimensionally on top of the CPU 100 chip via an external interface 108. The semiconductor memory device 1000.0 operates as a Level 4 (L4) L4 cache memory, although this is not particularly limited. Therefore, the semiconductor memory device 1000.0 is configured to be located in the Last Level Cache (LLC) layer. Note that the semiconductor memory device 1000.0 can also be used as a cache memory at other levels and is not limited to a L4 cache memory.

[0126] The CPU 100 also exchanges data with the main memory 300 via the external interface 108. The memory cells MCi in the memory cell array MCA within the main memory 300 are accessed from the outside using predetermined addresses.

[0127] The control unit 110 includes a cache controller 111. The cache controller 111 intercepts access from the CPU 100 to the memory and controls access to the cache memories 102, 104, 106, the semiconductor memory device 1000.0, and the main memory 300. [Embodiment 1]

[0128] Figure 8 shows an example of the configuration of the memory cell 40 of Embodiment 1 using an MTJ element. Figure 8 also illustrates the write current during data writing control of the memory cell 40 according to Embodiment 1.

[0129] The configuration differences between the memory cell 40 of Embodiment 1 shown in Figure 8 and the comparative example shown in Figure 2 are as follows.

[0130] 1) First, in the memory cell 40 of Embodiment 1, the read bit line pair, RBL and read bit line / RBL, is provided independently of the write bit line pair, WBL and write bit line / WBL.

[0131] The write bit line WBL and the write bit line / WBL correspond to the bit line BL and bit line / BL of the bit line pair in Figure 2. An NMOS transistor SRRTR01, which is a write selection transistor (write transistor), is provided between the write bit line WBL and the second memory node, and an NMOS transistor SRTR02, which is a write transistor, is provided between the write bit line / WBL and the first memory node. The gate potentials of the NMOS transistor SRTR01 and the NMOS transistor SRTR02 are controlled by the write word line WWL.

[0132] 2) Next, in the memory cell 40 of Embodiment 1, a first read-drive NMOS transistor RTr0 is provided, the gate of which is connected to the second storage node of the cross-coupled inverter cell SRCEL, so that it is either conductive or non-conductive. The source of the NMOS transistor RTr0 is connected to the low potential (for example, ground potential) during data storage. Between the drain of the NMOS transistor RTr0 and the read bit line RBL, an NMOS transistor RTr1, which is a read selection transistor (read transistor), is provided.

[0133] Furthermore, in the memory cell 40 of Embodiment 1, a second NMOS transistor / RTr0 for read driving is provided, whose gate is connected to the first storage node of the cross-coupled inverter cell SRCEL, and which is either conductive or non-conductive. The source of the NMOS transistor / RTr0 is connected to the low potential during data storage (for example, ground potential). A lead transistor, NMOS transistor / RTr1, is provided between the drain of the NMOS transistor / RTr0 and the read bit line / RBL.

[0134] The gate potential of the NMOS transistor RTr1 and the gate potential of the NMOS transistor / RTr1 are controlled by the readout word line RWL.

[0135] In other words, the memory cell 40 of Embodiment 1 has the following configuration.

[0136] The memory cell data retention mechanism has a first storage node and a second storage node, and stores the data. Here, the data retention mechanism includes a pair of first magnetic tunnel junction elements MTJ11 and second magnetic tunnel junction elements MTJ12 for non-volatilely maintaining the potential of the first storage node and the potential of the second storage node at a complementary first potential and a second potential, respectively, according to the data to be stored. The first and second magnetic tunnel junction elements MTJ11 and MTJ12 are supplied with a write current according to the data to be stored, and are made to complementary high-resistance and low-resistance states, similar to the memory cell 40 of the comparative example.

[0137] The first read-drive transistor, an NMOS transistor RTr0, is controlled by the potential of the second memory node to be either a conduction state or a non-conduction state, and in the conduction state, it drives the potential of the first read node to a first potential (low potential, e.g., ground potential). The second read-drive transistor, an NMOS transistor RTr0, is controlled by the potential of the second memory node to be either a conduction state or a non-conduction state, and in the conduction state, it drives the potential of the second read node to a first potential.

[0138] Here, the first read node is the connection node between the drain of the NMOS transistor RTr0 and the source of the lead transistor, the NMOS transistor RTr1. The second read node is the connection node between the drain of the NMOS transistor RTr0 and the source of the lead transistor, the NMOS transistor RTr1. Here, the driving element that drives the potential of the first or second read node is assumed to be an NMOS transistor for read driving. However, it is not limited to an NMOS transistor as long as it has the function of driving the potential of the first or second read node, controlled by the potential of the corresponding storage node. The same applies to subsequent embodiments.

[0139] The first and second MTJ elements MTJ11 and MTJ12 are provided such that the side of the first and second storage nodes that is set to a low potential according to the stored data (the second storage node in Figure 8) can be connected to a low potential via the side of the first and second magnetic tunnel junction elements that has low resistance (the second magnetic tunnel junction element MTJ12 in Figure 8). Similar to the memory cell 40 of the comparative example, the upper electrode side node (first node) of the first and second MTJ elements MTJ11 and MTJ12 is connected to ground potential via transistors MRTR11 and MRTR12, whose opening and closing is controlled by a POR signal.

[0140] Figure 9 is a conceptual diagram illustrating the configuration of the memory cell array 40 and the circuit for controlling reading and writing in the semiconductor memory device 1000 of Embodiment 1.

[0141] Here again, Figure 9 shows only a portion of the memory cells; in reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are omitted from the illustration in Figure 9.

[0142] Referring to Figures 8 and 9, the semiconductor memory device 1000 includes a row decoder 1010 and a row driver 1020 for row selection for each memory cell 40.0.0 to 40.1.1 in the memory cell array. The row decoder 1010 determines the row to be selected according to the input address signal Add. w, and the row driver 1020 sets the write word line WWL or read word line RWL corresponding to the selected row to an active potential (for example, the power supply potential Vdd).

[0143] Furthermore, the semiconductor memory device 1000 includes a column decoder 1110 and a column driver 1120 for performing column selection for each memory cell 40.0.0 to 40.1.1 in the memory cell array. (Data writing operation)

[0144] Figure 10 is a timing chart illustrating the data writing and reading operations to the semiconductor memory device 1000 in Embodiment 1.

[0145] Referring to Figures 9 and 10, when writing data, at time t1, the row driver 1020 activates the write word line WWL corresponding to the selected row. The column decoder 1110 determines the column to select according to the input address signal Add.c, and the column driver 1120 complementaryly drives the potentials of the write bit lines WBL, / WBL corresponding to the selected column according to the write data Din input to the write circuit 1150. As a result, the memory cell selection transistors MRTR01, MRTR02, SRTR01, and SRTR02 corresponding to the selected row and selected column are in a conductive state, and data is written to the first and second memory nodes of the cross-coupled inverter cell SRCEL from the driven bit line pair (for example, the bit lines WBL0, / WBL0 corresponding to column 0).

[0146] Figure 8 illustrates the case where the bit line WBL is driven to an "L" level (e.g., ground potential) and the bit line / WBL is driven to an "H" level (e.g., power supply potential). As a result, the first memory node of the cross-coupled inverter cell SRCEL becomes "H" level and the second memory node becomes "L" level. Accordingly, the NMOS transistor RTr0 for the first read drive becomes non-conductive (off), and the NMOS transistor / RTr0 for the second read drive becomes conductive (on).

[0147] On the other hand, a write current flows from the bit line / WBL through the first memory node to the second node CTN002 of the lower electrode LEL11 of the MTJ element MTJ11, and a write current is supplied from the third node CTN003 to the bit line WBL. As a result, the MTJ element MTJ11 enters an antiparallel state (RH state) with a high resistance value.

[0148] On the other hand, a write current flows from the bit line WBL through the second memory node to the second electrode LEL12 of the MTJ element MTJ12, and a write current is supplied from the third node to the bit line / WBL. As a result, the MTJ element MTJ12 enters a low-resistance parallel state (RL state). Here, although not particularly limited, for example, the data written to the cross-coupled inverter cell SRCEL in the manner described above is assumed to correspond to "0".

[0149] When the data written to the cross-coupled inverter cell SRCEL corresponds to "1", the potentials of the bit line BL and the bit line / BL are reversed, the first memory node becomes "L" level, and the second memory node becomes "H" level. In addition, the writing currents flowing to the lower electrode LEL11 of MTJ element MTJ11 and the lower electrode LEL12 of MTJ element MTJ12 are reversed. As a result, MTJ element MTJ11 becomes a low-resistance state RL, and MTJ element MTJ12 becomes a high-resistance state RH.

[0150] At time t2, the write word line WWL becomes inactive, and the write operation ends.

[0151] In the active state, the potential levels of the first and second memory nodes are complementary, being "H" level and "L" level, respectively. Meanwhile, the resistance values ​​of MTJ elements MTJ11 and MTJ12 are maintained in a complementary state even when the power is off. (Operation upon power-on)

[0152] Next, regarding the restoration of data to the cross-coupled inverter cell SRCEL after it has been powered off and then powered on again, the procedure is the same as in the comparative example shown in Figure 2, so we will not repeat the explanation. (Data reading operation)

[0153] Furthermore, referring to Figures 9 and 10, when reading data, the column decoder 1110 determines which column to select according to the input address signal Add.c, and the column driver 1120 precharges the potential of the read bit lines RBL0, / RBL0 corresponding to the selected column.

[0154] At time t3, the row decoder 1010 determines the row to select according to the input address signal Add.w, and the row driver 1020 sets the read word line RWL0 corresponding to the selected row to the activation potential (for example, the power supply potential Vdd).

[0155] Accordingly, the NMOS transistors RTr1, / RTr1 of the memory cells corresponding to the selected row and column are in a conductive state. On the other hand, as shown in Figure 8, the first memory node of the cross-coupled inverter cell SRCEL is at the "H" level, and the second memory node is at the "L" level. As a result, the first NMOS transistor RTr0 for read driving is in a non-conductive state (off state), while the second NMOS transistor RTr0 for read driving is in a conductive state (on state). Accordingly, the potential of the read bit line RBL0 is driven to the lower potential by the second NMOS transistor RTr0 for read driving, and the potential of the read bit line RBL0 is maintained at the precharge potential (for example, the power supply potential).

[0156] Accordingly, at time t4, the potential of the read bit line / RBL0 changes, the read data is stored in the multiplexer 1130, and the output level of the amplified data by the amplifier 1160 automatically changes to "0" and is output as read data Dot. At time t5, data output ends.

[0157] Here too, during data reading, if the state-holding capacity of the cross-coupled inverter cell SRCEL is sufficient, the MTJ element does not generate a current path that would change this state, and therefore does not contribute to the reading process.

[0158] Because MTJ elements are resistive elements, data writing is possible at high speed, but data reading tends to be slower compared to writing.

[0159] In the read operation described above, the potential of the read bit line pair is driven by the first and second NMOS transistors RTr0, / RTr0 for read driving. This allows for increased current driving force during readout, enabling high-speed data readout.

[0160] Furthermore, because the resistance values ​​of the first and second MTJ elements MTJ11 and MTJ12 become non-volatile complementary resistance values, it is possible to configure the cross-coupled inverter cell SRCEL to also retain its stored data non-volatilely. [Embodiment 2]

[0161] Figure 11 shows an example of the configuration of the memory cell 40 of Embodiment 2 using an MTJ element. Figure 11 also illustrates the write current during data writing control of the memory cell 40 according to Embodiment 1.

[0162] The differences in the configuration of the memory cell 40 of Embodiment 2 shown in Figure 11 and the memory cell 40 of Embodiment 1 shown in Figure 8 are as follows.

[0163] 1) First, in the memory cell 40 of Embodiment 2, a read bit line RBL is provided independently of the write bit line WBL and the write bit line / WBL of the write bit line pair. However, the read bit line / RBL is omitted.

[0164] 2) Next, in the memory cell 40 of Embodiment 2, a first read-drive NMOS transistor RTr0 is provided, the gate of which is connected to the second storage node of the cross-coupled inverter cell SRCEL, so that it is either conductive or non-conductive. The source of the NMOS transistor RTr0 is connected to the low potential (for example, ground potential) during data storage. Between the drain of the NMOS transistor RTr0 and the read bit line RBL, an NMOS transistor RTr1, which is a read selection transistor (read transistor), is provided.

[0165] However, in the memory cell 40 of Embodiment 2, the second NMOS transistor / RTr0 for reading drive and the NMOS transistor / RTr1 for reading are omitted.

[0166] In the configuration of the semiconductor memory device of Embodiment 2, the configuration of the circuit that controls writing and the circuit that controls reading are changed according to the configuration of the memory cell 40 as shown in Figure 11. (Data writing operation)

[0167] Figure 12 is a timing chart illustrating the data writing and reading operations to a semiconductor memory device (not shown) in Embodiment 2.

[0168] In the following description, the semiconductor memory device of Embodiment 2 will also be described as having a configuration corresponding to the row decoder 1010, row driver 1020, column decoder 1110, column driver 1120, multiplexer 1130, writing circuit 1150, and amplifier 1160 shown in Figure 9.

[0169] Referring to Figure 12, the operation during data writing is the same as that of the semiconductor memory device 1000 in Embodiment 1, so the explanation will not be repeated.

[0170] However, the second NMOS transistor RTr0 for read operation and the NMOS transistor RTr1 for lead operation are omitted. Therefore, when data writing is complete, only the first NMOS transistor RTr0 for read operation remains in a non-conductive (off) state. (Operation upon power-on)

[0171] Next, the data restoration to the cross-coupled inverter cell SRCEL after it has been powered off and then powered on is the same as the operation of the semiconductor memory device 1000 in Embodiment 1, so the explanation will not be repeated. (Data reading operation)

[0172] Furthermore, referring to Figure 12, when reading data, the column decoder 1110 determines the column to select according to the input address signal Add.c, and the column driver 1120 precharges the potential of the read bit line RBL0 corresponding to the selected column.

[0173] At time t3, the row decoder 1010 determines the row to select according to the input address signal Add.w, and the row driver 1020 sets the read word line RWL0 corresponding to the selected row to the activation potential (for example, the power supply potential Vdd).

[0174] Accordingly, the NMOS transistor RTr1 of the memory cell read transistor corresponding to the selected row and column is in a conductive state. On the other hand, as shown in Figure 11, the first memory node of the cross-coupled inverter cell SRCEL is at the "H" level, and the second memory node is at the "L" level. As a result, the NMOS transistor RTr0 for the first read drive is in a non-conductive state (off state).

[0175] Accordingly, the potential of the read bit line RBL0 is maintained at the precharge potential even at time t4.

[0176] Accordingly, at time t4, the potential of the read bit line RBL0 is maintained, the read data is stored in the multiplexer 1130, and the output level of the data amplified by the amplifier 1160 automatically changes to "0" and is output as read data Dot. At time t5, data output ends.

[0177] Here too, during data reading, if the state-holding capacity of the cross-coupled inverter cell SRCEL is sufficient, the MTJ element does not generate a current path that would change this state, and therefore does not contribute to the reading process.

[0178] On the other hand, when the stored data is "1", the first NMOS transistor RTr0 for reading is in a conductive state (on state). The potential of the read bit line RBL0 is then driven to a lower potential by the first NMOS transistor RTr0 for reading.

[0179] Therefore, the above read operation allows for increased current driving force during reading, enabling high-speed data retrieval.

[0180] Furthermore, because the resistance values ​​of the first and second MTJ elements MTJ11 and MTJ12 become non-volatile complementary resistance values, it is possible to configure the cross-coupled inverter cell SRCEL so that its stored data is also retained non-volatilely.

[0181] In the read operation described above, the potential of the read bit line is driven by the first NMOS transistor RTr0 for read driving. This allows for increased current driving force during readout, enabling high-speed data readout.

[0182] Furthermore, because the resistance values ​​of the first and second MTJ elements MTJ11 and MTJ12 become non-volatile complementary resistance values, it is possible to configure the cross-coupled inverter cell SRCEL to also retain its stored data non-volatilely. [Embodiment 3]

[0183] Figure 13 shows an example of the configuration of the memory cell 40 of Embodiment 3 using an MTJ element. Figure 13 also illustrates the write current during data writing control of the memory cell 40 according to Embodiment 3.

[0184] In the configuration of the semiconductor memory device of Embodiment 3, the configuration of the circuit that controls writing and the circuit that controls reading are changed according to the configuration of the memory cell 40 as shown in Figure 13.

[0185] Referring to Figure 13, the memory cell 40 of Embodiment 3 has a first storage node and a second storage node and includes a data holding mechanism for storing storage data.

[0186] Here, the data retention mechanism includes a pair of second magnetic tunnel junction elements MTJ12 and a first magnetic tunnel junction element MTJ11 for non-volatilely maintaining the potential of the first and second storage nodes at complementary first and second potentials, respectively, according to the stored data. The first and second magnetic tunnel junction elements MTJ11 and MTJ12 are supplied with a write current according to the stored data, and their resistances are complementary to high and low, respectively. Each of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 has a first node and an internal node. In this respect, it is the same as in Embodiment 1 and Embodiment 2.

[0187] Furthermore, referring to Figure 13, the data retention mechanism includes a first PMOS transistor TP2 whose gate potential is controlled by the potential of the second memory node and which is provided between the power supply potential and the first memory node, and a second PMOS transistor TP1 whose gate potential is controlled by the potential of the first memory node and which is provided between the power supply potential and the second memory node.

[0188] The first and second magnetic tunnel junction elements MTJ11 and MTJ12 each have lower electrodes LEL11 and LEL12, respectively, which have a second node and a third node. The lower electrodes LEL11 and LEL12 are provided to connect to the internal nodes of the first and second magnetic tunnel junction elements MTJ11 and MTJ12, respectively, and conduct the write current during data writing operations. The second nodes of the lower electrodes of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 are connected to the second storage node and the first storage node, respectively. The data holding mechanism further includes a second NMOS transistor TN02 whose gate potential is controlled by the potential of the second storage node and whose source is connected to ground potential, and a first NMOS transistor TN01 whose gate potential is controlled by the potential of the first storage node and whose source is connected to ground potential. The second nodes of the lower electrodes of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 are connected to the second and first memory nodes, respectively. The first nodes of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 are connected to the drains of the first and second NMOS transistors TN01 and TN02, respectively.

[0189] The semiconductor memory device of Embodiment 3 also has a configuration corresponding to the row decoder 1010, row driver 1020, column decoder 1110, column driver 1120, multiplexer 1130, writing circuit 1150, and amplifier 1160 shown in Figure 9.

[0190] The row decoder 1010, row driver 1020, column decoder 1110, column driver 1120, multiplexer 1130, and write circuit 1150 operate as a write control circuit.

[0191] The row decoder 1010, row driver 1020, column decoder 1110, column driver 1120, multiplexer 1130, and amplifier 1160 operate as a readout control circuit.

[0192] The semiconductor memory device of the third embodiment further comprises a plurality of write bit line pairs WBL, / WBL provided in the column direction of the memory cell array.

[0193] In the first memory node of the data retention mechanism, a first write bit line / WBL is provided in common to the memory cells in the column direction. In the second memory node of the data retention mechanism, a second write bit line WBL is provided in common to the memory cells in the column direction.

[0194] A pair of first write transistors, WLTR01 and WLTR02, are provided between the first and second storage nodes and the first and second write bit lines, respectively.

[0195] A write control circuit (not shown) supplies write current to the first magnetic tunnel junction element and the second magnetic tunnel junction element via the write bit line during the write operation to the data holding mechanism, such that their relative resistance states become low resistance and high resistance, respectively. The third nodes of the first and second magnetic tunnel junction elements are connectable to the first and second write bit lines via the first light transistors WLTR02 and WLTR01, respectively.

[0196] Therefore, the memory cell of Embodiment 3 has a configuration in which a cross-coupled SRAM cell is combined with a three-terminal MRAM cell.

[0197] For example, when writing data, as shown in Figure 13, if the data to be written is "0", the write control circuit drives the potential of the write bit line / WBL to the "H" level and the potential of the write bit line WBL to the "L" level. Furthermore, when the write control circuit activates the word line WWL, the write data is input from the write bit lines WBL, / WBL, and the potentials of the first and second memory nodes of the CMOS inverter constituting the crosscouple are set to the "H" level and "L" level, as shown in Figure 13.

[0198] At this time, the lower electrodes LEL11 and LEL12 of the first and second MTJ elements MTJ11 and MTJ12 are provided in the data writing path, and current flows through the lower electrodes. As a result, spin is injected into the first and second MTJ elements MTJ11 and MTJ12, and the resistance values ​​of the MTJs of the first and second MTJ elements MTJ11 and MTJ12 are set to the RL state and the RH state, respectively.

[0199] In other words, at this time, the resistance of the first MTJ element MTJ11 connected to the second memory node at the "L" level is set to the RL state, and the resistance of the second MTJ element MTJ12 connected to the first memory node at the "H" level is set to the RH state.

[0200] When the data to be written is "1", the potentials of the write bit lines WBL, / WBL are reversed, and the potentials of the first and second memory nodes, and the resistance values ​​of the MTJs of the first and second MTJ elements MTJ11, MTJ12 are reversed from those described above.

[0201] As described above, by combining a cross-coupled SRAM cell with a three-terminal MRAM cell, non-volatile storage is performed. When the power is turned on again, as the potential of the power supply node rises from the ground potential (GND) level to the power supply potential level (Vdd), the weighting of the resistance changes based on the difference in resistance magnitudes (RH state and RL state) of the first and second MTJ elements MTJ11 and MTJ12, which are connected in series with the first and second cross-coupled NMOS transistors, respectively, thereby restoring the stored value. [Embodiment 4]

[0202] Figure 14 shows an example of the configuration of the memory cell 40 of Embodiment 4 using an MTJ element. Figure 14 also illustrates the write current during data writing control of the memory cell 40 according to Embodiment 4.

[0203] In the configuration of the semiconductor memory device of Embodiment 4, the configuration of the circuit that controls writing and the circuit that controls reading are changed according to the configuration of the memory cell 40 as shown in Figure 14.

[0204] Referring to Figure 14, the memory cell 40 of Embodiment 4 has a first storage node and a second storage node, and includes a data holding mechanism for storing storage data.

[0205] Furthermore, the memory cell structure of Embodiment 3 shown in Figure 13 is adopted as the data retention mechanism.

[0206] In other words, the data retention mechanism includes a pair of second magnetic tunnel junction elements MTJ12 and a first magnetic tunnel junction element MTJ11 for non-volatilely maintaining the potential of the first memory node and the potential of the second memory node at complementary first and second potentials, respectively, according to the stored data. The first and second magnetic tunnel junction elements MTJ11 and MTJ12 are supplied with a write current according to the stored data, and their resistances are changed complementary to high and low, respectively. Each of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 has a first node and an internal node.

[0207] The configuration of the data retention mechanism is the same as that of the memory cell in Embodiment 3, so the explanation will not be repeated.

[0208] The differences between the configuration of the memory cell 40 in Embodiment 4 and the configuration of the memory cell in Embodiment 3 are as follows.

[0209] 1) First, in the memory cell 40 of Embodiment 4, the read bit line pair is provided with a read bit line RBL and a read bit line / RBL independently of the write bit line pair, the write bit line WBL and the write bit line / WBL. In Figure 14, the write bit line WBL0 and the write bit line / WBL0 of the write bit line pair, and the read bit line RBL0 and the read bit line / RBL0 of the read bit line pair are shown as a configuration corresponding to row 0.

[0210] An NMOS transistor SRTR01, which is a write selection transistor (write transistor), is provided between the write bit line WBL0 and the second memory node, and an NMOS transistor SRTR02, which is a write transistor, is provided between the write bit line / WBL and the first memory node. The gate potentials of the NMOS transistor SRTR01 and the NMOS transistor SRTR02 are controlled by the write word line WWL (WWL0 in Figure 14).

[0211] 2) Next, in the memory cell 40 of Embodiment 4, a first read-drive NMOS transistor RTr0 is provided, the gate of which is connected to the second storage node, so that it is either conductive or non-conductive. The source of the NMOS transistor RTr0 is connected to the low potential during data storage (for example, the ground potential). Between the drain of the NMOS transistor RTr0 and the read bit line RBL (RBL0 in Figure 14), an NMOS transistor RTr1, which is a read selection transistor (read transistor), is provided.

[0212] Furthermore, in the memory cell 40 of Embodiment 4, a second NMOS transistor / RTr0 for read driving is provided, whose gate is connected to the first storage node, resulting in a conductive or non-conductive state. The source of the NMOS transistor / RTr0 is connected to a low potential (for example, ground potential) during data storage. A lead transistor, NMOS transistor / RTr1, is provided between the drain of the NMOS transistor / RTr0 and the read bit line / RBL. Here again, the first read node is the connection node between the drain of the NMOS transistor RTr0 and the source of the lead transistor, NMOS transistor RTr1. The second read node is the connection node between the drain of the NMOS transistor / RTr0 and the source of the lead transistor, NMOS transistor / RTr1.

[0213] The timing charts for the data writing and data reading operations of the memory cell 40 in Embodiment 4 are the same as those in Embodiment 1.

[0214] The operation when the power is turned back on is as follows:

[0215] When the power is restored, the power supply potential (Vdd) level gradually rises from the ground potential (GND) level. At this time, the potentials of the first and second memory nodes rise in an unstable state. However, since the resistance values ​​recorded in the MTJ elements are non-volatile, they are the resistance values ​​for the RH state and the RL state, respectively. Similar to Embodiment 3, the weighting of the resistance changes depending on the difference in resistance magnitude (RH state and RL state) of the first and second MTJ elements MTJ11 and MTJ12, which are provided in series with the first and second memory nodes and the second and first PMOS transistors that are cross-coupled, and the stored values ​​can be restored. Through this operation, the recorded information of this memory cell before the power was cut off can be reproduced.

[0216] Furthermore, in the memory cell of Embodiment 4, the potential of the read bit line pair is driven by the first and second NMOS transistors RTr0, / RTr0 for read driving. Therefore, the current driving force during readout can be increased, enabling high-speed data readout. [Embodiment 5]

[0217] Figure 15 shows an example of the configuration of the memory cell 40 of Embodiment 5 using an MTJ element. Figure 15 also illustrates the write current during data writing control of the memory cell 40 according to Embodiment 5.

[0218] The relationship between the memory cell configuration of Embodiment 5 and the memory cell configuration of Embodiment 4 is the same as the relationship between the memory cell configuration of Embodiment 2 and the memory cell configuration of Embodiment 1.

[0219] In other words, it is as follows:

[0220] 1) First, in the memory cell 40 of Embodiment 5, a read bit line RBL is provided independently of the write bit line WBL and the write bit line / WBL of the write bit line pair. However, the read bit line / RBL is omitted.

[0221] 2) Next, in the memory cell 40 of Embodiment 5, a first read-drive NMOS transistor RTr0 is provided, the gate of which is connected to the second storage node of the data holding mechanism, so that it is either conductive or non-conductive. The source of the NMOS transistor RTr0 is connected to the low potential (for example, ground potential) during data storage. An NMOS transistor RTr1, which is a read selection transistor (read transistor), is provided between the drain of the NMOS transistor RTr0 and the read bit line RBL.

[0222] However, in the memory cell 40 of Embodiment 5, the second NMOS transistor / RTr0 for read driving and the NMOS transistor / RTr1 for read transistors are omitted. That is,

[0223] Each of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 has a first node and an internal node.

[0224] Each data holding mechanism includes a first PMOS transistor TP2 whose gate potential is controlled by the potential of the second memory node and is provided between the power supply potential and the first memory node; a second PMOS transistor TP1 whose gate potential is controlled by the potential of the first memory node and is provided between the power supply potential and the second memory node; a second NMOS transistor TN02 whose gate potential is controlled by the potential of the second memory node and whose source is connected to ground potential; and a first NMOS transistor TN01 whose gate potential is controlled by the potential of the first memory node and whose source is connected to ground potential.

[0225] Each of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 has lower electrodes LEL11 and LEL12, which have second and third nodes for conducting write current and are provided to connect to the internal node. The second nodes of the lower electrodes LEL11 and LEL12 of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 are connected to the second memory node and the first memory node, respectively.

[0226] The first nodes of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 are connected to the drains of the first and second NMOS transistors, respectively, and the third nodes of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 are provided to be connectable to the first and second write bit lines WBL0 and / WBL0 via the first write transistors SRTR01 and SRTR02, respectively.

[0227] In the configuration of the semiconductor memory device of Embodiment 5, the configuration of the circuit that controls writing and the circuit that controls reading are changed according to the configuration of the memory cell 40 as shown in Figure 15.

[0228] The timing charts for the data writing and data reading operations of the memory cell 40 in Embodiment 5, as well as the operation when the power is turned on, are the same as in Embodiment 4, so the explanation will not be repeated.

[0229] The configuration of the memory cell 40 in Embodiment 5 also achieves the same effects as in Embodiment 4. [Embodiment 6]

[0230] Figure 16 shows an example of the configuration of the memory cell 40 of Embodiment 6 using an MTJ element. Figure 16 also illustrates the write current during data writing control of the memory cell 40 according to Embodiment 6.

[0231] The memory cell 40 of Embodiment 6 has a first storage node and a second storage node, and includes a data holding mechanism for storing storage data.

[0232] The data retention mechanism includes a pair of second magnetic tunnel junction elements and first magnetic tunnel junction elements MTJ12 and MTJ11 for non-volatilely maintaining the potentials of the first and second storage nodes at complementary first and second potentials, respectively, according to the stored data. Furthermore, the data retention mechanism further includes a third magnetic tunnel junction element and a fourth magnetic tunnel junction element MTJ21 and MTJ22, which are provided corresponding to the first magnetic tunnel junction element and the second magnetic tunnel junction elements MTJ11 and MTJ12, respectively.

[0233] The memory cell 40 of Embodiment 6 differs from the memory cell configuration of Embodiment 3 in Figure 13 in that it includes the third magnetic tunnel junction element and the fourth magnetic tunnel junction elements MTJ21 and MTJ22.

[0234] Then, the first and third magnetic tunnel junction elements MTJ11 and MTJ21 are supplied with a write current according to the stored data, and their resistances change to high resistance and low resistance, respectively. The second and fourth magnetic tunnel junction elements MTJ12 and MTJ22 are supplied with a write current according to the stored data, and their resistances change to low resistance and high resistance, respectively, which are complementary to the resistances of the first and third magnetic tunnel junction elements MTJ11 and MTJ21.

[0235] Each of the first to fourth magnetic tunnel junction elements has a first node and an internal node.

[0236] The data retention mechanism includes a first PMOS transistor TP2 whose gate potential is controlled by the potential of the second memory node, provided between the power supply potential and the first memory node, with its drain connected to the power supply potential; a second PMOS transistor TP1 whose gate potential is controlled by the potential of the first memory node, provided between the power supply potential and the second memory node, with its drain connected to the power supply potential; a second NMOS transistor TN02 whose gate potential is controlled by the potential of the second memory node, with its source connected to ground potential; and a first NMOS transistor TN01 whose gate potential is controlled by the potential of the first memory node, with its source connected to ground potential.

[0237] Each of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 has a lower electrode provided to connect to an internal node, and the lower electrode has a second node CTN102 and a third node CTN103 for conducting the write current. The third and fourth magnetic tunnel junction elements MTJ21 and MTJ22 have internal nodes connected to their lower electrodes such that when the write current flows between the second node and the third node, the write current flows in the opposite direction to that of the first and second magnetic tunnel junction elements MTJ11 and MTJ12.

[0238] In this respect, the memory cell 40 of Embodiment 6 differs from the memory cell configuration of Embodiment 4 in Figure 14.

[0239] The second nodes of the lower electrodes of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 are connected to the first and second memory nodes, respectively, and the first nodes of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 are connected to the drains of the first and second NMOS transistors TN01 and TN02, respectively.

[0240] The first nodes of the third and fourth magnetic tunnel junction elements are connected to the sources of the second and first PMOS transistors TP2 and TP1, respectively.

[0241] In the configuration of the semiconductor memory device of Embodiment 6, the configuration of the circuit that controls writing and the circuit that controls reading are changed according to the configuration of the memory cell 40 as shown in Figure 16.

[0242] The semiconductor memory device of Embodiment 6 further comprises a plurality of write bit line pairs WBL, / WBL provided in the column direction of the memory cell array, wherein each write bit line pair includes a first write bit line / WBL provided in common to the first storage node of the corresponding data holding mechanism and a second write bit line WBL provided in common to the second storage node of the corresponding data holding mechanism.

[0243] The semiconductor memory device of Embodiment 6 includes a pair of first write transistors WLTR01 and WLTR02, respectively, provided between the first and second storage nodes and the first and second write bit lines WBL and / WBL, and a write control circuit (not shown) that supplies write current to the first magnetic tunnel junction element and the second magnetic tunnel junction element via the write bit lines so that their relative resistance states become low resistance and high resistance, respectively, during the write operation to the data holding mechanism. The third nodes of the first and second magnetic tunnel junction elements MTJ11 and MTJ12 are provided so as to be connectable to the first and second write bit lines WBL and / WBL via the first write transistors WLTR01 and WLTR02, respectively.

[0244] The timing charts for the data writing and data reading operations of the memory cell 40 in Embodiment 6, as well as the operation when the power is turned on, are the same as in Embodiment 4, so the explanation will not be repeated.

[0245] The configuration of the memory cell 40 in Embodiment 6 also produces the same effects as in Embodiment 4.

[0246] However, pillars for two magnetic tunnel elements (MTJs) are formed on the same lower electrode, with one upper electrode connected to the power supply (Vdd) side and the other upper electrode connected to the GND side.

[0247] Therefore, for example, in the configuration shown in Figure 16, the write bit line / WBL side is driven to the "H" level, and the write bit line WBL side is driven to the "L" level. The lower electrodes LEL11 and LEL12 of the first and second MTJ elements MTJ11 and MTJ12 are provided in the data writing path, and current flows through the lower electrodes.

[0248] As a result, spin is injected into the first and second MTJ elements MTJ11 and MTJ12, and the resistance values ​​of the MTJs of the first and second MTJ elements MTJ11 and MTJ12 are set to the RL state and the RH state, respectively. That is, at this time, the resistance of the first MTJ element MTJ11 connected to the second memory node at the "L" level is set to the RL state, and the resistance of the second MTJ element MTJ12 connected to the first memory node at the "H" level is set to the RH state.

[0249] Meanwhile, spin is injected into the third and fourth MTJ elements MTJ21 and MTJ22, and the resistance values ​​of the MTJs of the third and fourth MTJ elements MTJ21 and MTJ22 are set to the RH state and the RL state, respectively. That is, at this time, the resistance of the third MTJ element MTJ21 connected to the second memory node at the "L" level is set to the RH state, and the resistance of the fourth MTJ element MTJ22 connected to the first memory node at the "H" level is set to the RL state.

[0250] When the data to be written is "1", the potentials of the write bit lines WBL, / WBL are reversed, and the potentials of the first and second memory nodes, and the resistance values ​​of the MTJs of the first and second MTJ elements MTJ11, MTJ12 are reversed from those described above.

[0251] In the following description, the third and fourth magnetic tunnel junction elements MTJ21 and MTJ22 are configured such that when a writing current flows between the second node and the third node, the writing current flows in the opposite direction to that of the first and second magnetic tunnel junction elements MTJ11 and MTJ12, with the internal nodes connected to the lower electrodes.

[0252] Figure 17 is a first diagram showing a cross-sectional structure of the memory cell 40 of Embodiment 6, including the transistor WLTR01 and the third node CTN103 of the lower electrode.

[0253] As shown in Figure 17, the transistor WLTR01 is formed on the silicon substrate by a front-end process.

[0254] A multilayer wiring consisting of n layers is formed on the silicon substrate.

[0255] The source side of transistor WLTR01 is connected to the third node CTN103 of the lower electrode LEL via via holes VH, multilayer wiring, and contact CL, while the drain side of transistor WLTR01 is connected to the bit line WBL. Here, although not particularly limited, the bit line WBL is shown as being formed by, for example, the first layer wiring ML1. However, the bit line WBL may also be formed by upper layer wiring. The potential of the bit line WBL is then selectively driven according to the data to be written.

[0256] The configuration of the first magnetic tunnel junction element MTJ11 is the same as in Figure 4, so the explanation will not be repeated. A similar structure is also formed on the side of the second magnetic tunnel junction element MTJ12.

[0257] Figure 18 shows an example of the planar and cross-sectional structures of the lower electrode of the first magnetic tunnel junction element MTJ11 of the memory cell 40 of Embodiment 6.

[0258] Referring to Figure 18(a), in the memory cell 40 of Embodiment 6, the lower electrode of the magnetic tunnel junction element MTJ11 has a C-shaped planar structure consisting of a first portion and a second portion extending laterally in the figure, and a third portion extending vertically in the figure. The third portion is an integrated electrode connecting the first portion and the second portion.

[0259] Similar to Figure 3, Figure 18(a) is a conceptual diagram showing the internal node side of the MTJ element when the MTJ element is viewed from the side of the lower electrode LEL opposite to the MTJ element, with the lower electrode LEL itself being seen through (assuming the lower electrode LEL is transparent).

[0260] Referring to Figure 18(a), the first portion of the lower electrode LEL is connected on one side to an internal node of the third magnetic tunnel junction element MTJ21. The second portion of the lower electrode LEL is connected on one side to an internal node of the first magnetic tunnel junction element MTJ11.

[0261] On the other side of the second portion of the lower electrode LEL, opposite to the aforementioned one side, a contact hole is provided for connecting to the source node (node ​​CTN103) of the light transistor WLTR01.

[0262] On the other hand, a contact hole is provided on the other surface of the first portion of the lower electrode LEL that is opposite to the aforementioned one surface, for connecting to a second memory node (node ​​CTN102).

[0263] Figure 18(b) shows the AA' section of Figure 18(a), and Figure 18(c) shows the BB' section of Figure 18(a).

[0264] As shown in Figure 18(b), the first node of the third magnetic tunnel junction element MTJ21 is connected to the PMOS transistor TP1 via the upper electrode UEL.

[0265] As shown in Figure 18(c), the first node of the first magnetic tunnel junction element MTJ11 is connected to the NMOS transistor TN01 via the upper electrode UEL.

[0266] In this configuration, when a write current flows between the second and third nodes of the lower electrode LEL of the third magnetic tunnel junction element MTJ21, the write current flows in the opposite direction to that of the first magnetic tunnel junction element MTJ11.

[0267] The lower electrodes of the fourth magnetic tunnel junction element MTJ22 and the second magnetic tunnel junction element MTJ12 have a similar configuration.

[0268] The semiconductor memory device of Embodiment 6 also has a configuration corresponding to the row decoder 1010, row driver 1020, column decoder 1110, column driver 1120, multiplexer 1130, writing circuit 1150, and amplifier 1160 shown in Figure 9.

[0269] The row decoder 1010, row driver 1020, column decoder 1110, column driver 1120, multiplexer 1130, and write circuit 1150 operate as a write control circuit.

[0270] The row decoder 1010, row driver 1020, column decoder 1110, column driver 1120, multiplexer 1130, and amplifier 1160 operate as a readout control circuit.

[0271] Therefore, it has the same effect as the memory cell configuration of Embodiment 3 shown in Figure 13. However, by using the configuration shown in Figure 16, non-volatile storage is performed, and when the power is turned on again, as the potential of the power supply node rises from the ground potential (GND) level to the power supply potential level (Vdd), the weighting of the resistance changes not only based on the difference in resistance magnitudes (RH state and RL state) of the first and second MTJ elements MTJ11 and MTJ12, which are provided in series with the first and second NMOS transistors cross-coupled with the first and second storage nodes, but also based on the difference in resistance magnitudes (RL state and RH state) of the third and fourth MTJ elements MTJ21 and MTJ22, respectively, thereby allowing the stored value to be recovered more effectively. [Embodiment 7]

[0272] Figure 19 shows an example of the configuration of the memory cell 40 of Embodiment 7 using an MTJ element. Figure 19 also illustrates the write current during data writing control of the memory cell 40 according to Embodiment 7.

[0273] In the configuration of the semiconductor memory device of Embodiment 7, the configuration of the circuit that controls writing and the circuit that controls reading are changed according to the configuration of the memory cell 40 as shown in Figure 19.

[0274] Referring to Figure 19, the memory cell 40 of Embodiment 7 has a first storage node and a second storage node, and includes a data holding mechanism for storing storage data.

[0275] Furthermore, the memory cell structure of Embodiment 6 shown in Figure 16 is adopted as the data retention mechanism.

[0276] The configuration of the data retention mechanism is the same as that of the memory cell in Embodiment 6 shown in Figure 16, so the explanation will not be repeated.

[0277] The differences between the configuration of the memory cell 40 in Embodiment 7 and the configuration of the memory cell in Embodiment 6 are as follows.

[0278] 1) First, in the memory cell 40 of Embodiment 7, the read bit line pair, RBL and read bit line / RBL, is provided independently of the write bit line pair, WBL and write bit line / WBL. In Figure 14, the write bit line pair, WBL0 and write bit line / WBL0, and the read bit line pair, RBL0 and read bit line / RBL0 are shown as a configuration corresponding to column 0.

[0279] A write selection transistor (write transistor) NMOS transistor SRTR01 is provided between the write bit line WBL0 and the second memory node, and a write transistor NMOS transistor SRTR02 is provided between the write bit line / WBL and the first memory node. The gate potentials of NMOS transistor SRTR01 and NMOS transistor SRTR02 are controlled by the write word line WWL (WWL0 in Figure 19).

[0280] 2) Next, in the memory cell 40 of Embodiment 7, a first read-drive NMOS transistor RTr0 is provided, the gate of which is connected to the first storage node, so that it is either conductive or non-conductive. The source of the NMOS transistor RTr0 is connected to the low potential during data storage (for example, the ground potential). Between the drain of the NMOS transistor RTr0 and the read bit line RBL (RBL0 in Figure 19), an NMOS transistor RTr1, which is a read selection transistor (read transistor), is provided.

[0281] Furthermore, in the memory cell 40 of Embodiment 7, a second read-drive NMOS transistor / RTr0 is provided, whose gate is connected to the second storage node, resulting in a conduction or non-conduction state. The source of the NMOS transistor / RTr0 is connected to a low potential (for example, ground potential) during data storage. A read transistor, an NMOS transistor / RTr1, is provided between the drain of the NMOS transistor / RTr0 and the read bit line / RBL. In Figure 19, the gate potential of the first read-drive NMOS transistor RTr0 is controlled by the potential of the first storage node, and the gate potential of the second read-drive NMOS transistor RTr0 is controlled by the potential of the second storage node. However, the gate potential of the first NMOS transistor RTr0 for read operation may be controlled by the potential of the second memory node, and the gate potential of the second NMOS transistor RTr0 for read operation may be controlled by the potential of the first memory node.

[0282] The timing charts for the data writing and data reading operations of the memory cell 40 in Embodiment 7 are the same as those in Embodiment 1.

[0283] The operation when the power is turned back on is the same as in Embodiment 6.

[0284] In the memory cell of Embodiment 7, the potential of the read bit line pair is driven by the first and second NMOS transistors RTr0, / RTr0 for read driving. This allows for increased current driving force during readout, enabling high-speed data readout.

[0285] Furthermore, just as the configuration of the memory cell array in Embodiment 4 shown in Figure 14 corresponds to the memory cell structure of Embodiment 3 shown in Figure 13, and the configuration of the memory cell array in Embodiment 5 shown in Figure 15 can also be applied to the memory cell of Embodiment 7.

[0286] In other words, in the memory cell configuration of Embodiment 7 shown in Figure 19, it is also possible to omit the read bit line / RBL, and to omit the second read drive NMOS transistor / RTr0 and the read transistor NMOS transistor / RTr1. [Embodiment 8]

[0287] Figure 20 shows an example of the configuration of the memory cell 40 of Embodiment 8 using an MTJ element. Figure 20 also illustrates the write current during data writing control of the memory cell 40 according to Embodiment 8.

[0288] In the configuration of the semiconductor memory device of Embodiment 8, the configuration of the circuit that controls writing and the circuit that controls reading are changed according to the configuration of the memory cell 40 as shown in Figure 20.

[0289] Referring to Figure 20, the memory cell 40 of Embodiment 8 has a first storage node and a second storage node, and includes a data holding mechanism for storing storage data.

[0290] Furthermore, as a data retention mechanism, a structure is adopted in which the PMOS transistors TP1 and TP2 are omitted from the memory cell structure of Embodiment 6 shown in Figure 16. Consequently, the first nodes of the third magnetic tunnel junction element and the fourth magnetic tunnel junction elements MTJ21 and MTJ22 are directly connected to the power supply potential Vdd.

[0291] The other configurations are the same as those of Embodiment 7 shown in Figure 19, so we will not repeat the explanation. In Figure 20, the gate potential of the first read-drive NMOS transistor RTr0 is controlled by the potential of the first memory node, and the gate potential of the second read-drive NMOS transistor RTr0 is controlled by the potential of the second memory node. However, the gate potential of the first read-drive NMOS transistor RTr0 may be controlled by the potential of the second memory node, and the gate potential of the second read-drive NMOS transistor RTr0 may be controlled by the potential of the first memory node.

[0292] The cross-coupled structure on the PMOS transistor side is limited to MTJ elements only, and the resistance from the power supply is determined by the resistance value of the programmed resistor element. The thickness of the tunnel insulating film is adjusted to achieve the required resistance value.

[0293] To keep the amount of current flowing through the memory cell low, the amount of leakage current flowing inside the memory cell can be reduced by increasing the thickness of the tunnel insulating film. [Embodiment 9]

[0294] Figure 21 shows an example of the configuration of the memory cell 40 of Embodiment 9 using an MTJ element. Figure 21 also illustrates the write current during data writing control of the memory cell 40 according to Embodiment 9.

[0295] In the configuration of the semiconductor memory device of Embodiment 9, the configuration of the circuit that controls writing and the circuit that controls reading are changed according to the configuration of the memory cell 40 as shown in Figure 20.

[0296] The memory cell configuration shown in Figure 21 is the same as the memory cell configuration of Embodiment 8 shown in Figure 20, but with the read bit line / RBL omitted, and the second read drive NMOS transistor / RTr0 and the read transistor NMOS transistor / RTr1 omitted.

[0297] The configuration shown in Figure 21 can achieve the same effects as Embodiment 8 shown in Figure 20. (Examples of systems including semiconductor memory devices described in each embodiment)

[0298] Furthermore, the semiconductor memory devices formed according to the above embodiments can be used as memory devices for circuits that perform data processing, as explained in Figure 7.

[0299] In other words, a CPU (Central Processing Unit) has multiple levels of cache memory. For example, it is common to have a hierarchical cache memory structure, such as a Level 1 (L1) primary cache memory, a Level 2 (L2) secondary cache memory, a Level 3 (L3) tertiary cache memory, and so on. Conventionally, in this case, the cache memory was implemented using SRAM (Static Random Access Memory). However, SRAM has weaknesses such as low memory density (memory cells are composed of 6 transistors) and relatively high power consumption in standby mode (considerable leakage current). By replacing this with the semiconductor memory devices of each embodiment, it is possible to reduce the silicon area per unit of memory capacity and significantly reduce power consumption in standby mode.

[0300] Therefore, for example, the semiconductor memory devices of the MRAMs in each of the embodiments described above can be used as last-level caches such as L3 caches and L4 caches.

[0301] Furthermore, with the spread of new technologies such as AI, IoT, and 5G, there is a demand for high-speed and highly reliable memory solutions. Therefore, the applications of the semiconductor memory devices of each embodiment are not limited to those described above, but are envisioned as storage systems in fields where high-speed and highly reliable memory is required, such as data storage in industrial automation systems, data storage in medical devices, and applications in data centers.

[0302] According to the semiconductor memory device configurations of each embodiment described above, stable data recording and high-speed data writing and reading become possible in the SOT-MRAM.

[0303] Finally, while various embodiments relating to this disclosure have been described, these are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents.

[0304] Therefore, the embodiments disclosed herein are illustrative of configurations for specifically carrying out the present invention and do not limit the technical scope of the present invention. The technical scope of the present invention is indicated by the claims rather than by the description of the embodiments, and modifications within the literal scope and equivalent meaning of the claims are intended.

[0305] 10 Arithmetic system, 40 Memory cells, MTJ11, MTJ12, MTJ21, MTJ22 Magnetic tunnel junction elements, T1 First node of MTJ element, T2 Second node of MTJ element, T3 Third node of MTJ element, WBL0, / WBL0, WBL1, / WBL1 Write bit lines, RBL0, / RBL0, RBL1, / RBL1 Read bit lines, RWL0, RWL1 Read word lines, WWL0, WWL1 Write word lines, 1000 Semiconductor memory device, 1010 Row decoder, 1020 Row driver, 1110 Column decoder, 1120 Column driver, 1130 Multiplexer, 1150 Writing circuit, 1160 Read amplifier.

Claims

1. A semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell having a first storage node and a second storage node, and including a data holding mechanism for storing storage data, the data holding mechanism including a pair of first and second magnetic tunnel junction elements for non-volatilely maintaining the potentials of the first storage node and the second storage node complementaryly to a first potential and a second potential, respectively, according to the storage data, the first and second magnetic tunnel junction elements are supplied with a write current according to the storage data, and are controlled by the potential of either the first or second storage node to be either a conducting state or a non-conducting state, and further includes a first read drive element for driving the potential of the first read node to the first potential in the conducting state, The semiconductor memory device further comprises: the first and second magnetic tunnel junction elements, wherein the side of the first and second storage nodes set to the first potential according to the storage data is connected to the potential source of the first potential via the lower-resistance side of the first and second magnetic tunnel junction elements; a plurality of first read bit lines provided in the column direction of the memory cell array so as to be shared by the memory cells and connected to the first read node of each of the data holding mechanisms; a plurality of first read switching elements provided between the first read bit lines and the plurality of first read nodes; and a read control circuit that, in a read operation, selectively controls the first read switching element that reads data and reads the potential of the first read node of the selected memory cell as read data via the first read bit lines.

2. The semiconductor memory device according to claim 1, further comprising a plurality of write bit line pairs provided in the column direction of the memory cell array, wherein each write bit line pair includes a first write bit line provided in common to the first storage node of the corresponding data holding mechanism and a second write bit line provided in common to the second storage node of the corresponding data holding mechanism, a pair of first write switching elements provided between the first and second storage nodes and the first and second write bit lines, respectively, and a write control circuit that, in a write operation to the data holding mechanism, provides the write current to the first magnetic tunnel junction element and the second magnetic tunnel junction element via the write bit line to complementaryly set the potential of the first storage node and the potential of the second storage node to the first potential and the second potential, respectively, according to the stored data, and sets their respective resistance states to the low resistance and the high resistance.

3. Each of the first and second magnetic tunnel junction elements has a first node and an internal node, and each data holding mechanism includes a cross-coupled inverter cell having a first inverter and a second inverter whose input nodes and output nodes are cross-connected to each other, the first storage node and the second storage node each correspond to the cross-connected nodes, each of the first and second magnetic tunnel junction elements includes a first electrode having a second node and a third node for conducting the write current, which are provided to connect to the internal node, the second node of the first electrode of the first and second magnetic tunnel junction elements is connected to the first storage node which is the output node of the first inverter and the second storage node which is the output node of the second inverter, respectively, and the first node of the first and second magnetic tunnel junction elements is connected to the ground potential which is the first potential for a predetermined period after power is turned on. The semiconductor memory device according to claim 2, wherein the third node of each of the magnetic tunnel junction elements in the plurality of memory cells is connectable to the plurality of write bit line pairs via the pair of first write switching elements.

4. Each data holding mechanism is controlled by the potential of the other of the first and second storage nodes to be either conductive or non-conductive, and further includes a second read drive element for driving the potential of a second read node to the first potential in the conductive state; further includes a plurality of second read bit lines provided in the column direction of the memory cell array so as to be shared by the memory cells and so as to be connectable to the second read node of each data holding mechanism; and a plurality of second read switching elements provided between the second read bit lines and the plurality of second read nodes, respectively; and the read control circuit selectively controls the first and second read switching elements that read data in the read operation, and reads the potentials of the first and second read nodes of the selected memory cell via the first and second read bit lines, the semiconductor memory device according to claim 1.

5. Each of the first and second magnetic tunnel junction elements has a first node and an internal node, and each data holding mechanism includes: a first PMOS transistor whose gate potential is controlled by the potential of the second memory node and is provided between the power supply potential and the first memory node; a second PMOS transistor whose gate potential is controlled by the potential of the first memory node and is provided between the power supply potential and the second memory node; a first NMOS transistor whose gate potential is controlled by the potential of the second memory node and whose source is connected to ground potential; and a second NMOS transistor whose gate potential is controlled by the potential of the first memory node and whose source is connected to ground potential, and each of the first and second magnetic tunnel junction elements has a first electrode having a second node and a third node for conducting the write current, provided to be connected to the internal node, and the second node of the first electrode of the first and second magnetic tunnel junction elements is connected to the first memory node and the second memory node, respectively. The semiconductor memory device according to claim 2, wherein the first nodes of the first and second magnetic tunnel junction elements are each connected to the drains of the first and second NMOS transistors, and the third nodes of the first and second magnetic tunnel junction elements are each provided to be connectable to the first and second write bit lines via the first write switching element.

6. Each data holding mechanism further includes a second read drive element controlled by the potential of the other of the first and second storage nodes to drive the potential of a second read node to the first potential in a conductive state; a plurality of second read bit lines provided in the column direction of the memory cell array so as to be shared by the memory cells and so as to be connectable to the second read node of each data holding mechanism; and a plurality of second read switching elements provided between the second read bit lines and the plurality of second read nodes, respectively; the read control circuit selectively controls the first and second read switching elements that read data in the read operation, and reads the potentials of the first and second read nodes of the selected memory cell via the first and second read bit lines, the semiconductor memory device according to claim 5.

7. Each data holding mechanism further includes a third magnetic tunnel junction element and a fourth magnetic tunnel junction element provided corresponding to the first magnetic tunnel junction element and the second magnetic tunnel junction element, respectively, wherein the first and third magnetic tunnel junction elements are supplied with a write current according to the stored data, causing them to change between high resistance and low resistance, respectively, and the second and fourth magnetic tunnel junction elements are supplied with a write current according to the stored data, causing them to change between low resistance and high resistance, respectively, and each of the first to fourth magnetic tunnel junction elements has a first node and an internal node, and each data holding mechanism includes a first PMOS transistor whose gate potential is controlled by the potential of the second storage node, provided between the power supply potential and the first storage node, and whose drain is connected to the power supply potential, and a second PMOS transistor whose gate potential is controlled by the potential of the first storage node, provided between the power supply potential and the second storage node, and whose drain is connected to the power supply potential, The first NMOS transistor has a gate potential controlled by the potential of the second memory node and a source connected to ground potential, and the second NMOS transistor has a gate potential controlled by the potential of the first memory node and a source connected to ground potential, each of the first and second magnetic tunnel junction elements has a first electrode provided to connect to an internal node, the first electrode has a second node and a third node for conducting the write current, each of the third and fourth magnetic tunnel junction elements has the internal node connected to the first electrode such that when the write current flows between the second node and the third node, the write current flows in the opposite direction to that of the first and second magnetic tunnel junction elements, the second node of the first electrode of the first and second magnetic tunnel junction elements is connected to the first memory node and the second memory node, respectively. The first nodes of the first and second magnetic tunnel junction elements are connected to the drains of the first and second NMOS transistors, respectively.The semiconductor memory device according to claim 2, wherein the first nodes of the third and fourth magnetic tunnel junction elements are each connected to the sources of the first and second PMOS transistors, and the third nodes of the first and second magnetic tunnel junction elements are each connectable to the first and second write bit lines via the first write switching element.

8. Each data holding mechanism further includes a third magnetic tunnel junction element and a fourth magnetic tunnel junction element provided corresponding to the first magnetic tunnel junction element and the second magnetic tunnel junction element, respectively, wherein the first and third magnetic tunnel junction elements are supplied with a write current according to the stored data, causing them to change between high resistance and low resistance, respectively, the second and fourth magnetic tunnel junction elements are supplied with a write current according to the stored data, causing them to change between low resistance and high resistance, respectively, each of the first to fourth magnetic tunnel junction elements has a first node and an internal node, and each data holding mechanism includes a first NMOS transistor whose gate potential is controlled by the potential of the second storage node and whose source is connected to ground potential, and a second NMOS transistor whose gate potential is controlled by the potential of the first storage node and whose source is connected to ground potential. Each of the first and second magnetic tunnel junction elements has a first electrode provided to connect to the internal node, the first electrode has a second node and a third node for conducting the write current, each of the third and fourth magnetic tunnel junction elements is provided such that the internal node is connected to the first electrode such that when the write current flows between the second node and the third node, the write current flows in the opposite direction to that of the first and second magnetic tunnel junction elements, the second node of the first electrode of the first and second magnetic tunnel junction elements is connected to the first memory node and the second memory node, respectively, the first node of the first and second magnetic tunnel junction elements is connected to the drains of the first and second NMOS transistors, respectively, and the third node of the first and second magnetic tunnel junction elements is connectable to the first and second write bit lines via the first write switching element, respectively. The semiconductor memory device according to claim 2, wherein the first nodes of the third and fourth magnetic tunnel junction elements are each connected to the power supply potential.

9. Each data holding mechanism further includes a second read drive element controlled by the potential of the other of the first and second storage nodes to drive the potential of a second read node to the first potential in a conductive state; a plurality of second read bit lines provided in the column direction of the memory cell array so as to be shared by the memory cells and so as to be connectable to the second read node of each data holding mechanism; and a plurality of second read switching elements provided between the second read bit lines and the plurality of second read nodes, respectively, wherein the read control circuit selectively controls the first and second read switching elements that read data in the read operation and reads the potentials of the first and second read nodes of the selected memory cell via the first and second read bit lines, the semiconductor memory device according to claim 8.

10. A semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell having a first storage node and a second storage node, and including a data holding mechanism for storing storage data, the data holding mechanism including a pair of first and second magnetic tunnel junction elements for non-volatilely holding the potentials of the first storage node and the second storage node complementaryly to a first potential and a second potential, respectively, according to the storage data, the first and second magnetic tunnel junction elements are supplied with a write current according to the storage data and change complementaryly to high resistance and low resistance, respectively, each of the first and second magnetic tunnel junction elements has a first node and an internal node, a first PMOS transistor whose gate potential is controlled by the potential of the second storage node and provided between the power supply potential and the first storage node, and a second PMOS transistor whose gate potential is controlled by the potential of the first storage node and provided between the power supply potential and the second storage node, The magnetic tunnel junction includes a first NMOS transistor whose gate potential is controlled by the potential of the second memory node and whose source is connected to ground potential, and a second NMOS transistor whose gate potential is controlled by the potential of the first memory node and whose source is connected to ground potential, wherein each of the first and second magnetic tunnel junction elements has a first electrode having a second node and a third node for conducting the write current, which are provided to be connected to the internal node, the second node of the first electrode of the first and second magnetic tunnel junction elements are connected to the first memory node and the second memory node, respectively, and the first node of the first and second magnetic tunnel junction elements are connected to the drains of the first and second NMOS transistors, respectively. The memory cell array further comprises a plurality of write bit line pairs provided in the column direction, wherein each write bit line pair includes a first write bit line provided in common to the first storage node of the corresponding data holding mechanism and a second write bit line provided in common to the second storage node of the corresponding data holding mechanism.A semiconductor memory device comprising: a pair of first write switching elements provided between the first and second memory nodes and the first and second write bit lines, respectively; and a write control circuit that, in a write operation to the data holding mechanism, supplies a write current to the first magnetic tunnel junction element and the second magnetic tunnel junction element via the write bit lines such that their relative resistance states become low resistance and high resistance, respectively, wherein the third nodes of the first and second magnetic tunnel junction elements are each connectable to the first and second write bit lines via the first write switching element.

11. A semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell having a first storage node and a second storage node, and including a data holding mechanism for storing storage data, the data holding mechanism including a pair of first magnetic tunnel junction elements and second magnetic tunnel junction elements for non-volatilely holding the potential of the first storage node and the potential of the second storage node complementary to a first potential and a second potential, respectively, according to the storage data, further including a third magnetic tunnel junction element and a fourth magnetic tunnel junction element provided corresponding to the first magnetic tunnel junction element and the second magnetic tunnel junction element, respectively, the first and third magnetic tunnel junction elements change to high resistance and low resistance, respectively, when a write current is supplied according to the storage data, and the second and fourth magnetic tunnel junction elements change to low resistance and high resistance, respectively, when the write current is supplied according to the storage data. Each of the first to fourth magnetic tunnel junction elements includes a first node and an internal node, a first PMOS transistor whose gate potential is controlled by the potential of the second memory node, provided between the power supply potential and the first memory node, with its drain connected to the power supply potential, a second PMOS transistor whose gate potential is controlled by the potential of the first memory node, provided between the power supply potential and the second memory node, with its drain connected to the power supply potential, a first NMOS transistor whose gate potential is controlled by the potential of the second memory node, with its source connected to ground potential, and a second NMOS transistor whose gate potential is controlled by the potential of the first memory node, with its source connected to ground potential, and each of the first and second magnetic tunnel junction elements includes a first electrode provided to connect to the internal node, the first electrode having a second node and a third node for conducting the write current,Each of the third and fourth magnetic tunnel junction elements is provided such that the internal node is connected to the first electrode such that when the write current flows between the second node and the third node, the write current flows in the opposite direction to that of the first and second magnetic tunnel junction elements; the second node of the first electrode of the first and second magnetic tunnel junction elements is connected to the first memory node and the second memory node, respectively; the first node of the first and second magnetic tunnel junction elements is connected to the drains of the first and second NMOS transistors, respectively; and the first node of the third and fourth magnetic tunnel junction elements is connected to the sources of the first and second PMOS transistors, respectively. A semiconductor memory device further comprising a plurality of write bit line pairs provided in the column direction of the memory cell array, wherein each write bit line pair includes a first write bit line provided in common to the first storage node of the corresponding data holding mechanism and a second write bit line provided in common to the second storage node of the corresponding data holding mechanism, a pair of first write switching elements provided between the first and second storage nodes and the first and second write bit lines, and a write control circuit that, in a write operation to the data holding mechanism, supplies write current to the first magnetic tunnel junction element and the second magnetic tunnel junction element via the write bit lines such that their resistance states become low resistance and high resistance, respectively, wherein the third nodes of the first and second magnetic tunnel junction elements are provided so as to be connectable to the first and second write bit lines via the first write switching element.

12. An information processing system equipped with a semiconductor memory device according to any one of claims 1 to 10.

13. An information processing system equipped with a semiconductor memory device according to any one of claims 1 to 10 as a cache memory.

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