Information processing method, information processing device, and semiconductor storage device

Abstract

This information processing device acquires area information indicating an unstable area including an unstable element related to data storage in a data storage area of a memory array, writes data to the unstable area on the basis of the acquired area information, reads the data written to the unstable area from the unstable area, and outputs, as a random number, the data read from the unstable area.

Description

Information processing method, information processing apparatus, and semiconductor memory device

[0001] The present invention relates to an information processing method, an information processing apparatus, and a semiconductor memory device.

[0002] Patent Document 1 discloses a semiconductor memory device according to the background art. The semiconductor memory device includes a memory array, an error detection and correction circuit, and a random number generation circuit. The random number generation circuit uses unstable factors of the memory array, such as the number of error occurrences, as a seed to generate random numbers by a pseudo-random number generation algorithm or the like.

[0003] According to the semiconductor memory device according to the background art, the random number generation circuit uses unstable factors of the memory array as a seed to generate random numbers. Therefore, since implementation of the random number generation circuit is required, the circuit scale of the semiconductor memory device increases, and the random number generation processing becomes complicated.

[0004] Japanese Patent No. 6103958

[0005] An object of the present invention is to obtain an information processing method, an information processing apparatus, and a semiconductor memory device that can achieve reduction in the circuit scale of the semiconductor memory device and simplification of random number generation processing.

[0006] In the information processing method according to one aspect of the present invention, an information processing apparatus acquires area information indicating an unstable area including unstable factors related to data storage in a data storage area of a memory array, writes data to the unstable area based on the acquired area information, reads the data written to the unstable area from the unstable area, and outputs the data read from the unstable area as random numbers.

[0007] This is a simplified diagram showing the configuration of a semiconductor memory device according to an embodiment. This is a flowchart showing the process performed by the information processing device according to an embodiment. This is a simplified diagram showing the configuration of a semiconductor memory device according to a first modification. This is a flowchart showing the process performed by the information processing device according to the first modification. This is a simplified diagram showing the configuration of a semiconductor memory device according to a second modification. This is a flowchart showing the process performed by the information processing device according to the second modification. This is a flowchart showing the process performed by the information processing device according to a third modification. This is a flowchart showing the process performed by the information processing device according to a fourth modification.

[0008] Embodiments of the present invention will be described in detail below with reference to the drawings. Elements denoted by the same reference numerals in different drawings represent the same or corresponding elements.

[0009] Figure 1 is a simplified diagram showing the configuration of a semiconductor memory device 1 according to an embodiment of the present invention. The semiconductor memory device 1 comprises an information processing device 11, a memory array 12, a host interface 13, and a memory interface 14. The information processing device 11 accesses the memory array 12 via the memory interface 14. The information processing device 11 also accesses a host device 2 via the host interface 13. The host device 2 is a personal computer or the like. The semiconductor memory device 1 is detachably connected to the host device 2.

[0010] The information processing device 11 is configured with a circuit configuration such as an LSI and uses a processor such as a CPU. The information processing device 11 has an acquisition unit 21, a writing unit 22, a reading unit 23, a determination unit 24, an output unit 25, an error processing unit 26, and a management unit 27, as functions realized by the processor executing a program read from a non-volatile storage medium such as ROM. The processing details of each unit will be described later. Note that each unit may be configured with hardware circuits such as FPGAs.

[0011] The memory array 12 is composed of multiple memory cell transistors, such as NAND flash memory, arranged in a matrix. The memory area of ​​the memory array 12 has a management area 30 where management information is stored and a data storage area 31 where data is stored. The data storage area 31 has multiple blocks B (B1 to Bn), and each block B has multiple pages P. The size of each page P is 4KB or 8KB, and the size of each block B is 128 pages or 256 pages, etc.

[0012] The management unit 27 identifies unstable regions within the data storage area 31 of the memory array 12 that contain unstable elements related to data storage. The management unit for the unstable region may be block B or page P. Unstable elements related to data storage include errors (bit errors) in the binary data of "0" or "1" stored in each memory cell transistor. The unstable region includes regions where the number of error bits per unit area, such as block B or page P, exceeds an allowable upper limit according to the error correction capability of the error processing unit 26. The unstable region also includes regions where the amount of time variation in the number of error bits per unit area exceeds an allowable upper limit.

[0013] In this embodiment, the management unit 27 identifies block B4 as unstable region R1 and block B6 as unstable region R2 among all blocks B1 to Bn. In other words, in this embodiment, unstable region R corresponds to a faulty block. The faulty block may be a congenital faulty block caused by the manufacturing process of the semiconductor memory device 1, or an acquired faulty block caused by aging. The management unit 27 stores region information such as block addresses indicating unstable regions R1 and R2 in the management area 30 of the memory array 12.

[0014] Although there are various types of defects that can occur in block B, the management unit 27 excludes the following blocks from being identified as unstable regions R: (1) blocks in which a defect occurs where the read time or write time exceeds the permissible upper limit; (2) blocks in which a defect occurs where the read operation or write operation cannot be performed; and (3) blocks in which a defect occurs where the stored data is fixedly converted to either "0" or "1".

[0015] The information processing device 11 generates random numbers by utilizing the data storage instability elements present in the unstable region R. The random number generation process by the information processing device 11 will be described below.

[0016] Figure 2 is a flowchart showing the process executed by the information processing device 11 according to the embodiment.

[0017] First, in step SP01, the acquisition unit 21 acquires region information indicating unstable regions R1 and R2 by reading it from the management region 30.

[0018] Next, in step SP02, the writing processing unit 22 writes arbitrary data to the unstable region R1 based on the region information obtained in step SP01. The writing processing unit 22 may perform the writing of data to the unstable region R1 multiple times. This improves the randomness of the data. In this case, the writing processing unit 22 may write the data read from the unstable region R1 back to the same unstable region R1, or to a different unstable region R2.

[0019] Next, in step SP03, the read processing unit 23 reads the data written to the unstable area R1 in step SP02 from the unstable area R1. Since the unstable area R1 has unstable elements related to data storage, the data read from the unstable area R1 in step SP03 has random bit errors compared to the data written to the unstable area R1 in step SP02. Note that no error correction processing is performed by the error processing unit 26 on the data read from the unstable area R1 in step SP03.

[0020] Next, in step SP04, the determination unit 24 calculates the randomness of the data by performing a random number test on the data read from the unstable region R1 in step SP03. The determination unit 24 can use any random number test method such as NIST_FIPS_PUB_140-2, NIST_SP800-22, or DIEHARD. The determination unit 24 determines whether the calculated randomness is above or below the acceptable lower limit.

[0021] If the randomness is below the acceptable lower limit (step SP04: NO), the information processing device 11 repeats the processing from step SP02 onwards. In this case, the writing processing device 22 may write the data read from unstable area R1 in step SP03 to the same unstable area R1, or to a different unstable area R2.

[0022] If the randomness is above the acceptable lower limit (step SP04: YES), then in step SP05, the output unit 25 outputs the data whose randomness is above the acceptable lower limit as random numbers. This ensures that the randomness of the output random numbers is above the acceptable lower limit. The random numbers output from the output unit 25 may be stored in the memory array 12, transmitted to the host device 2 for authentication processing, etc., or used within the information processing device 11 for encryption processing, etc.

[0023] According to this embodiment, the data read from the unstable region R of the memory array 12 can be used directly as random numbers, and since the implementation of a random number generation circuit is unnecessary, it is possible to reduce the circuit size of the semiconductor memory device 1 and simplify the random number generation process.

[0024] Furthermore, according to this embodiment, the unstable region R includes a region where the number of error bits per unit area exceeds the allowable upper limit, or a region where the time variation of the number of error bits per unit area exceeds the allowable upper limit. This increases the instability of data storage in the unstable region R, and as a result, improves the randomness of the data read from the unstable region R.

[0025] Furthermore, according to this embodiment, if the randomness of the data read from the unstable region R is below the acceptable lower limit, the information processing device 11 writes the data read from the unstable region R back to the same or another unstable region R, and reads the data that has been written back to the unstable region R back to the unstable region R. This improves the randomness of the data read from the unstable region R.

[0026] The following describes various modifications of the above embodiment. The modifications described below can be applied in any combination.

[0027] (First Modification) Figure 3 is a simplified diagram showing the configuration of the semiconductor memory device 1 according to the first modification. The information processing device 11 further includes a reference voltage shift unit 41 compared to the configuration shown in Figure 1.

[0028] Figure 4 is a flowchart showing the process executed by the information processing device 11 according to the first modified example. The information processing method executed by the information processing device 11 further includes step SP11 which is executed between step SP02 and step SP03 for the process shown in Figure 2.

[0029] In step SP11, the reference voltage shift unit 41 shifts the reference voltage referenced in the read operation in step SP03 in a direction that increases the number of error bits. The shift includes raising or lowering. As an example of a specific means, the reference voltage shift unit 41 compares the number of error bits when the original reference voltage is raised with the number of error bits when the original reference voltage is lowered, and uses the reference voltage used when the number of error bits is higher as the read voltage when reading the data. The reference voltage is usually set lower than the threshold voltage of the memory cell transistor in the write state where electrons are injected into the floating gate, and higher than the threshold voltage of the memory cell transistor in the erase state where electrons are not injected into the floating gate. The reference voltage shift unit 41 intentionally increases the number of error bits by shifting the reference voltage so that it is higher than the lowest value of the threshold voltage distribution of the memory cell transistor in the write state, or lower than the highest value of the threshold voltage of the memory cell transistor in the erase state. Furthermore, in the case of a multilevel cell where multiple levels of reference voltages are set, the reference voltage shift unit 41 intentionally increases the number of error bits by shifting the reference voltage so that it is higher than the lowest value of a threshold voltage distribution higher than the reference voltage, or lower than the highest value of a threshold voltage distribution lower than the reference voltage.

[0030] In step SP03, the read processing unit 23 reads the data written to the unstable region R1 in step SP02 from the unstable region R1 using the reference voltage shifted in step SP11.

[0031] In this modified example, the target blocks for data writing and reading are not limited to faulty blocks; they may also be normal blocks. Furthermore, this modified example is applicable not only to single-level cells with a single reference voltage, but also to multi-level cells with multiple reference voltages.

[0032] According to this modified version, when reading data from the unstable region R, the number of error bits is intentionally increased by shifting the reference voltage of the reading operation. This improves the randomness of the data read from the unstable region R.

[0033] (Second Modification) Figure 5 is a simplified diagram showing the configuration of the semiconductor memory device 1 according to the second modification. The information processing device 11 further includes a voltage distribution shift unit 42 compared to the configuration shown in Figure 1.

[0034] Figure 6 is a flowchart showing the process executed by the information processing device 11 according to the second modified example. The information processing method executed by the information processing device 11 further includes step SP12, which is executed between step SP01 and step SP02, for the process shown in Figure 2.

[0035] In step SP12, the voltage distribution shift unit 42 shifts the threshold voltage distribution of the memory cell transistors in a direction that increases the number of error bits. The shift includes an increase or decrease. The voltage distribution shift unit 42 pre-shifts the threshold voltage distribution targeted in the write process of step SP02. As an example of a specific means, the voltage distribution shift unit 42 intentionally increases the number of error bits by shifting the threshold voltage distribution so that the highest value of the threshold voltage distribution of the memory cell transistors in the erase state becomes higher than the reference voltage, or the lowest value of the threshold voltage distribution of the memory cell transistors in the write state becomes lower than the reference voltage. In the case of a multilevel cell where multiple levels of reference voltages are set, the voltage distribution shift unit 42 intentionally increases the number of error bits by shifting the threshold voltage distribution so that the highest value of the threshold voltage distribution lower than the reference voltage becomes higher than the reference voltage, or the lowest value of the threshold voltage distribution higher than the reference voltage becomes lower than the reference voltage.

[0036] In step SP03, the read processing unit 23 reads the data written to the unstable region R1 in step SP02 using the reference voltage, after the threshold voltage distribution has been shifted in step SP12.

[0037] In this modified example, the target blocks for data writing and reading are not limited to faulty blocks; they may also be normal blocks. Furthermore, this modified example is applicable not only to single-level cells with a single reference voltage, but also to multi-level cells with multiple reference voltages.

[0038] According to this modification, the number of error bits is intentionally increased by shifting the threshold voltage distribution of the memory cell transistors before writing data to the unstable region R. This improves the randomness of the data read from the unstable region R.

[0039] (Third Modification) FIG. 7 is a flowchart showing a process executed by an information processing apparatus 11 according to the third modification. The information processing method executed by the information processing apparatus 11 further includes step SP13 executed between step SP02 and step SP03 in addition to the process shown in FIG. 2.

[0040] In step SP13, after writing data to the unstable region R1 in step SP02, the write processing unit 22 writes next data into the unstable region R1 without erasing the data written in step SP02, so that a threshold voltage distribution shifted from a target threshold voltage distribution is obtained, and the number of error bits is intentionally increased. The next data may be the same as the data written in step SP02, or may be different data.

[0041] In step SP03, the read processing unit 23 reads the data doubly written in step SP02 and step SP13 from the unstable region R1.

[0042] It should be noted that, in the present modification, the target block for writing and reading data is not limited to a defective block, and may be a normal block. In addition, the present modification is applicable not only to single-level cells in which one reference voltage is set, but also to multi-level cells in which a plurality of levels of reference voltages are set.

[0043] According to the present modification, after writing data to the unstable region R1, next data is written without erasing the already written data, thereby improving the randomness of data read from the unstable region R1.

[0044] (Fourth Modification) FIG. 8 is a flowchart showing a process executed by an information processing apparatus 11 according to the fourth modification. The information processing method executed by the information processing apparatus 11 further includes step SP14 executed between step SP01 and step SP02 in addition to the process shown in FIG. 2.

[0045] In step SP14, before the data write processing for the unstable region R1 in step SP02, the write processing unit 22 performs data erase processing on the unstable region R1 to be written in step SP02. In the write processing in step SP02, as part of the write processing, erase processing is performed on the unstable region R1 to be written before writing the relevant data. In this modified example, the write processing unit 22 executes erase processing in advance on the unstable region R1 to be written before the erase processing performed as part of the write processing in step SP02. In other words, in this modified example, double erase processing is executed on the unstable region R1, which consists of the erase processing in step SP14 and the erase processing performed as part of the write processing in step SP02. By executing the double erase processing, the threshold voltage distribution obtained in the write processing in step SP02 shifts from the target threshold voltage distribution, thereby intentionally increasing the number of error bits.

[0046] In step SP03, the read processing unit 23 reads the data written in step SP02 from the unstable region R1.

[0047] It should be noted that, in this modified example, the target block to which data is written and from which data is read is not limited to a defective block, and may be a normal block. In addition, this modified example is not limited to single-level cells in which one reference voltage is set, but is also applicable to multi-level cells in which multiple levels of reference voltages are set.

[0048] According to this modified example, by reading the data written to the unstable region R1 that has been subjected to double erase processing, the randomness of the data read from the unstable region R1 can be improved.

[0049] Hereinafter, various aspects of the present invention will be described.

[0050] An information processing method according to a first aspect of the present invention involves an information processing device acquiring region information indicating an unstable region in the data storage area of ​​a memory array that includes an unstable element related to data storage, writing data to the unstable region based on the acquired region information, reading the data written to the unstable region from the unstable region, and outputting the data read from the unstable region as a random number.

[0051] According to the first embodiment, data read from the unstable region of the memory array can be used directly as random numbers, and since the implementation of a random number generation circuit is unnecessary, it is possible to reduce the circuit size of the semiconductor memory device and simplify the random number generation process.

[0052] In the second aspect of the present invention, the information processing method involves writing data to the unstable region multiple times, as in the first aspect.

[0053] According to the second embodiment, the randomness of the data read from the unstable region can be improved by performing data writing to the unstable region multiple times.

[0054] In the third aspect of the present invention, the information processing method, in the first or second aspect, outputs a random number when the randomness of the data read from the unstable region is equal to or greater than the allowable lower limit.

[0055] According to the third embodiment, the randomness of the output random numbers can be guaranteed to be above the acceptable lower limit.

[0056] The information processing method according to the fourth aspect of the present invention, in any one of the first to third aspects, includes an unstable region in which the number of error bits per unit area exceeds an allowable upper limit, or a region in which the amount of time variation of the number of error bits per unit area exceeds an allowable upper limit.

[0057] According to the fourth embodiment, the instability of data storage in the unstable region can be increased, and as a result, the randomness of the data read from the unstable region can be improved.

[0058] The information processing method according to the fifth aspect of the present invention further includes, in any one of the first to fourth aspects, if the randomness of the data read from the unstable area is less than an acceptable lower limit, writing the data read from the unstable area to the unstable area and reading the data written to the unstable area from the unstable area.

[0059] According to the fifth embodiment, the randomness of the data read from the unstable region can be improved by writing the data read from the unstable region back to the unstable region and reading the data written to the unstable region back from the unstable region.

[0060] The information processing method according to the sixth aspect of the present invention further increases the number of error bits by shifting the reference voltage of the read operation when reading data from the unstable region, in any one of the first to fifth aspects.

[0061] According to the sixth embodiment, when reading data from an unstable region, the randomness of the data read from the unstable region can be improved by shifting the reference voltage of the reading operation.

[0062] The information processing method according to the seventh aspect of the present invention further increases the number of error bits by shifting the threshold voltage distribution of the memory cell transistor before writing data to the unstable region, in any one of the first to sixth aspects.

[0063] According to the seventh embodiment, the randomness of data read from an unstable region can be improved by shifting the threshold voltage distribution of the memory cell transistor before writing data to the unstable region.

[0064] The information processing method according to the eighth aspect of the present invention further increases the number of error bits by writing the next data without erasing the written data after writing data to the unstable area, in any one of the first to seventh aspects.

[0065] According to the eighth embodiment, the randomness of the data read from the unstable region can be improved by writing the next data without erasing the previously written data after writing data to the unstable region.

[0066] The information processing method according to the ninth aspect of the present invention further increases the number of error bits by performing multiple erase operations on the unstable region before writing data to the unstable region, in any one of the first to eighth aspects.

[0067] According to the ninth embodiment, the randomness of data read from the unstable region can be improved by performing multiple erase operations on the unstable region before writing data to the unstable region.

[0068] An information processing device according to a tenth aspect of the present invention comprises a circuit configuration which acquires region information indicating an unstable region containing unstable elements related to data storage within the data storage area of ​​a memory array, writes data to the unstable region based on the acquired region information, reads the data written to the unstable region from the unstable region, and outputs the data read from the unstable region as a random number.

[0069] According to the tenth embodiment, data read from the unstable region of the memory array can be used directly as random numbers, and since the implementation of a random number generation circuit is unnecessary, it is possible to reduce the circuit size of the semiconductor memory device and simplify the random number generation process.

[0070] A semiconductor memory device according to an eleventh aspect of the present invention comprises an information processing device and a memory array, wherein the information processing device acquires region information indicating an unstable region containing an unstable element related to data storage in the data storage area of ​​the memory array, writes data to the unstable region based on the acquired region information, reads the data written to the unstable region from the unstable region, and outputs the data read from the unstable region as a random number.

[0071] According to the eleventh embodiment, data read from the unstable region of the memory array can be used directly as random numbers, and since the implementation of a random number generation circuit is unnecessary, it is possible to reduce the circuit size of the semiconductor memory device and simplify the random number generation process.

[0072] A program according to a twelfth aspect of the present invention is a program for causing an information processing device to execute processing, wherein the processing involves acquiring region information indicating an unstable region in the data storage area of ​​a memory array that includes an unstable element related to data storage, writing data to the unstable region based on the acquired region information, reading the data written to the unstable region from the unstable region, and outputting the data read from the unstable region as a random number.

[0073] According to the twelfth embodiment, data read from the unstable region of the memory array can be used directly as random numbers, and since the implementation of a random number generation circuit is unnecessary, it is possible to reduce the circuit size of the semiconductor memory device and simplify the random number generation process.

[0074] The functions of the elements disclosed herein may be implemented using general-purpose processors, dedicated processors, integrated circuits, ASICs ("Application-Specific Integrated Circuits"), conventional circuit configurations and / or combinations thereof, or processing circuit configurations, which are configured to perform the disclosed elements or programmed to perform the disclosed functions. A processor is considered a processing circuit configuration or circuit configuration if it includes transistors and other circuit configurations within it. In this disclosure, a circuit configuration, unit or means is hardware that performs the listed functions or hardware programmed to perform such functions. Hardware may be any hardware disclosed herein or other known hardware programmed to perform the listed functions or configured to perform such functions. When hardware is a processor that may be considered a type of circuit configuration, a circuit configuration, means or unit is a combination of hardware and software, software used to configure the hardware and / or processor.

Claims

1. An information processing method comprising: an information processing device acquiring region information indicating an unstable region containing unstable elements related to data storage within the data storage area of ​​a memory array; writing data to the unstable region based on the acquired region information; reading the data written to the unstable region from the unstable region; and outputting the data read from the unstable region as a random number.

2. The information processing method according to claim 1, wherein data is written to the unstable region multiple times.

3. The information processing method according to claim 1, wherein, in outputting the random number, a random number is output when the randomness of the data read from the unstable region is equal to or greater than the allowable lower limit.

4. The information processing method according to claim 1, wherein the unstable region includes a region in which the number of error bits per unit area exceeds an allowable upper limit, or a region in which the amount of time variation of the number of error bits per unit area exceeds an allowable upper limit.

5. The information processing method according to claim 1, further comprising: if the randomness of the data read from the unstable region is less than an acceptable lower limit, writing the data read from the unstable region to the unstable region, and reading the data written to the unstable region from the unstable region.

6. The information processing method according to claim 1, further comprising increasing the number of error bits by shifting the reference voltage of the read operation when reading data from the unstable region.

7. The information processing method according to claim 1, further comprising increasing the number of error bits by shifting the threshold voltage distribution of the memory cell transistor before writing data to the unstable region.

8. The information processing method according to claim 1, further comprising increasing the number of error bits by writing the next data without erasing the written data after writing data to the unstable area.

9. The information processing method according to claim 1, further comprising increasing the number of error bits by performing multiple erase operations on the unstable region before writing data to the unstable region.

10. An information processing device comprising a circuit configuration, the circuit configuration acquiring region information indicating an unstable region containing unstable elements related to data storage within the data storage area of ​​a memory array, writing data to the unstable region based on the acquired region information, reading the data written to the unstable region from the unstable region, and outputting the data read from the unstable region as a random number.

11. A semiconductor memory device comprising an information processing device and a memory array, wherein the information processing device acquires region information indicating an unstable region containing an unstable element related to data storage within the data storage area of ​​the memory array, writes data to the unstable region based on the acquired region information, reads the data written to the unstable region from the unstable region, and outputs the data read from the unstable region as a random number.

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