Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention relates to a semiconductor device comprising: a nanosheet laminate in which a plurality of nanosheet layers made of a semiconductor material are laminated; a gate electrode covering the entire periphery of each of the nanosheet layers via a gate insulating film; a source / drain provided on both sides of the nanosheet laminate and connected in common to the plurality of nanosheet layers; and an inner spacer sandwiched between the nanosheet layers between the gate electrode and the source / drain on both sides of the gate electrode, wherein the inner spacer extends to the outside of the nanosheet layers.

Description

Semiconductor device and method of manufacturing semiconductor device

[0001] The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.

[0002] Regarding a semiconductor device having a surrounding gate transistor, the following Patent Document 1 describes a configuration in which an inner spacer formed of an insulating material is disposed between a metal gate covering the entire circumference of a nanosheet layer constituting a semiconductor channel and a source / drain.

[0003] US Publication No. 2024 / 0429103

[0004] In a surrounding gate transistor having such a configuration, suppression of parasitic capacitance between a source / drain and a metal gate is required along with miniaturization of semiconductor devices.

[0005] Therefore, an object of the present invention is to provide a semiconductor device and a method of manufacturing a semiconductor device capable of reducing parasitic capacitance between a source / drain and a gate electrode in a surrounding gate transistor.

[0006] To achieve the above object, the present invention provides: a nanosheet stacked body in which a plurality of nanosheet layers made of a semiconductor material are stacked; a gate electrode covering the entire circumference of each of the nanosheet layers with a gate insulating film interposed therebetween; source / drains provided on both sides of the nanosheet stacked body and commonly connected to the plurality of nanosheet layers; and inner spacers sandwiched between the nanosheet layers between the gate electrode and the source / drains on both sides of the gate electrode, wherein the inner spacers extend outward beyond the nanosheet layers. The present invention is the above-described semiconductor device, and also relates to a method of manufacturing the semiconductor device.

[0007] According to the present invention, it is possible to provide a semiconductor device and a method of manufacturing a semiconductor device capable of reducing parasitic capacitance between a source / drain and a gate electrode in a surrounding gate transistor.

[0008] This is a cross-sectional view of the main part of the semiconductor device according to the first embodiment. This is a process diagram (1) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (2) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (3) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (4) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (5) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (6) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (7) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (8) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (9) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (10) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (11) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (12) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a process diagram (13) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a cross-sectional view of the main part of the semiconductor device according to the second embodiment. This is a process diagram (1) showing the manufacturing method of the semiconductor device according to the second embodiment. This is a process diagram (2) showing the manufacturing method of the semiconductor device according to the second embodiment. This is a process diagram (3) showing the manufacturing method of the semiconductor device according to the second embodiment. This is a process diagram (part 4) showing the manufacturing method of a semiconductor device according to the second embodiment. This is a cross-sectional view of the main part of the semiconductor device according to the third embodiment. This is a process diagram (part 1) showing the manufacturing method of a semiconductor device according to the third embodiment. This is a process diagram (part 2) showing the manufacturing method of a semiconductor device according to the third embodiment. This is a process diagram (part 3) showing the manufacturing method of a semiconductor device according to the third embodiment. This is a process diagram (part 4) showing the manufacturing method of a semiconductor device according to the third embodiment. This is a cross-sectional view of the main part of the semiconductor device according to the fourth embodiment. This is a process diagram (part 1) showing the manufacturing method of a semiconductor device according to the fourth embodiment. This is a process diagram (part 2) showing the manufacturing method of a semiconductor device according to the fourth embodiment. This is a process diagram (part 3) showing the manufacturing method of a semiconductor device according to the fourth embodiment. This is a process diagram (part 4) showing the manufacturing method of a semiconductor device according to the fourth embodiment. This is a process diagram (part 5) showing the manufacturing method of a semiconductor device according to the fourth embodiment.This is a process diagram (6) showing the manufacturing method of a semiconductor device according to the fourth embodiment. This is a process diagram (7) showing the manufacturing method of a semiconductor device according to the fourth embodiment. This is a process diagram (8) showing the manufacturing method of a semiconductor device according to the fourth embodiment.

[0009] Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the embodiments described below, the same reference numerals are used for the same components, and some redundant descriptions will be omitted.

[0010] <First Embodiment> <Configuration of Semiconductor Device of the First Embodiment> Figure 1 is a diagram showing the configuration of a semiconductor device 1 of the first embodiment, and is a cross-sectional view in the gate length direction of the all-around gate transistor 1a having this semiconductor device 1. The all-around gate transistor 1a shown in Figure 1 is provided on one main surface side of a semiconductor substrate 10 and has a nanosheet laminate 13 formed by stacking a plurality of nanosheet layers 12 made of semiconductor material. Each nanosheet layer 12 constitutes a semiconductor channel and is stacked with intervals between them, and its entire circumference is surrounded by a gate electrode 26g via a gate insulating film 25, forming a GAA (Gate All Around) structure. The gate electrode 26g may have a multilayer structure of two or more layers.

[0011] Furthermore, the all-around gate transistor 1a has source / drain 21sd on both sides in the channel length direction of the nanosheet laminate 13. The source / drain 21sd is epitaxially grown from the nanosheet layer 12 and the semiconductor substrate 10 and is commonly connected to multiple nanosheet layers 12.

[0012] Furthermore, the all-around gate transistor 1a has insulating inner spacers 24a between the gate electrode 26g and the source / drain 21sd on both sides of the gate electrode 26g. Each inner spacer 24a is sandwiched between the nanosheet layers 12 and between the nanosheet layers 12 and the semiconductor substrate 10, and has a film thickness similar to that of the gate electrode 26g. In addition, each inner spacer 24a is sandwiched above and below in the film thickness direction by insulating liner layers 19.

[0013] Furthermore, the all-around gate transistor 1a has insulating sidewalls 24b above the nanosheet laminate 13 between the gate electrode 26g and the source / drain 21sd on both sides of the gate electrode 26g. These inner spacers 24a and sidewalls 24b are made of the same low dielectric material and insulate the source / drain 21sd from the gate electrode 26g.

[0014] In the configuration described above, the all-around gate transistor 1a has an inner spacer 24a and a sidewall 24b that extend beyond the nanosheet layer 12. This increases the distance [d1] between the gate electrode 26g and the source / drain 21sd, while maintaining the overall width of the source / drain 21sd and the gate electrode 26g, which is the gate length.

[0015] <Method of Manufacturing a Semiconductor Device of the First Embodiment> Figures 2 to 14 are process diagrams (1) to (13) showing the manufacturing method of the semiconductor device 1 of the first embodiment described above. Hereinafter, the manufacturing method of the semiconductor device 1 of the first embodiment and the detailed configuration of each part will be explained in accordance with the manufacturing process sequence of the semiconductor device shown in Figures 2 to 14. Figures 2 to 14 are diagrams showing the cross-sectional portions corresponding to Figure 1.

[0016] First, as shown in Figure 2, a line-shaped nanosheet laminate 13 extending in the left-right direction in the drawing is patterned on a semiconductor substrate 10 made of, for example, silicon. The nanosheet laminate 13 has a structure in which a sacrificial sheet layer 11 and a nanosheet layer 12 made of semiconductor material are stacked alternately in that order. The sacrificial sheet layer 11 is made of a material that can be selectively etched with respect to the nanosheet layer 12 made of semiconductor material. For example, when silicon is used as the semiconductor material constituting the nanosheet layer 12, silicon germanium is used as the sacrificial sheet layer 11.

[0017] Subsequently, a laminated structure St1 is formed in a line extending in the depth direction on the drawing, with an insulating layer 14, a dummy gate 15, an insulating layer 16, and a cap layer 17 formed in this order. Insulating sacrificial sidewalls 18 are formed on both sides of the laminated structure St1. This laminated structure St1 and sacrificial sidewalls 18 form a line that crosses the nanosheet laminate 13. The insulating layer 14 and insulating layer 16 are formed using, for example, silicon oxide. The dummy gate 15 is formed using, for example, polysilicon, and the cap layer 17 is formed using, for example, silicon nitride. The sacrificial sidewalls 18 are formed using, for example, SiBCN (boronated silicon carbide nitride).

[0018] Subsequently, using the cap layer 17 and the sacrificial sidewall 18 as a mask, the line-shaped nanosheet laminate 13 is etched to pattern the nanosheet laminate 13 in an island-like manner, as shown in the figure.

[0019] Next, as shown in Figure 3, the sacrificial sheet layer 11 exposed on the side wall of the nanosheet laminate 13 is selectively reduced by isotropic etching.

[0020] Next, as shown in Figure 4, insulating sacrificial inner spacers 20 are formed between the nanosheet layers 12 exposed on the side walls of the nanosheet laminate 13 via an insulating liner layer 19. This causes the sacrificial inner spacers 20 to be sandwiched between the nanosheet layers 12 and between the bottom nanosheet layer 12 and the semiconductor substrate 10 at both ends of the exposed side of the nanosheet laminate 13. The sacrificial inner spacers 20 are formed from a material that can be selectively etched with respect to the liner layer 19.

[0021] The formation of the liner layer 19 and the sacrificial inner spacer 20 described above is carried out as follows. First, a liner layer 19 made of, for example, silicon oxide is deposited by isotropic deposition, then a silicon nitride film is deposited to fill the spaces between the nanosheet layers 12, and then the silicon nitride film and the liner layer 19 are etched back by anisotropic etching. This leaves the liner layer 19 and the silicon nitride film only between the nanosheet layers 12 and between the bottom nanosheet layer 12 and the semiconductor substrate 10, and the remaining silicon nitride film is formed as the sacrificial inner spacer 20.

[0022] Next, as shown in Figure 5, source / drain 21sd are formed on both sides of the exposed surface of the nanosheet laminate 13. At this time, source / drain 21sd containing impurities are formed by epitaxial growth from the exposed surfaces of the nanosheet layer 12 and the semiconductor substrate 10. The source / drain 21sd formed in this way has a height that exceeds the height of the nanosheet laminate 13 and overlaps with the dummy gate 15 and the sacrificial sidewall 18.

[0023] Next, as shown in Figure 6, an insulating etching stopper layer 22 is formed on one main surface of the semiconductor substrate 10 so as to cover the cap layer 17, the sacrificial sidewall 18, and the source / drain 21sd.

[0024] Next, as shown in Figure 7, the etching stopper layer 22 is left on the side walls of the cap layer 17 and the sacrificial sidewall 18 by anisotropic etching.

[0025] Next, as shown in Figure 8, an embedded insulating film 23 is formed on one main surface of the semiconductor substrate 10 so as to embed the stacked structure St1, the sacrificial sidewall 18, the source / drain 21sd, and the etching stopper layer 22. The embedded insulating film 23 is made of, for example, silicon oxide.

[0026] Next, as shown in Figure 9, chemical mechanical polishing (CMP) is performed from above the embedded insulating film 23 to expose the dummy gate 15. As a result of this CMP, the dummy gate 15, sacrificial sidewall 18, etching stopper layer 22, and embedded insulating film 23 are exposed on the flattened polished surface.

[0027] Next, as shown in Figure 10, the sacrificial sidewall 18 and etching stopper layer 22 (see Figure 9) between the dummy gate 15 and the embedded insulating film 23 are removed by selective etching. This exposes the portions where the liner layer 19 and sacrificial inner spacer 20 are laminated at both ends of the gate width direction (depth direction in the drawing) of the nanosheet laminate 13, although this is not shown in Figure 10. In this state, the sacrificial inner spacer 20 is covered by the liner layer 19, so the liner layer 19 is then removed to expose the sacrificial inner spacer 20.

[0028] Next, as shown in Figure 11, the sacrificial inner spacers 20 (see Figure 10) are selectively etched away from the exposed side walls of the nanosheet laminate 13. This replaces the sacrificial inner spacers 20 with cavities Gp1, forming cavities Gp1 between the nanosheet layers 12 next to the sacrificial sheet layer 11. Each cavity Gp1 has a cylindrical shape surrounded by a source / drain 21sd and the sacrificial sheet layer 11 and nanosheet layer 12 via a liner layer 19.

[0029] Next, as shown in Figure 12, the cavity Gp1 is expanded toward the source / drain 21sd by selective etching of the source / drain 21sd. At this time, the source / drain 21sd located on top of the nanosheet laminate 13 also recedes outward from the nanosheet layer 12. This increases the distance [d1] between the sacrificial sheet layer 11 and the source / drain 21sd without reducing the overall width of the source / drain 21sd or the width of the sacrificial sheet layer 11.

[0030] Next, as shown in Figure 13, the cavity Gp1 and the space between the dummy gate 15 and the embedded insulating film 23 are filled with a low-dielectric film 201. The low-dielectric film 201 embedded in the cavity Gp1 is formed as an inner spacer 24a. The low-dielectric film 201 embedded between the dummy gate 15 and the embedded insulating film 23 is formed as a new sidewall 24b.

[0031] The low dielectric film 201 may be made of low dielectric constant materials such as SiBCN (boronated silicon carbide), SiOC (silicon oxide), SiN (silicon nitride), and SiOCN (silicon oxycarbide nitride). These low dielectric constant materials are preferably used because they act as etching stoppers in the etching of the embedded insulating film 23 made of silicon oxide when contacts connected to the source / drain 21sd are formed thereafter.

[0032] Next, as shown in Figure 14, the dummy gate 15 and the insulating layer 14 below it (see Figure 13) are selectively removed, followed by the selective removal of the sacrificial sheet layer 11 of the nanosheet laminate 13 (see Figure 13). This exposes the central part of the silicon nanosheet layer 12 around its entire circumference.

[0033] Following the above steps, as shown in Figure 1, a gate insulating film 25 and a gate electrode 26g are formed to cover the entire circumference of the nanosheet layer 12, completing the all-around gate transistor 1a. The gate electrode 26g formed here is linear, similar to the dummy gate 15 (see Figures 2 and 13).

[0034] <Effects of the First Embodiment> According to the first embodiment described above, since the inner spacer 24a and sidewall 24b of the full-circumference gate transistor 1a extend to the outside of the nanosheet layer 12, it is possible to increase the distance [d1] between the gate electrode 26g and the source / drain 21sd without reducing the overall width and gate length of the source / drain 21sd. As a result, it is possible to reduce the parasitic capacitance between the source / drain 21sd and the gate electrode 26g in the full-circumference gate transistor 1a without changing the device design.

[0035] ≪Second Embodiment≫ <Configuration of the Semiconductor Device of the Second Embodiment> Figure 15 is a diagram showing the configuration of the semiconductor device 2 of the second embodiment, and is a cross-sectional view in the gate length direction of the all-around gate transistor 2a of this semiconductor device 2. The difference between the semiconductor device 2 shown in Figure 15 and the semiconductor device 1 of the first embodiment (see Figure 1) is that the inner spacer 24a' and sidewall 24b' between the source / drain 21sd and the gate electrode 26g are made of different insulating materials. Furthermore, other configurations, including the fact that the inner spacer 24a' and sidewall 24b' extend beyond the nanosheet layer 12, are the same as those of the first embodiment, so their explanation is omitted here.

[0036] <Method of Manufacturing a Semiconductor Device of the Second Embodiment> Figures 16 to 19 are process diagrams (1) to (4) showing the method of manufacturing the semiconductor device 2 of the second embodiment described above. Hereinafter, the method of manufacturing the semiconductor device 2 of the second embodiment and the detailed configuration of each part will be described in accordance with the drawings used in the description of the first embodiment and the order of the semiconductor device manufacturing process shown in Figures 16 to 19.

[0037] First, the procedure described in Figures 2 to 12 in the first embodiment is carried out until the cavity Gp1 (see Figure 11) after the removal of the sacrificial inner spacer 20 (see Figure 10) is expanded towards the source / drain 21sd side.

[0038] After the above steps, as shown in Figure 16, a low-dielectric film 202 is deposited on top of the semiconductor substrate 10 to fill the cavity Gp1. At this time, the low-dielectric film 202 is deposited with a thickness that intentionally leaves a space between the dummy gate 15 and the embedded insulating film 23, rather than completely filling the space. The material used for such a low-dielectric film 202 can be any material with a low dielectric constant, such as silicon oxide. In this case, the low-dielectric film 202 is also deposited on the dummy gate 15, the embedded insulating film 23, the side walls of the source / drain 21sd, and even on top of the uppermost nanosheet layer 12.

[0039] Next, as shown in Figure 17, the low-dielectric film 202 covering the dummy gate 15, the embedded insulating film 23, the side walls of the source / drain 21sd, and the uppermost nanosheet layer 12 is removed by isotropic etching, leaving the low-dielectric film 202 inside the cavity Gp1. As a result, the low-dielectric film 202 remaining inside the cavity Gp1 becomes a new inner spacer 24a'.

[0040] Next, as shown in Figure 18, an insulating sidewall 24b' is formed to fill the space between the dummy gate 15 and the embedded insulating film 23. The insulating material constituting the sidewall 24b' can be a low dielectric constant material such as SiBCN, SiOC, SiN, and SiOCN. These low dielectric constant materials are preferably used because they act as etching stoppers in the etching of the embedded insulating film 23 made of silicon oxide when contacts connected to the source / drain 21sd are formed later.

[0041] To form such a sidewall 24b', first, an insulating material film is deposited on one main surface of the semiconductor substrate 10 so as to fill the space between the dummy gate 15 and the embedded insulating film 23. Then, the insulating material film is etched back until the dummy gate 15 is exposed. The insulating material film remaining between the dummy gate 15 and the embedded insulating film 23 is then formed as the sidewall 24b'.

[0042] Next, as shown in Figure 19, the dummy gate 15 and the insulating layer 14 below it (see Figure 18) are selectively removed, followed by the selective removal of the sacrificial sheet layer 11 of the nanosheet laminate 13 (see Figure 18). This exposes the central part of the silicon nanosheet layer 12 around its entire circumference.

[0043] After the above steps, as shown in Figure 15, a gate insulating film 25 and a gate electrode 26g are formed to cover the entire circumference of the nanosheet layer 12, completing the all-around gate transistor 2a. The gate electrode 26g formed here is linear, similar to the dummy gate 15 (see Figures 16 and 18).

[0044] <Effects of the Second Embodiment> Even in the second embodiment described above, the inner spacer 24a' and the sidewall 24b' of the all-around gate transistor 2a are extended to the outside of the nanosheet layer 12, whereby similar to the first embodiment, it is possible to reduce the parasitic capacitance between the source / drain 21sd and the gate electrode 26g in the all-around gate transistor 2a without changing the element design. Furthermore, by using different materials for the inner spacer 24a' and the sidewall 24b', the inner spacer 24a' can be formed using a material selected focusing only on dielectric constant. This makes it possible to further reduce the parasitic capacitance.

[0045] <<Third Embodiment>> <Configuration of Semiconductor Device According to Third Embodiment> FIG. 20 is a diagram showing the configuration of a semiconductor device 3 according to the third embodiment, and is a cross-sectional view in the gate length direction of an all-around gate transistor 3a included in the semiconductor device 3. The difference between the semiconductor device 3 shown in FIG. 20 and the semiconductor device 1 of the first embodiment (see FIG. 1) is that an inner spacer 24a'' and a sidewall 24b'' are thicker than the gate electrode 26g, and the liner layer 19 (see FIG. 1) is not disposed around the inner spacer 24a''. Other configurations are the same as those of the first embodiment, so descriptions thereof are omitted here.

[0046] That is, the film thickness of the inner spacer 24a'' is larger than the total film thickness of the gate electrode 26g and the gate insulating film 25 in the portion sandwiched between the inner spacers 24a''. Furthermore, the film thickness of the sidewall 24b'' is larger than the total film thickness of the gate electrode 26g and the gate insulating film 25 in the portion sandwiched between the sidewalls 24b''.

[0047] <Method for Manufacturing Semiconductor Device According to Third Embodiment> FIGS. 21 to 24 are process diagrams (Part 1 to Part 4) showing the method for manufacturing the semiconductor device 3 of the third embodiment described above. Hereinafter, the method for manufacturing the semiconductor device 3 according to the third embodiment and the detailed configuration of each part will be described along the order of the manufacturing steps of the semiconductor device shown in the drawings used in the description of the first embodiment and FIGS. 21 to 24.

[0048] First, the procedure described in the first embodiment with reference to FIGS. 2 to 11 is performed, and the process is carried out until the sacrificial inner spacer 20 (see FIG. 10) is removed to form the cavity Gp1.

[0049] After the above process, as shown in FIG. 21, the liner layer 19 covering the inner wall of the cavity Gp1 is selectively removed by etching.

[0050] Next, as shown in FIG. 22, the nanosheet layer 12 made of silicon and the source / drain 21sd are thinned by selective etching, and the cavity Gp1 is expanded toward the nanosheet layer 12 side and the source / drain 21sd side. At this time, the source / drain 21sd located above the nanosheet laminate 13 also recedes. Thereby, the distance d1 between the sacrificial sheet layer 11 and the source / drain 21sd is increased without reducing the overall width of the source / drain 21sd and the width of the sacrificial sheet layer 11. In addition, the height of the cavity Gp1 is made larger than the film thickness of the sacrificial sheet layer 11, so that both ends of the nanosheet layer 12 are thinned. The upper surface of the uppermost nanosheet layer 12 is also thinned.

[0051] Next, as shown in FIG. 23, the inside of the cavity Gp1 and the gap between the dummy gate 15 and the buried insulating film 23 are filled with a low-dielectric film 201. The low-dielectric film 201 embedded in the cavity Gp1 is formed as an inner spacer 24a". In addition, the low-dielectric film 201 embedded between the dummy gate 15 and the buried insulating film 23 is formed as a new sidewall 24b".

[0052] For the low-dielectric film 201, for example, in addition to SiBCN, low dielectric constant materials such as SiOC, SiN, and SiOCN are used. These low dielectric constant materials are preferably used because they serve as an etching stopper in the etching of the buried insulating film 23 made of silicon oxide when a contact connected to the source / drain 21sd is formed later.

[0053] Next, as shown in FIG. 24, the dummy gate 15 and the insulating layer 14 thereunder (see FIG. 23) are selectively removed, and then the sacrificial sheet layer 11 (see FIG. 23) of the nanosheet laminate 13 is selectively removed. Thereby, the central portion of the silicon nanosheet layer 12 is exposed over the entire circumference.

[0054] Following the above steps, as shown in Figure 20, a gate insulating film 25 and a gate electrode 26g are formed to cover the entire circumference of the nanosheet layer 12, completing the all-around gate transistor 3a. The gate electrode 26g formed here is linear, similar to the dummy gate 15 (see Figures 21 and 23).

[0055] <Effects of the Third Embodiment> Even in the third embodiment described above, since the inner spacer 24a'' and sidewall 24b'' of the full-circumference gate transistor 3a extend to the outside of the nanosheet layer 12, it is possible to reduce the parasitic capacitance between the source / drain 21sd and the gate electrode 26g of the full-circumference gate transistor 3a without changing the device design, similar to the first embodiment. Furthermore, since the inner spacer 24a'' and sidewall 24b'' are thicker than the gate electrode 26g located between them, it is possible to further reduce the parasitic capacitance.

[0056] ≪Fourth Embodiment≫ <Configuration of the Semiconductor Device of the Fourth Embodiment> Figure 25 is a diagram showing the configuration of the semiconductor device 4 of the fourth embodiment, and is a cross-sectional view in the gate length direction of the all-around gate transistor 4a of this semiconductor device 4. The difference between the semiconductor device 4 shown in Figure 25 and the semiconductor device 1 of the first embodiment (see Figure 1) is that the gate electrode 26g and the source / drain 21sd are insulated by a cavity Gp1 and a second cavity Gp2. In addition, a sealing insulating film 42 is provided to seal the cavity Gp1 and the second cavity Gp2. The other configurations are the same as those of the first embodiment, so their explanation is omitted here.

[0057] Each cavity Gp1 is used as an insulating spacer sandwiched between the nanosheet layers 12 and between the nanosheet layers 12 and the semiconductor substrate 10, insulating the source / drain 21sd from the gate electrode 26g. Each cavity Gp1 is sandwiched above and below in the film thickness direction by an insulating liner layer 19 and has a film thickness similar to that of the gate electrode 26g. Furthermore, each cavity Gp1 is provided so as to protrude outside the nanosheet layers 12.

[0058] Furthermore, the second cavity Gp2 is located above the nanosheet laminate 13, between the source / drain 21sd and the gate electrode 26g, and insulates the source / drain 21sd and the gate electrode 26g. The second cavity Gp2 is provided so as to extend beyond the nanosheet layer 12.

[0059] Furthermore, the sealing insulating film 42 is provided between the linear gate electrode 26g and the insulating film 41 above the gate electrode 26g and the embedded insulating film 23, and has a linear shape. Such a sealing insulating film 42 is positioned to a depth that covers the boundary portion between the source / drain 21sd and the embedded insulating film 23.

[0060] <Method of Manufacturing a Semiconductor Device of the Fourth Embodiment> Figures 26 to 33 are process diagrams (1) to (8) showing the method of manufacturing the semiconductor device 4 of the fourth embodiment described above. Hereinafter, the method of manufacturing the semiconductor device 4 of the fourth embodiment and the detailed configuration of each part will be described in accordance with the drawings used in the description of the first embodiment and the order of the semiconductor device manufacturing process shown in Figures 26 to 33.

[0061] First, the procedure described in Figures 2 to 5 in the first embodiment is carried out until source / drain 21sd are formed on both sides of the exposed surface of the nanosheet laminate 13 by epitaxial growth.

[0062] After the above, as shown in Figure 26, an insulating etching stopper layer 22 is formed on one main surface of the semiconductor substrate 10 so as to cover the cap layer 17, the sacrificial sidewall 18, and the source / drain 21sd.

[0063] Next, as shown in Figure 27, an embedded insulating film 23 is formed on the etching stopper layer 22 so as to embed the laminated structure St1, the sacrificial sidewall 18, the source / drain 21sd, and the etching stopper layer 22. The embedded insulating film 23 is made of, for example, silicon oxide.

[0064] Next, as shown in Figure 28, chemical mechanical polishing (CMP) is performed from above the embedded insulating film 23 to expose the dummy gate 15. As a result of this CMP, the dummy gate 15, sacrificial sidewall 18, etching stopper layer 22, and embedded insulating film 23 are exposed on the flattened polished surface.

[0065] Next, as shown in Figure 29, the linear dummy gate 15 and the insulating layer 14 below it (see Figure 28) are selectively removed, and then the sacrificial sheet layer 11 of the nanosheet laminate 13 (see Figure 28) is selectively removed. This exposes the central part of the silicon nanosheet layer 12 around its entire circumference.

[0066] Next, as shown in Figure 30, a gate insulating film 25 and a gate electrode 26g are formed to cover the entire circumference of the nanosheet layer 12, and the gate electrode 26g is filled with an insulating film 41. In this process, first the gate insulating film 25 and gate electrode 26g are formed, and then the gate insulating film 25 and gate electrode 26g are etched back to reduce the thickness of the gate insulating film 25 and gate electrode 26g above the uppermost nanosheet layer 12. After that, an insulating film 41 is deposited on one main surface of the semiconductor substrate 10 so as to fill the space between the sacrificial sidewalls 18, and the insulating film 41 is etched back so that the insulating film 41 remains only between the sacrificial sidewalls 18.

[0067] Next, as shown in Figure 31, the sacrificial sidewall 18 and etching stopper layer 22 (see Figure 30) between the gate electrode 26g and insulating film 41 and the embedded insulating film 23 and source / drain 21sd are selectively etched away. This exposes the portions where the liner layer 19 and sacrificial inner spacer 20 are laminated at both ends of the gate width direction (depth direction in the drawing) of the nanosheet laminate 13. In this state, the sacrificial inner spacer 20 is covered by the liner layer 19, so the liner layer 19 is then removed to expose the sacrificial inner spacer 20.

[0068] Next, as shown in Figure 32, the sacrificial inner spacers 20 (see Figure 31) are selectively etched away from the exposed side walls of the nanosheet laminate 13. This replaces the sacrificial inner spacers 20 with cavities Gp1, forming cavities Gp1 between the nanosheet layers 12 next to the sacrificial sheet layer 11. Each cavity Gp1 has a cylindrical shape surrounded by a source / drain 21sd and the sacrificial sheet layer 11 and nanosheet layer 12 via a liner layer 19.

[0069] Next, as shown in Figure 33, the cavity Gp1 is expanded toward the source / drain 21sd by selective etching of the source / drain 21sd. At this time, the source / drain 21sd located above the nanosheet laminate 13 also recedes outward beyond the nanosheet layer 12. This increases the distance [d1] between the sacrificial sheet layer 11 and the source / drain 21sd without reducing the overall width of the source / drain 21sd or the width of the sacrificial sheet layer 11.

[0070] Subsequently, as shown in Figure 25, the space between the embedded insulating film 23 and the insulating film 41 is sealed with the sealing insulating film 42. As a result, the upper part between the source / drain 21sd and the gate electrode 26g located above the nanosheet laminate 13 is sealed with the sealing insulating film 42, and a second cavity Gp2 is formed above the nanosheet laminate 13. Furthermore, the cavity Gp1 between the nanosheet layers 12 is also sealed with the sealing insulating film 42. Such a sealing insulating film 42 can be formed using, for example, SiN.

[0071] Furthermore, the sealing insulating film 42 extends below the embedded insulating film 23 towards the semiconductor substrate 10, overlapping with the source / drain 21sd and formed to cover the boundary between the source / drain 21sd and the embedded insulating film 23. This prevents the contact from being exposed into the second cavity Gp2 when a contact connected to the source / drain 21sd is formed in a subsequent process. Subsequently, the upper part between the source / drain and the gate electrode, located above the nanosheet laminate, is sealed with the sealing insulating film, forming a second cavity above the nanosheet laminate.

[0072] With the above steps completed, the all-around gate transistor 4a described earlier is finished.

[0073] <Effects of the Fourth Embodiment> According to the fourth embodiment described above, by replacing the inner spacer between the source / drain 21sd and the gate electrode 26g of the full-circumference gate transistor 4a with a cavity Gp1, replacing the insulating sidewall with a second cavity Gp2, and extending these cavities Gp1 and the second cavity Gp2 to the outside of the nanosheet layer 12, it becomes possible to reduce the parasitic capacitance between the source / drain 21sd and the gate electrode 26g of the full-circumference gate transistor 4a without changing the device design, similar to the first embodiment. Furthermore, by insulating the space between the source / drain 21sd and the gate electrode 26g with cavities Gp1 and the second cavity Gp2, it is possible to further reduce the parasitic capacitance.

[0074] 1, 2, 3, 4… Semiconductor device 1a, 2a, 3a, 4a… Full-circumference gate transistor 10… Semiconductor substrate 11… Sacrificial sheet layer 12… Nanosheet layer 13… Nanosheet laminate 14… Insulating layer 15… Dummy gate 16… Insulating layer 17… Cap layer 18… Sacrificial sidewall 19… Liner layer 20… Sacrificial inner spacer 21sd… Source / drain 22… Etching stopper layer 23… Embedded insulating film 24a, 24a', 24a''… Inner spacer 24b, 24b'… Sidewall 25… Gate insulating film 26g… Gate electrode 41… Insulating film 42… Sealing insulating film 201, 202… Low dielectric film 202… Low dielectric film Gp1… Cavity Gp2… Second cavity St1… Laminated structure

Claims

1. A semiconductor device comprising: a nanosheet laminate formed by stacking a plurality of nanosheet layers made of a semiconductor material on a substrate; a gate electrode covering the entire circumference of each nanosheet layer via a gate insulating film; source / drain provided on both sides of the nanosheet laminate and connected in common to the plurality of nanosheet layers; and inner spacers sandwiched between the nanosheet layers and between the nanosheet layers and the substrate between the gate electrode and the source / drain on both sides of the gate electrode, wherein the inner spacers extend outward beyond the nanosheet layers.

2. The semiconductor device according to claim 1, further comprising an insulating sidewall extending beyond the nanosheet layer between the gate electrode and the source / drain located above the nanosheet laminate.

3. The semiconductor device according to claim 2, wherein the inner spacer and the sidewall are made of the same material.

4. The semiconductor device according to claim 2, wherein the inner spacer and the sidewall are made of different materials.

5. The semiconductor device according to claim 1, wherein the inner spacer is sandwiched in the film thickness direction by an insulating liner layer.

6. The semiconductor device according to claim 1, wherein the inner spacer is thicker than the gate electrode and the gate insulating film in the portion sandwiched by the inner spacer.

7. The semiconductor device according to claim 1, further comprising an insulating sidewall extending beyond the nanosheet layer between the gate electrode and the source / drain located above the nanosheet laminate, wherein the sidewall is thicker than the gate electrode and the gate insulating film sandwiched by the sidewall.

8. The semiconductor device according to claim 1, wherein a cavity is provided as the inner spacer.

9. The semiconductor device according to claim 8, wherein a second cavity is provided between the gate electrode and the source / drain located above the nanosheet laminate, the upper part of which is sealed with a sealing insulating layer.

10. A method for manufacturing a semiconductor device, comprising the steps of: patterning a linear nanosheet laminate in an island shape on a substrate by etching from a linear dummy gate and a sacrificial sidewall covering the side wall of the dummy gate; sandwiching sacrificial inner spacers between the nanosheet layers and between the nanosheet layers and the substrate at both ends of the exposed surface of the island-shaped nanosheet laminate; forming sources / drains at both ends of the exposed surface of the island-shaped nanosheet laminate by epitaxial growth from the nanosheet layers; replacing the sacrificial inner spacers with cavities by selectively removing the sacrificial sidewalls and then selectively removing the sacrificial inner spacers; expanding the cavities outward beyond the spaces between the nanosheet layers by etching back the sources / drains; selectively removing the sacrificial sheet layers constituting the nanosheet laminate after removing the dummy gate to expose the entire circumference of each nanosheet laminate; and forming a gate electrode that covers the entire circumference of each nanosheet layer via a gate insulating film.

11. The method for manufacturing a semiconductor device according to claim 10, wherein in the step of forming the source / drain, the source / drain is epitaxially grown to a height that exceeds the height of the nanosheet laminate and overlaps with the dummy gate and the sacrificial sidewall, and in the step of expanding the cavity, the source / drain is etched back so that the source / drain located above the nanosheet laminate is also recessed to the outside of the nanosheet layer.

12. The method for manufacturing a semiconductor device according to claim 10, further comprising the step of forming an insulating inner spacer to fill the cavity after expanding the cavity and before exposing the entire circumference of each nanosheet laminate.

13. The method for manufacturing a semiconductor device according to claim 10, wherein in the step of sandwiching a sacrificial inner spacer between the nanosheet layers, the sacrificial inner spacer is sandwiched between the nanosheet layers via an insulating liner layer.

14. A method for manufacturing a semiconductor device according to claim 10, wherein after forming the source / drain, the entire circumference of each nanosheet laminate is exposed to form the gate electrode, and then the sacrificial inner spacer is replaced with a cavity, and the cavity is expanded.

15. The method for manufacturing a semiconductor device according to claim 14, wherein in the step of forming the source / drain, the source / drain is epitaxially grown to a height that exceeds the height of the nanosheet laminate and overlaps with the dummy gate and the sacrificial sidewall; in the step of expanding the cavity, the source / drain is etched back so that the source / drain located above the nanosheet laminate is also recessed to the outside of the nanosheet layer; and thereafter, the upper part between the source / drain located above the nanosheet laminate and the gate electrode is sealed with a sealing insulating film to form a second cavity above the nanosheet laminate.

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