SiC WAFER

Abstract

Provided is an SiC wafer with which it is possible to reduce the number of stacking faults on the entire surface of a wafer and suppress breaking and cracking of the wafer when the wafer is divided into a device-forming portion and a device-non-forming portion after a device is formed on the wafer (namely, the wafer exhibits good release properties). This SiC wafer comprises an SiC seed crystal layer and an SiC growth layer that includes an SiC single crystal grown from the SiC seed crystal layer. A release-promoting layer is formed in the inner part and / or on the surface of the SiC seed crystal layer and / or the SiC growth layer. The release-promoting layer has an absorption coefficient that is 1.2-99 times the absorption coefficient of portions other than the release-promoting layer of the SiC seed crystal layer for incident light having a target wavelength.

Description

SiC wafer

[0001] This disclosure relates to SiC wafers.

[0002] Silicon carbide (SiC) is attracting attention as a wide-bandgap material that can control high currents and high voltages with low loss. In particular, power semiconductor devices using SiC material (SiC power devices) have recently been expected to be used in a variety of applications because they are superior to those using Si semiconductors in terms of miniaturization, low power consumption, and high efficiency. For example, by adopting SiC power devices, converters, inverters, and on-board chargers for electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs) can be miniaturized and their efficiency improved.

[0003] Incidentally, Patent Document 1 (Japanese Patent Application Publication No. 2023-73458) discloses a method in which, after forming a device (for example, electrodes or wiring patterns) on the surface of a semiconductor wafer, a laser focused at a predetermined depth in the thickness direction of the semiconductor wafer is irradiated at regular intervals to form a modified layer in the planar direction within the semiconductor wafer, and the semiconductor wafer is divided into a device-formed portion and an unformed portion starting from this modified layer.

[0004] Japanese Patent Publication No. 2023-73458 WO2023 / 067736A1

[0005] However, with the method disclosed in Patent Document 1, if the formation of the modified layer within the semiconductor wafer is insufficient, there is a problem that cracks and fractures are likely to occur when the semiconductor wafer is divided into a device-formed portion and a non-device-formed portion. In response to this, it is conceivable to form a peel-promoting layer by implanting ions from the surface into the interior of a seed crystal as a pretreatment in semiconductor wafer manufacturing. This would allow the semiconductor wafer to be easily divided by irradiating the peel-promoting layer with a laser to form a modified layer during the subsequent semiconductor wafer manufacturing stage. On the other hand, the above ion implantation can generate defects on the surface of the seed crystal, leading to the problem of many stacking faults occurring in the growth layer on the seed crystal. Therefore, a SiC wafer is desired that has a low number of stacking faults across the entire wafer surface and that suppresses the occurrence of cracks and fractures when dividing the wafer into a device-formed portion and a non-device-formed portion after device formation (i.e., has good peelability).

[0006] The present inventors have now discovered that by forming a peel-promoting layer having an absorption coefficient 1.2 to 99 times that of the first crystal layer in a SiC wafer having a first crystal layer such as a SiC seed crystal layer and a second crystal layer such as a SiC growth layer, the number of stacking faults across the entire wafer can be reduced, and the occurrence of cracks and fractures in the wafer can be suppressed when dividing the wafer into a device-formed portion and an unformed portion after device formation (i.e., exhibiting good peelability).

[0007] Therefore, an object of the present invention is to provide a SiC wafer that reduces the number of stacking faults across the entire wafer surface and suppresses the occurrence of cracks and fractures in the wafer when it is divided into a device-formed portion and an unformed portion after device formation (i.e., exhibits good delamination properties).

[0008] The following embodiments are provided according to this disclosure: [Embodiment 1] A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peel-promoting layer is formed inside and / or on the surface of at least one of the first crystal layer and the second crystal layer, and the peel-promoting layer has an absorption coefficient of 1.2 to 99 times that of the portion of the first crystal layer other than the peel-promoting layer with respect to incident light of a target wavelength. [Embodiment 2] The SiC wafer according to Embodiment 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer. [Embodiment 3] The SiC wafer according to Embodiment 1 or 2, wherein the target wavelength is 500 to 600 nm or 1000 to 1100 nm. [Embodiment 4] The SiC wafer according to any one of Embodiments 1 to 3, wherein the peel-promoting layer is a SiC-derived layer containing a peel-promoting substance. [Aspect 5] The SiC wafer according to aspect 4, wherein the peeling-promoting substance is at least one ion selected from the group consisting of Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements. [Aspect 6] The SiC wafer according to aspect 5, wherein the peeling-promoting layer is a layer formed by implanting the ion into at least one of the first crystal layer and the second crystal layer. [Aspect 7] The peeling-promoting layer is formed by implanting the ion in doses of 1 × 10⁻¹⁶ １３ ~5 x 10 １６ ions / cm ２ A SiC wafer according to embodiment 6, having a portion that is [Embodiment 8] The second crystal layer is 5.00 × 10 １３ atoms / cm ３ A SiC wafer according to any one of embodiments 1 to 7, having a portion containing rare earth elements at the above concentrations.

[0009] This is a schematic cross-sectional view showing an example of a SiC wafer according to the present disclosure. This is a diagram showing an example of the overall system configuration according to the first embodiment of the present disclosure. This is an explanatory diagram of a pretreatment for forming a layer containing microvoids. This is an explanatory diagram of a pretreatment for forming a layer containing a peel-promoting substance. This is an explanatory diagram of a pretreatment for forming a layer containing another peel-promoting substance. This is a diagram showing an example of the appearance of the cut surface when a SiC wafer is cut along a plane passing through the peel-promoting layer. This is a diagram showing another schematic diagram showing the thermal etching process in a first example of the processing steps according to the second embodiment of the present disclosure. This is a schematic diagram showing the surface oxidation process in a second example of the processing steps according to the second embodiment of the present disclosure. This is a schematic diagram showing the plasma etching process in a third example of the processing steps according to the second embodiment of the present disclosure.

[0010] The SiC wafer of this disclosure comprises a first crystal layer containing a SiC single crystal and a second crystal layer containing a SiC single crystal formed on the first crystal layer. Therefore, the SiC wafer of this disclosure is mainly composed of a SiC single crystal and is usable as a SiC single crystal wafer. Here, the expression "mainly composed of a SiC single crystal" means that the main part of the SiC wafer other than the peeling accelerator layer is composed of a SiC single crystal (not a SiC polycrystalline layer), regardless of whether the SiC-derived peeling accelerator layer described later maintains the form of a SiC single crystal or not. Typically, the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing a SiC single crystal grown from the SiC seed crystal layer, and therefore the SiC wafer as a whole can be composed of one SiC single crystal (or at least mainly composed of a SiC single crystal). Therefore, the following explanation will be based on a SiC wafer in which the first crystal layer is a SiC seed crystal layer and the second crystal layer is a SiC growth layer.

[0011] Figure 1 conceptually shows a SiC wafer 10. The SiC wafer 10 comprises a SiC seed crystal layer 12 (first crystal layer) and a SiC growth layer 14 (second crystal layer) containing a SiC single crystal grown from the SiC seed crystal layer 12. A peel-promoting layer 16 is formed inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. The peel-promoting layer 16 has an absorption coefficient of 1.2 to 99 times that of the portion of the SiC seed crystal layer 12 (first crystal layer) other than the peel-promoting layer 16, with respect to incident light of a target wavelength. This makes it possible to provide a SiC wafer 10 that reduces the number of stacking faults across the entire wafer and suppresses the occurrence of cracks and fractures in the wafer when dividing it into a device-formed portion and an unformed portion after device formation (i.e., exhibits good peelability).

[0012] In other words, as described above, in the method disclosed in Patent Document 1, if the formation of the modified layer within the semiconductor wafer is insufficient, there is a problem that cracks and fractures are likely to occur when the semiconductor wafer is divided into a device-formed portion and a non-device-formed portion. In response to this, it is conceivable to form a peel-promoting layer by implanting ions from the surface into the interior of a seed crystal as a pretreatment in semiconductor wafer manufacturing. This would allow the semiconductor wafer to be easily divided by irradiating the peel-promoting layer with a laser to form a modified layer during the subsequent semiconductor wafer manufacturing stage. On the other hand, the above ion implantation can generate defects on the surface of the seed crystal, leading to the problem of many stacking faults occurring in the growth layer on the seed crystal. Therefore, a SiC wafer is desired that has a small number of stacking faults across the entire wafer surface and that suppresses the occurrence of cracks and fractures when dividing the wafer into a device-formed portion and a non-device-formed portion after device formation (i.e., has good peelability). This problem is successfully resolved according to the present invention.

[0013] The SiC wafer 10 preferably has a thickness of 500 μm or less, and more preferably 300 to 500 μm. The shape of the SiC wafer 10 is not particularly limited, but it is preferably disc-shaped (circular). In this specification, "circular shape" does not have to be a perfect circle, but may be a substantially circular shape that can be generally recognized as circular overall. For example, it may be a shape in which a part of the circle is cut out for the purpose of specifying the crystal orientation or for other purposes, or a shape in which a slit is provided in a part of the circle, in which case the size can be determined based on the diameter of the largest circle inscribed in the outer edge excluding the cut-out outer edge or the slit. The diameter of the SiC wafer 10 is not particularly limited, but may be 100 mm (4 inches) or more, 145 mm or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more.

[0014] The SiC seed crystal layer 12 is typically composed of a SiC single crystal and has a crystal growth surface. In this case, the polymorph (polytype), off-angle and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal, are not particularly limited, but the polymorph is preferably 4H, 6H, or 3C. Alternatively, a SiC single crystal deposited on a Si substrate may be used as the SiC seed crystal layer 12. The crystal growth surface on the SiC single crystal as the SiC seed crystal layer 12 may be either the Si surface or the C surface, or both the Si surface and the C surface, but it is preferably the Si surface. Therefore, it is preferable that the peel-promoting layer 116 is formed near this Si surface. The diameter of the SiC seed crystal layer 12 is not particularly limited, but it may be 100 mm (4 inches) or larger, 145 mm or larger, 150 mm (6 inches) or larger, or 200 mm (8 inches) or larger.

[0015] The SiC growth layer 14 contains SiC single crystals grown from the SiC seed crystal layer 12. The polymorph (polytype), off-angle and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal, are not particularly limited, but the polymorph is preferably 4H, 6H, or 3C.

[0016] Preferably, the SiC growth layer 14 contains a rare earth element. Examples of rare earth elements include Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, and combinations thereof. From the viewpoint of reducing fractures and cracks, the rare earth element is preferably Y and / or Ce. When the SiC growth layer 14 contains a rare earth element, the SiC growth layer 14 contains 5.00×10 １３ atoms / cm ３ It is preferable to have a portion containing the rare earth element at a concentration of or higher, more preferably 5.00×10 １３ to 8.00×10 １５ atoms / cm ３ , more preferably 3.00×10 １４ to 8.00×10 １５ atoms / cm ３ , particularly preferably 3.00×10 １４ to 3.20×10 １５ atoms / cm ３ .

[0017] The exfoliation accelerating layer 16 is formed inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. In other words, the SiC wafer 10 includes the exfoliation accelerating layer 16 inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. The exfoliation accelerating layer is a SiC-derived layer (for example, a SiC-based layer) for accelerating division of the SiC wafer 10 into an upper portion and a lower portion with the exfoliation accelerating layer 16 serving as a starting point or boundary, and is, for example, a layer in which the crystal structure of SiC is incomplete compared to other portions, or exfoliation or division is likely to occur due to other causes. FIG. 1 illustrates a configuration in which the exfoliation accelerating layer 16 is formed inside the SiC seed crystal layer 12. By forming the exfoliation accelerating layer 16 in the SiC wafer 10 as described above, the occurrence of fractures and cracks can be suppressed when the SiC wafer 10 is divided into a device-formed portion and a device-unformed portion after a device is formed on the SiC wafer 10.

[0018] The peel-accelerating layer 16 has an absorption coefficient of 1.2 to 99 times that of the portion of the SiC seed crystal layer 12 other than the peel-accelerating layer 16, with respect to incident light of the target wavelength. Typically, the absorption coefficient of the peel-accelerating layer 16 is 20 to 99 times that of the portion of the SiC seed crystal layer 12 other than the peel-accelerating layer 16, and more typically, it is 50 to 99 times. In this way, by having a predetermined difference in absorption coefficients between the peel-accelerating layer 16 and the SiC seed crystal layer 12, it is possible to reduce the number of stacking faults across the entire wafer while ensuring good peelability after device formation on the SiC wafer 10.

[0019] Here, the incident light of the target wavelength refers to light of a specific wavelength incident from the SiC seed crystal layer 12 side of the SiC wafer 10 toward the peeling acceleration layer 16. The target wavelength (specific wavelength) is preferably 495 to 635 nm or 995 to 1110 nm, more preferably 500 to 600 nm or 1000 to 1100 nm, and even more preferably 532 to 546 nm or 1030 to 1040 nm. By scanning light of such a wavelength in the in-plane direction of the SiC wafer 10, the SiC seed crystal layer 12 can be easily peeled from the SiC wafer 10 along the peeling acceleration layer 16.

[0020] Examples of incident light include pulsed laser light and CW (Continuous Wave) lasers. When using pulsed laser light as the incident light, the pulse width is preferably 1 ps to 10 ns.

[0021] The method for calculating the absorption coefficient of the peeling acceleration layer 16 and the absorption coefficient of the SiC seed crystal layer 12 is not particularly limited, but for example, it can be calculated as follows. First, the SiC growth layer 14 is removed from the SiC wafer 10 (the device layer is also removed if a device layer is formed), and the thickness d of the composite layer of the SiC seed crystal layer 12 and the peeling acceleration layer 16 is calculated. ３ The thickness (μm) is measured. Light from a light source is incident on this composite layer from the SiC seed crystal layer 12 side using an ultraviolet-visible-near-infrared spectrophotometer. The light that passes through the composite layer is received by a detector installed on the peel-promoting layer 16 side and the total transmittance (%) is measured. After that, the thickness d from the composite layer is measured further. ２The peel-promoting layer 16 (μm) is removed, and the thickness is d １ For the SiC seed crystal layer 12 which has a thickness of (μm), the total transmittance (%) is measured using the same method as above. Next, of the measured total transmittance (%), the thickness d for light of the target wavelength is measured. １ Transmittance T of SiC seed crystal layer 12 of (μm) １ (%), and thickness d ３ Transmittance T of the composite layer of the SiC seed crystal layer 12 and the peel-promoting layer 16, which is (μm) in size. ３ Calculate the percentage (%). Then, use the following formula (1): A １ = (-logT) １ ) / d １ Based on (1), the absorption coefficient A in the SiC species crystal layer 12 １ While seeking the following equation (2): A ２ = (logT １ -logT ３ ) / d ２ Based on (2), the absorption coefficient A in the peel-promoting layer 16 ２ This calculates the absorption coefficient A of the peel-promoting layer 16. ２ and the absorption coefficient A of the SiC species crystal layer 12 １ The absorption coefficient ratio A can be calculated. ２ / A １ By calculating the absorption coefficient A of the peel-promoting layer 16, ２ The absorption coefficient A of the portion of the SiC crystal layer 12 other than the peeling promotion layer 16. １ It is possible to determine how many times it is greater than or equal to.

[0022] The peel-promoting layer 16 is preferably a layer formed by implanting ion I into at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. This ion I corresponds to a peel-promoting substance. Therefore, the peel-promoting layer 16 is preferably a SiC-derived layer containing a peel-promoting substance. Based on the above, a "SiC-derived layer" typically means a layer formed by somehow modifying the SiC crystal (especially a SiC single crystal) constituting the SiC seed crystal layer 12 and / or the SiC growth layer 14 (for example, a SiC-based layer), and can be a layer in which the SiC crystal has been modified. The peel-promoting substance is preferably an ion of Si, C, Al, B, P, N, O, H, a noble gas element, a rare earth element, or a combination thereof, and more preferably an ion of C, B, P, H, a noble gas element, or a combination thereof.

[0023] The injection conditions for ion I are as follows: injection dose is 1 × 10⁻⁶ １３ ~5 x 10 １６ ions / cm ２ This is typical, and more typically, 1 × 10⁻⁶. １３ ~3 x 10 １６ ions / cm ２ Furthermore, typically 1 × 10 １３ ~1 x 10 １６ ions / cm ２ Therefore, the peel-promoting layer 16 has an injection dose of ion I of 1 × 10⁻⁶. １３ ~5 x 10 １６ ions / cm ２ It typically has a portion that is 1 × 10⁻⁶, and more typically it is 1 × 10⁻⁶. １３ ~3 x 10 １６ ions / cm ２ It has a portion that is 1 × 10 １３ ~1 x 10 １６ ions / cm ２ It has a portion that is such. In this case, "injection dose" means the number of ions per unit area in the peel-promoting layer 16. Furthermore, as conditions for implanting ions I, the acceleration voltage is preferably 70 to 600 keV. The temperature during implantation of ions I is preferably room temperature to 800°C.

[0024] As described above, this disclosure provides a SiC wafer 10 that reduces the number of stacking faults across the entire wafer surface and suppresses the occurrence of cracks and fractures in the wafer when it is divided into a device-formed portion and an unformed portion after device formation (i.e., exhibits good delamination properties). The first and second embodiments of a system or process for manufacturing such a SiC wafer 10 will be described below. The descriptions of the first and second embodiments apply to the SiC wafer 10 described above insofar as they do not contradict the present invention, but the present invention is not limited to them. Therefore, in the following description, the SiC wafer 40, the pre-treated seed crystal 114, the grown SiC crystal 115, and the delamination-promoting layer 116 can correspond to the SiC wafer 10, the SiC seed crystal layer 12, the SiC growth layer 14, and the delamination-promoting layer 16 described above, respectively.

[0025] In the descriptions of the first and second embodiments, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the embodiments in order to make the explanation clearer. However, these are merely examples and do not limit the interpretation of this disclosure.

[0026] In the descriptions of the first and second embodiments, the semiconductor wafer is a SiC (silicon carbide) wafer, but the method can also be applied to semiconductor wafers other than SiC wafers. Examples of semiconductor wafers other than SiC wafers include GaN (gallium nitride) wafers, AlN (aluminum nitride) wafers, or diamond wafers.

[0027] [First Embodiment] Figure 2 shows an example of the overall system configuration according to the first embodiment of this disclosure.

[0028] In the second entity, a surface device step and a wafer splitting step are performed. The second entity may be a company acting as a device manufacturer that extracts SiC chips from the SiC wafer 40 and provides SiC chips or devices having SiC chips. The SiC wafer 40 is broadly divided into a layer as a base SiC crystal and a layer as a grown SiC crystal (oriented SiC crystal).

[0029] In the surface device step, a device is formed on the first main surface (surface) of the SiC wafer 40 (corresponding to the surface of the SiC wafer 10 on the SiC growth layer 14 side). The device may include electrodes and wiring patterns.

[0030] In the wafer splitting step, the SiC wafer 40 having the device is split along the planar direction (a direction perpendicular to the thickness direction, in other words, a direction parallel to the first main surface). In this wafer splitting step, the SiC wafer 40 is split in the planar direction by a method called laser slicing using a laser device, for example. Specifically, for example, the laser device irradiates a peel-promoting layer 116 that has been formed in advance inside the SiC wafer 40 from the second main surface (back side) side of the SiC wafer 40 (corresponding to the surface of the SiC seed crystal layer 12 of the SiC wafer 10). As a result, a modified layer is formed in the peel-promoting layer 116, and starting from this modified layer, the SiC wafer 40 is split into a main wafer portion 111, which is the SiC wafer portion having the first main surface, and a remaining wafer portion 112, which is the SiC wafer portion having the second main surface.

[0031] In laser slicing, the peel-accelerating layer 116 within the SiC wafer 40 irradiated with laser light is a layer that is more prone to peeling due to an incomplete SiC crystal structure compared to other parts, or for other reasons. By irradiating this peel-accelerating layer 116 with laser light to create a modified layer, and then dividing the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 along the peel-accelerating layer 116, the division (peeling) can be performed more easily than when other parts are used as the modified layer. Possible reasons for this include, for example, the peel-accelerating layer 116 having an incomplete crystal structure compared to other parts and having weaker interatomic bonding forces. It is also possible that the peel-accelerating layer 116 readily absorbs laser light, thus facilitating the formation of a modified layer. Various other factors may also be considered, but in any case, by peeling off the portion including the first main surface from the SiC wafer 40 starting from the peel-accelerating layer 116, the SiC wafer 40 can be divided into a main wafer 111 and a remaining wafer 112 with less force. This makes it possible to suppress the generation of distortion during peeling in the device formation portion of the main wafer 111, thereby preventing the occurrence of cracks and fractures.

[0032] The peel-promoting layer 116 is formed within the SiC wafer 40 when the SiC wafer 40 is manufactured in a first entity different from the second entity. This method will be described later.

[0033] In addition, during the wafer splitting step, the SiC wafer 40 may be split into the main wafer 111 and the remaining wafer 112 by a method other than laser slicing. For example, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 by etching away the peeling acceleration layer 116 on the SiC wafer 40. In this case, electrolytic etching, chemical etching, thermal etching, etc., can be used for etching. By performing the wafer splitting step by etching in this way, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 without using a laser device. Furthermore, peeling can also be performed using ultrasound, known as sonic lift-off. Specifically, by using sound waves to split the SiC wafer 40 into the main wafer 111 and the remaining wafer 112, the peeled surfaces of the main wafer 111 and the remaining wafer 112 can be made flat and smooth, thus eliminating material waste and allowing the remaining wafer 112 to be reused, thereby reducing wafer manufacturing costs. In addition to the above, it is possible to divide the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 by processing the peeling-promoting layer 116 formed in the SiC wafer 40 using any method.

[0034] In the first entity, the acquisition step, processing step, pre-processing step, growth step, and wafer provision step are performed (in this embodiment, an inspection step is also performed between the acquisition step and the processing step, as will be described later). The first entity is a company that provides a new service, that is, a company that acquires (recovers) the remaining wafer 112 of the SiC wafer 40 from the second entity, grows a grown SiC crystal on the remaining wafer 112 to regenerate the SiC wafer 40, and provides the regenerated SiC wafer 40 to the same or a different second entity. There is one or more second entities for each first entity. Note that the wafer splitting step described above may be performed in the first entity instead of the second entity.

[0035] In the acquisition step, the remaining wafer 112 is acquired from the second entity. In the processing step, the slice surface of the remaining wafer 112 is processed to acquire a seed crystal 113a made of SiC single crystal material.

[0036] In the pretreatment step, an inhibitory region is formed on or near the surface of the seed crystal 113a obtained in the processing step, or a seed crystal 113b made of newly prepared SiC single crystal material, which partially disrupts or inhibits the SiC crystal structure. This pretreatment is performed on the seed crystals 113a and 113b to form the aforementioned peeling-promoting layer 116, and a pretreated seed crystal 114 is obtained. Details of the pretreatment step will be described later.

[0037] In the growth step, a new SiC wafer 40 is manufactured by growing a growth SiC crystal (an example of a semiconductor crystal layer) 115 on the surface of the seed crystal 114 obtained in the pretreatment step. Inside the SiC wafer 40 manufactured here, a peeling-promoting layer 116 is formed by the inhibiting region formed on the seed crystal 114 in the pretreatment step.

[0038] In the wafer supply step, the SiC wafer 40 obtained in the growth step is provided to a second entity that is the same as or different from the source from which the remaining wafer 112 was obtained.

[0039] In conventional processes not to which this disclosure applies, the portion of the SiC wafer 40 corresponding to the remaining wafer 112 is ground without separating it from the main wafer 111, and the resulting grinding waste is discarded. In contrast, in this embodiment, the remaining wafer 112 is separated from the main wafer 111 and recovered without being discarded as grinding waste, and this is recycled into a new semiconductor wafer by the first entity and provided to the second entity. The second entity forms a device on the semiconductor wafer provided by the first entity (SiC wafer 40 recycled from the remaining wafer 112), and then separates it into the main wafer 111 and the remaining wafer 112. The remaining wafer 112 is recovered by the first entity and used as a seed crystal 114 to form a grown SiC crystal together with the peeling accelerator layer 116, and is then used again as SiC wafer 40. By repeating this process, the portion of the SiC wafer 40 that was conventionally ground or discarded, namely the remaining wafer 112, can be reused. In this disclosure, the reuse of expensive SiC wafers is made possible, thereby reducing the manufacturing cost of devices. Furthermore, since waste can be significantly reduced throughout the entire SiC wafer manufacturing process, including high-temperature processes, it is also possible to reduce the environmental impact.

[0040] The processing step may be performed by the processing device 172, the pretreatment step may be performed by the pretreatment device 173, and the growth step may be performed by the growth device 174 (the inspection step described later may be performed by the inspection device 171).

[0041] Below, we will first describe the acquisition step, processing step, pretreatment step, growth step, and wafer supply step among the steps in the first entity, and then describe the inspection step.

[0042] <Acquisition Step> In the acquisition step, the remaining wafers 112 are acquired from one or more second entities. Any number of remaining wafers 112 may be sent to the first entity at any time the second entity has chosen, or an acquisition schedule, including the number of remaining wafers 112 to be acquired from each of the one or more second entities and the acquisition timing, may be shared between the second entity and the first entity, and the remaining wafers 112 may be acquired from the second entity according to the acquisition schedule. Note that if the wafer splitting step is performed by the first entity, the acquisition step is unnecessary.

[0043] <Processing Step> The processing in the processing step includes removing the slice surface (typically grinding and / or polishing) and removing the processed altered layer including the removed slice surface. The processing apparatus 172 may include, for example, an apparatus for grinding and / or polishing the slice surface (e.g., a grinder) and an apparatus for removing the processed altered layer, and these apparatuses may be a single apparatus (i.e., grinding and removal may be performed by one apparatus). For example, the processing apparatus 172 may be an apparatus for grinding and polishing such as the CMP (Chemical Mechanical Polishing) method.

[0044] In the processing step, a seed crystal 113a is obtained as a result of processing the remaining wafer 112. The seed crystal 113a may be composed mainly of the underlying SiC crystal, or it may be composed of the underlying SiC crystal and some oriented SiC crystal. Alternatively, instead of the seed crystal 113a, a new SiC single crystal material may be prepared and used as the seed crystal 113b.

[0045] <Pre-treatment step> In the pre-treatment apparatus 173, inhibition regions are formed on or near the surface of the seed crystals 113a and 113b, which partially disrupt or inhibit the formation of the crystal structure when growing the SiC crystal in the next growth step. Due to the presence of these inhibition regions, a peel-promoting layer 116, which is easier to peel off than other parts, is formed inside the SiC wafer 40 manufactured from the seed crystals 113a and 113b in the growth step. Specifically, for example, the pre-treatment apparatus 173 forms inhibition regions on the seed crystals 113a and 113b by performing one of the processing treatments described in Figures 3 to 5 below as a pre-treatment.

[0046] Figure 3 is an explanatory diagram of the pretreatment for forming a layer containing minute voids as a peel-promoting layer 116. In Figure 3, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0047] In the pretreatment step, for example as shown in Figure 3(b), pulsed laser light from a laser 201, which is a pretreatment device 173, is irradiated onto the surface of the seed crystal 113a at regular intervals in a grid pattern, thereby forming grooves 202 on the surface of the seed crystal 113a by laser processing. In the subsequent growth step, the seed crystal 113a with these grooves 202 formed on it is used as a pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form a grown SiC crystal 115. As a result, for example as shown in Figure 3(c), voids formed by the grooves 202 occur at regular intervals between the seed crystal 114 and the grown SiC crystal 115, and because the crystal structure is partially divided by these voids, a peel-promoting layer 116 is formed along the voids as a layer that is easily peeled off. In this way, a SiC wafer 40 having a peel-promoting layer 116 between the first main surface 40a on the front side (grown SiC crystal 115 side) and the second main surface 40b on the back side (seed crystal 114 side) is manufactured.

[0048] Furthermore, it is preferable that the grooves 202 formed on the surface of the seed crystal 113a in the pretreatment step have a maximum depth of 1 μm or more. In this way, it is possible to form a peel-promoting layer 116 in the region including the grooves 202 while sufficiently growing the SiC crystal in the growth step.

[0049] Figure 4 is an explanatory diagram of the pretreatment for forming a layer containing a substance for promoting peeling (hereinafter referred to as "peeling-promoting substance") as a peeling-promoting layer 116. In Figure 4, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a cross-sectional enlargement view.

[0050] In the pretreatment step, for example as shown in Figure 4(b), fine particles 211 mainly composed of carbon are dispersed on the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the dispersed fine particles 211 on its surface is used as the pretreated seed crystal 114, and a SiC crystal is grown on its surface (for example, to a thickness of 50 μm or more) to form a grown SiC crystal 115. As a result, for example as shown in Figure 4(c), fine particles 211 are sandwiched in places between the seed crystal 114 and the grown SiC crystal 115, and because the formation of the crystal structure is inhibited by these fine particles 211, a peel-promoting layer 116 is formed as a layer with an incomplete crystal structure. In this way, a SiC wafer 40 having a peel-promoting layer 116 between the first main surface 40a on the front side (the side with the grown SiC crystal 115) and the second main surface 40b on the back side (the side with the seed crystal 114) is manufactured.

[0051] Furthermore, the carbon-based fine particles 211 dispersed on the surface of the seed crystal 113a in the pretreatment step are preferably graphite or diamond fine particles with a particle size of 10 μm or less. In this way, it is possible to sufficiently grow the SiC crystal in the growth step while forming the peel-promoting layer 116 in the region containing the fine particles 211.

[0052] Figure 5 is an explanatory diagram of the pretreatment for forming a layer containing a different peel-promoting substance as the peel-promoting layer 116, which is different from the one in Figure 4. In Figure 5, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0053] In the pretreatment step, ions 221 are injected into the seed crystal 113a from the surface, as shown in Figure 5(b). Specifically, ions 221 generated by an ion source are accelerated and injected from the outside toward the surface of the seed crystal 113a, thereby injecting and dispersing the ions 221 near the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the ions 221 dispersed inside is used as the pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form the grown SiC crystal 115. As a result, as shown in Figure 5(c), ions 221 are placed in various places near the boundary between the seed crystal 114 and the grown SiC crystal 115, and the formation of the crystal structure is inhibited by these ions 221, resulting in the formation of a peel-promoting layer 116 with an incomplete crystal structure. In this way, a SiC wafer 40 having a peel-promoting layer 116 between the first main surface 40a on the front side (the side with the growing SiC crystal 115) and the second main surface 40b on the back side (the side with the seed crystal 114) is manufactured. In the subsequent wafer splitting step, if the peel-promoting layer 116 in the SiC wafer 40 is removed by etching as described above, it is preferable to form the peel-promoting layer 116 using the method described in Figure 5.

[0054] Furthermore, it is preferable to use one or more ions from among Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements as the ions 221 implanted into the seed crystal 113a in the pretreatment step. In this way, it is possible to sufficiently grow the SiC crystal in the growth step while forming the peeling-promoting layer 116 in the region containing the ions 221.

[0055] In the pretreatment step, seed crystal 114 is obtained by performing one of the pretreatments described above on seed crystals 113a and 113b using the pretreatment apparatus 173. Although Figures 3 to 5 illustrate an example of performing pretreatment on seed crystal 113a obtained in the processing step, the same pretreatment can be performed on a newly prepared seed crystal 113b to obtain seed crystal 114.

[0056] <Growth Step> In the growth apparatus 174, a grown SiC crystal (oriented SiC crystal) 115 is grown on the seed crystal 114 to a thickness of 50 μm or more. Such crystal growth may be carried out by sublimation or CVD (Chemical Vapor Deposition), or by other methods. As a result, as explained in Figures 3 to 5, a new SiC wafer 40 is obtained, which consists of a seed crystal 114, which is a crystalline layer made of a single-crystal material of SiC, and a grown SiC crystal 115, which is a crystalline layer of SiC formed on the seed crystal 114, and has a peel-promoting layer 116 between the first main surface 40a on the grown SiC crystal 115 side and the second main surface 40b on the seed crystal 114 side. In this SiC wafer 40, the peel-promoting layer 116 formed on at least one of the seed crystal 114 and the grown SiC crystal 115 contains voids due to grooves 202 or contains an incomplete crystalline structure due to fine particles 211 or ions 221.

[0057] Furthermore, as illustrated in Figure 4(c), the peeling acceleration layer 116 is preferably formed within a range of 10 μm or less in the thickness direction (up and down direction in the figure) perpendicular to the first main surface 40a and the second main surface 40b. Specifically, when observing a cross-section of the SiC wafer 40 in the thickness direction at any position including the peeling acceleration layer 116, it is preferable that the thickness of the peeling acceleration layer 116 in that cross-section is 10 μm or less. In this way, the thickness of the peeling acceleration layer 116 can be made thinner than the height of the unevenness of the slice surface that occurs when a conventional SiC wafer without a peeling acceleration layer 116 is divided by laser slicing (generally about 20 to 50 μm), thereby reducing the amount of grinding debris generated in the processing step and reducing the amount of SiC waste. The peeling acceleration layer 116 is a part of the seed crystal 114 or the grown SiC crystal 115, as shown in Figures 3 to 5.

[0058] Furthermore, in the peel-promoting layer 116, as illustrated in Figure 4(c), it is preferable that peel-promoting substances consisting of voids formed by grooves 202, fine particles 211, or ions 221 are distributed at intervals of 200 μm or less and over a range of at least 500 μm in the planar direction parallel to the first main surface 40a and the second main surface 40b (left-right direction in the figure). In this way, when the first entity divides the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 in the wafer splitting step, it is possible to form a peel-promoting layer 116 that can be easily peeled off with little force.

[0059] Figures 6A to 6C show examples of cross-sections of the SiC wafer 40 shown in Figure 3(c) when it is cut along a plane parallel to the first main surface 40a and passing through at least a portion of the peel-accelerating layer 116. Figure 6A shows an example of a cross-section when the peel-accelerating layer 116 is formed over the entire surface in the planar direction at a predetermined depth within the SiC wafer 40. Figure 6B shows an example of a cross-section when the peel-accelerating layer 116 is formed over the entire circumference of the region near the outer periphery within the SiC wafer 40. Figure 6C shows an example of a cross-section when the peel-accelerating layer 116 is partially formed in the region near the outer periphery within the SiC wafer 40. Note that the peel-accelerating layer 116 may be formed in arrangements other than those shown.

[0060] As shown in the examples above, the peel-promoting layer 116 may be formed over the entire surface in the planar direction when the SiC wafer 40 is viewed from the direction of the first main surface 40a, or it may be formed only in a part of the surface. As long as the peel-promoting layer 116 is distributed over a certain range in the planar direction, for example, a range of 500 μm or more, the peel-promoting layer 116 can be formed in any region within the SiC wafer 40.

[0061] <Wafer Provision Step> A new SiC wafer 40, composed of a seed crystal 114 and a grown SiC crystal 115, is provided to a second entity that is the same as or different from the source from which the remaining wafer that forms the basis of the SiC wafer was obtained. In this way, the acquired remaining wafer 112 is regenerated into such a new SiC wafer 40 and provided to the second entity, so the second entity can obtain a main wafer from that SiC wafer 40.

[0062] The above describes the acquisition step, processing step, pretreatment step, growth step, and wafer supply step.

[0063] In this embodiment, an inspection step is included between the acquisition step and the processing step to inspect the slice surface of the acquired remaining wafer 112. The inspection step is, for example, as follows:

[0064] <Inspection Step> The inspection step includes measuring at least one of the following: the height difference of the slice surface and the thickness of the processed altered layer having the slice surface. In this embodiment, both are measured. The height difference of the slice surface is the height difference caused by the surface irregularities resulting from the laser irradiation or the separation of the main wafer 111 and the remaining wafer 112 in the wafer splitting step.

[0065] The inspection step is performed by the inspection device 171. The inspection device 171 may include a laser microscope and a Raman spectrometer. The height difference of the slice surface may be measured using the laser microscope. The thickness of the processed altered layer may be measured using the Raman spectrometer. The measurement methods for both the height difference of the slice surface and the thickness of the processed altered layer are not limited to this example. For example, the height difference of the slice surface may be measured using a white light interferometer or a contact-type shape measuring instrument.

[0066] At least one of the following (x) and (y) may be performed. (x) The processing in the processing step includes determining the amount to remove from the slice surface based on at least one of the measured height difference of the slice surface of the acquired remaining wafer 112 and the measured thickness of the processed altered layer, and removing material from the slice surface according to the determined amount. This allows for appropriate (with minimal excess or deficiency) slicing of the slice surface according to the quality (condition) of the acquired remaining wafer 112. For example, if the PV value (maximum valley depth) is measured as an example of the height difference of the slice surface, and the processing altered layer depth is measured as an example of the thickness of the processed altered layer, then the amount to remove = PV value + (processed altered layer depth × N). N may be any value greater than 0 (for example, any natural number). A processing command associated with information representing the amount to remove may be input to the processing device 172 (or the control device of the processing device 172), and the processing device 172 may perform slicing according to that amount. The "amount of material removed" may be defined by parameter values ​​for each of one or more parameter items. Examples of parameter items include the processing time and processing power (e.g., temperature and pressure) of the processing apparatus 172. (y) In the growth step, the thickness of the growing SiC crystal to be grown is determined based on at least one of the measured height difference of the slice surface of the remaining wafer 112 and the measured thickness of the processed altered layer, and the growing SiC crystal is grown to the determined thickness. This allows for appropriate (with minimal excess or deficiency) crystal growth according to the quality (condition) of the acquired remaining wafer 112. For example, the thickness to be grown may be determined based on at least one of X, Y, Z, and α. Specifically, for example, the thickness to be grown may be X - Y + Z + α. X may be the thickness required at the start of the surface device step or wafer splitting step in the second entity (the thickness requested by the second entity). Y may be the thickness of the growing SiC crystal when received by the first entity. Z can be the amount of material removed as determined in (x) above. α can be any value determined as the machining margin (for example, about 50 μm) to remove the irregularities after growth and flatten the surface.A crystal growth command, associated with information indicating the thickness to be grown, may be input to the growth apparatus 174 (or the control device for the growth apparatus 174), thereby causing the growth apparatus 174 to grow a SiC crystal of that thickness on the seed crystal.

[0067] [Second Embodiment] The second embodiment will now be described. In this description, the differences from the first embodiment will be explained, and the similarities with the first embodiment will be omitted or simplified.

[0068] In the second embodiment, crystal growth in the growth step is carried out using the method disclosed in the prior application Patent Document 2 (WO2023 / 067736A1) by the same applicant as the present application (hereinafter, this method will be conveniently referred to as the "NGK method" based on the applicant's notation). That is, in the growth step, a SiC single crystal as a seed crystal and a SiC powder layer are placed in a container in contact with each other, and the container is placed in a firing furnace and heat treatment is performed, thereby growing a SiC single crystal on the seed crystal. According to the NGK method, it is possible to obtain a SiC single crystal (grown SiC crystal) with a lower BPD density than the sublimation method and a BPD density of about the same as that of the CVD method. The second embodiment can utilize all or part of the technology disclosed in Patent Document 2.

[0069] Furthermore, when crystal growth is performed using the NGK method, the flatness of the processed surface does not need to be as high as when crystal growth is performed using the sublimation or CVD methods, and the processed surface does not need to be perfectly flat. Specifically, for example, the following applies:

[0070] When homoepitaxial growth is performed on a seed crystal using sublimation or CVD, it is usually essential that the growth surface is atomically flat and that there is no processed or altered layer. This is because irregularities can form on the epitaxial growth surface, or defects such as dislocations can be introduced into the crystal.

[0071] On the other hand, because SiC wafers are hard and stable against heat and chemicals, surface planarization and removal of processing damage using the CMP method after slicing or grinding is extremely time-consuming, and the consumption of polishing slurry and polishing pads is also high.

[0072] Therefore, in this embodiment, in the processing step, the removal of the processed altered layer is performed by a thermal etching process, a surface oxidation process, or a plasma etching process (i.e., any process that results in a lower degree of flatness after etching than etching by the CMP method). Below, examples of each process for removing the processed altered layer in the processing step of the second embodiment will be described. In this embodiment, etching other than the thermal etching process, surface oxidation process, and plasma etching process, such as etching by the CMP method, or etching by other etching processes (e.g., hydrogen etching) may be performed.

[0073] Figure 7 schematically illustrates the thermal etching process.

[0074] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a thermal etching process. This apparatus is illustrated in Figure 7. In the thermal etching process, the surface of the remaining wafer (including the processed altered layer) that has been heated and processed in the electric furnace 302 is sublimated to a thickness of several micrometers.

[0075] For example, gas (such as nitrogen or argon, an inert gas) is introduced into an electric furnace 302, which is made of insulating material and equipped with a heater 301, through a gas pipe 305, creating an inert gas atmosphere inside the electric furnace 302. The electric furnace 302 may also be under vacuum.

[0076] The material is heated by heater 301, but the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 1000 to 2000°C), and may be set taking into account the required amount of etching (for example, 1800°C may be set). The holding time at the maximum temperature is a time within a certain time range (for example, 1 minute to 5 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0077] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 303 (for example, graphite) on a spacer 304 (for example, graphite), or it may be placed using a sheath or the like made of a heat-resistant material.

[0078] If the surface of the remaining wafer 112 is carbonized after this thermal etching process, the carbonized layer on the surface may be removed by annealing in an atmospheric furnace or the like, or by polishing or other processing. To prevent surface carbonization, a carbon getter material such as Ta may be placed inside the electric furnace 302.

[0079] Figure 8 schematically illustrates the surface oxidation process.

[0080] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a surface oxidation process. This apparatus is illustrated in Figure 8. In the surface oxidation process, the surface of the remaining wafer (including the processed altered layer) that has been heated in an oxidizing atmosphere (including an air atmosphere) in an electric furnace 402 is oxidized to a thickness of several micrometers. The oxide film may be removed by processing such as polishing, or it may be volatilized or melted (reacted with the raw material powder) during crystal growth.

[0081] For example, in an electric furnace 402 made of insulating material and equipped with a heater 401, the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 800 to 2000°C), and may be set taking into account the required amount of etching (for example, 1400°C may be set). Also, the holding time at the maximum temperature is a time within a certain time range (for example, 5 minutes to 50 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0082] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 403 (for example, alumina) on a spacer 404 (for example, alumina).

[0083] Figure 9 schematically illustrates the plasma etching process.

[0084] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a plasma etching process. This apparatus is an example of the apparatus shown in Figure 9. In the plasma etching process, the surface of the remaining processed wafer (including the processed altered layer) is etched to a thickness of several micrometers.

[0085] Plasma etching includes methods such as RIE (Reactive Ion Etching), ECR (Electron Cyclotron Resonance), ICP (Inductively Coupled Plasma), and CCP (Capacitively Coupled Plasma), but there are no particular limitations; for example, RIE can be applied.

[0086] The substrate temperature, gas type, processing time, and apparatus configuration may be set as appropriate depending on the desired etching rate and surface condition. The remaining wafer surface may be pre-treated by ashing or other methods to remove any surface deposits.

[0087] An upper electrode 501 and a lower electrode 503 are located in the chamber 502. Gas is introduced from the gas introduction pipe 505 and exhausted from the gas exhaust pipe 504, and plasma is generated between electrodes 501 and 503 by the high-frequency power supply 509s.

[0088] The above is an explanation of examples of each process related to the removal of the processed altered layer in the processing step according to the second embodiment. Furthermore, there are differences between the sublimation method, CVD method and the NGK method regarding crystal growth, for example, as follows.

[0089] In other words, while sublimation and CVD methods require precise cleaning after CMP polishing and before epitaxial layer formation, the NGK method does not require such cleaning.

[0090] Furthermore, in sublimation and CVD methods, the rapid heating rate increases the likelihood of seed crystal warping and subsequent breakage. Also, in sublimation and CVD methods, multiple seed crystals can be placed in the growth chamber, but if even one seed crystal is damaged, it will affect the others. On the other hand, in the NGK method, the heating rate is slower than in sublimation and CVD methods, so even if the seed crystal is slightly warped, the likelihood of breakage due to that warping is low. In addition, in the NGK method, one seed crystal is stored in each container, so even if one seed crystal is damaged, it will not affect the others.

[0091] Furthermore, in both the second and first embodiments, the diameter of the remaining wafer 112 acquired in the acquisition step may be 6 inches or more, and for example, the diameter of the remaining wafer may be 8 inches or more (for example, in the second embodiment). For example, in both cases where the diameter is 6 inches or 8 inches, the thickness of the main wafer 111 may be about 100 μm, but in the case of a 6-inch diameter, the thickness of the remaining wafer 112 may be about 250 μm, and in the case of an 8-inch diameter, the thickness of the remaining wafer 112 may be about 400 μm.

[0092] The present invention will be further described in detail by the following examples. However, the present invention is not limited to the following examples.

[0093] Example 1 (Comparison) (1) Pretreatment As shown in Figure 5(a), a commercially available disc-shaped SiC single crystal substrate (4H-SiC, diameter 150 mm (6 inches), off-angle 4°, thickness 0.35 mm) was prepared as the seed crystal 113a. As shown in Figure 5(b), hydrogen ions (corresponding to the peeling accelerating substance) were implanted as ions 221 into the SiC single crystal substrate in order to form the peeling accelerating layer 116 described later. The conditions for implanting hydrogen ions at this time were: the depth of ion implantation was 1 μm in the thickness direction from the surface of the SiC single crystal substrate, the acceleration voltage was 170 keV, and the implantation dose was 9 × 10⁻⁶ １２ ions / cm ２ , and the temperature was 500°C.

[0094] (2) Preparation of SiC mixed powder Commercially available β-SiC powder (volume basis D50 particle size: 65.0 μm) and an oxide (Y) which is a liquid phase formation aid ２ O ３The oxides (D50 particle size based on volume: 5.0 μm) were weighed so that the oxide content relative to the SiC powder content was 1.1% by weight, and then placed in a polypropylene container along with pebbles and water. After placing the polypropylene container on a pot stand, the container was rotated at a speed of 50 rpm to mix the raw materials. The slurry obtained by mixing the raw materials was dried in a dryer and recovered to obtain SiC mixed powder.

[0095] (3) Arrangement of SiC mixed powder and seed crystal The SiC single crystal substrate as the seed crystal 113a pretreated in (1) and the SiC mixed powder obtained in (2) were placed in a graphite container.

[0096] (4) Heat treatment The graphite container prepared in (3) above was placed in a location in the resistance furnace (firing furnace) where the temperature range was within ±75°C of the set temperature, and heat treatment was performed for 20 hours at a set temperature of 2450°C in a mixed gas atmosphere of argon and nitrogen. As a result, as shown in Figure 1 (see also Figure 5(c)), a SiC wafer 10 was obtained in which a SiC single crystal was grown on a SiC single crystal substrate, a SiC growth layer 14 was provided on the SiC seed crystal layer 12, and a peeling acceleration layer 16 was formed inside the SiC seed crystal layer 12.

[0097] (5) Measurement of the crystal growth thickness of the SiC wafer The thickness of 25 arbitrary locations on the SiC wafer 10 obtained in (4) above was measured with a micrometer, and the arithmetic mean was calculated. The thickness of the seed crystal 113a was also calculated at the time of (3) above using the same method. Then, the crystal growth thickness (μm) of the SiC growth layer 14 was calculated by subtracting the arithmetic mean of the thickness of the seed crystal 113a from the arithmetic mean of the thickness of the SiC wafer 10. As a result, it was confirmed that the crystal growth thickness of the SiC growth layer 14 was 100 μm or more.

[0098] (6) Polishing The surface (Si side and C side) of the SiC wafer 10 obtained in (4) above was polished using diamond abrasive grains, and then chemical mechanical polishing (CMP) was performed. At this time, the amount of polishing on each surface (both sides) of the SiC wafer 10 was adjusted so that the thickness of the SiC wafer 10 after polishing was 350 μm. The thickness of the SiC growth layer 14 and the SiC seed crystal layer 12 in the SiC wafer 10 after polishing can be calculated from the amount of polishing.

[0099] (7) Device fabrication process A SiC-MOSFET device was formed on the SiC growth layer 14 of the polished SiC wafer 10 obtained in (6) above.

[0100] (8) Peeling off the SiC seed crystal layer A pulsed laser with a wavelength of 632 nm was irradiated onto the peeling acceleration layer 16 from the SiC seed crystal layer 12 side of the SiC wafer 10 obtained in (7) above, as incident light of the target wavelength. By scanning this pulsed laser light in the in-plane direction of the SiC wafer 10, the SiC seed crystal layer 12 was peeled off from the SiC wafer 10 along the peeling acceleration layer 16. The laser irradiation conditions at this time were an irradiation fluence of 100 J / cm ２ The pulse width was set to 10 ns, and the laser focusing position was set to a depth of 200 μm in the thickness direction from the surface of the SiC wafer 10 on the SiC seed crystal layer 12 side. As a result, the SiC wafer 10 on which the SiC-MOSFET device was formed was divided into a main wafer 111 (SiC growth layer 14 on which the device was formed) and a remaining wafer 112 (SiC seed crystal layer 12).

[0101] (9) Evaluation of peelability (good product rate) A total of 100 SiC wafers 10 on which SiC-MOSFET devices were formed were prepared using the same procedure as in (1) to (7) above. These SiC wafers 10 were divided into 100 sets of main wafers 111 and remaining wafers 112 using the same procedure as in (8) above. The peeled surfaces of the obtained main wafers 111 and remaining wafers 112 were irradiated with a halogen lamp, and the condition of these peeled surfaces was observed visually. If there were no cracks or cracks of 1 mm or more on the peeled surface of either the main wafers 111 or the remaining wafers 112, it was considered "acceptable". If there were cracks or cracks of 1 mm or more, it was considered "unacceptable". The peelability, i.e., the good product rate (%), was calculated by counting the number of "acceptable" wafers among the 100 sets of main wafers 111 and remaining wafers 112. The results are shown in Table 1.

[0102] (10) Evaluation of stacking fault count For the SiC wafer 10 obtained in (6) above before the device fabrication process, surface topography and PL images of the SiC wafer 10 were acquired using a SiC wafer defect inspection device (Lasetech, SICA88). From the acquired topography and PL images, the defect types were identified according to standard recipes compliant with IEC63068 and JEITA EDR-4712, and the number of stacking faults across the entire surface of the SiC wafer 10 was confirmed. The results are shown in Table 1.

[0103] (11) Confirmation of rare earth element concentration The SiC-MOSFET device layer of the SiC wafer 10 on which the SiC-MOSFET device obtained in (7) above is formed is removed, and the rare earth element concentration (atoms / cm³) in the SiC growth layer 14 is confirmed. ３ This was confirmed by D-SIMS analysis. The D-SIMS measurement was performed using the IMF-7f analyzer manufactured by CAMECA, Inc., and the primary ion species Cs ＋ The experiment was also conducted under the condition of an acceleration voltage of 15 kV. The results are shown in Table 1.

[0104] (12) Calculation of absorption coefficient ratio In the SiC wafer 10 on which the SiC-MOSFET device obtained in (7) above is formed, the thickness d of the composite layer of the SiC seed crystal layer 12 and the peeling acceleration layer 16 is calculated by removing the SiC-MOSFET device layer and the SiC growth layer 14. ３ The thickness (μm) was measured. For this composite layer, a UV-Vis-Near-Infrared spectrophotometer (Hitachi High-Tech Science UH4150) was used to illuminate the SiC seed crystal layer 12 side (C-plane side) with light from a light source. The light that passed through the composite layer was received by a detector placed on the delamination-promoting layer 16 side (Si-plane side), and the total transmittance (%) was measured. Subsequently, the thickness d from the composite layer was further measured. ２ The peel-promoting layer 16 (μm) is removed, and the thickness is d １ The total transmittance (%) was measured for the SiC seed crystal layer 12, which was (μm) in thickness, using the same method as described above.

[0105] Of the above total transmittance (%) measurement results, the thickness d for light with a wavelength of 632 nm １ Transmittance T of SiC seed crystal layer 12 of (μm) １ (%), and thickness d３ Transmittance T of the composite layer of the SiC seed crystal layer 12 and the peel-promoting layer 16, which is (μm) in size. ３ I checked the percentage.

[0106] And then, equation (1): A １ = (-logT) １ ) / d １ Based on (1), the absorption coefficient A in the SiC species crystal layer 12 １ While calculating the following formula (2): A ２ = (logT １ -logT ３ ) / d ２ Based on (2), the absorption coefficient A in the peel-promoting layer 16 ２ The absorption coefficient ratio A was calculated. ２ / A １ By calculating this, we determined how many times greater the absorption coefficient of the peel-promoting layer 16 is compared to the absorption coefficient of the portion of the SiC seed crystal layer 12 other than the peel-promoting layer 16. The results are shown in Table 1.

[0107] Example 2 In (1) above, the hydrogen ion injection conditions are set as follows: Injection dose is 1 × 10 １３ ions / cm ２ In the above (2), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that no oxide was added. The results are shown in Table 1.

[0108] Example 3 In (1) above, the injection conditions for hydrogen ions are set to an injection dose of 2 × 10 １３ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0109] Example 4 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 4 × 10 １３ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0110] Example 5 In the above (1), as the hydrogen ion implantation conditions, the implantation dose was set to 6×10 １３ ions / cm ２ A SiC wafer 10 and the like were produced and various evaluations were performed in the same manner as in Example 2 except for the above setting. The results were as shown in Table 1.

[0111] Example 6 In the above (1), as the hydrogen ion implantation conditions, the implantation dose was set to 8×10 １３ ions / cm ２ A SiC wafer 10 and the like were produced and various evaluations were performed in the same manner as in Example 2 except for the above setting. The results were as shown in Table 1.

[0112] Example 7 In the above (1), as the hydrogen ion implantation conditions, the implantation dose was set to 1×10 １４ ions / cm ２ A SiC wafer 10 and the like were produced and various evaluations were performed in the same manner as in Example 2 except for the above setting. The results were as shown in Table 1.

[0113] Example 8 In the above (1), as the hydrogen ion implantation conditions, the implantation dose was set to 2×10 １４ ions / cm ２ A SiC wafer 10 and the like were produced and various evaluations were performed in the same manner as in Example 2 except for the above setting. The results were as shown in Table 1.

[0114] Example 9 In the above (1), as the hydrogen ion implantation conditions, the implantation dose was set to 4×10 １４ ions / cm ２ A SiC wafer 10 and the like were produced and various evaluations were performed in the same manner as in Example 2 except for the above setting. The results were as shown in Table 1.

[0115] Example 10 In the above (1), as the hydrogen ion implantation conditions, the implantation dose was set to 7×10 １４ ions / cm ２ A SiC wafer 10 and the like were produced and various evaluations were performed in the same manner as in Example 2 except for the above setting. The results were as shown in Table 1.

[0116] Example 11 In the above (1), as the hydrogen ion implantation conditions, the implantation dose was set to 9×10１４ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0117] Example 12 In (1) above, the injection conditions for hydrogen ions are set to an injection dose of 1 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0118] Example 13 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 3 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0119] Example 14 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 4 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0120] Example 15 In (1) above, the hydrogen ion injection conditions were set to an injection dose of 7 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0121] Example 16 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 9 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0122] Example 17 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 2 × 10 １６ ions / cm ２Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0123] Example 18 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 3 × 10 １６ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0124] Example 19 In (1) above, the hydrogen ion injection conditions were set to an injection dose of 5 × 10 １６ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0125] Example 20 (Comparison) In (1) above, the hydrogen ion injection conditions were set to an injection dose of 6 × 10 １６ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0126] Example 21 (Comparison) In (1) above, a commercially available disc-shaped SiC single crystal substrate (4H-SiC, diameter 200 mm (8 inches), off-angle 4°, thickness 0.35 mm) was prepared as the seed crystal 113a, and the hydrogen ion implantation conditions were set to an implantation dose of 6 × 10 １６ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 2. The results are shown in Table 1.

[0127] Example 22 In (1) above, the hydrogen ion injection conditions were set to an injection dose of 9 × 10 １３ ions / cm ２ In the above (2), the SiC wafer 10 and other components were prepared and various evaluations were carried out in the same manner as in Example 1, except that the oxide content relative to the SiC powder content was weighed to be 13.2% by weight. The results are shown in Table 2.

[0128] In Example 23, the SiC wafer 10 and other components were manufactured and various evaluations were performed in the same manner as in Example 22, except that the oxide content relative to the SiC powder content was weighed to be 8.1% by weight as described in (2) above. The results are shown in Table 2.

[0129] Example 24 In Example 24, the SiC wafer 10 and other components were manufactured and various evaluations were performed in the same manner as in Example 22, except that the oxide content relative to the SiC powder content was weighed to be 7.2% by weight as described in (2) above. The results are shown in Table 2.

[0130] Example 25 In (2) above, the oxide (CeO) is used as a liquid phase formation aid. ２ Except for weighing out the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 6.1% by weight, SiC wafers 10 and other components were prepared and various evaluations were performed in the same manner as in Example 22. The results are shown in Table 2.

[0131] In Example 26, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 22, except that in (1) above, C ions were used as ion 221, and in (2) above, the oxide content relative to the SiC powder content was weighed to be 5.8% by weight. The results are shown in Table 2.

[0132] In Example 27, the SiC wafer 10 and other components were prepared and various evaluations were performed in the same manner as in Example 22, except that He ions were used as ion 221 in (1) above, and the oxide content relative to the SiC powder content was weighed to be 5.1% by weight in (2) above. The results are shown in Table 2.

[0133] In Example 28, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 22, except that Xe ions were used as ion 221 in (1) above, and the oxide content relative to the SiC powder content was weighed to be 4.2% by weight in (2) above. The results are shown in Table 2.

[0134] In Example 29, the SiC wafer 10 and other components were prepared and various evaluations were performed in the same manner as in Example 22, except that in (1) above, P ions were used as ion 221, and in (2) above, the oxide content relative to the SiC powder content was weighed to be 3.5% by weight. The results are shown in Table 2.

[0135] In Example 30, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 22, except that in (1) above, B ions were used as ion 221, and in (2) above, the oxide content relative to the SiC powder content was weighed to be 2.1% by weight. The results are shown in Table 2.

[0136] Example 31 In (1) above, a commercially available disc-shaped SiC single crystal substrate (4H-SiC, 200 mm (8 inches) in diameter, 4° off-angle, 0.35 mm thick) was prepared as the seed crystal 113a, and in (2) above, the oxide content relative to the SiC powder content was weighed to be 2.1% by weight, the SiC wafer 10 and other products were manufactured and various evaluations were performed in the same manner as in Example 22. The results are shown in Table 2.

[0137] Example 32 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 6 × 10 １５ ions / cm ２ In (2) above, no oxide is added; in (8) above, a pulsed laser with a wavelength of 498 nm is irradiated; and in (12) above, the absorption coefficient ratio A is determined based on light with a wavelength of 498 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0138] Example 33 In (1) above, C ions are used as ion 221, In (8) above, a pulsed laser with a wavelength of 500 nm is irradiated, and In (12) above, the absorption coefficient ratio A is determined based on light with a wavelength of 500 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0139] Example 34 In (1) above, Xe ions are used as ion 221, in (8) above, a pulsed laser with a wavelength of 532 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on light with a wavelength of 532 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0140] Example 35 In (1) above, He ions are used as ion 221, in (8) above, a pulsed laser with a wavelength of 546 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on light with a wavelength of 546 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0141] Example 36 In (8) above, a pulsed laser with a wavelength of 600 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on the light with a wavelength of 600 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0142] Example 37 In (8) above, a pulsed laser with a wavelength of 602 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on the light with a wavelength of 602 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0143] Example 38 In (8) above, a pulsed laser with a wavelength of 998 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on the light with a wavelength of 998 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0144] Example 39 In (1) above, He ions are used as ion 221, in (8) above, a pulsed laser with a wavelength of 1000 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on light with a wavelength of 1000 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0145] Example 40 In (1) above, B ions are used as ion 221, in (8) above, a pulsed laser with a wavelength of 1030 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on light with a wavelength of 1030 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0146] Example 41 In (1) above, P ions are used as ion 221, in (8) above, a pulsed laser with a wavelength of 1040 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on light with a wavelength of 1040 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0147] Example 42 In (1) above, a commercially available disc-shaped SiC single crystal substrate (4H-SiC, diameter 200 mm (8 inches), off-angle 4°, thickness 0.35 mm) is prepared as the seed crystal 113a, in (8) above, a pulsed laser with a wavelength of 1080 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on the light with a wavelength of 1080 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0148] Example 43 In (1) above, C ions are used as ion 221, in (8) above, a pulsed laser with a wavelength of 1100 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on light with a wavelength of 1100 nm.２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0149] Example 44 In (8) above, a pulsed laser with a wavelength of 1102 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on the light with a wavelength of 1102 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0150] Example 45 In (8) above, a pulsed laser with a wavelength of 1106 nm is irradiated, and in (12) above, the absorption coefficient ratio A is determined based on the light with a wavelength of 1106 nm. ２ / A １ Except for the calculation of [a certain value], the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 32. The results are shown in Table 2.

[0151]

[0152]

[0153] Tables 1 and 2 show that, although the cause is unclear, in SiC wafers 10 where the delamination accelerating layer 16 has an absorption coefficient 1.2 to 99 times that of the portion of the SiC seed crystal layer 12 other than the delamination accelerating layer 16 with respect to incident light of the target wavelength, the delamination performance is good and the number of stacking faults across the entire wafer is reduced.

[0154] 10, 40 SiC wafer 12 SiC seed crystal layer 14 SiC growth layer 16, 116 Peeling acceleration layer 111 Main wafer 112 Remaining wafer 113a, 113b Seed crystal 114 Pre-treated seed crystal 115 Grown SiC crystal 171 Inspection device 172 Processing device 173 Pre-treatment device 174 Growth device I Ion

Claims

1. A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peel-promoting layer is formed inside and / or on the surface of at least one of the first crystal layer and the second crystal layer, and the peel-promoting layer has an absorption coefficient of 1.2 to 99 times that of the portion of the first crystal layer other than the peel-promoting layer with respect to incident light of a target wavelength.

2. The SiC wafer according to claim 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer.

3. The SiC wafer according to claim 1 or 2, wherein the target wavelength is 500 to 600 nm or 1000 to 1100 nm.

4. The SiC wafer according to claim 1 or 2, wherein the peel-promoting layer is a SiC-derived layer containing a peel-promoting substance.

5. The SiC wafer according to claim 4, wherein the peel-promoting substance is at least one ion selected from the group consisting of Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements.

6. The SiC wafer according to claim 5, wherein the peeling-promoting layer is a layer formed by implanting the ions into at least one of the first crystal layer and the second crystal layer.

7. The peel-promoting layer has an ion implantation dose of 1 × 10 １３ ~5 x 10 １６ ions / cm ２ The SiC wafer according to claim 6, having a portion that is...

8. The second crystal layer is 5.00 × 10 １３ atoms / cm ３ A SiC wafer according to claim 1 or 2, having a portion containing rare earth elements at the above concentration.

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