SiC WAFER

Abstract

Provided is an SiC wafer which is capable of suppressing the occurrence of cracking and breakage of the wafer when the SiC wafer is divided into a device formation part and a device non-formation part after the formation of a device on the wafer, while being capable of suppressing unintended delamination. The SiC wafer comprises an SiC seed crystal layer and an SiC growth layer that is grown from the SiC seed crystal layer and contains an SiC single crystal. A delamination promotion layer is formed in a specific pattern so as to be parallel to both surfaces of the SiC wafer inside and / or on the surface of at least one of the SiC seed crystal layer and the SiC growth layer, whereby a region that includes the delamination promotion layer and a region that does not include the delamination promotion layer are present in a region that has the same thickness as the delamination promotion layer and includes the specific pattern. The delamination promotion layer is an SiC-derived layer that has a void, an amorphous portion, or a portion that includes a delamination promotion substance, and the specific pattern includes a plurality of constituent units that are separated from each other.

Description

SiC wafer

[0001] This disclosure relates to SiC wafers.

[0002] Silicon carbide (SiC) is attracting attention as a wide-bandgap material that can control high currents and high voltages with low loss. In particular, power semiconductor devices using SiC material (SiC power devices) have recently been expected to be used in a variety of applications because they are superior to those using Si semiconductors in terms of miniaturization, low power consumption, and high efficiency. For example, by adopting SiC power devices, converters, inverters, and on-board chargers for electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs) can be miniaturized and their efficiency improved.

[0003] Incidentally, after forming devices (e.g., electrodes and wiring patterns) on the surface of a semiconductor wafer, the semiconductor wafer is generally divided into a device-formed portion and an unformed portion (the back surface portion of the wafer). At this time, the unformed portion is considered a waste portion of the wafer and is often ground and / or removed. Several wafer slicing technologies have been proposed as methods to reduce the costs associated with grinding and / or removing the back surface portion of the wafer. For example, Patent Document 1 (Japanese Patent Application Publication No. 2022-169468) discloses a method in which a modified zone is formed in a semiconductor wafer by laser irradiation, and the wafer is peeled off along the modified zone.

[0004] Japanese Patent Publication No. 2022-169468 WO2023 / 067736A1

[0005] As described above, conventional semiconductor wafer delamination methods involve grinding and / or removing the back surface portion of the wafer after device formation, resulting in significant waste in terms of cost and environmental impact. In this regard, while wafer removal methods for cost reduction, such as those disclosed in Patent Document 1, involve pre-implanting ions across the entire wafer and then forming a modified zone by laser irradiation, there is a problem of unintended delamination and / or cracking occurring during subsequent wafer processing. Furthermore, while it is conceivable to introduce a delamination-promoting layer inside the semiconductor wafer to suppress cracking during slicing (dividing) of the wafer after device formation, even in this case, the problem of unintended delamination and / or cracking during subsequent wafer processing remains. Therefore, there is a need for a semiconductor wafer that can suppress unintended delamination while also suppressing cracking and fracture when dividing the wafer into a device-formed portion and an un-device-formed portion after device formation.

[0006] The present inventors have now discovered that by forming a delamination-promoting layer in a predetermined pattern within a SiC wafer having a first crystal layer such as a SiC seed crystal layer and a second crystal layer such as a SiC growth layer, it is possible to provide a SiC wafer that can suppress unintended delamination while also suppressing the occurrence of cracks and fractures in the wafer when it is divided into a device-formed portion and an unformed portion after device formation.

[0007] Therefore, an object of the present invention is to provide a SiC wafer that can suppress unintended delamination while also suppressing the occurrence of cracks and fractures in the wafer when it is divided into a device-formed portion and an unformed portion after device formation on the wafer.

[0008] The following embodiments are provided according to this disclosure: [Embodiment 1] A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peel-promoting layer is formed in a predetermined pattern parallel to both sides of the SiC wafer on the interior and / or surface of at least one of the first crystal layer and the second crystal layer, so that a region having the same thickness as the peel-promoting layer encompassing the predetermined pattern contains a region containing the peel-promoting layer and a region not containing the peel-promoting layer, the peel-promoting layer is a SiC-derived layer having voids, amorphous portions, or portions containing a peel-promoting substance, and the predetermined pattern includes a plurality of spaced-apart constituent units. [Embodiment 2] The SiC wafer according to Embodiment 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer. [Aspect 3] The SiC wafer according to aspect 1 or 2, wherein, when the SiC wafer is viewed in cross-section, the width of the peeling accelerating layer is 0.5 to 15.0 μm, and the distance between adjacent peeling accelerating layers is 0.5 to 15.0 μm. [Aspect 4] The second crystal layer has a thickness of 55 μm or more, and the nitrogen atom concentration of the second crystal layer at a depth of 55 μm in the thickness direction of the SiC wafer from the surface of the SiC wafer on the second crystal layer side is 1.00 × 10 １８ atoms / cm ３ The above is the SiC wafer according to any one of embodiments 1 to 3. [Embodiment 5] The second crystal layer is 5.00 × 10 １３ atoms / cm ３[Aspect 6] A SiC wafer according to any one of embodiments 1 to 4, having a portion containing rare earth elements at the above concentration. [Aspect 7] A SiC wafer according to any one of embodiments 1 to 5, wherein the peeling accelerating layer has a thickness of 30.0 μm or less. [Aspect 8] A SiC wafer according to any one of embodiments 1 to 6, wherein the peeling accelerating substance is at least one ion selected from the group consisting of Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements. [Aspect 8] A SiC wafer according to any one of embodiments 1 to 7, wherein the diameter of the inscribed circle of the constituent unit is 0.5 to 15.0 μm, and the diameter of the circumscribed circle of the constituent unit is 0.5 μm or more. [Aspect 9] A SiC wafer according to any one of embodiments 1 to 8, wherein one or more of the constituent units are polygonal. [Aspect 10] A SiC wafer according to any one of embodiments 1 to 8, wherein one or more of the constituent units are circular. [Aspect 11] A SiC wafer according to any one of embodiments 1 to 8, wherein one or more of the constituent units are elliptical.

[0009] This is a schematic cross-sectional view showing an example of a SiC wafer according to the present disclosure. This is a plan view showing an example of a pattern mask having a triangular aperture pattern and a peel-promoting layer patterned in a triangular shape using the same. This is a plan view showing another example of a pattern mask having a triangular aperture pattern and a peel-promoting layer patterned in a triangular shape using the same. This is a plan view showing an example of a pattern mask having a circular aperture pattern and a peel-promoting layer patterned in a circular shape using the same. This is a plan view showing an example of a pattern mask having a square aperture pattern and a peel-promoting layer patterned in a square shape using the same. This is a plan view showing an example of a pattern mask having a hexagonal aperture pattern and a peel-promoting layer patterned in a hexagonal shape using the same. This is a plan view showing an example of a pattern mask having an elliptical aperture pattern and a peel-promoting layer patterned in an elliptical shape using the same. This is a diagram showing an example of the overall system configuration according to the first embodiment of the present disclosure. This is an explanatory diagram of a pretreatment for forming a layer containing minute voids. This is an explanatory diagram of a pretreatment for forming a layer containing a peel-promoting substance. This is an explanatory diagram of a pretreatment for forming a layer containing another peel-promoting substance. This is a diagram showing an example of the appearance of the cross-section when a SiC wafer is cut along a plane passing through the peel-promoting layer. This figure shows another example of the appearance of the cross-section when a SiC wafer is cut along a plane passing through the peel-accelerating layer. This figure shows another example of the appearance of the cross-section when a SiC wafer is cut along a plane passing through the peel-accelerating layer. This figure schematically shows the thermal etching process in the first example of the processing steps according to the second embodiment of this disclosure. This figure schematically shows the surface oxidation process in the second example of the processing steps according to the second embodiment of this disclosure. This figure schematically shows the plasma etching process in the third example of the processing steps according to the second embodiment of this disclosure.

[0010] The SiC wafer of this disclosure comprises a first crystal layer containing a SiC single crystal and a second crystal layer containing a SiC single crystal formed on the first crystal layer. Therefore, the SiC wafer of this disclosure is mainly composed of a SiC single crystal and is usable as a SiC single crystal wafer. Here, the expression "mainly composed of a SiC single crystal" means that the main part of the SiC wafer other than the peeling accelerator layer is composed of a SiC single crystal (not a SiC polycrystalline layer), regardless of whether the SiC-derived peeling accelerator layer described later maintains the form of a SiC single crystal or not. Typically, the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing a SiC single crystal grown from the SiC seed crystal layer, and therefore the SiC wafer as a whole can be composed of one SiC single crystal (or at least mainly composed of a SiC single crystal). Therefore, the following explanation will be based on a SiC wafer in which the first crystal layer is a SiC seed crystal layer and the second crystal layer is a SiC growth layer.

[0011] Figure 1 conceptually shows a SiC wafer 10. The SiC wafer 10 comprises a SiC seed crystal layer 12 (first crystal layer) and a SiC growth layer 14 (second crystal layer) containing a SiC single crystal grown from the SiC seed crystal layer 12. Furthermore, a peel-promoting layer 16 is formed inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. The peel-promoting layer 16 is formed in a predetermined pattern parallel to both sides of the SiC wafer 10. As a result, a region R (hereinafter sometimes referred to as the peel-promoting region R) with the same thickness as the peel-promoting layer 16 encompassing the predetermined pattern within the SiC wafer 10 is formed within the region R containing the peel-promoting layer 16. １ and the region R that does not include the peel-promoting layer 16 ２ The peel-promoting layer 16 is a SiC-derived layer having voids, amorphous portions, or portions containing a peel-promoting substance. The predetermined pattern includes a plurality of spaced-apart structural units. By having such a configuration, the SiC wafer 10 can suppress unintended peeling while also suppressing the occurrence of cracks and fractures in the wafer when it is divided into a device-formed portion and an unformed portion after device formation.

[0012] In other words, as described above, conventional semiconductor wafer delamination methods involve grinding and / or removing the back surface portion of the wafer after device formation, which is wasteful in terms of cost and environmental impact. In this regard, while wafer removal methods for cost reduction, such as the one disclosed in Patent Document 1, involve pre-implanting ions across the entire wafer and then forming a modified zone by laser irradiation, there is a problem of unintended delamination and / or cracking occurring during subsequent wafer processing. Furthermore, while it is conceivable to introduce a delamination-promoting layer inside the semiconductor wafer to suppress cracking during slicing (dividing) of the wafer after device formation, even in this case, the problem of unintended delamination and / or cracking during subsequent wafer processing still remains. Therefore, there is a need for a semiconductor wafer that can suppress unintended delamination while also suppressing cracking and fracture when dividing the wafer into a device-formed portion and an un-device-formed portion after device formation. This problem is successfully resolved according to the present invention. In particular, since the SiC wafer 10 of the present invention has a peel-promoting layer 16 partially or intermittently formed inside it according to a predetermined pattern, it is possible to suppress unintended peeling of the wafer caused by the formation of the peel-promoting layer 16 evenly throughout the entire in-plane direction inside the SiC wafer 10.

[0013] The SiC wafer 10 preferably has a thickness of 500 μm or less, and more preferably 300 to 500 μm. The shape of the SiC wafer 10 is not particularly limited, but it is preferably disc-shaped (circular). In this specification, "circular shape" does not have to be a perfect circle, but may be a substantially circular shape that can be generally recognized as circular overall. For example, it may be a shape in which a part of the circle is cut out for the purpose of specifying the crystal orientation or for other purposes, or a shape in which a slit is provided in a part of the circle, in which case the size can be determined based on the diameter of the largest circle inscribed in the outer edge excluding the cut-out outer edge or the slit. The diameter of the SiC wafer 10 is not particularly limited, but may be 100 mm (4 inches) or more, 145 mm or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more.

[0014] Typically, the SiC seed crystal layer 12 is formed of a SiC single crystal and has a crystal growth surface. In this case, the polytype, off-angle, and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal are not particularly limited, but the polytype is preferably 4H, 6H, or 3C. Alternatively, a SiC single crystal grown on a Si substrate may be used as the SiC seed crystal layer 12. The crystal growth surface on the SiC single crystal serving as the SiC seed crystal layer 12 may be a Si face, a C face, or both the Si face and the C face, and is preferably a Si face. Therefore, it is preferable that the delamination acceleration layer 16 is formed in the vicinity of this Si face. The diameter of the SiC seed crystal layer 12 is not particularly limited, and may be 100 mm (4 inches) or more, 145 mm or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more.

[0015] The SiC growth layer 14 includes a SiC single crystal grown from the SiC seed crystal layer 12. The polytype, off-angle, and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal are not particularly limited, but the polytype is preferably 4H, 6H, or 3C.

[0016] The SiC growth layer 14 preferably has a portion containing nitrogen atoms at a concentration of 1.00×10 １８ atoms / cm ３ or higher, and this concentration is more preferably 1.00×10 １８ to 1.50×10 １９ atoms / cm ３ , more preferably 1.00×10 １８ to 1.00×10 １９ atoms / cm ３ , still more preferably 2.00×10 １８ to 1.00×10 １９ atoms / cm ３ , particularly preferably 2.00×10 １８ to 8.00×10 １８ atoms / cm ３ .

[0017] The SiC growth layer 14 has a thickness of 5 μm or more, and the nitrogen atom concentration of the SiC growth layer 14 at a depth of 5 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC growth layer 14 on the SiC growth layer 14 side of the SiC wafer 10 is 1.00 × 10 １８ atoms / cm ３ Preferably, it is 1.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ More preferably 2.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ Particularly preferred is 2.00 × 10 １８ ~8.00 x 10 １８ atoms / cm ３ That is the case.

[0018] The SiC growth layer 14 has a thickness of 10 μm or more, and the nitrogen atom concentration of the SiC growth layer 14 at a depth of 10 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC growth layer 14 on the SiC wafer 10 side is 1.00 × 10 １８ atoms / cm ３ Preferably, it is 1.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ More preferably 2.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ Particularly preferred is 2.00 × 10 １８ ~8.00 x 10 １８ atoms / cm ３ That is the case.

[0019] The SiC growth layer 14 has a thickness of 25 μm or more, and the nitrogen atom concentration of the SiC growth layer 14 at a depth of 25 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC growth layer 14 on the SiC wafer 10 side is 1.00 × 10⁻¹⁴ １８ atoms / cm ３ Preferably, it is 1.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３More preferably 2.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ Particularly preferred is 2.00 × 10 １８ ~8.00 x 10 １８ atoms / cm ３ That is the case.

[0020] The SiC growth layer 14 has a thickness of 55 μm or more, and the nitrogen atom concentration of the SiC growth layer 14 at a depth of 55 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC growth layer 14 on the SiC growth layer 14 side of the SiC wafer 10 is 1.00 × 10 １８ atoms / cm ３ Preferably, it is 1.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ More preferably 2.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ Particularly preferred is 2.00 × 10 １８ ~8.00 x 10 １８ atoms / cm ３ That is the case.

[0021] The SiC growth layer 14 preferably contains rare earth elements, and examples of rare earth elements include Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, and combinations thereof. From the viewpoint of reducing cracking and fracture, the rare earth element is preferably Y and / or Ce. When the SiC growth layer 14 contains rare earth elements, the SiC growth layer 14 has a density of 5.00 × 10⁻¹⁶. １３ atoms / cm ３ It is preferable that the mixture contains a portion of rare earth elements at the above concentration, and more preferably this concentration is 5.00 × 10⁻⁶. １３ ~8.00 x 10 １５ atoms / cm ３ More preferably 3.00 × 10 １４ ~8.00 x 10 １５ atoms / cm ３ Particularly preferred is 3.00 × 10 １４ ~3.20 x 10 １５atoms / cm ３ .

[0022] The SiC growth layer 14 has a thickness of 5 μm or more, and the rare earth element concentration of the SiC growth layer 14 at a depth position of 5 μm in the thickness direction of the SiC wafer 10 from the surface on the SiC growth layer 14 side of the SiC wafer 10 is 5.00×10 １３ atoms / cm ３ or more, more preferably 5.00×10 １３ to 8.00×10 １５ atoms / cm ３ , still more preferably 3.00×10 １４ to 8.00×10 １５ atoms / cm ３ , particularly preferably 3.00×10 １４ to 3.20×10 １５ atoms / cm ３ .

[0023] The SiC growth layer 14 has a thickness of 10 μm or more, and the rare earth element concentration of the SiC growth layer 14 at a depth position of 10 μm in the thickness direction of the SiC wafer 10 from the surface on the SiC growth layer 14 side of the SiC wafer 10 is 5.00×10 １３ atoms / cm ３ or more, more preferably 5.00×10 １３ to 8.00×10 １５ atoms / cm ３ , still more preferably 3.00×10 １４ to 8.00×10 １５ atoms / cm ３ , particularly preferably 3.00×10 １４ to 3.20×10 １５ atoms / cm ３ .

[0024] The SiC growth layer 14 has a thickness of 25 μm or more, and the rare earth element concentration of the SiC growth layer 14 at a depth position of 25 μm in the thickness direction of the SiC wafer 10 from the surface on the SiC growth layer 14 side of the SiC wafer 10 is 5.00×10 １３ atoms / cm ３ or more, more preferably 5.00×10 １３~8.00 x 10 １５ atoms / cm ３ More preferably 3.00 × 10 １４ ~8.00 x 10 １５ atoms / cm ３ Particularly preferred is 3.00 × 10 １４ ~3.20 x 10 １５ atoms / cm ３ That is the case.

[0025] The SiC growth layer 14 has a thickness of 55 μm or more, and the rare earth element concentration of the SiC growth layer 14 at a depth of 55 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC growth layer 14 on the SiC growth layer 14 side of the SiC wafer 10 is 5.00 × 10 １３ atoms / cm ３ Preferably, it is 5.00 × 10 １３ ~8.00 x 10 １５ atoms / cm ３ More preferably 3.00 × 10 １４ ~8.00 x 10 １５ atoms / cm ３ Particularly preferred is 3.00 × 10 １４ ~3.20 x 10 １５ atoms / cm ３ That is the case.

[0026] The peel-promoting layer 16 is formed in a predetermined pattern parallel to both sides of the SiC wafer 10 on the interior and / or surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. In other words, the SiC wafer 10 has a peel-promoting layer 16 formed in a predetermined pattern parallel to both sides of the SiC wafer 10 on the interior and / or surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. As a result, as shown in Figure 1, in the in-plane direction inside the SiC wafer 10, a region R (peeling region R) with the same thickness as the peel-promoting layer 16 encompassing the predetermined pattern exists within the region R including the peel-promoting layer 16. １ and the region R that does not include the peel-promoting layer 16 ２This means that such a layer exists. The peel-promoting layer 16 is a SiC-derived layer (for example, a SiC-based layer) that promotes the division of the SiC wafer 10 into an upper and lower portion with the peel-promoting layer 16 as the starting point or boundary, and is, for example, a layer in which the SiC crystal structure is incomplete compared to other parts, or in which peeling or splitting is more likely to occur due to other causes. In this regard, in Figure 1, the region R including the peel-promoting layer 16 １ An example configuration is provided in which a peeling-promoting layer (typically a peeling-promoting layer 16) is formed partially or intermittently in a predetermined pattern inside the SiC seed crystal layer 12. By forming the peeling-promoting layer 16 in a predetermined pattern inside the SiC wafer 10 in this way, it is possible to provide a SiC wafer 10 that can suppress unintended peeling while also suppressing the occurrence of cracks and fractures in the wafer when it is divided into a device-formed portion and an unformed portion after device formation.

[0027] Here, the "predetermined pattern" includes multiple constituent units spaced apart from each other. That is, as shown in Figure 1, a region R containing the peeling-promoting layer 16 in the in-plane direction inside the SiC wafer 10. １ (Typically, the peel-promoting layer 16) and the region R that does not include the peel-promoting layer 16 ２ Where such a layer exists, region R including a certain peel-promoting layer 16 １ and region R including another peel-promoting layer 16 １ These are separated from each other, and their region R １ Each of these regions represents a "constituent unit." The shape of this constituent unit is not particularly limited, as long as it is a shape that can suppress unintended delamination of the wafer by forming the delamination-promoting layer 16 in a predetermined pattern in the in-plane direction inside the SiC wafer 10. Examples of such constituent unit shapes include polygons (triangles, quadrilaterals, hexagons, etc.), circles, ellipses, and combinations thereof. Therefore, one or more of the constituent units may be polygons, circles, or ellipses. Specifically, as shown in Figures 2 to 7, the region R containing the delamination-promoting layer 16 as constituent units of various shapes １The peel-accelerating layer (typically 16) may be formed in the in-plane direction inside the SiC wafer 10. Note that the "polygon" does not need to be a perfect polygon; it may be a roughly polygonal shape (roughly triangular, roughly quadrilateral, roughly hexagonal, etc.). For example, it may be a shape in which part of the polygon is cut out, or some or all of the vertices or ends of the polygon may be rounded. Furthermore, the quadrilateral shape as a constituent unit is in the region R including the peel-accelerating layer 16, as shown in Figure 5. １ This also includes cases where the stripes are formed in a striped pattern as a roughly rectangular shape in the in-plane direction within the SiC wafer 10, and one or both ends of the stripe shape (roughly rectangular) may form part of the arc shape of the outer edge of the SiC wafer 10. Similarly, "circular" and "elliptical" may be roughly circular and roughly elliptical, respectively. For example, the roughly elliptical shape may also include a long shape (capsule shape) with rounded ends as shown in Figure 7.

[0028] As described above, various shapes can be used for the constituent units, but when the constituent units are viewed from above, the diameter of the inscribed circle of the constituent unit is preferably 0.5 to 15.0 μm, more preferably 0.5 to 12.0 μm, even more preferably 1.0 to 7.0 μm, and particularly preferably 2.0 to 5.0 μm. Furthermore, the diameter of the circumscribed circle of the constituent unit is preferably 0.5 μm or more, more preferably 0.5 to 50.0 μm, even more preferably 1.0 to 20.0 μm, and particularly preferably 2.0 to 5.0 μm. These preferred numerical ranges for the circumscribed circle are particularly applicable when the constituent units are polygons or circles other than stripes. On the other hand, when the constituent units are formed in a stripe shape as shown in Figure 5, the diameter of the circumscribed circle depends on the size of the wafer. For example, if the diameter of the wafer is 200 mm (8 inches), the diameter of the circumscribed circle can be up to about 200 mm. Therefore, if the constituent unit is striped, it is preferable that at least the diameter of the inscribed circle is within the above range. In this case, the diameter of the circumscribed circle is preferably 0.1 to 1.0 times the diameter of the wafer in the case of a circular wafer, and preferably 0.1 to 1.0 times the length of one side of the wafer in the case of a polygonal wafer. In this way, by controlling the size of the constituent unit to the above range, rather than simply forming the above-described shape constituent unit in multiple locations, it is possible to more effectively suppress unintended delamination while also suppressing the occurrence of wafer cracks and fractures when dividing the wafer after device formation.

[0029] As described above, the "predetermined pattern" includes a plurality of constituent units spaced apart from each other. In this case, when the SiC wafer 10 is viewed in cross-section, the peeling accelerating layer 16 (for example, the region R including the peeling accelerating layer 16) is included. １ The width of the peel-promoting layer 16 is preferably 0.5 to 15.0 μm, more preferably 0.5 to 12.0 μm, even more preferably 1.0 to 7.0 μm, and particularly preferably 2.0 to 5.0 μm. Also, the adjacent peel-promoting layer 16 (for example, the region R including the peel-promoting layer 16) １The spacing between the components is preferably 0.5 to 15.0 μm, more preferably 0.5 to 12.0 μm, even more preferably 1.0 to 7.0 μm, and particularly preferably 2.0 to 5.0 μm. In this way, by distributing the peeling-promoting layer 16, which has a predetermined width, at predetermined spacings in the in-plane direction within the SiC wafer 10, unlike when the peeling-promoting layer 16 is evenly distributed throughout the entire area, it is possible to suppress unintended peeling while also suppressing the occurrence of wafer cracks and fractures when dividing the wafer after device formation. Therefore, by combining the size control of the component units described above with the distribution (width and / or spacing) control of the component units, it is possible to more effectively suppress unintended peeling while also suppressing the occurrence of wafer cracks and fractures when dividing the wafer after device formation.

[0030] The peel-promoting layer 16 is a SiC-derived layer having voids, amorphous portions, or portions containing a peel-promoting substance. When the peel-promoting layer 16 contains a peel-promoting substance, it is preferable that the layer is formed by implanting ions I into at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. These ions I correspond to the peel-promoting substance. Based on this, the "SiC-derived layer" typically means a layer formed by somehow modifying the SiC crystal (especially the SiC single crystal) constituting the SiC seed crystal layer 12 and / or the SiC growth layer 14 (for example, a SiC-based layer), and can be a layer in which the SiC crystal has been modified. The peel-promoting substance is preferably an ion of Si, C, Al, B, P, N, O, H, a noble gas element, a rare earth element, or a combination thereof, more preferably an ion of Si, C, B, P, N, H, a noble gas element, a rare earth element, or a combination thereof, and even more preferably an ion of Si, C, B, P, a noble gas element, or a combination thereof.

[0031] If the peel-accelerating layer 16 contains voids, it is preferable that the peel-accelerating layer 16 is a layer obtained by forming minute grooves in at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. For example, by forming grooves (voids) at predetermined intervals at the interface between the SiC seed crystal layer 12 and the SiC growth layer 14, a peel-accelerating layer 16 can be formed in which the crystal structure near the interface is partially changed, modified, or fragmented. When such a peel-accelerating layer 16 is formed, the SiC seed crystal layer 12 becomes easier to peel from the SiC wafer 10 along the voids.

[0032] When the peel-accelerating layer 16 includes an amorphous portion, it is preferable that the peel-accelerating layer 16 is a layer formed by implanting ions I into at least one of the SiC seed crystal layer 12 and the SiC growth layer 14, and irradiating the portion into which ions I have been implanted with incident light of a specific wavelength. The specific wavelength in "incident light of a specific wavelength" is typically 495 to 635 nm or 995 to 1110 nm. Examples of incident light include pulsed laser light and CW (Continuous Wave) lasers.

[0033] The peel-promoting layer 16 preferably has a thickness of 30 μm or less, more preferably 0.5 to 20 μm, even more preferably 0.5 to 10 μm, and particularly preferably 0.5 to 5 μm.

[0034] As described above, this disclosure provides a SiC wafer 10 that can suppress unintended delamination while also suppressing the occurrence of cracks and fractures in the wafer when it is divided into a device-formed portion and an unformed portion after device formation on the wafer. The first and second embodiments of a system or process for manufacturing such a SiC wafer 10 will be described below. The descriptions of the first and second embodiments apply to the SiC wafer 10 described above insofar as they do not contradict the present invention, but the present invention is not limited to them. Therefore, in the following description, the SiC wafer 40, the pre-treated seed crystal 114, the grown SiC crystal 115, and the delamination-promoting region 116 can correspond to the same thickness region R (delamination-promoting region R) as the SiC wafer 10, the SiC seed crystal layer 12, the SiC growth layer 14, and the delamination-promoting layer 16 encompassing a predetermined pattern, respectively.

[0035] In the descriptions of the first and second embodiments, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the embodiments in order to make the explanation clearer. However, these are merely examples and do not limit the interpretation of this disclosure.

[0036] In the descriptions of the first and second embodiments, the semiconductor wafer is a SiC (silicon carbide) wafer, but the method can also be applied to semiconductor wafers other than SiC wafers. Examples of semiconductor wafers other than SiC wafers include GaN (gallium nitride) wafers, AlN (aluminum nitride) wafers, or diamond wafers.

[0037] [First Embodiment] Figure 8 shows an example of the overall system configuration according to the first embodiment of this disclosure.

[0038] In the second entity, a surface device step and a wafer splitting step are performed. The second entity may be a company acting as a device manufacturer that extracts SiC chips from the SiC wafer 40 and provides SiC chips or devices having SiC chips. The SiC wafer 40 is broadly divided into a layer as a base SiC crystal and a layer as a grown SiC crystal (oriented SiC crystal).

[0039] In the surface device step, a device is formed on the first main surface (surface) of the SiC wafer 40 (corresponding to the surface of the SiC wafer 10 on the SiC growth layer 14 side). The device may include electrodes and wiring patterns.

[0040] In the wafer splitting step, the SiC wafer 40 having the device is split along the planar direction (a direction perpendicular to the thickness direction, in other words, a direction parallel to the first main surface). In this wafer splitting step, the SiC wafer 40 is split along the planar direction by a method called laser slicing using a laser device, for example. Specifically, for example, the laser device irradiates a peel-promoting region 116 that has been pre-formed inside the SiC wafer 40 from the second main surface (back surface) side of the SiC wafer 40 (corresponding to the surface of the SiC seed crystal layer 12 of the SiC wafer 10) with laser light (for example, a pulsed laser). As a result, a modified layer is formed in the peel-promoting region 116 (particularly the peel-promoting layer), and starting from this modified layer, the SiC wafer 40 is split into a main wafer portion 111, which is the SiC wafer portion having the first main surface, and a remaining wafer portion 112, which is the SiC wafer portion having the second main surface.

[0041] In laser slicing, the peeling-promoting layer in the peeling-promoting region 116 within the SiC wafer 40 irradiated with laser light is a layer that is more easily peeled than other parts due to an incomplete SiC crystal structure or other reasons. By irradiating this peeling-promoting region 116 (especially the peeling-promoting layer) with laser light to create a modified layer, and then dividing the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 along the peeling-promoting region 116, starting from this modified layer, the wafer can be divided (peeled) more easily than when other parts are used as the modified layer. Possible reasons for this include, for example, the peeling-promoting region 116 (especially the peeling-promoting layer) having an incomplete crystal structure and weaker interatomic bonding compared to other parts. It is also possible that the peeling-promoting region 116 (especially the peeling-promoting layer) readily absorbs laser light, thus facilitating the formation of a modified layer. While various other factors may be involved, regardless of the cause, by peeling off the portion including the first main surface from the SiC wafer 40 starting from the peeling-promoting region 116 (especially the peeling-promoting layer), the SiC wafer 40 can be divided into the main wafer 111 and the remaining wafer 112 with less force. This suppresses the generation of distortion during peeling in the device formation portion of the main wafer 111, thereby preventing the occurrence of cracks and fractures.

[0042] The peel-promoting region 116 is formed within the SiC wafer 40 when the SiC wafer 40 is manufactured in a first entity different from the second entity. This method will be described later.

[0043] In addition, during the wafer splitting step, the SiC wafer 40 may be split into a main wafer 111 and a remaining wafer 112 by a method other than laser slicing. For example, the SiC wafer 40 can be split into a main wafer 111 and a remaining wafer 112 by etching away the peeling promotion region 116 in the SiC wafer 40. In this case, electrolytic etching, chemical etching, thermal etching, etc., can be used for etching. By performing the wafer splitting step by etching in this way, the SiC wafer 40 can be split into a main wafer 111 and a remaining wafer 112 without using a laser device. Furthermore, peeling can also be performed using ultrasound, known as sonic lift-off. Specifically, by using sound waves to split the SiC wafer 40 into a main wafer 111 and a remaining wafer 112, the peeled surfaces of the main wafer 111 and the remaining wafer 112 can be made flat and smooth, thus eliminating material waste and allowing the remaining wafer 112 to be reused, thereby reducing wafer manufacturing costs. In addition to the above, it is possible to divide the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 by processing the peeling-promoting region 116 formed within the SiC wafer 40 using any method.

[0044] In the first entity, the acquisition step, processing step, pre-processing step, growth step, patterning evaluation step, and wafer provision step are performed (in this embodiment, an inspection step is also performed between the acquisition step and the processing step, as will be described later). The first entity is a company that provides a new service, that is, a company that acquires (recovers) the remaining wafer 112 of the SiC wafer 40 from the second entity, grows a grown SiC crystal on the remaining wafer 112 to regenerate the SiC wafer 40, and provides the regenerated SiC wafer 40 to the same or a different second entity. There is one or more second entities for each first entity. Note that the wafer splitting step described above may be performed in the first entity instead of the second entity.

[0045] In the acquisition step, the remaining wafer 112 is acquired from the second entity. In the processing step, the slice surface of the remaining wafer 112 is processed to acquire a seed crystal 113a made of SiC single crystal material.

[0046] In the pretreatment step, an inhibitory region is formed on or near the surface of the seed crystal 113a obtained in the processing step, or a seed crystal 113b made of newly prepared SiC single crystal material, which partially disrupts or inhibits the SiC crystal structure. This pretreatment is performed on the seed crystals 113a and 113b to form the aforementioned peeling-promoting region 116, and a pretreated seed crystal 114 is obtained. Details of the pretreatment step will be described later.

[0047] In the growth step, a new SiC wafer 40 is manufactured by growing a growth SiC crystal (an example of a semiconductor crystal layer) 115 on the surface of the seed crystal 114 obtained in the pretreatment step. Inside the SiC wafer 40 manufactured here, a peeling-promoting region 116 is formed by the inhibiting region formed on the seed crystal 114 in the pretreatment step.

[0048] In the wafer supply step, the SiC wafer 40 obtained in the growth step is provided to a second entity that is the same as or different from the source from which the remaining wafer 112 was obtained.

[0049] In conventional processes not to which this disclosure applies, the portion of the SiC wafer 40 corresponding to the remaining wafer 112 is ground without separating it from the main wafer 111, and the resulting grinding waste is discarded. In contrast, in this embodiment, the remaining wafer 112 is separated from the main wafer 111 and recovered without being discarded as grinding waste, and this is recycled into a new semiconductor wafer by the first entity and provided to the second entity. In the second entity, after forming a device on the semiconductor wafer provided by the first entity (SiC wafer 40 recycled from the remaining wafer 112), the main wafer 111 and the remaining wafer 112 are separated. The remaining wafer 112 is recovered by the first entity and used as a seed crystal 114 to form a grown SiC crystal together with the peeling-promoting region 116, and is then used again as SiC wafer 40. By repeating this process, the portion of the SiC wafer 40 that was conventionally ground or discarded, namely the remaining wafer 112, can be reused. In this disclosure, the reuse of expensive SiC wafers is made possible, thereby reducing the manufacturing cost of devices. Furthermore, since waste can be significantly reduced throughout the entire SiC wafer manufacturing process, including high-temperature processes, it is also possible to reduce the environmental impact.

[0050] The processing step may be performed by the processing device 172, the pretreatment step may be performed by the pretreatment device 173, and the growth step may be performed by the growth device 174 (the inspection step described later may be performed by the inspection device 171).

[0051] Below, we will first describe the acquisition step, processing step, pretreatment step, growth step, patterning evaluation step, and wafer provision step among the steps in the first entity, and then describe the inspection step.

[0052] <Acquisition Step> In the acquisition step, the remaining wafers 112 are acquired from one or more second entities. Any number of remaining wafers 112 may be sent to the first entity at any time the second entity has chosen, or an acquisition schedule, including the number of remaining wafers 112 to be acquired from each of the one or more second entities and the acquisition timing, may be shared between the second entity and the first entity, and the remaining wafers 112 may be acquired from the second entity according to the acquisition schedule. Note that if the wafer splitting step is performed by the first entity, the acquisition step is unnecessary.

[0053] <Processing Step> The processing in the processing step includes removing the slice surface (typically grinding and / or polishing) and removing the processed altered layer including the removed slice surface. The processing apparatus 172 may include, for example, an apparatus for grinding and / or polishing the slice surface (e.g., a grinder) and an apparatus for removing the processed altered layer, and these apparatuses may be a single apparatus (i.e., grinding and removal may be performed by one apparatus). For example, the processing apparatus 172 may be an apparatus for grinding and polishing such as the CMP (Chemical Mechanical Polishing) method.

[0054] In the processing step, a seed crystal 113a is obtained as a result of processing the remaining wafer 112. The seed crystal 113a may be composed mainly of the underlying SiC crystal, or it may be composed of the underlying SiC crystal and some oriented SiC crystal. Alternatively, instead of the seed crystal 113a, a new SiC single crystal material may be prepared and used as the seed crystal 113b.

[0055] <Pre-treatment step> In the pre-treatment apparatus 173, inhibitory regions are formed on or near the surface of the seed crystals 113a and 113b, which partially disrupt or inhibit the formation of the crystal structure when growing the SiC crystal in the next growth step. Due to the presence of these inhibitory regions, peel-promoting regions 116 (particularly a peel-promoting layer) that are more easily peeled off than other parts are formed inside the SiC wafer 40 manufactured from the seed crystals 113a and 113b in the growth step. Specifically, for example, the pre-treatment apparatus 173 forms inhibitory regions on the seed crystals 113a and 113b by performing one of the processing treatments described in Figures 9 to 11 below as a pre-treatment.

[0056] Figure 9 is an explanatory diagram of the pretreatment for forming a layer containing minute voids in the peel-promoting region 116. In Figure 9, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0057] In the pretreatment step, for example as shown in Figure 9(b), pulsed laser light from a laser 201, which is a pretreatment device 173, is irradiated onto the surface of the seed crystal 113a in a grid pattern, preferably at intervals of 0.5 to 15.0 μm, thereby forming laser-processed grooves 202 on the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with these grooves 202 formed on it is used as a pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form grown SiC crystals 115. As a result, for example as shown in Figure 9(c), voids formed by the grooves 202 occur at regular intervals between the seed crystal 114 and the grown SiC crystal 115, and because the crystal structure is partially divided by these voids, peel-promoting regions 116 are formed along the voids as layers that are easily peeled off. In this way, a SiC wafer 40 having a peeling-promoting region 116 between the first main surface 40a on the front side (the side with the growing SiC crystal 115) and the second main surface 40b on the back side (the side with the seed crystal 114) is manufactured.

[0058] Furthermore, it is preferable that the grooves 202 formed on the surface of the seed crystal 113a in the pretreatment step have a maximum depth of 1 μm or more. In this way, it is possible to form a peel-promoting region 116 in the region including the grooves 202 while sufficiently growing the SiC crystal in the growth step.

[0059] Figure 10 is an explanatory diagram of the pretreatment for forming a layer containing a substance for promoting delamination (hereinafter referred to as "delamination promoting substance") in the delamination promoting region 116. In Figure 10, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0060] In the pretreatment step, a pattern mask with a predetermined opening pattern is formed on the surface of the seed crystal 113a. Then, as shown in Figure 10(b), for example, fine particles 211 mainly composed of carbon are dispersed in the unmasked areas on the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the fine particles 211 dispersed on its surface is used as the pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form grown SiC crystals 115. As a result, as shown in Figure 10(c), for example, fine particles 211 are sandwiched in places between the seed crystal 114 and the grown SiC crystal 115, and because the formation of the crystal structure is inhibited by these fine particles 211, peel-promoting regions 116 (particularly the peel-promoting layer) are formed as layers with an incomplete crystal structure. In this way, a SiC wafer 40 having a peeling-promoting region 116 between the first main surface 40a on the front side (the side with the growing SiC crystal 115) and the second main surface 40b on the back side (the side with the seed crystal 114) is manufactured.

[0061] Furthermore, the carbon-based fine particles 211 dispersed on the surface of the seed crystal 113a in the pretreatment step are preferably graphite or diamond fine particles with a particle size of 10 μm or less. In this way, it is possible to sufficiently grow the SiC crystal in the growth step while forming a peel-promoting region 116 in the region containing the fine particles 211.

[0062] Figure 11 is an explanatory diagram of a pretreatment for forming a layer containing a different peel-promoting substance in the peel-promoting region 116 than that shown in Figure 10. In Figure 11, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0063] In the pretreatment step, a pattern mask with a predetermined opening pattern is formed on the surface of the seed crystal 113a. Then, as shown in Figure 11(b), for example, ions 221 are injected from the surface into the unmasked region of the seed crystal 113a. Specifically, for example, ions 221 generated by an ion source are accelerated and injected from the outside toward the surface of the seed crystal 113a, thereby injecting and dispersing the ions 221 near the surface of the unmasked region of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the ions 221 dispersed inside is used as the pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form the grown SiC crystal 115. As a result, as shown in Figure 11(c), for example, ions 221 are arranged in places near the boundary between the seed crystal 114 and the grown SiC crystal 115, and because the formation of the crystal structure is inhibited by these ions 221, a peel-promoting region 116 (particularly a peel-promoting layer) is formed as a layer with an incomplete crystal structure. In this way, a SiC wafer 40 having a peel-promoting region 116 between the first main surface 40a on the front side (grown SiC crystal 115 side) and the second main surface 40b on the back side (seed crystal 114 side) is manufactured. In the subsequent wafer splitting step, if the peel-promoting region 116 in the SiC wafer 40 is to be removed by etching as described above, it is preferable to form the peel-promoting region 116 using the method described in Figure 11.

[0064] Furthermore, it is preferable to use one or more ions from among Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements as the ions 221 implanted into the seed crystal 113a in the pretreatment step. In this way, it is possible to sufficiently grow the SiC crystal in the growth step while forming a peel-promoting layer in the region containing the ions 221.

[0065] Figure 11 also serves as an explanatory diagram of the pretreatment for forming an amorphous portion in the peel-promoting region 116. In the pretreatment step, after forming a predetermined pattern on the surface of the seed crystal 113a with a mask, ions 221 are injected from the surface into the unmasked region of the seed crystal 113a, as shown in Figure 11(b). Specifically, ions 221 generated by an ion source are accelerated and injected from the outside toward the surface of the seed crystal 113a, thereby injecting and dispersing the ions 221 near the surface of the unmasked region of the seed crystal 113a. Next, incident light of a specific wavelength (e.g., laser light) is irradiated onto the entire wafer from the second main surface 40b. In the subsequent growth step, the seed crystal 113a with the ions 221 dispersed inside is used as the pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form the grown SiC crystal 115. As a result, as shown in Figure 11(c), for example, ions 221 are arranged in places near the boundary between the seed crystal 114 and the grown SiC crystal 115, and because the formation of the crystal structure is inhibited by these ions 221, a peel-promoting region 116 (particularly a peel-promoting layer) is formed as a layer with an incomplete crystal structure. In this way, a SiC wafer 40 having a peel-promoting region 116 between the first main surface 40a on the front side (grown SiC crystal 115 side) and the second main surface 40b on the back side (seed crystal 114 side) is manufactured. In the subsequent wafer splitting step, if the peel-promoting region 116 in the SiC wafer 40 is to be removed by etching as described above, it is preferable to form the peel-promoting region 116 using the method described in Figure 11.

[0066] Furthermore, the same ions as described above can be used as the ions 221 that are implanted into the seed crystal 113a in the pretreatment step.

[0067] In the pretreatment step, seed crystal 114 is obtained by performing one of the pretreatments described above on seed crystals 113a and 113b using the pretreatment device 173. Although Figures 9 to 11 illustrate an example of performing pretreatment on seed crystal 113a obtained in the processing step, the same pretreatment can be performed on a newly prepared seed crystal 113b to obtain seed crystal 114.

[0068] <Growth Step> In the growth apparatus 174, a grown SiC crystal (oriented SiC crystal) 115 is grown on the seed crystal 114 with a thickness of 50 μm or more. Such crystal growth may be carried out by sublimation or CVD (Chemical Vapor Deposition), or by other methods. As a result, as explained in Figures 9 to 11, a new SiC wafer 40 is obtained, which consists of a seed crystal 114, which is a crystalline layer made of a single-crystal material of SiC, and a grown SiC crystal 115, which is a crystalline layer of SiC formed on the seed crystal 114, and has a peel-promoting region 116 between the first main surface 40a on the grown SiC crystal 115 side and the second main surface 40b on the seed crystal 114 side. In this SiC wafer 40, the peel-promoting region 116 (particularly the peel-promoting layer) formed on at least one of the seed crystal 114 and the grown SiC crystal 115 contains voids due to grooves 202 or an incomplete crystalline structure due to fine particles 211 or ions 221.

[0069] Furthermore, it is preferable that the peeling acceleration region 116 (and the peeling acceleration layer) is formed within a range of 30 μm or less in the thickness direction (up and down direction in the figure) perpendicular to the first main surface 40a and the second main surface 40b, as illustrated in Figure 10(c). Specifically, it is preferable that when the cross-section of the SiC wafer 40 in the thickness direction is observed at any position including the peeling acceleration region 116, the thickness of the peeling acceleration region 116 (and the thickness of the peeling acceleration layer) at that cross-section is 30 μm or less. In this way, the thickness of the peeling acceleration region 116 can be made thinner than the height of the unevenness of the slice surface that occurs when a conventional SiC wafer without a peeling acceleration region 116 is divided by laser slicing (generally about 50 μm), thereby reducing the amount of grinding debris generated in the processing step and reducing the amount of SiC waste. Furthermore, as shown in Figures 9 to 11, the peeling acceleration region 116 is a part of the seed crystal 114 or the grown SiC crystal 115.

[0070] Furthermore, in the peel-promoting region 116, as illustrated in Figures 9(c) and 10(c), it is preferable that regions containing peel-promoting substances consisting of voids formed by grooves 202, or fine particles 211 or ions 221 (i.e., peel-promoting layers) are distributed at intervals of 0.5 to 15.0 μm in the planar direction parallel to the first main surface 40a and the second main surface 40b (left-right direction in the figure). In other words, it is preferable that the separation distance between adjacent peel-promoting layers is 0.5 to 15.0 μm. It is also preferable that the width of the peel-promoting layer is 0.5 to 15.0 μm. In this way, it is possible to suppress unintended peeling of the wafer in each process related to the wafer, other than the splitting step.

[0071] Figures 12A to 12C show examples of cross-sections when the SiC wafer 40 shown in Figure 9(c) is cut by a plane parallel to the first main surface 40a and passing through at least a portion of the peeling acceleration region 116. Figure 12A shows an example of a cross-section when the peeling acceleration region 116 is formed over the entire surface in the planar direction at a predetermined depth within the SiC wafer 40. Figure 12B shows an example of a cross-section when the peeling acceleration region 116 is formed over the entire circumference of the region near the outer edge within the SiC wafer 40. Figure 12C shows an example of a cross-section when the peeling acceleration region 116 is partially formed in the region near the outer edge within the SiC wafer 40. Note that the peeling acceleration region 116 may be formed in arrangements other than those shown.

[0072] As shown in the examples above, the peel-promoting region 116 may be formed over the entire surface in the planar direction when the SiC wafer 40 is viewed from the direction of the first main surface 40a, or it may be formed only in a part of the region. However, the peel-promoting layer included in the peel-promoting region 116 is formed in a predetermined pattern.

[0073] <Patterning Evaluation Step> In order to evaluate whether a peel-promoting layer has been formed along a predetermined pattern by the pretreatment step, at least one of the following evaluations (A), (B), and (C) may be performed depending on the composition of the peel-promoting layer.

[0074] (A) Patterning evaluation of the peeling-promoting layer containing peeling-promoting substances If the peeling-promoting layer contains peeling-promoting substances, the concentration of the elements constituting the peeling-promoting substances may be measured by a secondary ion mass spectrometer (SIMS). For example, the SiC wafer 40 may be cut in the in-plane direction on a plane containing a peeling-promoting region 116 parallel to the first main surface 40a, and then chemical mechanical polishing (CMP) may be performed. The concentration of the elements constituting the peeling-promoting substances in the peeling-promoting region 116 exposed by CMP can be measured using a secondary ion mass spectrometer (SIMS), and 2D imaging can be performed to evaluate whether the peeling-promoting layer is distributed along a predetermined pattern.

[0075] (B) Patterning evaluation of peel-promoting layer containing amorphous portion If the peel-promoting layer contains an amorphous portion, the crystallinity of the peel-promoting layer may be evaluated using a Raman spectrometer. For example, after cutting a small piece from the SiC wafer 40, the cross-section of the small piece is polished. By performing Raman spectroscopy on an arbitrary position in this cross-section that includes the peel-promoting layer and evaluating the crystallinity of the peel-promoting layer, it is possible to evaluate whether the peel-promoting layer is distributed along a predetermined pattern.

[0076] (C) Patterning evaluation of peel-promoting layer containing voids If the peel-promoting layer contains voids, the peel-promoting layer may be observed using a scanning electron microscope (SEM). For example, after cutting a small piece from the SiC wafer 40, the cross-section of the small piece is polished. By observing any position containing the peel-promoting layer in this cross-section with an SEM, it is possible to evaluate whether the peel-promoting layer is distributed along a predetermined pattern.

[0077] <Wafer Provision Step> A new SiC wafer 40, composed of a seed crystal 114 and a grown SiC crystal 115, is provided to a second entity that is the same as or different from the source from which the remaining wafer that forms the basis of the SiC wafer was obtained. In this way, the acquired remaining wafer 112 is regenerated into such a new SiC wafer 40 and provided to the second entity, so the second entity can obtain a main wafer from that SiC wafer 40.

[0078] The above describes the acquisition step, processing step, pretreatment step, growth step, patterning evaluation step, and wafer provision step.

[0079] In this embodiment, an inspection step is included between the acquisition step and the processing step to inspect the slice surface of the acquired remaining wafer 112. The inspection step is, for example, as follows:

[0080] <Inspection Step> The inspection step includes measuring at least one of the following: the height difference of the slice surface and the thickness of the processed altered layer having the slice surface. In this embodiment, both are measured. The height difference of the slice surface is the height difference caused by the surface irregularities resulting from the laser irradiation or the separation of the main wafer 111 and the remaining wafer 112 in the wafer splitting step.

[0081] The inspection step is performed by the inspection device 171. The inspection device 171 may include a laser microscope and a Raman spectrometer. The height difference of the slice surface may be measured using the laser microscope. The thickness of the processed altered layer may be measured using the Raman spectrometer. The measurement methods for both the height difference of the slice surface and the thickness of the processed altered layer are not limited to this example. For example, the height difference of the slice surface may be measured using a white light interferometer or a contact-type shape measuring instrument.

[0082] At least one of the following (x) and (y) may be performed. (x) The processing in the processing step includes determining the amount to remove from the slice surface based on at least one of the measured height difference of the slice surface of the acquired remaining wafer 112 and the measured thickness of the processed altered layer, and removing material from the slice surface according to the determined amount. This allows for appropriate (with minimal excess or deficiency) slicing of the slice surface according to the quality (condition) of the acquired remaining wafer 112. For example, if the PV value (maximum valley depth) is measured as an example of the height difference of the slice surface, and the processing altered layer depth is measured as an example of the thickness of the processed altered layer, then the amount to remove = PV value + (processed altered layer depth × N). N may be any value greater than 0 (for example, any natural number). A processing command associated with information representing the amount to remove may be input to the processing device 172 (or the control device of the processing device 172), and the processing device 172 may perform slicing according to that amount. The "amount of material removed" may be defined by parameter values ​​for each of one or more parameter items. Examples of parameter items include the processing time and processing power (e.g., temperature and pressure) of the processing apparatus 172. (y) In the growth step, the thickness of the growing SiC crystal to be grown is determined based on at least one of the measured height difference of the slice surface of the remaining wafer 112 and the measured thickness of the processed altered layer, and the growing SiC crystal is grown to the determined thickness. This allows for appropriate (with minimal excess or deficiency) crystal growth according to the quality (condition) of the acquired remaining wafer 112. For example, the thickness to be grown may be determined based on at least one of X, Y, Z, and α. Specifically, for example, the thickness to be grown may be X - Y + Z + α. X may be the thickness required at the start of the surface device step or wafer splitting step in the second entity (the thickness requested by the second entity). Y may be the thickness of the growing SiC crystal when received by the first entity. Z can be the amount of material removed as determined in (x) above. α can be any value determined as the machining margin (for example, about 50 μm) to remove the irregularities after growth and flatten the surface.A crystal growth command, associated with information indicating the thickness to be grown, may be input to the growth apparatus 174 (or the control device for the growth apparatus 174), thereby causing the growth apparatus 174 to grow a SiC crystal of that thickness on the seed crystal.

[0083] [Second Embodiment] The second embodiment will now be described. In this description, the differences from the first embodiment will be explained, and the similarities with the first embodiment will be omitted or simplified.

[0084] In the second embodiment, crystal growth in the growth step is carried out using the method disclosed in the prior application Patent Document 2 (WO2023 / 067736A1) by the same applicant as the present application (hereinafter, this method will be conveniently referred to as the "NGK method" based on the applicant's notation). That is, in the growth step, a SiC single crystal as a seed crystal and a SiC powder layer are placed in a container in contact with each other, and the container is placed in a firing furnace and heat treatment is performed, thereby growing a SiC single crystal on the seed crystal. According to the NGK method, it is possible to obtain a SiC single crystal (grown SiC crystal) with a lower BPD density than the sublimation method and a BPD density of about the same as that of the CVD method. The second embodiment can utilize all or part of the technology disclosed in Patent Document 2.

[0085] Furthermore, when crystal growth is performed using the NGK method, the flatness of the processed surface does not need to be as high as when crystal growth is performed using the sublimation or CVD methods, and the processed surface does not need to be perfectly flat. Specifically, for example, the following applies:

[0086] When homoepitaxial growth is performed on a seed crystal using sublimation or CVD, it is usually essential that the growth surface is atomically flat and that there is no processed or altered layer. This is because irregularities can form on the epitaxial growth surface, or defects such as dislocations can be introduced into the crystal.

[0087] On the other hand, because SiC wafers are hard and stable against heat and chemicals, surface planarization and removal of processing damage using the CMP method after slicing or grinding is extremely time-consuming, and the consumption of polishing slurry and polishing pads is also high.

[0088] Therefore, in this embodiment, in the processing step, the removal of the processed altered layer is performed by a thermal etching process, a surface oxidation process, or a plasma etching process (i.e., any process that results in a lower degree of flatness after etching than etching by the CMP method). Below, examples of each process for removing the processed altered layer in the processing step of the second embodiment will be described. In this embodiment, etching other than the thermal etching process, surface oxidation process, and plasma etching process, such as etching by the CMP method, or etching by other etching processes (e.g., hydrogen etching) may be performed.

[0089] Figure 13 schematically illustrates the thermal etching process.

[0090] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a thermal etching process. This apparatus is illustrated in Figure 13. In the thermal etching process, the surface of the remaining wafer (including the processed altered layer) that has been heated and processed in the electric furnace 302 is sublimated to a thickness of several micrometers.

[0091] For example, gas (such as nitrogen or argon, an inert gas) is introduced into an electric furnace 302, which is made of insulating material and equipped with a heater 301, through a gas pipe 305, creating an inert gas atmosphere inside the electric furnace 302. The electric furnace 302 may also be under vacuum.

[0092] The material is heated by heater 301, but the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 1000 to 2000°C), and may be set taking into account the required amount of etching (for example, 1800°C may be set). The holding time at the maximum temperature is a time within a certain time range (for example, 1 minute to 5 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0093] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 303 (for example, graphite) on a spacer 304 (for example, graphite), or it may be placed using a sheath or the like made of a heat-resistant material.

[0094] If the surface of the remaining wafer 112 is carbonized after this thermal etching process, the carbonized layer on the surface may be removed by annealing in an atmospheric furnace or the like, or by polishing or other processing. To prevent surface carbonization, a carbon getter material such as Ta may be placed inside the electric furnace 302.

[0095] Figure 14 schematically illustrates the surface oxidation process.

[0096] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a surface oxidation process. This apparatus is illustrated in Figure 14. In the surface oxidation process, the surface of the remaining wafer (including the processed altered layer) that has been processed by heating in an oxidizing atmosphere (including an air atmosphere) in an electric furnace 402 is oxidized to a thickness of several micrometers. The oxide film may be removed by processing such as polishing, or it may be volatilized or melted (reacted with the raw material powder) during crystal growth.

[0097] For example, in an electric furnace 402 made of insulating material and equipped with a heater 401, the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 800 to 2000°C), and may be set taking into account the required amount of etching (for example, 1400°C may be set). Also, the holding time at the maximum temperature is a time within a certain time range (for example, 5 minutes to 50 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0098] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 403 (for example, alumina) on a spacer 404 (for example, alumina).

[0099] Figure 15 schematically illustrates the plasma etching process.

[0100] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a plasma etching process. This apparatus is an example of the apparatus shown in Figure 15. In the plasma etching process, the surface of the remaining processed wafer (including the processed altered layer) is etched to a thickness of several micrometers.

[0101] Plasma etching includes methods such as RIE (Reactive Ion Etching), ECR (Electron Cyclotron Resonance), ICP (Inductively Coupled Plasma), and CCP (Capacitively Coupled Plasma), but there are no particular limitations; for example, RIE can be applied.

[0102] The substrate temperature, gas type, processing time, and apparatus configuration may be set as appropriate depending on the desired etching rate and surface condition. The remaining wafer surface may be pre-treated by ashing or other methods to remove any surface deposits.

[0103] An upper electrode 501 and a lower electrode 503 are located in the chamber 502. Gas is introduced from the gas introduction pipe 505 and exhausted from the gas exhaust pipe 504, and plasma is generated between electrodes 501 and 503 by the high-frequency power supply 509s.

[0104] The above is an explanation of examples of each process related to the removal of the processed altered layer in the processing step according to the second embodiment. Furthermore, there are differences between the sublimation method, CVD method and the NGK method regarding crystal growth, for example, as follows.

[0105] In other words, while sublimation and CVD methods require precise cleaning after CMP polishing and before epitaxial layer formation, the NGK method does not require such cleaning.

[0106] Furthermore, in sublimation and CVD methods, the rapid heating rate increases the likelihood of seed crystal warping and subsequent breakage. Also, in sublimation and CVD methods, multiple seed crystals can be placed in the growth chamber, but if even one seed crystal is damaged, it will affect the others. On the other hand, in the NGK method, the heating rate is slower than in sublimation and CVD methods, so even if the seed crystal is slightly warped, the likelihood of breakage due to that warping is low. In addition, in the NGK method, one seed crystal is stored in each container, so even if one seed crystal is damaged, it will not affect the others.

[0107] Furthermore, in both the second and first embodiments, the diameter of the remaining wafer 112 acquired in the acquisition step may be 6 inches or more, and for example, the diameter of the remaining wafer may be 8 inches or more (for example, in the second embodiment). For example, in both cases where the diameter is 6 inches or 8 inches, the thickness of the main wafer 111 may be about 100 μm, but in the case of a 6-inch diameter, the thickness of the remaining wafer 112 may be about 250 μm, and in the case of an 8-inch diameter, the thickness of the remaining wafer 112 may be about 400 μm.

[0108] The present invention will be further described in detail by the following examples. However, the present invention is not limited to the following examples.

[0109] Example 1 (1) Pretreatment As shown in Figure 11(a), a commercially available disc-shaped SiC single crystal substrate (4H-SiC, diameter 150 mm (6 inches), off-angle 4°, thickness 0.35 mm) was prepared as a seed crystal 113a. A pattern mask 20 with a triangular opening pattern 20a as shown in Figure 2 was formed on the crystal growth surface of this SiC single crystal substrate by photolithography patterning. As shown in Figure 11(b), hydrogen ions (corresponding to the peeling accelerator) were implanted as ions 221 into the SiC single crystal substrate in order to form a peeling accelerator layer, which will be described later. The hydrogen ion implantation conditions at this time were an acceleration voltage of 170 keV and an implantation dose of 8.0 × 10 １５ ions / cm ２ The temperature was 500°C. After hydrogen ion implantation, the pattern mask was removed with a resist stripping solution.

[0110] (2) Preparation of SiC mixed powder Commercially available β-SiC powder (volume-based D50 particle size: 65.0 μm) and an oxide (SiO₂) which is a liquid phase formation aid ２ The oxides (D50 particle size based on volume: 0.5 μm) were weighed so that the oxide content relative to the SiC powder content was 8.1% by weight, and then placed in a polypropylene container along with pebbles and water. After placing the polypropylene container on a pot stand, the container was rotated at a speed of 50 rpm to mix the raw materials. The slurry obtained by mixing the raw materials was dried in a dryer and collected to obtain SiC mixed powder.

[0111] (3) Arrangement of SiC mixed powder and seed crystal The SiC single crystal substrate, which is the seed crystal 113a pretreated in (1) above, and the SiC mixed powder prepared in (2) above were placed in a graphite container.

[0112] (4) Heat treatment The graphite container prepared in (3) above was placed in a location in the resistance furnace (firing furnace) where the temperature range was within ±75°C of the set temperature, and heat treatment was performed for 20 hours at a set temperature of 2450°C in a mixed gas atmosphere of argon and nitrogen (the partial pressure of nitrogen gas was calculated to be 0.0003 atm). As a result, as shown in Figure 1 (see also Figure 11(c)), a SiC single crystal was grown on the SiC single crystal substrate, and a SiC growth layer 14 was provided on the SiC seed crystal layer 12, and a peel-promoting layer 16 (region R including the peel-promoting layer 16) was formed in a predetermined pattern inside the SiC seed crystal layer 12. １ A SiC wafer 10 containing ) was obtained.

[0113] (5) Measurement of the crystal growth thickness of the SiC wafer The thickness of 25 arbitrary locations on the SiC wafer 10 obtained in (4) above was measured with a micrometer, and the arithmetic mean was calculated. The thickness of the seed crystal 113a was also calculated at the time of (3) above using the same method. Then, the crystal growth thickness (μm) of the SiC growth layer 14 was calculated by subtracting the arithmetic mean of the thickness of the seed crystal 113a from the arithmetic mean of the thickness of the SiC wafer 10. As a result, it was confirmed that the crystal growth thickness of the SiC growth layer 14 was 100 μm or more.

[0114] (6) Polishing The surface (Si surface and C surface) of the SiC wafer 10 obtained in (4) above was polished using diamond abrasive grains, and then chemical mechanical polishing (CMP) was performed.

[0115] (7) Device fabrication process A SiC-MOSFET device was formed on the SiC growth layer 14 of the polished SiC wafer 10 obtained in (6) above.

[0116] (8) Thickness measurement of the peeling-promoting layer In the SiC wafer 10 on which the SiC-MOSFET device obtained in (7) is formed, the layer of the SiC-MOSFET device is removed from the surface on the SiC growth layer 14 side (first main surface 40a), and the surface of the SiC seed crystal layer 12 (second main surface 40b) is polished to a predetermined thickness, thereby determining the hydrogen ion (peeling-promoting substance) concentration (atoms / cm³) at a depth position corresponding to that thickness. ３ The hydrogen ion concentration at each depth was measured. This measurement was performed at approximately 1 μm intervals from the second main surface 40b after the device layer removal, at depths of 310 to 370 μm in the thickness direction. １８ atoms / cm ３ By considering the depth position where this occurs as the region where the peel-promoting layer 16 exists, the thickness d of the peel-promoting layer 16 is determined. ２ The (μm) was calculated. Dynamic secondary ion mass spectrometry (D-SIMS) was used to measure the hydrogen ion concentration. For this D-SIMS measurement, a CAMECA IMF-6f analyzer was used, and the primary ion species was Cs ＋ The experiment was also conducted under the condition of an acceleration voltage of 15.0 kV. The results are shown in Table 1A.

[0117] (9) Evaluation of the patterning of the surface of the peel-promoting layer A 5 mm wide x 5 mm long SiC wafer piece was cut from the center of the SiC wafer 10 obtained in (7) above after device formation. The cross-section of the cut SiC wafer piece was polished using diamond abrasive grains and then chemically mechanically polished (CMP). The cross-section of this SiC wafer piece was observed with a fluorescence microscope (Nikon Corporation, ECLIPSE LV100D) at a field of view of 700 μm x 500 μm and a magnification of 200x, and the distance d from the surface of the SiC seed crystal layer 12 (second main surface 40b) to the interface between the SiC seed crystal layer 12 and the peel-promoting layer 16 was determined. １ The (μm) was measured. For the cut SiC wafer small piece, the distance d from the Si surface (surface of the SiC seed crystal layer 12) was measured. １ After mechanical polishing, the peel-accelerating layer 16 was exposed on the surface of the SiC growth layer 14 by chemical mechanical polishing (CMP) using diamond abrasive grains. The region R on this surface, including the peel-accelerating layer 16, is then exposed. １ region R that does not include the peel-promoting layer 16 ２ Within any 5 mm x 5 mm area including any of the above, a two-dimensional high-resolution secondary ion mass spectrometer (NanoSIMS) is used to analyze the peeling-promoting substance (H ＋ The concentration was measured and 2D imaging was performed. For this NanoSIMS measurement, a CAMECA Nano-SIMS 50L was used as the analyzer, and the primary ion species Cs ＋ The procedure was also performed under the condition of an acceleration voltage of 8000 kV. From the obtained imaging images, H ＋ By observing the shape of the region where the substance was detected, it was confirmed whether the peel-promoting layer 16 was formed in a predetermined pattern (triangular shape), that is, whether multiple spaced-apart constituent units (triangular portions) were formed. Furthermore, the inscribed circles C in any five constituent units among the multiple constituent units were examined. Ｉ Diameter (μm) and circumscribed circle C Ｃ The diameter (μm) was measured, and their arithmetic mean was calculated. This confirmed whether the peel-promoting layer 16 was formed along the patterning described in (1) above. The results are shown in Table 1D.

[0118] (10) Evaluation of the patterning of the cross-section of the peel-promoting layer Ten small pieces of SiC wafer measuring 5 mm horizontally x 5 mm vertically with different cross-sections were cut from the center of the SiC wafer 10 obtained in (7) above after device formation. The cross-sections of the cut SiC wafer pieces were polished using diamond abrasive grains and then chemically mechanically polished (CMP). In the cross-section of the SiC wafer pieces, the peel-promoting substance (H) was evaluated using a two-dimensional high-resolution secondary ion mass spectrometer (NanoSIMS). ＋ The concentration was measured and 2D imaging was performed. For this NanoSIMS measurement, a CAMECA Nano-SIMS 50L was used as the analyzer, and the primary ion species Cs ＋ The procedure was also performed under the condition of an acceleration voltage of 8000 kV. From the obtained imaging images, H ＋ The width (μm) of the region where H is detected (exfoliation promoting layer 16), and the adjacent H ＋ The separation distance (μm) between the regions where the substance was detected (exfoliation promoting layer 16) was measured at multiple locations (for example, 5 locations), and the average values ​​of the above width and separation distance were calculated for each of the 10 SiC wafer pieces. The average values ​​of the above widths for the 10 SiC wafer pieces were arranged in descending order of value, and the median of these values ​​was used as the width d of the exfoliation promoting layer 16. ３ Similarly, the average values ​​of the above separation distances were arranged in ascending order, and the median of these values ​​was used as the separation distance d between adjacent peel-promoting layers 16. ４ The results are shown in Table 1A.

[0119] (11) Analysis of impurity concentration In the SiC wafer 10 on which the SiC-MOSFET device obtained in (7) above is formed, the layer of the SiC-MOSFET device is removed from the surface on the SiC growth layer 14 side (first main surface 40a), and the first main surface 40a is polished to a predetermined thickness, thereby determining the nitrogen atom concentration (atoms / cm³) at a depth position corresponding to that thickness. ３ ) and rare earth element concentration (atoms / cm ３The following measurements were taken. These measurements were performed at depths of 5 μm, 10 μm, 25 μm, and 55 μm in the thickness direction from the first main surface 40a after the device layer removal, thereby confirming the nitrogen atom concentration and rare earth element concentration at each depth in the SiC growth layer 14. Dynamic secondary ion mass spectrometry (D-SIMS) was used for the concentration measurements. For the rare earth element concentration, the IMS-7f manufactured by CAMECA was used as the analyzer, and the primary ion species O ２ ＋ The tests were conducted under the conditions of an acceleration voltage of 11.0 kV. For nitrogen atom concentration, a CAMECA IMS-7f was used as the analyzer, and the primary ion species Cs was measured. ＋ The tests were conducted under the conditions of an acceleration voltage of 15.0 kV. The results are shown in Tables 1A and 1C.

[0120] (12) Evaluation of the yield rate after device formation A total of 100 SiC wafers 10 on which SiC-MOSFET devices were formed were prepared using the same procedure as in (1) to (7) above. These SiC wafers 10 were visually inspected for the presence of delamination, cracks, and bubbles. If there was no delamination, cracks, or bubbles (i.e., no unintended delamination occurred), it was deemed "acceptable," and if there was delamination, cracks, or bubbles, it was deemed "unacceptable." The yield rate (%) was calculated by counting the number of "acceptable" wafers out of the 100 SiC wafers 10. The results are shown in Table 1D.

[0121] (13) Peeling off the SiC seed crystal layer A pulsed laser with a wavelength of 1064 nm was irradiated as incident light onto the peeling acceleration layer 16 from the SiC seed crystal layer 12 side of the SiC wafer 10 obtained in (7) above. By scanning this pulsed laser light in the in-plane direction of the SiC wafer 10, the SiC seed crystal layer 12 was peeled off from the SiC wafer 10 along the peeling acceleration layer 16. The laser irradiation conditions at this time were an irradiation fluence of 100 J / cm ２The pulse width was set to 10 ns, and the laser focusing position was set to a depth of 200 μm in the thickness direction from the surface of the SiC wafer 10 on the SiC seed crystal layer 12 side. As a result, the SiC wafer 10 on which the SiC-MOSFET device was formed was divided into a main wafer 111 (SiC growth layer 14 on which the device was formed) and a remaining wafer 112 (SiC seed crystal layer 12).

[0122] (14) Evaluation of the yield rate after peeling A total of 100 SiC wafers 10 on which SiC-MOSFET devices were formed were prepared using the same procedure as in (1) to (7) above. These SiC wafers 10 were divided into 100 sets of main wafers 111 and remaining wafers 112 using the same procedure as in (13) above. The peeled surfaces of the obtained main wafers 111 and remaining wafers 112 were irradiated with a halogen lamp, and the condition of these peeled surfaces was observed visually. If there were no cracks or cracks of 1 mm or more on the peeled surface of either the main wafers 111 or the remaining wafers 112, it was considered "acceptable". If there were cracks or cracks of 1 mm or more, it was considered "unacceptable". The yield rate (%) after peeling was calculated by counting the number of "acceptable" wafers out of the 100 sets of main wafers 111 and remaining wafers 112. The results are shown in Table 1D.

[0123] Examples 2 and 3 In (1) above, the width d of the peel-promoting layer 16 is as shown in Tables 1A and 1D. ３ , separation distance d ４ , thickness d ２ Except for changing the patterning conditions (see Figure 2), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 1A, 1C, and 1D.

[0124] Example 4 In (1) above, the width d of the peel-promoting layer 16 is as shown in Tables 1A and 1D. ３ , separation distance d ４ , thickness d ２ Except for changing the patterning conditions (see Figure 3), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 1A, 1C, and 1D.

[0125] Examples 5 and 6 In (1) above, the width d of the peel-promoting layer 16 is as shown in Tables 1A and 1D. ３ , separation distance d ４ , thickness d ２ Except for changing the patterning conditions (see Figure 2), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 1A, 1C, and 1D.

[0126] Examples 7 and 8 i) In (1) above, the width d of the peel-promoting layer 16 as shown in Tables 1A and 1D ３ , separation distance d ４ , thickness d ２ Except for the following changes to the patterning conditions (see Figure 2), and the following changes in (4) above, the partial pressure of nitrogen gas was changed to 0.0010 atm (Example 7) or 0.0025 atm (Example 8) as shown in Table 1A, the SiC wafer 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 1A, 1C, and 1D.

[0127] Examples 9 and 10 i) In (1) above, the width d of the peel-promoting layer 16 as shown in Tables 1A and 1D ３ , separation distance d ４ , thickness d ２ and the patterning conditions were changed (see Figure 2), ii) in (2) above, the oxide (Y) is a liquid phase generation aid. ２ O ３ ) (Volume-based D50 particle size: 5.0 μm) was weighed so that the oxide content relative to the SiC powder content was 6.4% by weight (Example 9) or 0.2% by weight (Example 10). iii) In (4) above, the partial pressure of nitrogen gas was changed to 0.0025 atm as shown in Table 1A. Except for these changes, SiC wafers 10 and other components were manufactured and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 1A, 1C, and 1D.

[0128] Example 11 i) In (1) above, the width d of the peel-promoting layer 16 as shown in Tables 1A and 1D ３ , separation distance d ４ , thickness d ２and the patterning conditions were changed (see Figure 2), ii) in (2) above, the oxide (Gd ２ O ３ Except for weighing the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 8.1% by weight, SiC wafers 10 and other components were prepared and various evaluations were performed in the same manner as in Example 9. The results are shown in Tables 1A, 1C, and 1D.

[0129] Examples 12-15 In (1) above, the width d of the peel-promoting layer 16 is as shown in Tables 1A and 1D. ３ , separation distance d ４ , thickness d ２ Except for changing the patterning conditions (see Figure 2), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 9. The results are shown in Tables 1A, 1C, and 1D.

[0130] Examples 16-21 i) In (1) above, the width d of the peel-promoting layer 16 as shown in Tables 1B and 1D ３ , separation distance d ４ , thickness d ２ Except for the following changes, the patterning conditions were modified (see Figure 2), and the ion species to be implanted was changed as shown in Table 1D in (1) above, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 9. The results are shown in Tables 1B to 1D.

[0131] Example 22 In (1) above, the width d of the peel-promoting layer 16 is as shown in Tables 1B and 1D. ３ , separation distance d ４ , thickness d ２ Except for changing the patterning conditions (see the circular shape shown in Figure 4), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 9. The results are shown in Tables 1B to 1D.

[0132] Examples 23 and 24 In (1) above, the width d of the peel-promoting layer 16 is as shown in Tables 1B and 1D. ３ , separation distance d ４ , thickness d ２Except for changing the patterning conditions (see the roughly rectangular shape (striped) shown in Figure 5), the SiC wafer 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 9. The results are shown in Tables 1B to 1D.

[0133] Example 25 In (1) above, the width d of the peel-promoting layer 16 is as shown in Tables 1B and 1D. ３ , separation distance d ４ , thickness d ２ Except for changing the patterning conditions (see the hexagonal shape shown in Figure 6), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 9. The results are shown in Tables 1B to 1D.

[0134] Example 26 In (1) above, the width d of the peel-promoting layer 16 is as shown in Tables 1B and 1D. ３ , separation distance d ４ , thickness d ２ Except for changing the patterning conditions (see the circular shape shown in Figure 4), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 9. The results are shown in Tables 1B to 1D.

[0135] Example 27 In (1) above, the width d of the peel-promoting layer 16 is as shown in Tables 1B and 1D. ３ , separation distance d ４ , thickness d ２ Except for changing the patterning conditions (see the elliptical shape shown in Figure 7), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 9. The results are shown in Tables 1B to 1D.

[0136] Example 28 (Comparison) Except that the pretreatment described in (1) above was not performed (i.e., the peel-promoting layer 16 was not formed), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 1B to 1D.

[0137] Example 29 (Comparison) In this example, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that no patterning was formed (i.e., the peeling acceleration layer 16 was formed evenly over the entire crystal growth surface of the SiC single crystal substrate). The results are shown in Tables 1B to 1D. In this example, the SiC seed crystal layer peeled off unintentionally during device formation on the SiC wafer, so the evaluation of the good product rate after peeling in (14) above was not performed.

[0138]

[0139]

[0140]

[0141]

[0142] 10, 40 SiC wafer 12 SiC seed crystal layer 14 SiC growth layer 16 Peeling acceleration layer 20 Pattern mask 20a Aperture pattern 111 Main wafer 112 Remaining wafer 113a, 113b Seed crystal 114 Pre-treated seed crystal 115 Grown SiC crystal 116 Peeling acceleration region 171 Inspection device 172 Processing device 173 Pre-treatment device 174 Growth device R Region with the same thickness as the peeling acceleration layer (peeling acceleration region) R １ Region R containing the peel-promoting layer ２ Region C that does not contain the peel-promoting layer Ｉ Inscribed circle C Ｃ Circumscribed circle I ion

Claims

1. A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peel-promoting layer is formed in a predetermined pattern parallel to both sides of the SiC wafer on the interior and / or surface of at least one of the first crystal layer and the second crystal layer, so that a region having the same thickness as the peel-promoting layer encompassing the predetermined pattern contains a region containing the peel-promoting layer and a region not containing the peel-promoting layer, the peel-promoting layer being a SiC-derived layer having voids, amorphous portions, or portions containing a peel-promoting substance, and the predetermined pattern containing a plurality of spaced-apart constituent units.

2. The SiC wafer according to claim 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer.

3. The SiC wafer according to claim 1, wherein, when the SiC wafer is viewed in cross-section, the width of the peeling accelerating layer is 0.5 to 15.0 μm, and the distance between adjacent peeling accelerating layers is 0.5 to 15.0 μm.

4. The second crystal layer has a thickness of 55 μm or more, and the nitrogen atom concentration of the second crystal layer at a depth of 55 μm in the thickness direction of the SiC wafer from the surface of the SiC wafer on the second crystal layer side is 1.00 × 10 １８ atoms / cm ３ The SiC wafer according to any one of claims 1 to 3.

5. The second crystal layer is 5.00 × 10 １３ atoms / cm ３ A SiC wafer according to any one of claims 1 to 3, having a portion containing rare earth elements at the above concentration.

6. The SiC wafer according to any one of claims 1 to 3, wherein the peeling-promoting layer has a thickness of 30.0 μm or less.

7. The SiC wafer according to any one of claims 1 to 3, wherein the peeling-promoting substance is at least one ion selected from the group consisting of Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements.

8. The SiC wafer according to any one of claims 1 to 3, wherein the diameter of the inscribed circle of the constituent unit is 0.5 to 15.0 μm, and the diameter of the circumscribed circle of the constituent unit is 0.5 μm or more.

9. The SiC wafer according to claim 8, wherein one or more of the constituent units are polygonal.

10. The SiC wafer according to claim 8, wherein one or more of the constituent units are circular.

11. The SiC wafer according to claim 8, wherein one or more of the constituent units are elliptical in shape.

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