SiC WAFER

Abstract

Provided is an SiC wafer in which, when the SiC wafer is divided into a device formed portion and a device unformed portion after a device is formed on the wafer, it is possible to improve the flatness of peeled surfaces of said portions. This SiC wafer comprises: a first crystal layer containing an SiC single crystal; and a second crystal layer formed on the first crystal layer and containing an SiC single crystal. A peeling auxiliary layer is formed inside and / or on the surface of at least one of the first crystal layer and the second crystal layer. The peeling auxiliary layer is an SiC-derived layer containing voids or a peeling auxiliary substance, and the peeling auxiliary layer has a thickness of more than 10.0 μm but not more than 30.0 μm.

Description

SiC wafer

[0001] This disclosure relates to SiC wafers.

[0002] Silicon carbide (SiC) is attracting attention as a wide-bandgap material that can control high currents and high voltages with low loss. In particular, power semiconductor devices using SiC material (SiC power devices) have recently been expected to be used in a variety of applications because they are superior to those using Si semiconductors in terms of miniaturization, low power consumption, and high efficiency. For example, by adopting SiC power devices, converters, inverters, and on-board chargers for electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs) can be miniaturized and their efficiency improved.

[0003] Incidentally, Patent Document 1 (Japanese Patent Application Publication No. 2023-73458) discloses a method in which, after forming a device (for example, electrodes or wiring patterns) on the surface of a semiconductor wafer, a laser focused at a predetermined depth in the thickness direction of the semiconductor wafer is irradiated at regular intervals to form a modified layer in the planar direction within the semiconductor wafer, and the semiconductor wafer is divided into a device-formed portion and an unformed portion starting from this modified layer.

[0004] Japanese Patent Publication No. 2023-73458 WO2023 / 067736A1

[0005] However, in methods such as those disclosed in Patent Document 1, the formation of the modified layer within the semiconductor wafer may be insufficient and / or non-uniform. In such cases, when the semiconductor wafer is divided into a device-formed portion and a non-device-formed portion, there is a problem in that the flatness of the device-formed portion and the non-device-formed portion deteriorates. Therefore, it is desirable to improve the flatness of these peeled surfaces when the semiconductor wafer is divided into a device-formed portion and a non-device-formed portion after device formation.

[0006] The present inventors have now discovered that by forming a peeling assist layer having a thickness of more than 10.0 μm and less than or equal to 30.0 μm in a SiC wafer having a first crystal layer such as a SiC seed crystal layer and a second crystal layer such as a SiC growth layer, the flatness of the peeled surfaces can be improved when the wafer is divided into a device-formed portion and an unformed portion after device formation.

[0007] Therefore, an object of the present invention is to provide a SiC wafer that can improve the flatness of the peeled surfaces when the wafer is divided into a device-formed portion and an unformed portion after device formation.

[0008] The following embodiments are provided according to this disclosure: [Embodiment 1] A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peeling assist layer is formed inside and / or on the surface of at least one of the first crystal layer and the second crystal layer, the peeling assist layer is a SiC-derived layer containing voids or peeling assist material, and the peeling assist layer has a thickness of more than 10.0 μm and less than or equal to 30.0 μm. [Embodiment 2] The SiC wafer according to Embodiment 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer. [Embodiment 3] The second crystal layer is 5.00 × 10 １３ atoms / cm ３ A SiC wafer according to embodiment 1 or 2, having a portion containing rare earth elements at the above concentration. [Embodiment 4] The peeling auxiliary layer has a region in which the voids or the peeling auxiliary material are distributed at intervals of 200 μm or less in the in-plane direction of the SiC wafer, and the region is 0.19 mm ２ A SiC wafer according to any one of embodiments 1 to 3, having the above-mentioned area. [Embodiment 5] A SiC wafer according to any one of embodiments 1 to 4, wherein the peeling aid is at least one ion selected from the group consisting of Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements.

[0009] This is a schematic cross-sectional view showing an example of a SiC wafer according to the present disclosure. This is a diagram showing an example of the overall system configuration according to the first embodiment of the present disclosure. This is an explanatory diagram of a pretreatment for forming a layer containing minute voids. This is an explanatory diagram of a pretreatment for forming a layer containing a peeling aid. This is an explanatory diagram of a pretreatment for forming a layer containing another peeling aid. This is a diagram showing an example of the appearance of the cut surface when a SiC wafer is cut along a plane passing through the peeling aid layer. This is a diagram showing another schematic diagram showing the thermal etching process in a first example of the processing steps according to the second embodiment of the present disclosure. This is a schematic diagram showing the surface oxidation process in a second example of the processing steps according to the second embodiment of the present disclosure. This is a schematic diagram showing the plasma etching process in a third example of the processing steps according to the second embodiment of the present disclosure.

[0010] The SiC wafer of this disclosure comprises a first crystal layer containing a SiC single crystal and a second crystal layer containing a SiC single crystal formed on the first crystal layer. Therefore, the SiC wafer of this disclosure is mainly composed of a SiC single crystal and is usable as a SiC single crystal wafer. Here, the expression "mainly composed of a SiC single crystal" means that the main part of the SiC wafer other than the peeling auxiliary layer is composed of a SiC single crystal (not a SiC polycrystalline layer), regardless of whether the SiC-derived peeling auxiliary layer described later maintains the form of a SiC single crystal or not. Typically, the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing a SiC single crystal grown from the SiC seed crystal layer, and therefore the SiC wafer as a whole can be composed of one SiC single crystal (or at least mainly composed of a SiC single crystal). Therefore, the following explanation will be based on a SiC wafer in which the first crystal layer is a SiC seed crystal layer and the second crystal layer is a SiC growth layer.

[0011] Figure 1 conceptually shows a SiC wafer 10. The SiC wafer 10 comprises a SiC seed crystal layer 12 (first crystal layer) and a SiC growth layer 14 (second crystal layer) containing a SiC single crystal grown from the SiC seed crystal layer 12. A peeling assist layer 16 is formed inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. The peeling assist layer 16 is a SiC-derived layer containing voids or peeling assist material. The peeling assist layer 16 has a thickness of more than 10.0 μm and less than or equal to 30.0 μm. This makes it possible to provide a SiC wafer 10 that can improve the flatness of the peeled surfaces when the wafer is divided into a device-formed portion and an unformed portion after device formation.

[0012] In other words, as described above, in methods such as those disclosed in Patent Document 1, the formation of the modified layer within the semiconductor wafer may be insufficient and / or non-uniform. In such cases, when the semiconductor wafer is divided into a device-formed portion and a non-device-formed portion, there is a problem in that the flatness of the device-formed portion and the non-device-formed portion deteriorates. Therefore, when the semiconductor wafer is divided into a device-formed portion and a non-device-formed portion after device formation, it is desirable to improve the flatness of these peeled surfaces. This problem is successfully resolved according to the present invention. In addition, by improving the flatness of the peeled surface, the polishing time of the wafer after peeling can be reduced, and productivity in wafer manufacturing can be improved. The reason why the flatness of the peeled surface can be improved when the wafer is divided in this way is not clear, but it is presumed that because the peeling auxiliary layer 16 has a thickness of more than 10.0 μm and less than or equal to 30.0 μm, when the SiC seed crystal layer 12 is peeled from the SiC wafer 10 along the peeling auxiliary layer 16 by laser irradiation, it is easier to irradiate the laser to the target position and peeling can be suppressed in parts other than the peeling auxiliary layer 16.

[0013] The SiC wafer 10 preferably has a thickness of 500 μm or less, and more preferably 300 to 500 μm. The shape of the SiC wafer 10 is not particularly limited, but it is preferably disc-shaped (circular). In this specification, "circular shape" does not have to be a perfect circle, but may be a substantially circular shape that can be generally recognized as circular overall. For example, it may be a shape in which a part of the circle is cut out for the purpose of specifying the crystal orientation or for other purposes, or a shape in which a slit is provided in a part of the circle, in which case the size can be determined based on the diameter of the largest circle inscribed in the outer edge excluding the cut-out outer edge or the slit. The diameter of the SiC wafer 10 is not particularly limited, but may be 100 mm (4 inches) or more, 145 mm or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more.

[0014] The SiC seed crystal layer 12 is typically composed of a SiC single crystal and has a crystal growth surface. In this case, the polymorph (polytype), off-angle and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal, are not particularly limited, but the polymorph is preferably 4H, 6H, or 3C. Alternatively, a SiC single crystal deposited on a Si substrate may be used as the SiC seed crystal layer 12. The crystal growth surface on the SiC single crystal as the SiC seed crystal layer 12 may be the Si surface or the C surface, or both the Si surface and the C surface, but it is preferably the Si surface. Therefore, it is preferable that the peeling aid layer 116 is formed near this Si surface. The diameter of the SiC seed crystal layer 12 is not particularly limited, but it may be 100 mm (4 inches) or larger, 145 mm or larger, 150 mm (6 inches) or larger, or 200 mm (8 inches) or larger.

[0015] The SiC growth layer 14 contains SiC single crystals grown from the SiC seed crystal layer 12. The polymorph (polytype), off-angle and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal, are not particularly limited, but the polymorph is preferably 4H, 6H, or 3C.

[0016] The SiC growth layer 14 preferably contains a rare earth element, and examples of the rare earth element include Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, and combinations thereof. From the viewpoint of improving the flatness of the peeled surface during wafer division, the rare earth element is preferably Y and / or Ce. When the SiC growth layer 14 contains a rare earth element, the SiC growth layer 14 has 5.00×10 １３ atoms / cm ３ It is preferable to have a portion containing the rare earth element at a concentration equal to or higher than the above, and this concentration is more preferably 5.00×10 １３ to 8.00×10 １５ atoms / cm ３ , more preferably 3.00×10 １４ to 8.00×10 １５ atoms / cm ３ , particularly preferably 3.00×10 １４ to 3.20×10 １５ atoms / cm ３ .

[0017] The peeling assist layer 16 is formed inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. In other words, the SiC wafer 10 has the peeling assist layer 16 inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. The peeling assist layer 16 is a SiC-derived layer (for example, a SiC-based layer) for assisting dividing the SiC wafer 10 into an upper portion and a lower portion with the peeling assist layer 16 as a starting point or boundary, and is, for example, a layer in which the crystal structure of SiC is incomplete compared to other portions, or peeling or division is likely to occur due to other causes. In FIG. 1, a configuration in which the peeling assist layer 16 is formed inside the SiC seed crystal layer 12 is exemplified. By forming the peeling assist layer 16 in the SiC wafer 10 in this manner, when the SiC wafer 10 is divided into a device-formed portion and a device-non-formed portion after device formation on the SiC wafer 10, the flatness of these peeled surfaces can be improved.

[0018] The peeling auxiliary layer 16 is a SiC-derived layer containing voids or a peeling auxiliary substance. When the peeling auxiliary layer 16 contains a peeling auxiliary substance, it is preferable that it is a layer formed by implanting ions I into at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. These ions I correspond to the peeling auxiliary substance. Based on this, the "SiC-derived layer" typically means a layer formed by giving some kind of change to the SiC crystal (especially a SiC single crystal) constituting the SiC seed crystal layer 12 and / or the SiC growth layer 14 (for example, a SiC-based layer), and can be a layer in which the SiC crystal has been modified. The peeling auxiliary substance is preferably an ion of Si, C, Al, B, P, N, O, H, a noble gas element, a rare earth element, or a combination thereof. More preferably, it is an ion of Si, C, B, P, N, H, a noble gas element, a rare earth element, or a combination thereof, and even more preferably, it is an ion of Si, C, B, P, a noble gas element, or a combination thereof.

[0019] Furthermore, if the peeling aid layer 16 contains voids, it is preferable that the peeling aid layer 16 is a layer obtained by forming minute grooves in at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. For example, by forming grooves (voids) at regular intervals at the interface between the SiC seed crystal layer 12 and the SiC growth layer 14, a peeling aid layer 16 can be formed in which the crystal structure is partially changed, modified, or fragmented near the interface. The formation of such a peeling aid layer 16 makes it easier to peel the SiC seed crystal layer 12 from the SiC wafer 10 along the voids.

[0020] The peeling assist layer 16 has a thickness of more than 10.0 μm and less than or equal to 30.0 μm, preferably 15.0 to 30.0 μm, more preferably 20.0 to 30.0 μm, and even more preferably 20.0 to 25.0 μm. This makes it easier to irradiate the SiC seed crystal layer 12 from the SiC wafer 10 along the peeling assist layer 16 with a laser, suppresses peeling in areas other than the peeling assist layer 16, and is thought to further improve the flatness of the peeled surface.

[0021] The peeling aid layer 16 is preferably evenly distributed over a fairly wide area in the in-plane direction of the SiC wafer 10 (rather than being concentrated in a very small area). Specifically, it is preferable that voids or peeling aid materials are uniformly distributed over a predetermined area range or the entire surface in the in-plane direction of the SiC wafer 10. For example, the peeling aid layer 16 has a region in which voids or peeling aid materials are distributed at intervals of 200 μm or less in the in-plane direction of the SiC wafer 10, and this region is 0.19 mm ２ It is preferable that the above area is present. Alternatively, it is preferable that the peeling auxiliary layer 16 has voids or peeling auxiliary material distributed in the in-plane direction of the SiC wafer 10 at intervals of 200 μm or less, over a range of at least 500 μm.

[0022] As described above, this disclosure provides a SiC wafer 10 that can improve the flatness of the peeled surfaces when the wafer is divided into a device-formed portion and an unformed portion after device formation. The first and second embodiments of a system or process for manufacturing such a SiC wafer 10 will be described below. The descriptions of the first and second embodiments apply to the SiC wafer 10 described above insofar as they do not contradict the present invention, but this disclosure is not limited to them. Therefore, in the following description, the SiC wafer 40, the pre-treated seed crystal 114, the grown SiC crystal 115, and the peeling auxiliary layer 116 may correspond to the SiC wafer 10, the SiC seed crystal layer 12, the SiC growth layer 14, and the peeling auxiliary layer 16 described above, respectively.

[0023] In the descriptions of the first and second embodiments, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the embodiments in order to make the explanation clearer. However, these are merely examples and do not limit the interpretation of this disclosure.

[0024] In the description of the first embodiment and the second embodiment, the semiconductor wafer is an SiC (silicon carbide) wafer, but the present invention can also be applied to semiconductor wafers other than SiC wafers. Examples of semiconductor wafers other than SiC wafers may include GaN (gallium nitride) wafers, AlN (aluminum nitride) wafers, or diamond wafers.

[0025] [First Embodiment] FIG. 2 shows a configuration example of the entire system according to the first embodiment of the present disclosure.

[0026] In the second entity, a surface device step and a wafer dividing step are performed. The second entity may be a company as a device manufacturer that takes out SiC chips from the SiC wafer 40 and provides SiC chips or devices including SiC chips. The SiC wafer 40 is broadly classified into a layer as a base SiC crystal and a layer as a grown SiC crystal (oriented SiC crystal).

[0027] In the surface device step, a device is formed on a first main surface (front surface) of the SiC wafer 40 (corresponding to the surface on the SiC growth layer 14 side of the SiC wafer 10). The device may include electrodes and wiring patterns.

[0028] In the wafer dividing step, the SiC wafer 40 having the device is divided along a planar direction (a direction orthogonal to the thickness direction, in other words, a direction parallel to the first main surface). In this wafer dividing step, the SiC wafer 40 is divided in the planar direction by a method called laser slicing using a laser device, for example. Specifically, for example, from the second main surface (back surface) side of the SiC wafer 40 (corresponding to the surface of the SiC seed crystal layer 12 of the SiC wafer 10), a laser device irradiates a peeling assist layer 116 pre-formed inside the SiC wafer 40 with a laser beam (e.g., a pulsed laser). Accordingly, a modified layer is formed in the peeling assist layer 116, and starting from this modified layer, the SiC wafer 40 is divided into a main wafer 111 which is an SiC wafer portion having the first main surface and a remaining wafer 112 which is an SiC wafer portion having the second main surface.

[0029] In laser slicing, the peeling assist layer 116 within the SiC wafer 40 irradiated with laser light is a layer that is easier to peel off due to an incomplete SiC crystal structure compared to other parts, or for other reasons. By irradiating this peeling assist layer 116 with laser light to create a modified layer, and then dividing the SiC wafer 40 into the main wafer 111 and the remaining wafer 112 along the peeling assist layer 116, the division (peeling) can be performed more easily than when other parts are used as the modified layer. Possible reasons for this include, for example, the peeling assist layer 116 having an incomplete crystal structure compared to other parts and having weak interatomic bonding forces. It is also possible that the peeling assist layer 116 easily absorbs laser light, thus facilitating the formation of a modified layer. Various other factors may also be considered, but in any case, by peeling off the portion including the first main surface from the SiC wafer 40 starting from the peeling assist layer 116, the SiC wafer 40 can be divided into the main wafer 111 and the remaining wafer 112 with less force. This makes it possible to suppress the generation of distortion during peeling in the device formation portion of the main wafer 111, thereby preventing the occurrence of cracks and fractures.

[0030] The peeling aid layer 116 is formed within the SiC wafer 40 when the SiC wafer 40 is manufactured in a first entity different from the second entity. This method will be described later.

[0031] In addition, during the wafer splitting step, the SiC wafer 40 may be split into the main wafer 111 and the remaining wafer 112 by a method other than laser slicing. For example, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 by etching away the peeling auxiliary layer 116 on the SiC wafer 40. In this case, electrolytic etching, chemical etching, thermal etching, etc., can be used for etching. By performing the wafer splitting step by etching in this way, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 without using a laser device. Furthermore, peeling can also be performed using ultrasound, known as sonic lift-off. Specifically, by splitting the SiC wafer 40 into the main wafer 111 and the remaining wafer 112 using sound waves, the peeled surfaces of the main wafer 111 and the remaining wafer 112 can be made flat and smooth, thus eliminating material waste and allowing the remaining wafer 112 to be reused, thereby reducing wafer manufacturing costs. In addition to the above, it is possible to divide the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 by processing the peeling auxiliary layer 116 formed in the SiC wafer 40 using any method.

[0032] In the first entity, the acquisition step, processing step, pre-processing step, growth step, and wafer provision step are performed (in this embodiment, an inspection step is also performed between the acquisition step and the processing step, as will be described later). The first entity is a company that provides a new service, that is, a company that acquires (recovers) the remaining wafer 112 of the SiC wafer 40 from the second entity, grows a grown SiC crystal on the remaining wafer 112 to regenerate the SiC wafer 40, and provides the regenerated SiC wafer 40 to the same or a different second entity. There is one or more second entities for each first entity. Note that the wafer splitting step described above may be performed in the first entity instead of the second entity.

[0033] In the acquisition step, the remaining wafer 112 is acquired from the second entity. In the processing step, the slice surface of the remaining wafer 112 is processed to acquire a seed crystal 113a made of SiC single crystal material.

[0034] In the pretreatment step, an inhibitory region is formed on or near the surface of the seed crystal 113a obtained in the processing step, or a seed crystal 113b made of newly prepared SiC single crystal material, which partially disrupts or inhibits the SiC crystal structure. This pretreatment is performed on the seed crystals 113a and 113b to form the aforementioned peeling auxiliary layer 116, and a pretreated seed crystal 114 is obtained. Details of the pretreatment step will be described later.

[0035] In the growth step, a new SiC wafer 40 is manufactured by growing a growth SiC crystal (an example of a semiconductor crystal layer) 115 on the surface of the seed crystal 114 obtained in the pretreatment step. Inside the SiC wafer 40 manufactured here, a peeling aid layer 116 is formed by the inhibition region formed on the seed crystal 114 in the pretreatment step.

[0036] In the wafer supply step, the SiC wafer 40 obtained in the growth step is provided to a second entity that is the same as or different from the source from which the remaining wafer 112 was obtained.

[0037] In conventional processes not to which this disclosure applies, the portion of the SiC wafer 40 corresponding to the remaining wafer 112 is ground without separating it from the main wafer 111, and the resulting grinding waste is discarded. In contrast, in this embodiment, the remaining wafer 112 is separated from the main wafer 111 and recovered without being discarded as grinding waste, and this is recycled into a new semiconductor wafer by the first entity and provided to the second entity. The second entity forms a device on the semiconductor wafer provided by the first entity (SiC wafer 40 recycled from the remaining wafer 112), and then separates it into the main wafer 111 and the remaining wafer 112. The remaining wafer 112 is recovered by the first entity and used as a seed crystal 114 to form a grown SiC crystal together with the peeling auxiliary layer 116, and is then used again as SiC wafer 40. By repeating this process, the portion of the SiC wafer 40 that was conventionally ground or discarded, namely the remaining wafer 112, can be reused. In this disclosure, the reuse of expensive SiC wafers is made possible, thereby reducing the manufacturing cost of devices. Furthermore, since waste can be significantly reduced throughout the entire SiC wafer manufacturing process, including high-temperature processes, it is also possible to reduce the environmental impact.

[0038] The processing step may be performed by the processing device 172, the pretreatment step may be performed by the pretreatment device 173, and the growth step may be performed by the growth device 174 (the inspection step described later may be performed by the inspection device 171).

[0039] Below, we will first describe the acquisition step, processing step, pretreatment step, growth step, and wafer supply step among the steps in the first entity, and then describe the inspection step.

[0040] <Acquisition Step> In the acquisition step, the remaining wafers 112 are acquired from one or more second entities. Any number of remaining wafers 112 may be sent to the first entity at any time the second entity has chosen, or an acquisition schedule, including the number of remaining wafers 112 to be acquired from each of the one or more second entities and the acquisition timing, may be shared between the second entity and the first entity, and the remaining wafers 112 may be acquired from the second entity according to the acquisition schedule. Note that if the wafer splitting step is performed by the first entity, the acquisition step is unnecessary.

[0041] <Processing Step> The processing in the processing step includes removing the slice surface (typically grinding and / or polishing) and removing the processed altered layer including the removed slice surface. The processing apparatus 172 may include, for example, an apparatus for grinding and / or polishing the slice surface (e.g., a grinder) and an apparatus for removing the processed altered layer, and these apparatuses may be a single apparatus (i.e., grinding and removal may be performed by one apparatus). For example, the processing apparatus 172 may be an apparatus for grinding and polishing such as the CMP (Chemical Mechanical Polishing) method.

[0042] In the processing step, a seed crystal 113a is obtained as a result of processing the remaining wafer 112. The seed crystal 113a may be composed mainly of the underlying SiC crystal, or it may be composed of the underlying SiC crystal and some oriented SiC crystal. Alternatively, instead of the seed crystal 113a, a new SiC single crystal material may be prepared and used as the seed crystal 113b.

[0043] <Pre-treatment step> In the pre-treatment apparatus 173, inhibition regions are formed on or near the surface of the seed crystals 113a and 113b, which partially disrupt or inhibit the formation of the crystal structure when growing the SiC crystal in the next growth step. Due to the presence of these inhibition regions, a peeling assist layer 116 that is easier to peel off than other parts is formed inside the SiC wafer 40 manufactured from the seed crystals 113a and 113b in the growth step. Specifically, for example, the pre-treatment apparatus 173 forms inhibition regions on the seed crystals 113a and 113b by performing one of the processing treatments described in Figures 3 to 5 below as a pre-treatment.

[0044] Figure 3 is an explanatory diagram of the pretreatment for forming a layer containing minute voids as a peeling aid layer 116. In Figure 3, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0045] In the pretreatment step, for example as shown in Figure 3(b), pulsed laser light from a laser 201, which is a pretreatment device 173, is irradiated onto the surface of the seed crystal 113a at regular intervals in a grid pattern, thereby forming laser-processed grooves 202 on the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with these grooves 202 formed on it is used as a pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form a grown SiC crystal 115. As a result, for example as shown in Figure 3(c), voids formed by the grooves 202 occur at regular intervals between the seed crystal 114 and the grown SiC crystal 115, and because the crystal structure is partially divided by these voids, a peeling assist layer 116 is formed along the voids as a layer that is easily peeled off. In this way, a SiC wafer 40 having a peeling assist layer 116 between the first main surface 40a on the front side (grown SiC crystal 115 side) and the second main surface 40b on the back side (seed crystal 114 side) is manufactured.

[0046] Furthermore, it is preferable that the grooves 202 formed on the surface of the seed crystal 113a in the pretreatment step have a maximum depth of 1 μm or more. In this way, it is possible to form the peeling auxiliary layer 116 in the region including the grooves 202 while sufficiently growing the SiC crystal in the growth step.

[0047] Figure 4 is an explanatory diagram of the pretreatment for forming a layer containing a substance for assisting peeling (hereinafter referred to as "peeling assisting substance") as a peeling assisting layer 116. In Figure 4, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0048] In the pretreatment step, for example, as shown in Figure 4(b), fine particles 211 mainly composed of carbon are dispersed on the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the dispersed fine particles 211 on its surface is used as the pretreated seed crystal 114, and a SiC crystal is grown on its surface (for example, to a thickness of 50 μm or more) to form a grown SiC crystal 115. As a result, for example, as shown in Figure 4(c), fine particles 211 are sandwiched in places between the seed crystal 114 and the grown SiC crystal 115, and because the formation of the crystal structure is inhibited by these fine particles 211, a peeling aid layer 116 is formed as a layer with an incomplete crystal structure. In this way, a SiC wafer 40 having a peeling aid layer 116 between the first main surface 40a on the front side (grown SiC crystal 115 side) and the second main surface 40b on the back side (seed crystal 114 side) is manufactured.

[0049] Furthermore, the carbon-based fine particles 211 dispersed on the surface of the seed crystal 113a in the pretreatment step are preferably graphite or diamond fine particles with a particle size of 10 μm or less. In this way, it is possible to sufficiently grow the SiC crystal in the growth step while forming the peeling auxiliary layer 116 in the region containing the fine particles 211.

[0050] Figure 5 is an explanatory diagram of the pretreatment for forming a layer containing a different peeling aid material as the peeling aid layer 116, compared to that in Figure 4. In Figure 5, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0051] In the pretreatment step, ions 221 are injected into the seed crystal 113a from the surface, as shown in Figure 5(b). Specifically, ions 221 generated by an ion source are accelerated and injected from the outside toward the surface of the seed crystal 113a, thereby injecting and dispersing the ions 221 near the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the ions 221 dispersed inside is used as the pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form the grown SiC crystal 115. As a result, as shown in Figure 5(c), ions 221 are placed in various places near the boundary between the seed crystal 114 and the grown SiC crystal 115, and the formation of the crystal structure is inhibited by these ions 221, resulting in the formation of a peeling auxiliary layer 116 with an incomplete crystal structure. In this way, a SiC wafer 40 having a peeling assist layer 116 between the first main surface 40a on the front side (the side with the growing SiC crystal 115) and the second main surface 40b on the back side (the side with the seed crystal 114) is manufactured. In the subsequent wafer splitting step, if the peeling assist layer 116 in the SiC wafer 40 is removed by etching as described above, it is preferable to form the peeling assist layer 116 using the method described in Figure 5.

[0052] Furthermore, it is preferable to use one or more ions from among Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements as the ions 221 implanted into the seed crystal 113a in the pretreatment step. In this way, it is possible to form a peeling auxiliary layer 116 in the region containing the ions 221 while sufficiently growing the SiC crystal in the growth step.

[0053] In the pretreatment step, seed crystal 114 is obtained by performing one of the pretreatments described above on seed crystals 113a and 113b using the pretreatment apparatus 173. Although Figures 3 to 5 illustrate an example of performing pretreatment on seed crystal 113a obtained in the processing step, the same pretreatment can be performed on a newly prepared seed crystal 113b to obtain seed crystal 114.

[0054] <Growth Step> In the growth apparatus 174, a grown SiC crystal (oriented SiC crystal) 115 is grown on the seed crystal 114 to a thickness of 50 μm or more. Such crystal growth may be carried out by sublimation or CVD (Chemical Vapor Deposition), or by other methods. As a result, as explained in Figures 3 to 5, a new SiC wafer 40 is obtained, which consists of a seed crystal 114, which is a crystalline layer made of a single-crystal material of SiC, and a grown SiC crystal 115, which is a crystalline layer of SiC formed on the seed crystal 114, and has a peeling assist layer 116 between the first main surface 40a on the grown SiC crystal 115 side and the second main surface 40b on the seed crystal 114 side. In this SiC wafer 40, the peeling assist layer 116 formed on at least one of the seed crystal 114 and the grown SiC crystal 115 contains voids due to grooves 202 or contains an incomplete crystalline structure due to fine particles 211 or ions 221.

[0055] Furthermore, it is preferable that the peeling assist layer 116 is formed to have a thickness of more than 10.0 μm and less than or equal to 30.0 μm in the thickness direction perpendicular to the first main surface 40a and the second main surface 40b (up and down direction in the figure), as illustrated in Figure 4(c). Specifically, it is preferable that when a cross-section of the SiC wafer 40 in the thickness direction is observed at any position including the peeling assist layer 116, the thickness of the peeling assist layer 116 in that cross-section is more than 10.0 μm and less than or equal to 30.0 μm. In this way, the thickness of the peeling assist layer 116 can be made thinner than the height of the unevenness of the slice surface that occurs when a conventional SiC wafer without a peeling assist layer 116 is divided by laser slicing (generally about 20 to 50 μm), thereby reducing the amount of grinding debris generated in the processing step and reducing the amount of SiC waste. Furthermore, as shown in Figures 3 to 5, the peeling assist layer 116 is a part of the seed crystal 114 or the grown SiC crystal 115.

[0056] Furthermore, in the peel-off assist layer 116, as illustrated in Figure 4(c), the peel-off assist material consisting of voids formed by the grooves 202 and fine particles 211 or ions 221 is present at intervals of 200 μm or less in the planar direction parallel to the first main surface 40a and the second main surface 40b (left-right direction in the figure) and in a range of at least 500 μm (or 0.19 mm) ２ It is preferable that the layer is distributed over the area described above. In this way, when the first entity divides the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 in the wafer splitting step, it is possible to form a peeling assist layer 116 that can be easily peeled off with little force.

[0057] Figures 6A to 6C show examples of cross-sections of the SiC wafer 40 shown in Figure 3(c) when it is cut along a plane parallel to the first main surface 40a and passing through at least a portion of the peeling assist layer 116. Figure 6A shows an example of a cross-section when the peeling assist layer 116 is formed over the entire surface in the planar direction at a predetermined depth within the SiC wafer 40. Figure 6B shows an example of a cross-section when the peeling assist layer 116 is formed over the entire circumference of the region near the outer periphery within the SiC wafer 40. Figure 6C shows an example of a cross-section when the peeling assist layer 116 is partially formed in the region near the outer periphery within the SiC wafer 40. Note that the peeling assist layer 116 may be formed in arrangements other than those shown.

[0058] As shown in the examples above, the peeling aid layer 116 may be formed over the entire surface in the planar direction when the SiC wafer 40 is viewed from the direction of the first main surface 40a, or it may be formed only in a part of the area. A certain range in the planar direction, for example, a range of 500 μm or more (or 0.19 mm) ２ If the peeling aid layer 116 is distributed over the above area, the peeling aid layer 116 can be formed in any region within the SiC wafer 40.

[0059] <Wafer Provision Step> A new SiC wafer 40, composed of a seed crystal 114 and a grown SiC crystal 115, is provided to a second entity that is the same as or different from the source from which the remaining wafer that forms the basis of the SiC wafer was obtained. In this way, the acquired remaining wafer 112 is regenerated into such a new SiC wafer 40 and provided to the second entity, so the second entity can obtain a main wafer from that SiC wafer 40.

[0060] The above describes the acquisition step, processing step, pretreatment step, growth step, and wafer supply step.

[0061] In this embodiment, an inspection step is included between the acquisition step and the processing step to inspect the slice surface of the acquired remaining wafer 112. The inspection step is, for example, as follows:

[0062] <Inspection Step> The inspection step includes measuring at least one of the following: the height difference of the slice surface and the thickness of the processed altered layer having the slice surface. In this embodiment, both are measured. The height difference of the slice surface is the height difference caused by the surface irregularities resulting from the laser irradiation or the separation of the main wafer 111 and the remaining wafer 112 in the wafer splitting step.

[0063] The inspection step is performed by the inspection device 171. The inspection device 171 may include a laser microscope and a Raman spectrometer. The height difference of the slice surface may be measured using the laser microscope. The thickness of the processed altered layer may be measured using the Raman spectrometer. The measurement methods for both the height difference of the slice surface and the thickness of the processed altered layer are not limited to this example. For example, the height difference of the slice surface may be measured using a white light interferometer or a contact-type shape measuring instrument.

[0064] At least one of the following (x) and (y) may be performed. (x) The processing in the processing step includes determining the amount to remove from the slice surface based on at least one of the measured height difference of the slice surface of the acquired remaining wafer 112 and the measured thickness of the processed altered layer, and removing material from the slice surface according to the determined amount. This allows for appropriate (with minimal excess or deficiency) slicing of the slice surface according to the quality (condition) of the acquired remaining wafer 112. For example, if the PV value (maximum valley depth) is measured as an example of the height difference of the slice surface, and the processing altered layer depth is measured as an example of the thickness of the processed altered layer, then the amount to remove = PV value + (processed altered layer depth × N). N may be any value greater than 0 (for example, any natural number). A processing command associated with information representing the amount to remove may be input to the processing device 172 (or the control device of the processing device 172), and the processing device 172 may perform slicing according to that amount. The "amount of material removed" may be defined by parameter values ​​for each of one or more parameter items. Examples of parameter items include the processing time and processing power (e.g., temperature and pressure) of the processing apparatus 172. (y) In the growth step, the thickness of the growing SiC crystal to be grown is determined based on at least one of the measured height difference of the slice surface of the remaining wafer 112 and the measured thickness of the processed altered layer, and the growing SiC crystal is grown to the determined thickness. This allows for appropriate (with minimal excess or deficiency) crystal growth according to the quality (condition) of the acquired remaining wafer 112. For example, the thickness to be grown may be determined based on at least one of X, Y, Z, and α. Specifically, for example, the thickness to be grown may be X - Y + Z + α. X may be the thickness required at the start of the surface device step or wafer splitting step in the second entity (the thickness requested by the second entity). Y may be the thickness of the growing SiC crystal when received by the first entity. Z can be the amount of material removed as determined in (x) above. α can be any value determined as the machining margin (for example, about 50 μm) to remove the irregularities after growth and flatten the surface.A crystal growth command, associated with information indicating the thickness to be grown, may be input to the growth apparatus 174 (or the control device for the growth apparatus 174), thereby causing the growth apparatus 174 to grow a SiC crystal of that thickness on the seed crystal.

[0065] [Second Embodiment] The second embodiment will now be described. In this description, the differences from the first embodiment will be explained, and the similarities with the first embodiment will be omitted or simplified.

[0066] In the second embodiment, crystal growth in the growth step is carried out using the method disclosed in the prior application Patent Document 2 (WO2023 / 067736A1) by the same applicant as the present application (hereinafter, this method will be conveniently referred to as the "NGK method" based on the applicant's notation). That is, in the growth step, a SiC single crystal as a seed crystal and a SiC powder layer are placed in a container in contact with each other, and the container is placed in a firing furnace and heat treatment is performed, thereby growing a SiC single crystal on the seed crystal. According to the NGK method, it is possible to obtain a SiC single crystal (grown SiC crystal) with a lower BPD density than the sublimation method and a BPD density of about the same as that of the CVD method. The second embodiment can utilize all or part of the technology disclosed in Patent Document 2.

[0067] Furthermore, when crystal growth is performed using the NGK method, the flatness of the processed surface does not need to be as high as when crystal growth is performed using the sublimation or CVD methods, and the processed surface does not need to be perfectly flat. Specifically, for example, the following applies:

[0068] When homoepitaxial growth is performed on a seed crystal using sublimation or CVD, it is usually essential that the growth surface is atomically flat and that there is no processed or altered layer. This is because irregularities can form on the epitaxial growth surface, or defects such as dislocations can be introduced into the crystal.

[0069] On the other hand, because SiC wafers are hard and stable against heat and chemicals, surface planarization and removal of processing damage using the CMP method after slicing or grinding is extremely time-consuming, and the consumption of polishing slurry and polishing pads is also high.

[0070] Therefore, in this embodiment, in the processing step, the removal of the processed altered layer is performed by a thermal etching process, a surface oxidation process, or a plasma etching process (i.e., any process that results in a lower degree of flatness after etching than etching by the CMP method). Below, examples of each process for removing the processed altered layer in the processing step of the second embodiment will be described. In this embodiment, etching other than the thermal etching process, surface oxidation process, and plasma etching process, such as etching by the CMP method, or etching by other etching processes (e.g., hydrogen etching) may be performed.

[0071] Figure 7 schematically illustrates the thermal etching process.

[0072] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a thermal etching process. This apparatus is illustrated in Figure 7. In the thermal etching process, the surface of the remaining wafer (including the processed altered layer) that has been heated and processed in the electric furnace 302 is sublimated to a thickness of several micrometers.

[0073] For example, gas (such as nitrogen or argon, an inert gas) is introduced into an electric furnace 302, which is made of insulating material and equipped with a heater 301, through a gas pipe 305, creating an inert gas atmosphere inside the electric furnace 302. The electric furnace 302 may also be under vacuum.

[0074] The material is heated by heater 301, but the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 1000 to 2000°C), and may be set taking into account the required amount of etching (for example, 1800°C may be set). The holding time at the maximum temperature is a time within a certain time range (for example, 1 minute to 5 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0075] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 303 (for example, graphite) on a spacer 304 (for example, graphite), or it may be placed using a sheath or the like made of a heat-resistant material.

[0076] If the surface of the remaining wafer 112 is carbonized after this thermal etching process, the carbonized layer on the surface may be removed by annealing in an atmospheric furnace or the like, or by polishing or other processing. To prevent surface carbonization, a carbon getter material such as Ta may be placed inside the electric furnace 302.

[0077] Figure 8 schematically illustrates the surface oxidation process.

[0078] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a surface oxidation process. This apparatus is illustrated in Figure 8. In the surface oxidation process, the surface of the remaining wafer (including the processed altered layer) that has been heated in an oxidizing atmosphere (including an air atmosphere) in an electric furnace 402 is oxidized to a thickness of several micrometers. The oxide film may be removed by processing such as polishing, or it may be volatilized or melted (reacted with the raw material powder) during crystal growth.

[0079] For example, in an electric furnace 402 made of insulating material and equipped with a heater 401, the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 800 to 2000°C), and may be set taking into account the required amount of etching (for example, 1400°C may be set). Also, the holding time at the maximum temperature is a time within a certain time range (for example, 5 minutes to 50 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0080] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 403 (for example, alumina) on a spacer 404 (for example, alumina).

[0081] Figure 9 schematically illustrates the plasma etching process.

[0082] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a plasma etching process. This apparatus is an example of the apparatus shown in Figure 9. In the plasma etching process, the surface of the remaining processed wafer (including the processed altered layer) is etched to a thickness of several micrometers.

[0083] Plasma etching includes methods such as RIE (Reactive Ion Etching), ECR (Electron Cyclotron Resonance), ICP (Inductively Coupled Plasma), and CCP (Capacitively Coupled Plasma), but there are no particular limitations; for example, RIE can be applied.

[0084] The substrate temperature, gas type, processing time, and apparatus configuration may be set as appropriate depending on the desired etching rate and surface condition. The remaining wafer surface may be pre-treated by ashing or other methods to remove any surface deposits.

[0085] An upper electrode 501 and a lower electrode 503 are located in the chamber 502. Gas is introduced from the gas introduction pipe 505 and exhausted from the gas exhaust pipe 504, and plasma is generated between electrodes 501 and 503 by the high-frequency power supply 509s.

[0086] The above is an explanation of examples of each process related to the removal of the processed altered layer in the processing step according to the second embodiment. Furthermore, there are differences between the sublimation method, CVD method and the NGK method regarding crystal growth, for example, as follows.

[0087] In other words, while sublimation and CVD methods require precise cleaning after CMP polishing and before epitaxial layer formation, the NGK method does not require such cleaning.

[0088] Furthermore, in sublimation and CVD methods, the rapid heating rate increases the likelihood of seed crystal warping and subsequent breakage. Also, in sublimation and CVD methods, multiple seed crystals can be placed in the growth chamber, but if even one seed crystal is damaged, it will affect the others. On the other hand, in the NGK method, the heating rate is slower than in sublimation and CVD methods, so even if the seed crystal is slightly warped, the likelihood of breakage due to that warping is low. In addition, in the NGK method, one seed crystal is stored in each container, so even if one seed crystal is damaged, it will not affect the others.

[0089] Furthermore, in both the second and first embodiments, the diameter of the remaining wafer 112 acquired in the acquisition step may be 6 inches or more, and for example, the diameter of the remaining wafer may be 8 inches or more (for example, in the second embodiment). For example, in both cases where the diameter is 6 inches or 8 inches, the thickness of the main wafer 111 may be about 100 μm, but in the case of a 6-inch diameter, the thickness of the remaining wafer 112 may be about 250 μm, and in the case of an 8-inch diameter, the thickness of the remaining wafer 112 may be about 400 μm.

[0090] The present invention will be further described in detail by the following examples. However, the present invention is not limited to the following examples.

[0091] Example 1 (Comparison) (1) Pretreatment As shown in Figure 5(a), a commercially available disc-shaped SiC single crystal substrate (4H-SiC, diameter 150 mm (6 inches), off-angle 4°, thickness 0.35 mm) was prepared as the seed crystal 113a. As shown in Figure 5(b), hydrogen ions (corresponding to the peeling aid substance) were implanted as ions 221 into the SiC single crystal substrate in order to form the peeling aid layer 116 described later. The conditions for implanting hydrogen ions at this time were: the depth of ion implantation was 1 μm in the thickness direction from the surface of the SiC single crystal substrate, the acceleration voltage was 170 keV, and the implantation dose was 8 × 10⁻⁶ １５ ions / cm ２ , and the temperature was 500°C.

[0092] (2) Preparation of SiC mixed powder Commercially available β-SiC powder (volume-based D50 particle size: 65.0 μm) and an oxide (Gd) which is a liquid phase formation aid ２ O ３The oxides (D50 particle size based on volume: 5.0 μm) were weighed so that the oxide content relative to the SiC powder content was 8.1% by weight, and then placed in a polypropylene container along with pebbles and water. After placing the polypropylene container on a pot stand, the container was rotated at a speed of 50 rpm to mix the raw materials. The slurry obtained by mixing the raw materials was dried in a dryer and collected to obtain SiC mixed powder.

[0093] (3) Arrangement of SiC mixed powder and seed crystal The SiC single crystal substrate as the seed crystal 113a pretreated in (1) and the SiC mixed powder obtained in (2) were placed in a graphite container.

[0094] (4) Heat treatment The graphite container prepared in (3) above was placed in a resistance furnace (firing furnace) and heat-treated in an argon atmosphere at a set temperature of 1500°C for 1 hour to form a peeling aid layer 16. Next, the graphite container was placed in a location in the resistance furnace (firing furnace) where the temperature range was within ±75°C of the set temperature and heat-treated in a mixed gas atmosphere of argon and nitrogen at a set temperature of 2450°C for 20 hours. As a result, as shown in Figure 1 (see also Figure 5(c)), a SiC wafer 10 was obtained in which a SiC single crystal was grown on a SiC single crystal substrate, a SiC growth layer 14 was provided on the SiC seed crystal layer 12, and a peeling aid layer 16 was formed inside the SiC seed crystal layer 12.

[0095] (5) Measurement of the crystal growth thickness of the SiC wafer The thickness of 25 arbitrary locations on the SiC wafer 10 obtained in (4) above was measured with a micrometer, and the arithmetic mean was calculated. The thickness of the seed crystal 113a was also calculated at the time of (3) above using the same method. Then, the crystal growth thickness (μm) of the SiC growth layer 14 was calculated by subtracting the arithmetic mean of the thickness of the seed crystal 113a from the arithmetic mean of the thickness of the SiC wafer 10. As a result, it was confirmed that the crystal growth thickness of the SiC growth layer 14 was 100 μm or more.

[0096] (6) Polishing The surface (Si surface and C surface) of the SiC wafer 10 obtained in (4) above was polished using diamond abrasive grains, and then chemical mechanical polishing (CMP) was performed.

[0097] (7) Device fabrication process A SiC-MOSFET device was formed on the SiC growth layer 14 of the polished SiC wafer 10 obtained in (6) above.

[0098] (8) Peeling off the SiC seed crystal layer A pulsed laser with a wavelength of 1064 nm was irradiated as incident light onto the peeling auxiliary layer 16 from the SiC seed crystal layer 12 side of the SiC wafer 10 obtained in (7) above. By scanning this pulsed laser light in the in-plane direction of the SiC wafer 10, the SiC seed crystal layer 12 was peeled off from the SiC wafer 10 along the peeling auxiliary layer 16. The laser irradiation conditions at this time were an irradiation fluence of 100 J / cm ２ The pulse width was set to 10 ns, and the laser focusing position was set to a depth of 200 μm in the thickness direction from the surface of the SiC wafer 10 on the SiC seed crystal layer 12 side. As a result, the SiC wafer 10 on which the SiC-MOSFET device was formed was divided into a main wafer 111 (SiC growth layer 14 on which the device was formed) and a remaining wafer 112 (SiC seed crystal layer 12).

[0099] (9) Evaluation of flatness (good product rate) after peeling A total of 100 SiC wafers 10 on which SiC-MOSFET devices were formed were prepared using the same procedure as in (1) to (7) above. These SiC wafers 10 were divided into 100 sets of main wafers 111 and remaining wafers 112 using the same procedure as in (8) above. In accordance with ISO 25178, the maximum height Sz and arithmetic mean height Sa of the peeled surface of the obtained main wafers 111 and remaining wafers 112 were measured using a laser microscope. For each set, the wafer with the larger maximum height Sz and arithmetic mean height Sa was selected. If the maximum height Sz of the selected wafer was 25 μm or less and the arithmetic mean height Sa was 3 μm or less, it was considered "acceptable". If the maximum height Sz of the selected wafer exceeded 25 μm or the arithmetic mean height Sa exceeded 3 μm, it was considered "unacceptable". The percentage of good products was calculated from the perspective of flatness of the peeled surface by counting the number of wafers that passed the test out of 100 sets of main wafers 111 and remaining wafers 112. The results are shown in Table 1.

[0100] (10) Thickness measurement of the peeling aid layer In the SiC wafer 10 on which the SiC-MOSFET device obtained in (7) above is formed, the layer of the SiC-MOSFET device is removed from the surface on the SiC growth layer 14 side (first main surface 40a), and further polished by a predetermined thickness from the surface of the SiC seed crystal layer 12 (second main surface 40b), thereby measuring the hydrogen concentration (atoms / cm³) at a depth position corresponding to that thickness. ３ The hydrogen concentration at each depth was measured. This measurement was performed at approximately 1 μm intervals at depths of 310 to 370 μm in the thickness direction from the second main surface 40b after the device layer removal, to confirm the hydrogen concentration at each depth. The hydrogen concentration at this time was 1.0 × 10⁻⁶. １８ atoms / cm ３ The thickness (μm) of the peeling aid layer 16 was calculated by considering the depth position where the above occurs as the region where the peeling aid layer 16 exists. Dynamic secondary ion mass spectrometry (D-SIMS) was used to measure the hydrogen concentration at this time. For this D-SIMS measurement, an IMF-6f manufactured by CAMECA was used as the analytical instrument, and the primary ion species Cs ＋ The experiment was also conducted under the condition of an acceleration voltage of 15.0 kV. The results are shown in Table 1.

[0101] (11) Confirmation of rare earth element concentration The SiC-MOSFET device layer of the SiC wafer 10 on which the SiC-MOSFET device obtained in (7) above is formed is removed, and the surface (second main surface 40b) of the SiC seed crystal layer 12 is polished by 360 μm in the thickness direction, thereby determining the rare earth element concentration (atoms / cm³) at a depth position corresponding to that thickness. ３ The concentration of rare earth elements (atoms / cm³) in the SiC growth layer 14 was measured. ３ ) was confirmed. Dynamic secondary ion mass spectrometry (D-SIMS) was used to measure the concentration of rare earth elements at this time. For this D-SIMS measurement, the IMF-6f manufactured by CAMECA was used as the analytical instrument, and the primary ion species O ２ ＋ The experiment was also conducted under the condition of an acceleration voltage of 8 kV. The results are shown in Table 1.

[0102] Example 2 In Example 2, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that the heat treatment for forming the peeling auxiliary layer was performed for 2 hours as described in (4) above. The results are shown in Table 1.

[0103] Example 3 In Example 3, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that the heat treatment for forming the peeling auxiliary layer was performed for 3 hours as in (4) above. The results are shown in Table 1.

[0104] Example 4 In the same procedure as in Example 1, except that the heat treatment for forming the peeling auxiliary layer was performed at 1800°C for 3 hours, the SiC wafer 10 and other components were fabricated and various evaluations were carried out. The results are shown in Table 1.

[0105] Example 5 In Example 5, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that the heat treatment for forming the peeling auxiliary layer was carried out at 1800°C for 6 hours as in (4) above. The results are shown in Table 1.

[0106] Example 6 In Example 6, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that the heat treatment for forming the peeling auxiliary layer was carried out at 1800°C for 9 hours as in (4) above. The results are shown in Table 1.

[0107] Example 7 (Comparison) Except for the heat treatment performed at 1800°C for 12 hours to form the peeling auxiliary layer in (4) above, the SiC wafer 10 and other components were fabricated and various evaluations were attempted in the same manner as in Example 1. However, in (7) above, the SiC seed crystal layer spontaneously peeled off during the device fabrication process, making it impossible to calculate the yield rate in (9) above. When the peeled surfaces of the main wafer 111 and the remaining wafer 112 were observed with a laser microscope at the time of spontaneous peeling, the maximum height Sz of the peeled surfaces of the main wafer 111 and the remaining wafer 112 were 37.3 μm and 40.8 μm, respectively, and the arithmetic mean height Sa was 5.4 μm and 6.3 μm, respectively. The other evaluation results are shown in Table 1.

[0108] Example 8 (Comparison) In this example, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that ion implantation was not performed in (1) above, and heat treatment for the formation of the peeling auxiliary layer was not performed in (4) above. The results are shown in Table 1.

[0109] Example 9 In the same procedure as in Example 3, except that the oxide content relative to the SiC powder content was weighed to be 0.8% by weight, the SiC wafer 10 and other components were prepared and various evaluations were performed. The results are shown in Table 1.

[0110] Example 10 In (2) above, an oxide (Y) is used as a liquid phase formation aid. ２ O ３ Except for using (volume-based D50 particle size: 5.0 μm), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 3. The results are shown in Table 1.

[0111] Example 11 In (2) above, an oxide (Sm) is used as a liquid phase formation aid. ２ O ３ Except for using (volume-based D50 particle size: 5.0 μm), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 3. The results are shown in Table 1.

[0112] Example 12 In (2) above, an oxide (La ２ O ３ Except for using (volume-based D50 particle size: 5.0 μm), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 3. The results are shown in Table 1.

[0113] Example 13 In (2) above, an oxide (CeO) is used as a liquid phase formation aid. ２ Except for using (volume-based D50 particle size: 5.0 μm), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 3. The results are shown in Table 1.

[0114] Example 14 In (2) above, an oxide (Nd ２ O ３Except for using (volume-based D50 particle size: 4.0 μm), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 3. The results are shown in Table 1.

[0115] Example 15 (Comparison) In the same manner as in Example 1, except that an oxide was not added as a liquid phase formation aid as in (2) above, the SiC wafer 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 1.

[0116] Example 16 In Example 16, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 3, except that an oxide was not added as a liquid phase formation aid as in (2) above. The results are shown in Table 1.

[0117] Example 17 (Comparison) In the same manner as in Example 7, except that an oxide was not added as a liquid phase generation aid in (2) above, we attempted to manufacture a SiC wafer 10 and perform various evaluations. However, in (7) above, the SiC seed crystal layer spontaneously peeled off during the device manufacturing process, making it impossible to calculate the yield rate in (9) above. The other evaluation results are shown in Table 1.

[0118] Example 18 In Example 18, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 3, except that a commercially available disc-shaped SiC single crystal substrate (4H-SiC, 200 mm diameter (8 inches), off-angle 4°, thickness 0.35 mm) was prepared as the seed crystal 113a in (1) above. The results are shown in Table 1.

[0119]

[0120] From Table 1, it is presumed that when the thickness of the peeling aid layer exceeds 10.0 μm, the peeling aid layer becomes easier to target with the laser, thus increasing the uniformity of the modified layer formed by laser irradiation and improving the flatness of the peeled surface. Furthermore, although the cause is unclear, it was found that when the thickness of the peeling aid layer exceeds 30.0 μm, the SiC seed crystal layer spontaneously peels off before the peeling process described in (8) above, resulting in a deterioration of the flatness of the peeled surface. Note that in the SiC wafers 10 of Examples 2-6, 9-14, 16, and 18, the peeling aid layer 16 has a region in which the peeling aid material is distributed at intervals of 200 μm or less in the in-plane direction of the SiC wafer 10, and this region is 0.19 mm. ２ It can be said that the peeling aid layer 16 is present over an area of ​​the above (or at least a range of 500 μm or more), that is, it is present to a certain extent evenly in the in-plane direction of the SiC wafer 10.

[0121] 10, 40 SiC wafer 12 SiC seed crystal layer 14 SiC growth layer 16, 116 Peeling aid layer 111 Main wafer 112 Remaining wafer 113a, 113b Seed crystal 114 Pre-treated seed crystal 115 Grown SiC crystal 171 Inspection device 172 Processing device 173 Pre-treatment device 174 Growth device I Ion

Claims

1. A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peeling assist layer is formed inside and / or on the surface of at least one of the first crystal layer and the second crystal layer, the peeling assist layer is a SiC-derived layer containing voids or peeling assist material, and the peeling assist layer has a thickness of more than 10.0 μm and less than or equal to 30.0 μm.

2. The SiC wafer according to claim 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer.

3. The second crystal layer is 5.00 × 10 １３ atoms / cm ３ A SiC wafer according to claim 1 or 2, having a portion containing rare earth elements at the above concentration.

4. The peeling aid layer has a region in which the voids or the peeling aid material are distributed at intervals of 200 μm or less in the in-plane direction of the SiC wafer, and the region is 0.19 mm ２ A SiC wafer according to claim 1 or 2, which extends over the above area.

5. The SiC wafer according to claim 1 or 2, wherein the peeling aid is at least one ion selected from the group consisting of Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements.

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