SiC WAFER

Abstract

Provided is a SiC wafer which, after a device has been formed thereon, can be easily divided into a portion where the device is formed and a portion where the device is not formed (in other words, has good separability), and in which the occurrence of wafer breakage and cracking is suppressed. This SiC wafer comprises a SiC seed crystal layer and a SiC growth layer including a SiC single crystal grown from the SiC seed crystal layer, wherein: a separation promoting layer(s) is / are formed on the interior and / or the surface of the SiC seed crystal layer and / or the SiC growth layer; and within a prescribed region inside and / or around the separation promoting layer(s), the Raman shift value or half width of an E2mode transverse wave optical aliasing peak is minimized and satisfies a prescribed condition.

Description

SiC wafer

[0001] This disclosure relates to SiC wafers.

[0002] Silicon carbide (SiC) is attracting attention as a wide-bandgap material that can control high currents and high voltages with low loss. In particular, power semiconductor devices using SiC material (SiC power devices) have recently been expected to be used in a variety of applications because they are superior to those using Si semiconductors in terms of miniaturization, low power consumption, and high efficiency. For example, by adopting SiC power devices, converters, inverters, and on-board chargers for electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs) can be miniaturized and their efficiency improved.

[0003] Incidentally, Patent Document 1 (Japanese Patent Application Publication No. 2023-73458) discloses a method in which, after forming a device (for example, electrodes or wiring patterns) on the surface of a semiconductor wafer, a laser focused at a predetermined depth in the thickness direction of the semiconductor wafer is irradiated at regular intervals to form a modified layer in the planar direction within the semiconductor wafer, and the semiconductor wafer is divided into a device-formed portion and an unformed portion starting from this modified layer.

[0004] Japanese Patent Publication No. 2023-73458 WO2023 / 067736A1

[0005] However, in methods such as those disclosed in Patent Document 1, when the formation of the modified layer within the semiconductor wafer is insufficient, a strong force is required to separate the crystal structures of the wafers when dividing the semiconductor wafer into a device-formed portion and a non-device-formed portion. As a result, distortion occurs in the device-formed portion, which makes it prone to cracking and fractures. Therefore, there is a need for a SiC wafer that can be easily separated into a device-formed portion and a non-device-formed portion after device formation while suppressing the occurrence of cracking and fractures in the wafer (i.e., having good peelability).

[0006] The present inventors have now developed a method for measuring E in a SiC wafer having a first crystal layer such as a SiC seed crystal layer and a second crystal layer such as a SiC growth layer, in Raman spectroscopy. ２We have found that by forming a peel-promoting layer such that the Raman shift value or full width at half maximum of the transverse wave optical folding peak takes a minimum value in a predetermined region in the thickness direction and satisfies predetermined conditions, it is possible to provide a SiC wafer that can be easily separated (i.e., has good peelability) while suppressing the occurrence of cracks and fractures in the wafer when dividing it into a device-formed portion and an unformed portion after device formation on the wafer.

[0007] Therefore, an object of the present invention is to provide a SiC wafer that can be easily separated into a device-formed portion and an unformed portion after device formation on the wafer, while suppressing the occurrence of cracks and fractures in the wafer (i.e., has good peelability).

[0008] The following embodiments are provided according to this disclosure: [Embodiment 1] A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peel-promoting layer is formed inside and / or on the surface of at least one of the first crystal layer and the second crystal layer, and the first main surface which is the surface of the SiC wafer on the second crystal layer side, the second main surface which is the surface of the SiC wafer on the first crystal layer side, the first interface which is the interface between the peel-promoting layer and the second crystal layer or the first crystal layer that is closer to the first main surface, and the second interface which is the interface between the peel-promoting layer and the second crystal layer or the first crystal layer that is closer to the second main surface are parallel to each other. A coordinate system is assigned to the SiC wafer such that (i) the z-axis is set perpendicular to the first and second principal surfaces, and the direction from the second principal surface toward the first principal surface is considered positive (where the position of the second interface is defined as z=0), and (ii) the x-axis is set in the direction obtained by rotating the z-axis 90° clockwise is considered positive (where x=0 is defined as the center point when the SiC wafer is viewed from above). For each measurement point positioned in a grid at 5 μm intervals in the cross section in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, the E of the Raman spectrum is measured. ２When measuring the Raman shift value of the mode transverse optical folding peak, with the z-coordinate as the horizontal axis, the Raman shift value (cm －１ )−1) from 786±α (cm －１ −1) (where 0≦α≦10), the average value obtained by subtracting the standard shift value appearing in the range is plotted on a graph with the vertical axis corresponding thereto. In the graph, a region giving a minimum value k ｍ exists within the range of −20 μm≦z≦20 μm, and the minimum value k ｍ and the Raman shift value (cm －１ −1) in the range of −80 μm≦z≦−20 μm, the average value k obtained by subtracting the standard shift value therefrom Ｓ the difference (k Ｓ −k ｍ ) is 0.150 cm －１ −1 or more, the SiC wafer. [Aspect 2] In the graph, a region giving a maximum value k Ｍ (cm －１ −1) exists within the range of 0 μm≦z≦40 μm, and the maximum value k Ｍ and the average value k Ｓ the difference (k Ｍ −k Ｓ ) is 0.150 cm －１The SiC wafer according to Embodiment 1 is described above. [Embodiment 3] A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peel-promoting layer is formed inside and / or on the surface of at least one of the first crystal layer and the second crystal layer, and the first main surface which is the surface of the SiC wafer on the second crystal layer side, the second main surface which is the surface of the SiC wafer on the first crystal layer side, the first interface which is the interface between the peel-promoting layer and the second crystal layer or the first crystal layer that is closer to the first main surface, and the second interface which is the interface between the peel-promoting layer and the second crystal layer or the first crystal layer that is closer to the second main surface are parallel to each other. A coordinate system is assigned to the SiC wafer such that (i) the z-axis is set perpendicular to the first and second principal surfaces, and the direction from the second principal surface toward the first principal surface is considered positive (where the position of the second interface is defined as z=0), and (ii) the x-axis is set in the direction obtained by rotating the z-axis 90° clockwise is considered positive (where x=0 is defined as the center point when the SiC wafer is viewed from above). For each measurement point positioned in a grid at 5 μm intervals in the cross section in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, the E of the Raman spectrum is measured. ２ Mode transverse wave optical aliasing peak width at half maximum (cm) －１ When measuring ), in a graph plotted with the z-coordinate on the horizontal axis and the average of the half-width at each z-coordinate corresponding to the vertical axis, the minimum value w is found in the range -20 μm ≤ z ≤ 20 μm. ｍ There exists a region that gives the same result, and the local minimum value w ｍ And, the full width at half maximum (cm) in the range of -80 μm ≤ z ≤ -20 μm －１ ) The average value lol Ｓ The difference (lol) ｓ -w ｍ A SiC wafer having a coefficient of 0.240 or higher. [Aspect 4] A SiC wafer according to any one of aspects 1 to 3, wherein the first crystal layer is a SiC seed crystal layer and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer. [Aspect 5] The second crystal layer is 5.0 × 10 １３atoms / cm ３ A SiC wafer according to any one of embodiments 1 to 4, having a portion containing rare earth elements at the above concentration, wherein the rare earth element includes at least one selected from the group consisting of Gd, Sm, La, Nd, Y, and Ce. [Embodiment 6] The second crystal layer is 1.0 × 10 １８ atoms / cm ３ A SiC wafer according to any one of embodiments 1 to 5, having a portion containing nitrogen atoms at the above concentration. [Embodiment 7] A SiC wafer according to any one of embodiments 1 to 6, wherein the peel-promoting layer is a layer derived from SiC and includes voids, a peel-promoting substance, or an amorphous portion. [Embodiment 8] A SiC wafer according to embodiment 7, wherein the peel-promoting substance is at least one ion selected from the group consisting of group 1 elements, group 13 elements, group 14 elements, group 15 elements, and group 18 elements.

[0009] This is a schematic cross-sectional view showing an example of a SiC wafer according to the present disclosure. This is a diagram showing an example of the overall system configuration according to the first embodiment of the present disclosure. This is an explanatory diagram of a pretreatment for forming a layer containing minute voids. This is an explanatory diagram of a pretreatment for forming a layer containing a peel-promoting substance. This is an explanatory diagram of a pretreatment for forming a layer containing another peel-promoting substance. This is a diagram showing an example of the appearance of the cross-section when a SiC wafer is cut along a plane passing through the peel-promoting layer. This is a diagram showing another schematic diagram showing the thermal etching process in a first example of the processing step according to the second embodiment of the present disclosure. This is a schematic diagram showing the surface oxidation process in a second example of the processing step according to the second embodiment of the present disclosure. This is a schematic diagram showing the plasma etching process in a third example of the processing step according to the second embodiment of the present disclosure. This is a diagram showing the Raman shift value (cm) at each z-coordinate in Example 3 of the SiC wafer according to the present disclosure, with the z-coordinate on the horizontal axis and the Raman shift value (cm) at each z-coordinate on the vertical axis. －１ ) to standard shift value (786cm) －１ This graph plots the average value obtained by subtracting ( ) and assigning it to the corresponding value.

[0010] The SiC wafer of this disclosure comprises a first crystal layer containing a SiC single crystal and a second crystal layer containing a SiC single crystal formed on the first crystal layer. Therefore, the SiC wafer of this disclosure is mainly composed of a SiC single crystal and is usable as a SiC single crystal wafer. Here, the expression "mainly composed of a SiC single crystal" means that the main part of the SiC wafer other than the peeling accelerator layer is composed of a SiC single crystal, regardless of whether the SiC-derived peeling accelerator layer described later maintains the form of a SiC single crystal or not. Typically, the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing a SiC single crystal grown from the SiC seed crystal layer, and therefore the SiC wafer as a whole can be composed of one SiC single crystal (or even if not, it can be mainly composed of a SiC single crystal). Therefore, the following explanation will be based on a SiC wafer in which the first crystal layer is a SiC seed crystal layer and the second crystal layer is a SiC growth layer.

[0011] Figure 1 conceptually shows a SiC wafer 10. The SiC wafer 10 comprises a SiC seed crystal layer 12 (first crystal layer) and a SiC growth layer 14 (second crystal layer) containing a SiC single crystal grown from the SiC seed crystal layer 12. In addition, a peel-promoting layer 16 is formed inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. Here, (i) the first main surface 10a, which is the surface of the SiC wafer 10 on the SiC growth layer 14 side, (ii) the second main surface 10b, which is the surface of the SiC wafer 10 on the SiC seed crystal layer 12 side, (iii) the first interface 16a, which is the interface between the peeling acceleration layer 16 and the SiC growth layer 14 or SiC seed crystal layer 12 that is closer to the first main surface 10a, and (iv) the second interface 16b, which is the interface between the peeling acceleration layer 16 and the SiC growth layer 14 or SiC seed crystal layer 12 that is closer to the second main surface 10b, are parallel to each other. Furthermore, when Raman spectroscopy is performed on the cross-section of the SiC wafer 10, E is found inside and / or around the peeling acceleration layer 16. ２ Mode transverse wave optical aliasing peak (E ２The Raman shift value or full width at half maximum (FTO peak) is configured to take a minimum value and satisfy predetermined conditions. This makes it possible to provide a SiC wafer 10 that can be easily separated into a device-formed portion and an unformed portion after device formation on the wafer, while suppressing the occurrence of cracks and fractures in the wafer (i.e., has good peelability).

[0012] In other words, as described above, in methods such as those disclosed in Patent Document 1, when the formation of the modified layer within the semiconductor wafer is insufficient, a strong force is required to separate the crystal structures of the wafers when dividing the semiconductor wafer into a device-formed portion and a non-device-formed portion. As a result, distortion occurs in the device-formed portion, which makes it prone to cracking and fractures. Therefore, there is a need for a SiC wafer that can be easily divided into a device-formed portion and a non-device-formed portion after device formation while suppressing the occurrence of cracking and fractures in the wafer (i.e., having good peelability). This problem is successfully resolved according to the present invention.

[0013] As described above, in the present invention, when Raman spectroscopy is performed on a cross-section of the SiC wafer 10, E is detected in a predetermined region inside and / or around the peeling acceleration layer 16. ２ Mode transverse wave optical aliasing peak (E ２ - The Raman shift value or full width at half maximum of the FTO peak takes a minimum value and satisfies predetermined conditions. That is, the present invention is broadly divided into two aspects: (A) an aspect characterized by the Raman shift value (hereinafter referred to as aspect (A)), and (B) an aspect characterized by the full width at half maximum (hereinafter referred to as aspect (B)). Each aspect will be described in detail below.

[0014] (A)E ２- Aspects characterized by the Raman shift value of the FTO peak In this aspect (A), an x-z ​​coordinate system is assigned to the SiC wafer 10 such that (i) the z axis is set perpendicular to the first principal surface 10a and the second principal surface 10b, and the direction from the second principal surface 10b toward the first principal surface 10a is considered positive (however, the position of the second interface 16b is defined as z=0), and (ii) the x axis is set such that the direction obtained by rotating the z axis clockwise by 90° is considered positive (however, the center point when the SiC wafer 10 is viewed from above is defined as x=0). In this x-z coordinate system, in the cross section of the SiC wafer 10 in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, for each measurement point positioned in a grid at 5 μm intervals, the E of the Raman spectrum is ２ Mode transverse wave optical folding peak (786 cm) －１ (Appears nearby) Raman shift value k (cm －１ Next, with the z-coordinate as the horizontal axis, the Raman shift value k at each z-coordinate is measured to 786 ± α (cm). －１ ) (where 0 ≤ α ≤ 10, typically 0 ≤ α ≤ 5, more typically 0 ≤ α ≤ 3) is the standard shift value that appears in this range (e.g., 786 cm). －１ A graph is obtained by plotting the average value of the value obtained by subtracting (for example, k-786) (reflecting all x-coordinate values ​​on a given z-coordinate) on the vertical axis. In this graph, the SiC wafer 10 has a minimum value k in the range of -20 μm ≤ z ≤ 20 μm. ｍ There exists a region that gives k. Also, this local minimum value k ｍ And, the Raman shift value (cm) in the range of -80 μm ≤ z ≤ -20 μm －１ The average value k obtained by subtracting the above standard shift value from ) Ｓ The difference (k Ｓ -k ｍ ) is 0.150 cm －１This concludes the explanation. When Raman spectroscopy measurements are performed on a cross-section of the SiC wafer 10, it is found that the SiC wafer 10 has these characteristics inside and / or around the peeling acceleration layer 16, which allows for easy separation of the wafer into a device-formed portion and an unformed portion after device formation, while suppressing the occurrence of cracks and fractures (i.e., improving peelability). The reason for this is not clear, but the presumed mechanism is that stress concentrates inside and / or around the peeling acceleration layer 16 in the SiC wafer 10 having the above characteristics, making it easier for the SiC crystals in the area irradiated with a laser during wafer peeling to decompose, thus allowing the wafer to be easily peeled off.

[0015] Here, the "center point," which is the point where x = 0 when the SiC wafer 10 is viewed from above, is typically defined as the center point of the largest circle inscribed within the outer edge of the wafer when the wafer is viewed from above (or from above). Alternatively, if the SiC wafer 10 is rectangular, the intersection of the diagonals on the SiC wafer 10 may be defined as the "center point." Furthermore, the standard shift value is determined by the measurement equipment and measurement environment (measurement conditions) used for Raman spectroscopy, and E ２ - FTO peak is 786 cm －１ From a few centimeters －１ The degree of deviation may vary. For example, when performing Raman spectroscopy, E ２ - FTO peak is 784 cm －１ If it appears at (i.e., α=2 in "786-α"), then the Raman shift value k is 786 cm. －１ Calculating the above average value based on the subtracted value will result in an incorrect graph. To avoid such calculation errors, the range in which the standard shift value appears should be set to 786 ± α (cm) to allow for a shift (α). －１ (where 0 ≤ α ≤ 10), i.e., 776–796 cm －１ They have identified it as such.

[0016] Next, we will explain a specific example of the process of obtaining a graph in which the z-coordinate is plotted on the horizontal axis and the average value of k- (standard shift value) at each z-coordinate is plotted on the vertical axis. For convenience, here we will use a standard shift value of 786 cm.－１ The following explanation assumes this is the case, but in reality, the standard shift value is 776-796 cm as mentioned above. －１ It can be any value within the range. First, Raman spectral measurements are performed at 5 μm intervals in the x-z coordinate system of the cross-section of the SiC wafer 10, in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, that is, in the range of 50 μm × 160 μm of the cross-section of the SiC wafer 10. Therefore, Raman spectra will be obtained at a total of (50 / 5) × (160 / 5) = 320 measurement points. ２ - The FTO peak is generally 786 cm. －１ (This appears as a standard shift value, but in reality, it is 786 cm, depending on the strain within the crystal.) －１ Since it appears at a position slightly shifted from the original position, that position is called the Raman shift value k (cm －１ ) The value k obtained by subtracting the standard shift value from the Raman shift value k. ｚ，ｘ (that is, k ｚ，ｘ We find k = k - 786). ｚ，ｘ The "z" indicates the position (μm) of the z coordinate at each measurement point, and k ｚ，ｘ The "x" indicates the x-coordinate position (μm) at each measurement point. Therefore, there are a total of 320 k ｚ，ｘ This will result in the following: Based on this, for example, when the z-coordinate position is -80 μm, k at all x-coordinates ｚ，ｘ The average value of k ａ，－８０ Calculate the k value for all x coordinates when the z coordinate position is -75 μm. ｚ，ｘ The average value of k ａ，－７５ For example, the average value k at each z-coordinate is calculated. ａ，ｚ Calculate the result. The result of this calculation is shown in Table 1 below.

[0017]

[0018] Based on Table 1, the z-coordinate is used as the horizontal axis, and the average value k at each z-coordinate is used. ａ，ｚ By plotting the values ​​on the vertical axis, the above graph can be obtained.

[0019] The SiC wafer 10 has a minimum value k within the range of -20 µm ≤ z ≤ 20 µm in the above graph ｍ provided in a region exists, and the position of the z-coordinate at which the minimum value k ｍ is obtained is preferably within the range of -15 µm ≤ z ≤ 15 µm, more preferably within the range of -10 µm ≤ z ≤ 10 µm, and still more preferably within the range of -5 µm ≤ z ≤ 5 µm. Here, the minimum value k ｍ exists among the values from k ａ，－２０ to k ａ，２０ in Table 1.

[0020] Further, in the above graph, the minimum value k provided within the range of -20 µm ≤ z ≤ 20 µm ｍ and the average value k obtained by subtracting the standard shift value from the Raman shift value k (cm －１ ) in the range of -80 µm ≤ z ≤ -20 µm Ｓ , the difference (k Ｓ - k ｍ ) is 0.150 cm －１ or more, and this difference (k Ｓ - k ｍ ) is preferably 0.150 to 0.440 cm －１ , more preferably 0.200 to 0.440 cm －１ , still more preferably 0.250 to 0.440 cm －１ . Here, the average value k Ｓ refers to the average value of the values from k ａ，－８０ to k ａ，－２０ in Table 1.

[0021] In the above graph, there exists a region where a maximum value k Ｍ (cm －１ ) is provided within the range of 0 µm ≤ z ≤ 40 µm, and the difference between the maximum value k Ｍ and the average value k Ｓ (k Ｍ - k Ｓ ) is preferably 0.150 cm －１ or more. The maximum value k Ｍ (cm －１The z-coordinate position that gives the value is more preferably in the range of 5 μm ≤ z ≤ 35 μm, even more preferably in the range of 5 μm ≤ z ≤ 30 μm, and particularly preferably in the range of 5 μm ≤ z ≤ 25 μm. Maximum value k Ｍ and the average value k Ｓ The difference (k Ｍ -k Ｓ ) is more preferably 0.150 to 0.450 cm －１ More preferably 0.200 to 0.450 cm －１ Particularly preferred is 0.250 to 0.450 cm －１ Here, the maximum value is k. Ｍ In Table 1, k ａ，０ k ａ，４０ It can be said that it exists within the range of values ​​up to that point.

[0022] (B)E ２ - A mode characterized by the full width at half maximum of the FTO peak. In this mode (B), an x-z ​​coordinate system is assigned to the SiC wafer 10, similar to mode (A), and each measurement point is taken. For each of these measurement points, the E of the Raman spectrum is taken. ２ Mode transverse wave optical aliasing peak width at half maximum (cm) －１ Next, measure the z coordinate. Then, plot the z coordinate on the horizontal axis and the average value of the full width at half maximum (reflecting all x coordinate values ​​on a given z coordinate) on the vertical axis to obtain a graph. In this graph, the SiC wafer 10 has a local minimum value w in the range of -20 μm ≤ z ≤ 20 μm. ｍ There exists a region that gives this value. Also, this local minimum w ｍ And, the full width at half maximum (cm) in the range of -80 μm ≤ z ≤ -20 μm －１ ) The average value lol Ｓ The difference (lol) ｓ -w ｍThe ratio is 0.240 or higher. When Raman spectroscopy is performed on a cross-section of the SiC wafer 10, it is found that the SiC wafer 10 has these characteristics inside and / or around the peeling acceleration layer 16, which allows for easy separation of the wafer into a device-formed portion and an unformed portion after device formation, while suppressing the occurrence of cracks and fractures (i.e., improving peelability). The reason for this is not clear, but the estimated mechanism is that the atomic arrangement of the SiC crystals changes inside and / or around the peeling acceleration layer 16 in the SiC wafer 10 having the above characteristics, making it easier for the SiC crystals in the area irradiated with a laser during wafer peeling to decompose, thus allowing the wafer to be easily peeled off.

[0023] Next, we will explain a specific example of the process of obtaining a graph in which the z-coordinate is plotted on the horizontal axis and the average value of the half-width at each z-coordinate is plotted on the vertical axis. First, Raman spectrum measurements are performed at 5 μm intervals in the x-z coordinate system of the cross-section of the SiC wafer 10, in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, that is, in the range of 50 μm × 160 μm of the cross-section of the SiC wafer 10. Therefore, a total of (50 / 5) × (160 / 5) = 320 (points) of Raman spectra are obtained. As a result, the E at each z-coordinate and each x-coordinate is obtained. ２ - Half the width of the FTO peak lol ｚ，ｘ We will find this. ｚ，ｘ The "z" in the w column indicates the position of the z-coordinate (μm) at each measurement point. ｚ，ｘ The "x" indicates the x-coordinate position (μm) at each measurement point. Therefore, there are a total of 320 w ｚ，ｘ This will result in the following: Based on this, for example, when the z-coordinate position is -80 μm, w at all x-coordinates ｚ，ｘ The average value lol ａ，－８０ Calculate the w of all x coordinates when the z coordinate position is -75 μm. ｚ，ｘ The average value lol ａ，－７５ For example, the average value w at each z coordinate is calculated. ａ，ｚ Calculate the result. The result of this calculation is shown in Table 2 below.

[0024]

[0025] Based on Table 2, the z-coordinate is used as the horizontal axis, and the average value w is used for each z-coordinate. ａ，ｚ By plotting the values ​​on the vertical axis, the above graph can be obtained.

[0026] In the graph above, the SiC wafer 10 has a minimum value w in the range of -20 μm ≤ z ≤ 20 μm. ｍ Where there exists a region that gives a local minimum value w ｍ The z-coordinate position that gives the value is preferably in the range of -15 μm ≤ z ≤ 15 μm, more preferably in the range of -10 μm ≤ z ≤ 10 μm, and even more preferably in the range of -5 μm ≤ z ≤ 5 μm. Here, the local minimum value w ｍ In Table 2, w ａ，－２０ From lol ａ，２０ It can be said that it exists within the range of values ​​up to that point.

[0027] Furthermore, in the graph above, the local minimum value w is given in the range -20 μm ≤ z ≤ 20 μm. ｍ And the average value of the full width at half maximum in the range -80 μm ≤ z ≤ -20 μm w Ｓ The difference (lol) ｓ -w ｍ ) is 0.240 cm －１ That is all, so this difference (w ｓ -w ｍ ) is preferably 0.240 to 0.830 cm －１ , more preferably 0.300 to 0.830 cm －１ More preferably 0.350 to 0.830 cm －１ Here, the average value lol Ｓ In Table 2, w ａ，－８０ From lol ａ，－２０ This represents the average value up to a certain point.

[0028] As described above, the specific features of each of embodiments (A) and (B) have been explained. The following describes matters common to both embodiments (A) and (B).

[0029] The SiC wafer 10 preferably has a thickness of 500 μm or less, and more preferably 350 to 500 μm. The shape of the SiC wafer 10 is not particularly limited, but it is preferably disc-shaped (circular). In this specification, "circular shape" does not have to be a perfect circle, but may be a substantially circular shape that can be generally recognized as circular overall. For example, it may be a shape in which a part of the circle is cut out for the purpose of specifying the crystal orientation or for other purposes, or a shape in which a slit is provided in a part of the circle, in which case the size can be determined based on the diameter of the largest circle inscribed in the outer edge excluding the cut-out outer edge or the slit. The diameter of the SiC wafer 10 is not particularly limited, but may be 100 mm (4 inches) or more, 145 mm or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more.

[0030] The SiC seed crystal layer 12 is typically composed of a SiC single crystal and has a crystal growth surface. In this case, the polymorph (polytype), off-angle and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal, are not particularly limited, but the polymorph is preferably 4H, 6H, or 3C. Alternatively, a SiC single crystal deposited on a Si substrate may be used as the SiC seed crystal layer 12. The crystal growth surface on the SiC single crystal as the SiC seed crystal layer 12 may be either the Si surface or the C surface, or both the Si surface and the C surface, but it is preferably the Si surface. Therefore, it is preferable that the peel-promoting layer 116 is formed near this Si surface. The diameter of the SiC seed crystal layer 12 is not particularly limited, but it may be 100 mm (4 inches) or larger, 145 mm or larger, 150 mm (6 inches) or larger, or 200 mm (8 inches) or larger.

[0031] The SiC growth layer 14 contains SiC single crystals grown from the SiC seed crystal layer 12. The polymorph (polytype), off-angle and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal, are not particularly limited, but the polymorph is preferably 4H, 6H, or 3C.

[0032] The SiC growth layer 14 preferably contains rare earth elements. Examples of rare earth elements include Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, and combinations thereof. Preferably, Gd, Sm, La, Nd, Y, Ce, and combinations thereof, more preferably Y and / or Ce. When the SiC growth layer 14 contains rare earth elements, the SiC growth layer 14 has a density of 5.0 × 10⁻¹⁶. １３ atoms / cm ３ It is preferable that the mixture contains a portion of rare earth elements at the above concentration, and more preferably this concentration is 5.0 × 10⁻⁶. １３ ~7.0 x 10 １５ atoms / cm ３ More preferably 5.0 × 10 １３ ~5.0 x 10 １５ atoms / cm ３ Particularly preferred is 5.0 × 10 １３ ~2.0 x 10 １５ atoms / cm ３ Furthermore, the SiC growth layer 14 may also contain elements other than rare earth elements, such as Si. In this case, the preferred elemental concentration range is the same as that of the rare earth element concentration range described above.

[0033] The SiC growth layer 14 preferably contains nitrogen atoms. In that case, the SiC growth layer 14 is 1.0 × 10 １８ atoms / cm ３ It is preferable that the product contains a portion containing nitrogen atoms at the above concentration, and more preferably this concentration is 1.0 × 10⁻⁶. １８ ~1.0 x 10 １９ atoms / cm ３ More preferably 1.0 × 10 １８ ~8.0 x 10 １８ atoms / cm ３ Particularly preferably 1.0 × 10 １８ ~5.0 x 10 １８ atoms / cm ３The method for controlling the nitrogen atom concentration is not particularly limited, but for example, one method is to control the heat treatment conditions for crystal growth. Specifically, the nitrogen atom concentration can be preferably controlled by performing the heat treatment in a mixed gas atmosphere of argon and nitrogen, and controlling the argon mixing ratio to be in the range of 99.70 to 99.975% and the nitrogen mixing ratio to be in the range of 0.025 to 0.30%.

[0034] The peeling-promoting layer 16 is formed inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. In other words, the SiC wafer 10 has a peeling-promoting layer 16 inside and / or on the surface of at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. The peeling-promoting layer 16 is typically a SiC-derived layer (e.g., a SiC-based layer) that facilitates the division of the SiC wafer 10 into an upper and lower portion with the peeling-promoting layer 16 as the starting point or boundary, and is, for example, a layer in which the SiC crystal structure is incomplete compared to other parts, or in which peeling or splitting is more likely to occur due to other causes. Figure 1 illustrates a configuration in which the peeling-promoting layer 16 is formed inside the SiC seed crystal layer 12. By forming the peeling-promoting layer 16 inside the SiC wafer 10 in this way, the occurrence of cracks and fissures can be suppressed when dividing the SiC wafer 10 into a device-formed portion and a device-unformed portion after device formation.

[0035] The peel-promoting layer 16 is preferably a SiC-derived layer and contains voids, peel-promoting substances, or amorphous portions. If the peel-promoting layer 16 contains a peel-promoting substance, it is preferable that the peel-promoting layer 16 is a layer formed by implanting ions I into at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. These ions I correspond to the peel-promoting substance. Therefore, it is preferable that the peel-promoting layer 16 is a SiC-derived layer containing a peel-promoting substance. Based on these considerations, a "SiC-derived layer" typically means a layer formed by making some kind of change to the SiC crystal (especially a SiC single crystal) constituting the SiC seed crystal layer 12 and / or the SiC growth layer 14 (for example, a SiC-based layer), and may be a layer in which the SiC crystal has been modified. The peel-off promoting substance is preferably an ion of a Group 1, Group 13, Group 14, Group 15, Group 18 element, or a combination thereof; more preferably an ion of Si, C, Al, B, P, N, O, H, noble gas elements, rare earth elements, or a combination thereof; even more preferably an ion of Si, C, B, P, noble gas elements, or a combination thereof. The Group numbers of the Periodic Table shown in this specification are based on the Group number designation 1 to 18 according to the revised inorganic chemical nomenclature established by IUPAC (International Union of Pure and Applied Chemistry) in 1989, where Group 1 elements refer to H, Li, Na, K, etc., Group 13 elements refer to B, Al, Ga, In, etc., Group 14 elements refer to C, Si, Ge, Sn, Pb, etc., Group 15 elements refer to N, P, As, Sb, Bi, etc., and Group 18 elements refer to He, Ne, Ar, Kr, Xe, etc.

[0036] The injection conditions for ion I are as follows: injection dose is 1 × 10⁻⁶ １５ ~5 x 10 １６ ions / cm ２ Preferably, it is 1 × 10 １５ ~3 x 10 １６ ions / cm ２ More preferably 1 x 10 １５ ~2 x 10 １６ ions / cm ２ Particularly preferably 1 x 10 １５ ~1 x 10 １６ ions / cm ２In this case, "injection dose" refers to the number of ions per unit area in the peel-promoting layer 16. Furthermore, the accelerating voltage for ion I is preferably 70 to 600 keV. The temperature during ion I injection is preferably room temperature to 800°C. By controlling the ion I injection conditions, particularly the injection dose, the above-mentioned characteristics can be effectively controlled.

[0037] If the peel-promoting layer 16 contains voids, it is preferable that the peel-promoting layer 16 is a layer obtained by forming minute grooves in at least one of the SiC seed crystal layer 12 and the SiC growth layer 14. For example, by forming grooves (voids) at regular intervals on the surface of the SiC seed crystal layer 12 and / or the SiC growth layer 14, a peel-promoting layer 16 can be formed in which the crystal structure near the surface is partially changed, modified, or fragmented. When such a peel-promoting layer 16 is formed, the SiC seed crystal layer 12 becomes easier to peel from the SiC wafer 10 along the voids.

[0038] If the peel-promoting layer 16 includes an amorphous portion, it is preferable that the peel-promoting layer 16 is formed by implanting ions I into at least one of the SiC seed crystal layer 12 and the SiC growth layer 14, and irradiating the portion into which ions I are implanted with incident light of a specific wavelength. Because the peel-promoting layer 16 including the amorphous portion has a different crystal structure from the SiC seed crystal layer 12 and the SiC growth layer 14 other than the peel-promoting layer 16, the SiC wafer 10 can be easily divided into an upper portion and a lower portion with the peel-promoting layer 16 as the starting point or boundary. It is preferable that ions I are Si, C, Al, B, P, N, O, H, rare gas elements, rare earth elements, or a combination thereof.

[0039] As described above, this disclosure provides a SiC wafer 10 that can be easily separated into a device-formed portion and an unformed portion after device formation on the wafer, while suppressing the occurrence of cracks and fractures in the wafer (i.e., has good peelability). The first and second embodiments of a system or process for manufacturing such a SiC wafer 10 will be described below. The descriptions of the first and second embodiments apply to the SiC wafer 10 described above, insofar as they do not contradict the present invention, but the present invention is not limited to them. Therefore, in the following description, the SiC wafer 40, pre-treated seed crystal 114, grown SiC crystal 115, peel-promoting layer 116, first main surface 40a and second main surface 40b may correspond to the SiC wafer 10, SiC seed crystal layer 12, SiC growth layer 14, peel-promoting layer 16, first main surface 10a and second main surface 10b described above, respectively.

[0040] In the descriptions of the first and second embodiments, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the embodiments in order to make the explanation clearer. However, these are merely examples and do not limit the interpretation of this disclosure.

[0041] In the descriptions of the first and second embodiments, the semiconductor wafer is a SiC (silicon carbide) wafer, but the method can also be applied to semiconductor wafers other than SiC wafers. Examples of semiconductor wafers other than SiC wafers include GaN (gallium nitride) wafers, AlN (aluminum nitride) wafers, or diamond wafers.

[0042] [First Embodiment] Figure 2 shows an example of the overall system configuration according to the first embodiment of this disclosure.

[0043] In the second entity, a surface device step and a wafer splitting step are performed. The second entity may be a company acting as a device manufacturer that extracts SiC chips from the SiC wafer 40 and provides SiC chips or devices having SiC chips. The SiC wafer 40 is broadly divided into a layer as a base SiC crystal and a layer as a grown SiC crystal (oriented SiC crystal).

[0044] In the surface device step, a device is formed on the first main surface (surface) of the SiC wafer 40 (corresponding to the surface of the SiC wafer 10 on the SiC growth layer 14 side). The device may include electrodes and wiring patterns.

[0045] In the wafer splitting step, the SiC wafer 40 having the device is split along the planar direction (a direction perpendicular to the thickness direction, in other words, a direction parallel to the first main surface). In this wafer splitting step, the SiC wafer 40 is split along the planar direction by a method called laser slicing using a laser device, for example. Specifically, for example, the laser device irradiates a peel-promoting layer 116 that has been pre-formed inside the SiC wafer 40 from the second main surface (back surface) side of the SiC wafer 40 (corresponding to the surface of the SiC seed crystal layer 12 of the SiC wafer 10) with laser light (for example, a pulsed laser). As a result, a modified layer is formed in the peel-promoting layer 116, and starting from this modified layer, the SiC wafer 40 is split into a main wafer portion 111, which is the SiC wafer portion having the first main surface, and a remaining wafer portion 112, which is the SiC wafer portion having the second main surface.

[0046] In laser slicing, the peel-accelerating layer 116 within the SiC wafer 40 irradiated with laser light is a layer that is more prone to peeling due to an incomplete SiC crystal structure compared to other parts, or for other reasons. By irradiating this peel-accelerating layer 116 with laser light to create a modified layer, and then dividing the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 along the peel-accelerating layer 116, the division (peeling) can be performed more easily than when other parts are used as the modified layer. Possible reasons for this include, for example, the peel-accelerating layer 116 having an incomplete crystal structure compared to other parts and having weaker interatomic bonding forces. It is also possible that the peel-accelerating layer 116 readily absorbs laser light, thus facilitating the formation of a modified layer. Various other factors may also be considered, but in any case, by peeling off the portion including the first main surface from the SiC wafer 40 starting from the peel-accelerating layer 116, the SiC wafer 40 can be divided into a main wafer 111 and a remaining wafer 112 with less force. This makes it possible to suppress the generation of distortion during peeling in the device formation portion of the main wafer 111, thereby preventing the occurrence of cracks and fractures.

[0047] The peel-promoting layer 116 is formed within the SiC wafer 40 when the SiC wafer 40 is manufactured in a first entity different from the second entity. This method will be described later.

[0048] In addition, during the wafer splitting step, the SiC wafer 40 may be split into the main wafer 111 and the remaining wafer 112 by a method other than laser slicing. For example, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 by etching away the peeling acceleration layer 116 on the SiC wafer 40. In this case, electrolytic etching, chemical etching, thermal etching, etc., can be used for etching. By performing the wafer splitting step by etching in this way, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 without using a laser device. Furthermore, peeling can also be performed using ultrasound, known as sonic lift-off. Specifically, by using sound waves to split the SiC wafer 40 into the main wafer 111 and the remaining wafer 112, the peeled surfaces of the main wafer 111 and the remaining wafer 112 can be made flat and smooth, thus eliminating material waste and allowing the remaining wafer 112 to be reused, thereby reducing wafer manufacturing costs. In addition to the above, it is possible to divide the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 by processing the peeling-promoting layer 116 formed in the SiC wafer 40 using any method.

[0049] In the first entity, the acquisition step, processing step, pre-processing step, growth step, and wafer provision step are performed (in this embodiment, an inspection step is also performed between the acquisition step and the processing step, as will be described later). The first entity is a company that provides a new service, that is, a company that acquires (recovers) the remaining wafer 112 of the SiC wafer 40 from the second entity, grows a grown SiC crystal on the remaining wafer 112 to regenerate the SiC wafer 40, and provides the regenerated SiC wafer 40 to the same or a different second entity. There is one or more second entities for each first entity. Note that the wafer splitting step described above may be performed in the first entity instead of the second entity.

[0050] In the acquisition step, the remaining wafer 112 is acquired from the second entity. In the processing step, the slice surface of the remaining wafer 112 is processed to acquire a seed crystal 113a made of SiC single crystal material.

[0051] In the pretreatment step, an inhibitory region is formed on or near the surface of the seed crystal 113a obtained in the processing step, or a seed crystal 113b made of newly prepared SiC single crystal material, which partially disrupts or inhibits the SiC crystal structure. This pretreatment is performed on the seed crystals 113a and 113b to form the aforementioned peeling-promoting layer 116, and a pretreated seed crystal 114 is obtained. Details of the pretreatment step will be described later.

[0052] In the growth step, a new SiC wafer 40 is manufactured by growing a growth SiC crystal (an example of a semiconductor crystal layer) 115 on the surface of the seed crystal 114 obtained in the pretreatment step. Inside the SiC wafer 40 manufactured here, a peeling-promoting layer 116 is formed by the inhibiting region formed on the seed crystal 114 in the pretreatment step.

[0053] In the wafer supply step, the SiC wafer 40 obtained in the growth step is provided to a second entity that is the same as or different from the source from which the remaining wafer 112 was obtained.

[0054] In conventional processes not to which this disclosure applies, the portion of the SiC wafer 40 corresponding to the remaining wafer 112 is ground without separating it from the main wafer 111, and the resulting grinding waste is discarded. In contrast, in this embodiment, the remaining wafer 112 is separated from the main wafer 111 and recovered without being discarded as grinding waste, and this is recycled into a new semiconductor wafer by the first entity and provided to the second entity. The second entity forms a device on the semiconductor wafer provided by the first entity (SiC wafer 40 recycled from the remaining wafer 112), and then separates it into the main wafer 111 and the remaining wafer 112. The remaining wafer 112 is recovered by the first entity and used as a seed crystal 114 to form a grown SiC crystal together with the peeling accelerator layer 116, and is then used again as SiC wafer 40. By repeating this process, the portion of the SiC wafer 40 that was conventionally ground or discarded, namely the remaining wafer 112, can be reused. In this disclosure, the reuse of expensive SiC wafers is made possible, thereby reducing the manufacturing cost of devices. Furthermore, since waste can be significantly reduced throughout the entire SiC wafer manufacturing process, including high-temperature processes, it is also possible to reduce the environmental impact.

[0055] The processing step may be performed by the processing device 172, the pretreatment step may be performed by the pretreatment device 173, and the growth step may be performed by the growth device 174 (the inspection step described later may be performed by the inspection device 171).

[0056] Below, we will first describe the acquisition step, processing step, pretreatment step, growth step, and wafer supply step among the steps in the first entity, and then describe the inspection step.

[0057] <Acquisition Step> In the acquisition step, the remaining wafers 112 are acquired from one or more second entities. Any number of remaining wafers 112 may be sent to the first entity at any time the second entity has chosen, or an acquisition schedule, including the number of remaining wafers 112 to be acquired from each of the one or more second entities and the acquisition timing, may be shared between the second entity and the first entity, and the remaining wafers 112 may be acquired from the second entity according to the acquisition schedule. Note that if the wafer splitting step is performed by the first entity, the acquisition step is unnecessary.

[0058] <Processing Step> The processing in the processing step includes removing the slice surface (typically grinding and / or polishing) and removing the processed altered layer including the removed slice surface. The processing apparatus 172 may include, for example, an apparatus for grinding and / or polishing the slice surface (e.g., a grinder) and an apparatus for removing the processed altered layer, and these apparatuses may be a single apparatus (i.e., grinding and removal may be performed by one apparatus). For example, the processing apparatus 172 may be an apparatus for grinding and polishing such as the CMP (Chemical Mechanical Polishing) method.

[0059] In the processing step, a seed crystal 113a is obtained as a result of processing the remaining wafer 112. The seed crystal 113a may be composed mainly of the underlying SiC crystal, or it may be composed of the underlying SiC crystal and some oriented SiC crystal. Alternatively, instead of the seed crystal 113a, a new SiC single crystal material may be prepared and used as the seed crystal 113b.

[0060] <Pre-treatment step> In the pre-treatment apparatus 173, inhibition regions are formed on or near the surface of the seed crystals 113a and 113b, which partially disrupt or inhibit the formation of the crystal structure when growing the SiC crystal in the next growth step. Due to the presence of these inhibition regions, a peel-promoting layer 116, which is easier to peel off than other parts, is formed inside the SiC wafer 40 manufactured from the seed crystals 113a and 113b in the growth step. Specifically, for example, the pre-treatment apparatus 173 forms inhibition regions on the seed crystals 113a and 113b by performing one of the processing treatments described in Figures 3 to 5 below as a pre-treatment.

[0061] Figure 3 is an explanatory diagram of the pretreatment for forming a layer containing minute voids as a peel-promoting layer 116. In Figure 3, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0062] In the pretreatment step, for example as shown in Figure 3(b), pulsed laser light from a laser 201, which is a pretreatment device 173, is irradiated onto the surface of the seed crystal 113a at regular intervals in a grid pattern, thereby forming grooves 202 on the surface of the seed crystal 113a by laser processing. In the subsequent growth step, the seed crystal 113a with these grooves 202 formed on it is used as a pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form a grown SiC crystal 115. As a result, for example as shown in Figure 3(c), voids formed by the grooves 202 occur at regular intervals between the seed crystal 114 and the grown SiC crystal 115, and because the crystal structure is partially divided by these voids, a peel-promoting layer 116 is formed along the voids as a layer that is easily peeled off. In this way, a SiC wafer 40 having a peel-promoting layer 116 between the first main surface 40a on the front side (grown SiC crystal 115 side) and the second main surface 40b on the back side (seed crystal 114 side) is manufactured.

[0063] Furthermore, it is preferable that the grooves 202 formed on the surface of the seed crystal 113a in the pretreatment step have a maximum depth of 1 μm or more. In this way, it is possible to form a peel-promoting layer 116 in the region including the grooves 202 while sufficiently growing the SiC crystal in the growth step.

[0064] Figure 4 is an explanatory diagram of the pretreatment for forming a layer containing a substance for promoting peeling (hereinafter referred to as "peeling-promoting substance") as a peeling-promoting layer 116. In Figure 4, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a cross-sectional enlargement view.

[0065] In the pretreatment step, for example as shown in Figure 4(b), fine particles 211 mainly composed of carbon are dispersed on the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the dispersed fine particles 211 on its surface is used as the pretreated seed crystal 114, and a SiC crystal is grown on its surface (for example, to a thickness of 50 μm or more) to form a grown SiC crystal 115. As a result, for example as shown in Figure 4(c), fine particles 211 are sandwiched in places between the seed crystal 114 and the grown SiC crystal 115, and because the formation of the crystal structure is inhibited by these fine particles 211, a peel-promoting layer 116 is formed as a layer with an incomplete crystal structure. In this way, a SiC wafer 40 having a peel-promoting layer 116 between the first main surface 40a on the front side (the side with the grown SiC crystal 115) and the second main surface 40b on the back side (the side with the seed crystal 114) is manufactured.

[0066] Furthermore, the carbon-based fine particles 211 dispersed on the surface of the seed crystal 113a in the pretreatment step are preferably graphite or diamond fine particles with a particle size of 10 μm or less. In this way, it is possible to sufficiently grow the SiC crystal in the growth step while forming the peel-promoting layer 116 in the region containing the fine particles 211.

[0067] Figure 5 is an explanatory diagram of the pretreatment for forming a layer containing a different peel-promoting substance as the peel-promoting layer 116, which is different from the one in Figure 4. In Figure 5, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0068] In the pretreatment step, ions 221 are injected into the seed crystal 113a from the surface, as shown in Figure 5(b). Specifically, ions 221 generated by an ion source are accelerated and injected from the outside toward the surface of the seed crystal 113a, thereby injecting and dispersing the ions 221 near the surface of the seed crystal 113a. In the subsequent growth step, the seed crystal 113a with the ions 221 dispersed inside is used as the pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form the grown SiC crystal 115. As a result, as shown in Figure 5(c), ions 221 are placed in various places near the boundary between the seed crystal 114 and the grown SiC crystal 115, and the formation of the crystal structure is inhibited by these ions 221, resulting in the formation of a peel-promoting layer 116 with an incomplete crystal structure. In this way, a SiC wafer 40 having a peel-promoting layer 116 between the first main surface 40a on the front side (the side with the growing SiC crystal 115) and the second main surface 40b on the back side (the side with the seed crystal 114) is manufactured. In the subsequent wafer splitting step, if the peel-promoting layer 116 in the SiC wafer 40 is removed by etching as described above, it is preferable to form the peel-promoting layer 116 using the method described in Figure 5.

[0069] Furthermore, it is preferable to use one or more ions from among Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements as the ions 221 implanted into the seed crystal 113a in the pretreatment step. In this way, it is possible to sufficiently grow the SiC crystal in the growth step while forming the peeling-promoting layer 116 in the region containing the ions 221.

[0070] In the pretreatment step, seed crystal 114 is obtained by performing one of the pretreatments described above on seed crystals 113a and 113b using the pretreatment apparatus 173. Although Figures 3 to 5 illustrate an example of performing pretreatment on seed crystal 113a obtained in the processing step, the same pretreatment can be performed on a newly prepared seed crystal 113b to obtain seed crystal 114.

[0071] <Growth Step> In the growth apparatus 174, a grown SiC crystal (oriented SiC crystal) 115 is grown on the seed crystal 114 to a thickness of 50 μm or more. Such crystal growth may be carried out by sublimation or CVD (Chemical Vapor Deposition), or by other methods. As a result, as explained in Figures 3 to 5, a new SiC wafer 40 is obtained, which consists of a seed crystal 114, which is a crystalline layer made of a single-crystal material of SiC, and a grown SiC crystal 115, which is a crystalline layer of SiC formed on the seed crystal 114, and has a peel-promoting layer 116 between the first main surface 40a on the grown SiC crystal 115 side and the second main surface 40b on the seed crystal 114 side. In this SiC wafer 40, the peel-promoting layer 116 formed on at least one of the seed crystal 114 and the grown SiC crystal 115 contains voids due to grooves 202 or contains an incomplete crystalline structure due to fine particles 211 or ions 221.

[0072] Furthermore, as illustrated in Figure 4(c), the peeling acceleration layer 116 is preferably formed within a range of 10 μm or less in the thickness direction (up and down direction in the figure) perpendicular to the first main surface 40a and the second main surface 40b. Specifically, when observing a cross-section of the SiC wafer 40 in the thickness direction at any position including the peeling acceleration layer 116, it is preferable that the thickness of the peeling acceleration layer 116 in that cross-section is 10 μm or less. In this way, the thickness of the peeling acceleration layer 116 can be made thinner than the height of the unevenness of the slice surface that occurs when a conventional SiC wafer without a peeling acceleration layer 116 is divided by laser slicing (generally about 20 to 50 μm), thereby reducing the amount of grinding debris generated in the processing step and reducing the amount of SiC waste. The peeling acceleration layer 116 is a part of the seed crystal 114 or the grown SiC crystal 115, as shown in Figures 3 to 5.

[0073] Furthermore, in the peel-promoting layer 116, as illustrated in Figure 4(c), it is preferable that peel-promoting substances consisting of voids formed by grooves 202, fine particles 211, or ions 221 are distributed at intervals of 200 μm or less and over a range of at least 500 μm in the planar direction parallel to the first main surface 40a and the second main surface 40b (left-right direction in the figure). In this way, when the first entity divides the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 in the wafer splitting step, it is possible to form a peel-promoting layer 116 that can be easily peeled off with little force.

[0074] Figures 6A to 6C show examples of cross-sections of the SiC wafer 40 shown in Figure 3(c) when it is cut along a plane parallel to the first main surface 40a and passing through at least a portion of the peel-accelerating layer 116. Figure 6A shows an example of a cross-section when the peel-accelerating layer 116 is formed over the entire surface in the planar direction at a predetermined depth within the SiC wafer 40. Figure 6B shows an example of a cross-section when the peel-accelerating layer 116 is formed over the entire circumference of the region near the outer periphery within the SiC wafer 40. Figure 6C shows an example of a cross-section when the peel-accelerating layer 116 is partially formed in the region near the outer periphery within the SiC wafer 40. Note that the peel-accelerating layer 116 may be formed in arrangements other than those shown.

[0075] As shown in the examples above, the peel-promoting layer 116 may be formed over the entire surface in the planar direction when the SiC wafer 40 is viewed from the direction of the first main surface 40a, or it may be formed only in a part of the surface. As long as the peel-promoting layer 116 is distributed over a certain range in the planar direction, for example, a range of 500 μm or more, the peel-promoting layer 116 can be formed in any region within the SiC wafer 40.

[0076] <Wafer Provision Step> A new SiC wafer 40, composed of a seed crystal 114 and a grown SiC crystal 115, is provided to a second entity that is the same as or different from the source from which the remaining wafer that forms the basis of the SiC wafer was obtained. In this way, the acquired remaining wafer 112 is regenerated into such a new SiC wafer 40 and provided to the second entity, so the second entity can obtain a main wafer from that SiC wafer 40.

[0077] The above describes the acquisition step, processing step, pretreatment step, growth step, and wafer supply step.

[0078] In this embodiment, an inspection step is included between the acquisition step and the processing step to inspect the slice surface of the acquired remaining wafer 112. The inspection step is, for example, as follows:

[0079] <Inspection Step> The inspection step includes measuring at least one of the following: the height difference of the slice surface and the thickness of the processed altered layer having the slice surface. In this embodiment, both are measured. The height difference of the slice surface is the height difference caused by the surface irregularities resulting from the laser irradiation or the separation of the main wafer 111 and the remaining wafer 112 in the wafer splitting step.

[0080] The inspection step is performed by the inspection device 171. The inspection device 171 may include a laser microscope and a Raman spectrometer. The height difference of the slice surface may be measured using the laser microscope. The thickness of the processed altered layer may be measured using the Raman spectrometer. The measurement methods for both the height difference of the slice surface and the thickness of the processed altered layer are not limited to this example. For example, the height difference of the slice surface may be measured using a white light interferometer or a contact-type shape measuring instrument.

[0081] At least one of the following (x) and (y) may be performed. (x) The processing in the processing step includes determining the amount to remove from the slice surface based on at least one of the measured height difference of the slice surface of the acquired remaining wafer 112 and the measured thickness of the processed altered layer, and removing material from the slice surface according to the determined amount. This allows for appropriate (with minimal excess or deficiency) slicing of the slice surface according to the quality (condition) of the acquired remaining wafer 112. For example, if the PV value (maximum valley depth) is measured as an example of the height difference of the slice surface, and the processing altered layer depth is measured as an example of the thickness of the processed altered layer, then the amount to remove = PV value + (processed altered layer depth × N). N may be any value greater than 0 (for example, any natural number). A processing command associated with information representing the amount to remove may be input to the processing device 172 (or the control device of the processing device 172), and the processing device 172 may perform slicing according to that amount. The "amount of material removed" may be defined by parameter values ​​for each of one or more parameter items. Examples of parameter items include the processing time and processing power (e.g., temperature and pressure) of the processing apparatus 172. (y) In the growth step, the thickness of the growing SiC crystal to be grown is determined based on at least one of the measured height difference of the slice surface of the remaining wafer 112 and the measured thickness of the processed altered layer, and the growing SiC crystal is grown to the determined thickness. This allows for appropriate (with minimal excess or deficiency) crystal growth according to the quality (condition) of the acquired remaining wafer 112. For example, the thickness to be grown may be determined based on at least one of X, Y, Z, and α. Specifically, for example, the thickness to be grown may be X - Y + Z + α. X may be the thickness required at the start of the surface device step or wafer splitting step in the second entity (the thickness requested by the second entity). Y may be the thickness of the growing SiC crystal when received by the first entity. Z can be the amount of material removed as determined in (x) above. α can be any value determined as the machining margin (for example, about 50 μm) to remove the irregularities after growth and flatten the surface.A crystal growth command, associated with information indicating the thickness to be grown, may be input to the growth apparatus 174 (or the control device for the growth apparatus 174), thereby causing the growth apparatus 174 to grow a SiC crystal of that thickness on the seed crystal.

[0082] [Second Embodiment] The second embodiment will now be described. In this description, the differences from the first embodiment will be explained, and the similarities with the first embodiment will be omitted or simplified.

[0083] In the second embodiment, crystal growth in the growth step is carried out using the method disclosed in the prior application Patent Document 2 (WO2023 / 067736A1) by the same applicant as the present application (hereinafter, this method will be conveniently referred to as the "NGK method" based on the applicant's notation). That is, in the growth step, a SiC single crystal as a seed crystal and a SiC powder layer are placed in a container in contact with each other, and the container is placed in a firing furnace and heat treatment is performed, thereby growing a SiC single crystal on the seed crystal. According to the NGK method, it is possible to obtain a SiC single crystal (grown SiC crystal) with a lower BPD density than the sublimation method and a BPD density of about the same as that of the CVD method. The second embodiment can utilize all or part of the technology disclosed in Patent Document 2.

[0084] Furthermore, when crystal growth is performed using the NGK method, the flatness of the processed surface does not need to be as high as when crystal growth is performed using the sublimation or CVD methods, and the processed surface does not need to be perfectly flat. Specifically, for example, the following applies:

[0085] When homoepitaxial growth is performed on a seed crystal using sublimation or CVD, it is usually essential that the growth surface is atomically flat and that there is no processed or altered layer. This is because irregularities can form on the epitaxial growth surface, or defects such as dislocations can be introduced into the crystal.

[0086] On the other hand, because SiC wafers are hard and stable against heat and chemicals, surface planarization and removal of processing damage using the CMP method after slicing or grinding is extremely time-consuming, and the consumption of polishing slurry and polishing pads is also high.

[0087] Therefore, in this embodiment, in the processing step, the removal of the processed altered layer is performed by a thermal etching process, a surface oxidation process, or a plasma etching process (i.e., any process that results in a lower degree of flatness after etching than etching by the CMP method). Below, examples of each process for removing the processed altered layer in the processing step of the second embodiment will be described. In this embodiment, etching other than the thermal etching process, surface oxidation process, and plasma etching process, such as etching by the CMP method, or etching by other etching processes (e.g., hydrogen etching) may be performed.

[0088] Figure 7 schematically illustrates the thermal etching process.

[0089] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a thermal etching process. This apparatus is illustrated in Figure 7. In the thermal etching process, the surface of the remaining wafer (including the processed altered layer) that has been heated and processed in the electric furnace 302 is sublimated to a thickness of several micrometers.

[0090] For example, gas (such as nitrogen or argon, an inert gas) is introduced into an electric furnace 302, which is made of insulating material and equipped with a heater 301, through a gas pipe 305, creating an inert gas atmosphere inside the electric furnace 302. The electric furnace 302 may also be under vacuum.

[0091] The material is heated by heater 301, but the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 1000 to 2000°C), and may be set taking into account the required amount of etching (for example, 1800°C may be set). The holding time at the maximum temperature is a time within a certain time range (for example, 1 minute to 5 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0092] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 303 (for example, graphite) on a spacer 304 (for example, graphite), or it may be placed using a sheath or the like made of a heat-resistant material.

[0093] If the surface of the remaining wafer 112 is carbonized after this thermal etching process, the carbonized layer on the surface may be removed by annealing in an atmospheric furnace or the like, or by polishing or other processing. To prevent surface carbonization, a carbon getter material such as Ta may be placed inside the electric furnace 302.

[0094] Figure 8 schematically illustrates the surface oxidation process.

[0095] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a surface oxidation process. This apparatus is illustrated in Figure 8. In the surface oxidation process, the surface of the remaining wafer (including the processed altered layer) that has been heated in an oxidizing atmosphere (including an air atmosphere) in an electric furnace 402 is oxidized to a thickness of several micrometers. The oxide film may be removed by processing such as polishing, or it may be volatilized or melted (reacted with the raw material powder) during crystal growth.

[0096] For example, in an electric furnace 402 made of insulating material and equipped with a heater 401, the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 800 to 2000°C), and may be set taking into account the required amount of etching (for example, 1400°C may be set). Also, the holding time at the maximum temperature is a time within a certain time range (for example, 5 minutes to 50 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0097] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 403 (for example, alumina) on a spacer 404 (for example, alumina).

[0098] Figure 9 schematically illustrates the plasma etching process.

[0099] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a plasma etching process. This apparatus is an example of the apparatus shown in Figure 9. In the plasma etching process, the surface of the remaining processed wafer (including the processed altered layer) is etched to a thickness of several micrometers.

[0100] Plasma etching includes methods such as RIE (Reactive Ion Etching), ECR (Electron Cyclotron Resonance), ICP (Inductively Coupled Plasma), and CCP (Capacitively Coupled Plasma), but there are no particular limitations; for example, RIE can be applied.

[0101] The substrate temperature, gas type, processing time, and apparatus configuration may be set as appropriate depending on the desired etching rate and surface condition. The remaining wafer surface may be pre-treated by ashing or other methods to remove any surface deposits.

[0102] An upper electrode 501 and a lower electrode 503 are located in the chamber 502. Gas is introduced from the gas introduction pipe 505 and exhausted from the gas exhaust pipe 504, and plasma is generated between electrodes 501 and 503 by the high-frequency power supply 509s.

[0103] The above is an explanation of examples of each process related to the removal of the processed altered layer in the processing step according to the second embodiment. Furthermore, there are differences between the sublimation method, CVD method and the NGK method regarding crystal growth, for example, as follows.

[0104] In other words, while sublimation and CVD methods require precise cleaning after CMP polishing and before epitaxial layer formation, the NGK method does not require such cleaning.

[0105] Furthermore, in sublimation and CVD methods, the rapid heating rate increases the likelihood of seed crystal warping and subsequent breakage. Also, in sublimation and CVD methods, multiple seed crystals can be placed in the growth chamber, but if even one seed crystal is damaged, it will affect the others. On the other hand, in the NGK method, the heating rate is slower than in sublimation and CVD methods, so even if the seed crystal is slightly warped, the likelihood of breakage due to that warping is low. In addition, in the NGK method, one seed crystal is stored in each container, so even if one seed crystal is damaged, it will not affect the others.

[0106] Furthermore, in both the second and first embodiments, the diameter of the remaining wafer 112 acquired in the acquisition step may be 6 inches or more, and for example, the diameter of the remaining wafer may be 8 inches or more (for example, in the second embodiment). For example, in both cases where the diameter is 6 inches or 8 inches, the thickness of the main wafer 111 may be about 100 μm, but in the case of a 6-inch diameter, the thickness of the remaining wafer 112 may be about 250 μm, and in the case of an 8-inch diameter, the thickness of the remaining wafer 112 may be about 400 μm.

[0107] The present invention will be further described in detail by the following examples. However, the present invention is not limited to the following examples.

[0108] Example 1 (1) Pretreatment As shown in Figure 5(a), a commercially available disc-shaped SiC single crystal substrate (4H-SiC, diameter 150 mm (6 inches), off-angle 4°, thickness 0.35 mm) was prepared as a seed crystal 113a. As shown in Figure 5(b), hydrogen ions (corresponding to the peeling accelerating substance) were implanted as ions 221 into the SiC single crystal substrate in order to form the peeling accelerating layer 116 described later. The conditions for implanting hydrogen ions at this time were: the depth of ion implantation was 1.0 μm in the thickness direction from the surface of the SiC single crystal substrate, the acceleration voltage was 170 keV, and the implantation dose was 50 × 10⁻¹⁶ １５ ions / cm ２ , and the temperature was 500°C.

[0109] (2) Preparation of SiC mixed powder Commercially available β-SiC powder (volume-based D50 particle size: 65.0 μm) and an oxide (SiO₂) which is a liquid phase formation aid ２The oxides (D50 particle size based on volume: 0.5 μm) were weighed so that the oxide content relative to the SiC powder content was 8.1% by weight, and then placed in a polypropylene container along with pebbles and water. After placing the polypropylene container on a pot stand, the container was rotated at a speed of 50 rpm to mix the raw materials. The slurry obtained by mixing the raw materials was dried in a dryer and collected to obtain SiC mixed powder.

[0110] (3) Arrangement of SiC mixed powder and seed crystal The SiC single crystal substrate as the seed crystal 113a pretreated in (1) and the SiC mixed powder obtained in (2) were placed in a graphite container.

[0111] (4) Heat treatment The graphite container prepared in (3) above was placed in a location in the resistance furnace (sintering furnace) where the temperature range was within ±75°C of the set temperature, and heat treatment was performed for 20 hours at a set temperature of 2450°C in a mixed gas atmosphere of argon (mixing ratio: 99.975%) and nitrogen (mixing ratio: 0.025%). As a result, as shown in Figure 1 (see also Figure 5(c)), a SiC wafer 10 was obtained in which a SiC single crystal was grown on a SiC single crystal substrate, a SiC growth layer 14 was provided on the SiC seed crystal layer 12, and a peeling acceleration layer 16 was formed inside the SiC seed crystal layer 12.

[0112] (5) Measurement of the crystal growth thickness of the SiC wafer The thickness of 25 arbitrary locations on the SiC wafer 10 obtained in (4) above was measured with a micrometer, and the arithmetic mean was calculated. The thickness of the seed crystal 113a was also calculated at the time of (3) above using the same method. Then, the crystal growth thickness (μm) of the SiC growth layer 14 was calculated by subtracting the arithmetic mean of the thickness of the seed crystal 113a from the arithmetic mean of the thickness of the SiC wafer 10. As a result, it was confirmed that the crystal growth thickness of the SiC growth layer 14 was 100 μm or more.

[0113] (6) Polishing The surface (Si surface and C surface) of the SiC wafer 10 obtained in (4) above was polished using diamond abrasive grains, and then chemical mechanical polishing (CMP) was performed.

[0114] (7) Cutting the SiC wafer A small piece of SiC wafer measuring 5 mm wide x 5 mm long was cut from the center of the SiC wafer 10 obtained in (6) above.

[0115] (8) Cross-sectional polishing of SiC wafer pieces The cross-section of the SiC wafer pieces obtained in (7) above was polished using diamond abrasive grains, and then chemical mechanical polishing (CMP) was performed.

[0116] (9) Fluorescence Microscope Observation The cross-section of the SiC wafer piece obtained in (8) above was observed at 10x magnification using a fluorescence microscope (Nikon Corporation, ECLIPSE LV100D), and the distance d from the surface of the SiC seed crystal layer 12 (second main surface 10b) to the interface between the SiC seed crystal layer 12 and the peeling acceleration layer 16 (second interface 16b) was measured. １ (μm) was measured.

[0117] (10) Raman spectroscopy measurement (E ２ -FTO peak shift) The cross-section of the SiC wafer fragment obtained in (8) above was analyzed using a micro-laser Raman spectrometer (Horiba, LabRAM ARAMIS). The optical system was a Zernite-Turner type spectrometer, backscattering method, and a semiconductor-pumped solid-state laser (DPSS, 532 nm) was used as the light source. Calibration was performed using a Si wafer before measuring the sample. First, the measurement conditions were determined by point analysis of the vicinity of the surface of the SiC seed crystal layer 12 in the cross-section of the SiC wafer fragment. Specifically, the laser output was adjusted to 100 mW, the Hole (confocal hole diameter) was set to 100 μm, Slit was set to "none", the grating was set to 1800 gr / mm, and the objective lens was set to 10x, and the analysis was performed in point analysis mode. The exposure time was 1 second, the number of integrations was 2, and the wavenumber range was 700 to 1100 cm⁻¹. －１ The values ​​of the light-reducing filter were determined so that the count of the strongest peak was between 1000 and 10000. Next, for the SiC wafer piece, (i) the z-axis was set perpendicular to the first main surface 10a (surface of the SiC growth layer 14) and the second main surface 10b (surface of the SiC seed crystal layer 12), and the direction from the second main surface 10b toward the first main surface 10a was considered positive (however, the position of the second interface 16b (d distance d from the second main surface 10b) １(ii) The x-z coordinate system was assigned by defining z = 0 at a distance of (ii) and setting the x-axis to be positive in the direction obtained by rotating the z-axis 90° clockwise (however, the center point when viewing the SiC wafer piece in plan view is defined as x = 0). Here, the center point means the intersection of the diagonals in the SiC wafer piece. Next, for each measurement point positioned in a grid at 5 μm intervals in the cross section of the SiC wafer piece in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, the standard shift value of 786 cm was set. －１ The E in the Raman spectrum appears nearby. ２ Mode transverse wave optical aliasing peak (E ２ - Raman shift value k (cm) of FTO peak －１ The peak intensity (808.21–828.21 cm) was measured. At this time, an Ne lamp was used as the measurement standard, the peak intensity due to the Ne lamp was set to 300, and the peak (808.21–828.21 cm) caused by the Ne lamp emission line was measured. －１ The wavenumber at the peak top of the peak (within the range) is 818.21 cm. －１ The spectral position was corrected accordingly. Baseline correction was performed using the LabSpec6 software (manufactured by Horiba, Ltd.) with "Type" set to "Poly", "Degree" set to "2", and "Attach" set to "No". 818.21 cm －１ The peak of the Ne-Lamp emission line was peak-fitted with a Gauss-Lorentz function, resulting in 786 cm. －１ E of SiC appearing nearby ２ Mode transverse wave optical aliasing peak (E ２ The FTO peak was peak-fitted using the Lorentz function. Next, in this measurement, the z-coordinate was used as the horizontal axis, and the Raman shift value k (cm) at each z-coordinate was calculated. －１ ) to standard shift value (786cm) －１ A graph was obtained by plotting the average value of the values ​​obtained by subtracting (which reflects all x-coordinate values ​​on a given z-coordinate) on the vertical axis. Then, in this graph, the local minimum value k ｍ (cm －１ The z-coordinate position (μm) that gives ) was determined. Also, in this graph, the Raman shift value k (cm) in the range -80 μm ≤ z ≤ -20 μm was determined.－１ The average value k obtained by subtracting the above standard shift value from ) Ｓ Find the average value k Ｓ and local minimum value k ｍ The difference (k Ｓ -k ｍ ) (cm －１ ) was found. Furthermore, in this graph, the maximum value k Ｍ (cm －１ Find the z-coordinate position (μm) that gives ) and the local maximum value k Ｍ and the average value k Ｓ The difference (k Ｍ -k Ｓ ) (cm －１ The following was determined. The results are shown in Table 3A. Although the above measurements were performed on a small piece of SiC wafer cut from the center of the SiC wafer 10, the evaluation results from this center can be considered representative of the entire SiC wafer 10.

[0118] (11) Raman spectroscopy measurement (E ２ -FTO peak full width at half maximum) The cross-section of the SiC wafer fragment obtained in (8) above was analyzed using a micro-laser Raman spectrometer (Horiba, LabRAM ARAMIS). The optical system was a Zernite-Turner type spectrometer, backscattering method, and a semiconductor-pumped solid-state laser (DPSS, 532 nm) was used as the light source. Calibration was performed using a Si wafer before measuring the sample. First, the measurement conditions were determined by point analysis of the vicinity of the surface of the SiC seed crystal layer 12 in the cross-section of the SiC wafer fragment. Specifically, the laser output was adjusted to 100 mW, the Hole (confocal hole diameter) was set to 100 μm, Slit was set to "none", the grating was set to 1800 gr / mm, and the objective lens was set to 10x, and the analysis was performed in point analysis mode. The exposure time was 1 second, the number of integrations was 2, and the wavenumber range was 700 to 1100 cm⁻¹. －１The values ​​of the light-reducing filter were determined so that the count of the strongest peak was between 1000 and 10000. Next, for the SiC wafer piece, (i) the z-axis was set perpendicular to the first main surface 10a (surface of the SiC growth layer 14) and the second main surface 10b (surface of the SiC seed crystal layer 12), and the direction from the second main surface 10b toward the first main surface 10a was considered positive (however, the position of the second interface 16b (d distance d from the second main surface 10b) １ (ii) The x-z coordinate system was assigned by defining z=0 at a distance of (i) and setting the x-axis to be positive in the direction obtained by rotating the z-axis 90° clockwise (however, the center point when viewing the SiC wafer piece in plan view is defined as x=0). Here, the center point means the intersection of the diagonals in the SiC wafer piece. Next, for each measurement point positioned in a grid at 5 μm intervals in the cross section of the SiC wafer piece in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, the E of the Raman spectrum was measured. ２ Mode transverse wave optical aliasing peak (E ２ -FTO peak) half-width w (cm) －１ The peak intensity (808.21–828.21 cm) was measured. At this time, an Ne lamp was used as the measurement standard, the peak intensity due to the Ne lamp was set to 300, and the peak (808.21–828.21 cm) caused by the Ne lamp emission line was measured. －１ The wavenumber at the peak top of the peak (within the range) is 818.21 cm. －１ The spectral position was corrected accordingly. Baseline correction was performed using the LabSpec6 software (manufactured by Horiba, Ltd.) with "Type" set to "Poly", "Degree" set to "2", and "Attach" set to "No". 818.21 cm －１ The peak of the Ne-Lamp emission line was peak-fitted with a Gauss-Lorentz function, resulting in 786 cm. －１ E of SiC appearing nearby ２ Mode transverse wave optical aliasing peak (E ２The FTO peak was peak-fitted using the Lorentz function. Next, a graph was obtained in which the z-coordinate was plotted on the horizontal axis and the average value of the full width at half maximum w at each z-coordinate (reflecting all x-coordinate values ​​at a given z-coordinate) was plotted on the vertical axis. Then, in this graph, the local minimum w ｍ The z-coordinate position (μm) that gives the result was determined. Also, in this graph, the average value of the full width at half maximum for -80 μm ≤ z ≤ -20 μm is calculated. Ｓ Find the average value lol Ｓ And a very small value lol ｍ The difference (lol) ｓ -w ｍ The following was determined. The results are shown in Table 3A. Although the above measurements were performed on a small piece of SiC wafer cut from the center of the SiC wafer 10, the evaluation results from this center can be considered representative of the entire SiC wafer 10.

[0119] (12) Measurement of impurity concentration: The concentration of rare earth elements C on the first main surface 10a (surface of the SiC growth layer 14) of the SiC wafer piece obtained in (8) above. Ｌ (atoms / cm ３ ) and nitrogen atom concentration C Ｎ (atoms / cm ３ The primary ion species was measured by dynamic secondary ion mass spectrometry (D-SIMS). For the rare earth element concentration measurement, a CAMECA IMS-7f analyzer was used, and the primary ion species was O ２＋ The acceleration voltage was set to 11.0 kV. For nitrogen atom concentration measurement, a CAMECA IMS-7f analyzer was used, and the primary ion species was Cs. ＋ The acceleration voltage was set to 15.0 kV. The results are shown in Table 3C. Although the above measurements were performed on a small piece of SiC wafer cut from the center of the SiC wafer 10, the evaluation results from this center can be considered representative of the entire SiC wafer 10.

[0120] (13) Duplication of SiC wafers A total of 100 SiC wafers 10 were produced using the same procedure as in (1) to (6) above.

[0121] (14) Device fabrication process A SiC-MOSFET device was formed on the SiC growth layer 14 of the polished SiC wafer 10 obtained in (13) above.

[0122] (15) Peeling off the SiC seed crystal layer A pulsed laser with a wavelength of 1064 nm was irradiated onto the peeling acceleration layer 16 from the second main surface 10b (surface of the SiC seed crystal layer 12) side of the SiC wafer 10 after device formation obtained in (14) above. By scanning this pulsed laser light in the in-plane direction of the SiC wafer 10, the SiC seed crystal layer 12 was peeled off from the SiC wafer 10 along the peeling acceleration layer 16. The laser irradiation conditions at this time were an irradiation fluence of 100 J / cm ２ The pulse width was set to 10 ns, and the laser focusing position was set to a depth of 200 μm in the thickness direction from the surface of the SiC wafer 10 on the SiC seed crystal layer 12 side. As a result, the SiC wafer 10 on which 100 SiC-MOSFET devices were formed was divided into 100 sets of main wafers 111 (SiC growth layer 14 on which the devices were formed) and remaining wafers 112 (SiC seed crystal layer 12).

[0123] (16) Evaluation of peelability (good product rate) The peeled surfaces of the 100 sets of main wafers 111 and remaining wafers 112 obtained in (15) above were irradiated with a halogen lamp, and the condition of these peeled surfaces was observed visually. If there were no cracks or cracks of 1 mm or more on the peeled surface of either the main wafer 111 or the remaining wafer 112, it was considered "acceptable," and if there were cracks or cracks of 1 mm or more, it was considered "unacceptable." The peelability, i.e., the good product rate (%), was calculated by counting the number of "acceptable" wafers out of the 100 sets of main wafers 111 and remaining wafers 112. The results are shown in Table 3C.

[0124] Example 2 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 30 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0125] Example 3 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were carried out in the same manner as in Example 1. The results are shown in Tables 3A and 3C. The graph obtained in (10) above is shown in Figure 10.

[0126] Example 4 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 5 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0127] Example 5 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 4 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0128] Example 6 (Comparison) In (1) above, the hydrogen ion injection conditions were set to an injection dose of 3 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0129] Example 7 (Comparison) In (1) above, the hydrogen ion injection conditions were set to an injection dose of 1 × 10 １５ ions / cm ２ Except for the above, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0130] Example 8 In (2) above, the oxide (Gd ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0131] Example 9 In (1) above, the hydrogen ion injection conditions were set to an injection dose of 30 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0132] Example 10 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0133] Example 11 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 5 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0134] Example 12 In (1) above, the hydrogen ion injection conditions were set to an injection dose of 4 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0135] Example 13 (Comparison) In (1) above, the hydrogen ion injection conditions were set to an injection dose of 3 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0136] Example 14 (Comparison) In (1) above, the hydrogen ion injection conditions were set to an injection dose of 1 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3A and 3C.

[0137] Example 15 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for weighing out the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 4.0% by weight, SiC wafers 10 and other components were prepared and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0138] Example 16 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３Except for weighing out the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 2.0% by weight, SiC wafers 10 and other components were prepared and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0139] Example 17 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for weighing the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 1.0% by weight, SiC wafers 10 and other components were prepared and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0140] Example 18 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for weighing the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 0.5% by weight, SiC wafers 10 and other components were prepared and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0141] Example 19 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for weighing out the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 16.2% by weight, SiC wafers 10 and other components were prepared and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0142] Example 20 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for weighing the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 40.0% by weight, SiC wafers 10 and other components were prepared and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0143] Example 21 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for adding (volume-based D50 particle size: 5.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.950%) and nitrogen (mixing ratio: 0.050%) as in (4) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0144] Example 22 In (1) above, the hydrogen ion injection conditions were set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for adding (volume-based D50 particle size: 5.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.90%) and nitrogen (mixing ratio: 0.10%) as in (4) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0145] Example 23 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O３ Except for adding (volume-based D50 particle size: 5.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.80%) and nitrogen (mixing ratio: 0.20%) as in (4) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0146] Example 24 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for adding (volume-based D50 particle size: 5.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.70%) and nitrogen (mixing ratio: 0.30%) as in (4) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0147] Example 25 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Sm) is a liquid phase generating aid. ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0148] Example 26 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (La) is a liquid phase generating aid. ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0149] Example 27 In (1) above, the hydrogen ion injection conditions were set to an injection dose of 10 × 10１５ ions / cm ２ In the above (2), the oxide (Nd ２ O ３ Except for the addition of (volume-based D50 particle size: 4.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0150] Example 28 In (1) above, the hydrogen ion injection conditions are set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Y) is a liquid phase generating aid. ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0151] Example 29 In (1) above, the hydrogen ion injection conditions were set to an injection dose of 10 × 10 １５ ions / cm ２ In the above (2), the oxide (CeO) is a liquid phase generating aid. ２ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0152] Example 30 In (1) above, a commercially available disc-shaped SiC single crystal substrate (4H-SiC, diameter 200 mm (8 inches), off-angle 4°, thickness 0.35 mm) is prepared as the seed crystal 113a, and the implantation dose is set to 10 × 10 １５ ions / cm ２ In the above (2), the oxide (Gd ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0153] Example 31 In (1) above, aluminum ions (Al＋＋ ) with an acceleration voltage of 440 keV and an injection dose of 10 × 10 １５ ions / cm ２ Inject under the conditions described above, and in (2) above, the oxide (Gd) is used as a liquid phase generating aid. ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0154] Example 32 In (1) above, carbon ion (C ＋ ) with an acceleration voltage of 200 keV and an injection dose of 10 × 10 １５ ions / cm ２ Inject under the conditions described above, and in (2) above, the oxide (Gd) is used as a liquid phase generating aid. ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0155] Example 33 In (1) above, phosphate ion (P ＋＋ ) with an acceleration voltage of 600 keV and an injection dose of 10 × 10 １５ ions / cm ２ Inject under the conditions described above, and in (2) above, the oxide (Gd) is used as a liquid phase generating aid. ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0156] Example 34 In (1) above, helium ions (He ＋ ) with an acceleration voltage of 250 keV and an injection dose of 10 × 10 １５ ions / cm ２ Inject under the conditions described above, and in (2) above, the oxide (Gd) is used as a liquid phase generating aid. ２ O ３Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0157] Example 35 In (1) above, xenon ion (Xe ＋＋ ) with an acceleration voltage of 400 keV and an injection dose of 10 × 10 １５ ions / cm ２ Inject under the conditions described above, and in (2) above, the oxide (Gd) is used as a liquid phase generating aid. ２ O ３ Except for the addition of (volume-based D50 particle size: 5.0 μm), SiC wafers 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 3B and 3C.

[0158]

[0159]

[0160]

[0161] From Tables 3A to 3C, although the cause is unclear, by changing conditions such as the injection dose of ion I, the minimum value k can be reduced. ｍ The z-coordinate position and the average value k are given. Ｓ and local minimum value k ｍ The difference (k Ｓ -k ｍ ), maximum value k Ｍ and the average value k Ｓ The difference (k Ｍ -k Ｓ ), local minimum w ｍ The z-coordinate position and the average value w that give the value Ｓ And a very small value lol ｍ The difference (lol) ｓ -w ｍ It was found that the mean value k could be controlled. In particular, the mean value k Ｓ and local minimum value k ｍ The difference (k Ｓ -k ｍ ) is 0.150 cm －１ The above, and the average value w Ｓ And a very small value lol ｍ The difference (lol) ｓ -w ｍIt was found that the yield of good products improves when the ratio is 0.240 or higher.

[0162] 10, 40 SiC wafer 10a, 40a First main surface 10b, 40b Second main surface 12 SiC seed crystal layer 14 SiC growth layer 16, 116 Peeling acceleration layer 16a First interface 16b Second interface 111 Main wafer 112 Remaining wafer 113a, 113b Seed crystal 114 Pre-treated seed crystal 115 Grown SiC crystal 171 Inspection device 172 Processing device 173 Pre-treatment device 174 Growth device I Ion

Claims

1. A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peeling promotion layer is formed inside and / or on a surface of at least one of the first crystal layer and the second crystal layer, a first main surface that is a surface on the second crystal layer side of the SiC wafer, a second main surface that is a surface on the first crystal layer side of the SiC wafer, a first interface that is an interface closer to the first main surface among interfaces between the peeling promotion layer and the second crystal layer or the first crystal layer, and a second interface that is an interface closer to the second main surface among interfaces between the peeling promotion layer and the second crystal layer or the first crystal layer are parallel to each other, with respect to the SiC wafer, (i) a z-axis is set such that the z-axis is perpendicular to the first main surface and the second main surface, and a direction from the second main surface toward the first main surface is positive (provided that the position of the second interface is defined as z=0), and (ii) an x-axis is set such that a direction obtained by rotating the z-axis 90° clockwise is positive (provided that a center point when the SiC wafer is viewed in a plan view is defined as x=0), an x-z coordinate system is assigned, and for each measurement point positioned in a grid pattern at 5 μm intervals in a cross section within a range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, E of a Raman spectrum ２ When a Raman shift value of a mode transverse optical folded peak is measured, a graph is plotted with the z coordinate as a horizontal axis, and an average value of values obtained by subtracting a standard shift value appearing in a range of 786±α (cm －１ ) from the Raman shift value (cm －１ ) (provided that 0 ≤ α ≤ 10) is corresponded to a vertical axis,wherein a region giving a minimum value k ｍ exists within a range of -20 μm ≤ z ≤ 20 μm, and a difference between the minimum value k ｍ and an average value k －１ of values obtained by subtracting the standard shift value from the Raman shift value (cm Ｓ ) within a range of -80 μm ≤ z ≤ -20 μm (k Ｓ - k ｍ ) is 0.150 cm －１ or more, the SiC wafer.

2. In the graph above, the maximum value k is found in the range 0 μm ≤ z ≤ 40 μm. Ｍ (cm －１ There exists a region that gives the maximum value k Ｍ and the aforementioned average value k Ｓ The difference (k Ｍ -k Ｓ ) is 0.150 cm －１ The SiC wafer according to claim 1 is as described above.

3. A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a peel-promoting layer is formed inside and / or on the surface of at least one of the first crystal layer and the second crystal layer, and the first main surface which is the surface of the SiC wafer on the second crystal layer side, the second main surface which is the surface of the SiC wafer on the first crystal layer side, the first interface which is the interface between the peel-promoting layer and the second crystal layer or the first crystal layer that is closer to the first main surface, and the second interface which is the interface between the peel-promoting layer and the second crystal layer or the first crystal layer that is closer to the second main surface are parallel to each other. A coordinate system is assigned to the SiC wafer such that (i) the z-axis is set perpendicular to the first and second principal surfaces, and the direction from the second principal surface toward the first principal surface is considered positive (where the position of the second interface is defined as z=0), and (ii) the x-axis is set in the direction obtained by rotating the z-axis 90° clockwise is considered positive (where x=0 is defined as the center point when the SiC wafer is viewed from above). For each measurement point positioned in a grid at 5 μm intervals in the cross section in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, the E of the Raman spectrum is measured. ２ Mode transverse wave optical aliasing peak width at half maximum (cm) －１ When measuring ), in a graph plotted with the z-coordinate on the horizontal axis and the average of the half-width at each z-coordinate corresponding to the vertical axis, the minimum value w is found in the range -20 μm ≤ z ≤ 20 μm. ｍ There exists a region that gives the same result, and the local minimum value w ｍ And, the full width at half maximum (cm) in the range of -80 μm ≤ z ≤ -20 μm －１ ) The average value lol Ｓ The difference (lol) ｓ -w ｍ A SiC wafer in which the coefficient of gravity is 0.240 or higher.

4. The SiC wafer according to any one of claims 1 to 3, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer.

5. The second crystal layer is 5.0 × 10 １３ atoms / cm ３ A SiC wafer according to any one of claims 1 to 3, having a portion containing rare earth elements at the above concentration, wherein the rare earth element includes at least one selected from the group consisting of Gd, Sm, La, Nd, Y, and Ce.

6. The second crystal layer is 1.0 × 10 １８ atoms / cm ３ A SiC wafer according to any one of claims 1 to 3, having a portion containing nitrogen atoms at the above concentration.

7. The SiC wafer according to any one of claims 1 to 3, wherein the peel-promoting layer is a layer derived from SiC and includes voids, a peel-promoting substance, or an amorphous portion.

8. The SiC wafer according to claim 7, wherein the peel-promoting substance is at least one ion selected from the group consisting of Group 1 elements, Group 13 elements, Group 14 elements, Group 15 elements, and Group 18 elements.

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