SiC WAFER

Abstract

Provided is a SiC wafer having a low-cost configuration that does not require a peeling-promoting layer and that can be easily divided (i.e., has good peelability) while suppressing the occurrence of fractures and cracks in the wafer in a device-formed portion and a device-not-formed portion after forming a device on the wafer. The SiC wafer comprises a first crystal layer that contains a SiC single crystal, and a second crystal layer that is formed on the first crystal layer and contains a SiC single crystal. The difference between the nitrogen atom concentration in the first crystal layer and the nitrogen atom concentration in the second crystal layer is 1.00×1017-1.50×1018 atoms / cm3.

Description

SiC wafer

[0001] This disclosure relates to SiC wafers.

[0002] Silicon carbide (SiC) is attracting attention as a wide-bandgap material that can control high currents and high voltages with low loss. In particular, power semiconductor devices using SiC material (SiC power devices) have recently been expected to be used in a variety of applications because they are superior to those using Si semiconductors in terms of miniaturization, low power consumption, and high efficiency. For example, by adopting SiC power devices, converters, inverters, and on-board chargers for electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs) can be miniaturized and their efficiency improved.

[0003] Incidentally, Patent Document 1 (Japanese Patent Application Publication No. 2023-73458) discloses a method in which, after forming a device (for example, electrodes or wiring patterns) on the surface of a semiconductor wafer, a laser focused at a predetermined depth in the thickness direction of the semiconductor wafer is irradiated at regular intervals to form a modified layer in the planar direction within the semiconductor wafer, and the semiconductor wafer is divided into a device-formed portion and an unformed portion starting from this modified layer.

[0004] Japanese Patent Publication No. 2023-73458 WO2023 / 067736A1

[0005] However, with the method disclosed in Patent Document 1, if the formation of the modified layer within the semiconductor wafer is insufficient, there is a problem that cracks and fractures are likely to occur when the semiconductor wafer is divided into a device-formed portion and a non-device-formed portion. In response to this, it is conceivable to form a peel-accelerating layer by implanting ions from the surface into the interior of a seed crystal as a pretreatment in semiconductor wafer manufacturing. This would allow the semiconductor wafer to be easily divided by irradiating the peel-accelerating layer with a laser to form a modified layer during the subsequent semiconductor wafer manufacturing stage. However, the inclusion of a step to form a peel-accelerating layer in the semiconductor wafer manufacturing stage increases the wafer manufacturing cost. Therefore, there is a need for a SiC wafer that has a low-cost configuration that does not require a peel-accelerating layer, while being able to easily divide the device-formed portion and the non-device-formed portion after device formation while suppressing the occurrence of cracks and fractures in the wafer (i.e., having good peelability).

[0006] The present inventors have now discovered that, in a SiC wafer comprising a first crystal layer such as a SiC seed crystal layer and a second crystal layer such as a SiC growth layer, by controlling the nitrogen atom concentration difference between these two layers (the first crystal layer and the second crystal layer) to be within a specific range, it is possible to provide a SiC wafer that does not require a peeling accelerator layer, is low-cost, and can be easily separated into the device-formed portion and the non-device-formed portion after device formation on the wafer while suppressing the occurrence of cracks and fractures (i.e., has good peelability).

[0007] Therefore, an object of the present invention is to provide a SiC wafer that has a low-cost configuration that does not require a peel-promoting layer, and that can be easily separated into the device-formed portion and the non-device-formed portion after device formation on the wafer while suppressing the occurrence of cracks and fractures in the wafer (i.e., has good peelability).

[0008] According to the present disclosure, the following aspects are provided. [Aspect 1] A SiC wafer, comprising: a first crystal layer comprising a SiC single crystal; and a second crystal layer comprising a SiC single crystal formed on the first crystal layer, wherein a difference between a nitrogen atom concentration in the first crystal layer and a nitrogen atom concentration in the second crystal layer is 1.00×10 １７ to 1.50×10 １８ atoms / cm ３ for the SiC wafer. [Aspect 2] The SiC wafer according to Aspect 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer comprising the SiC single crystal grown from the SiC seed crystal layer. [Aspect 3] The SiC wafer according to Aspect 1 or 2, wherein a nitrogen atom concentration in the first crystal layer is 3.90×10 １８ to 1.53×10 １９ atoms / cm ３ for the SiC wafer. [Aspect 4] The SiC wafer according to any one of Aspects 1 to 3, wherein the second crystal layer has a portion containing a rare earth element at a concentration of 5.00×10 １３ atoms / cm ３ or higher. [Aspect 5] The SiC wafer according to any one of Aspects 1 to 4, wherein the second crystal layer has a portion containing a rare earth element at a concentration of 5.00×10 １３ to 3.20×10 １５ atoms / cm ３ .

[0009] It is a schematic cross-sectional view showing an example of the SiC wafer of the present disclosure. It is a diagram showing a configuration example of an entire system according to a first embodiment of the present disclosure. It is a diagram schematically showing a thermal etching process in a first example of a processing step according to a second embodiment of the present disclosure. It is a diagram schematically showing a surface oxidation process in a second example of a processing step according to a second embodiment of the present disclosure. It is a diagram schematically showing a plasma etching process in a third example of a processing step according to a second embodiment of the present disclosure.

[0010] The SiC wafer of this disclosure comprises a first crystal layer containing a SiC single crystal and a second crystal layer containing a SiC single crystal formed on the first crystal layer. Therefore, the SiC wafer of this disclosure is mainly composed of a SiC single crystal and is usable as a SiC single crystal wafer. Here, the expression "mainly composed of a SiC single crystal" means that although there is a difference in the degree of crystallinity between the first crystal layer and the second crystal layer due to the difference in nitrogen atom concentration, the first crystal layer and the second crystal layer themselves are composed of SiC single crystals (not SiC polycrystalline). Typically, the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing a SiC single crystal grown from the SiC seed crystal layer, and therefore the SiC wafer as a whole can be composed of one SiC single crystal. Accordingly, the following explanation will be based on a SiC wafer in which the first crystal layer is a SiC seed crystal layer and the second crystal layer is a SiC growth layer.

[0011] Figure 1 conceptually shows a SiC wafer 10. The SiC wafer 10 comprises a SiC seed crystal layer 12 (first crystal layer) and a SiC growth layer 14 (second crystal layer) containing a SiC single crystal grown from the SiC seed crystal layer 12. Furthermore, the difference between the nitrogen atom concentration in the SiC seed crystal layer 12 and the nitrogen atom concentration in the SiC growth layer 14 is 1.00 × 10⁻¹⁰. １７ ~1.50 x 10 １８ atoms / cm ３ Thus, by controlling the nitrogen atom concentration difference between the two layers (SiC seed crystal layer 12 and SiC growth layer 14) to be within a specific range, it is possible to provide a SiC wafer 10 that is low-cost, does not require a peeling accelerator layer, and can be easily separated into the device-formed portion and the unformed portion of the wafer after device formation (i.e., has good peelability).

[0012] That is, as described above, in the method disclosed in Patent Document 1, if the formation of a modified layer in a semiconductor wafer is insufficient, there is a problem that cracks are likely to occur when the semiconductor wafer is divided into a device-formed portion and a device-non-formed portion. In view of this, it is conceivable to form a separation-promoting layer by implanting ions from the surface of a seed crystal into the interior thereof as a pretreatment in semiconductor wafer production. It is considered that this allows the semiconductor wafer to be easily divided by irradiating the separation-promoting layer with a laser to form a modified layer in the subsequent semiconductor wafer production step. However, the inclusion of the step of forming the separation-promoting layer in the semiconductor wafer production step causes a problem that the wafer production cost increases. Therefore, there is a demand for an SiC wafer that has a low-cost configuration that does not require a separation-promoting layer, and that can be easily divided into a device-formed portion and a device-non-formed portion after device formation while suppressing the occurrence of wafer cracking and cracking (that is, has good separability). This problem is successfully solved by the present invention.

[0013] In the SiC wafer 10, the difference between the nitrogen atom concentration in the SiC seed crystal layer 12 and the nitrogen atom concentration in the SiC growth layer 14 is 1.00×10 １７ to 1.50×10 １８ atoms / cm ３ , and the nitrogen atom concentration difference is 1.00×10 １７ to 1.31×10 １８ atoms / cm ３ , which is preferably １７ to 1.22×10 １８ atoms / cm ３ , more preferably 1.00×10 １７ to 1.05×10 １８ atoms / cm ３Thus, by having a specific range of nitrogen atom concentration differences between the two layers, the SiC wafer 10 (after device formation) can be separated more easily without forming a delamination-promoting layer. Although the estimated mechanism is not certain, it is presumed that a certain difference in nitrogen atom concentration between the SiC seed crystal layer 12 and the SiC growth layer 14 causes (i) a change in the lattice constant (size of the unit cell) of the crystal (the more nitrogen it contains, the smaller the lattice constant), and (ii) as a result, lattice mismatch occurs at the interface between the two layers, generating internal stress near that interface, making delamination at the interface of the two layers easier. However, if the difference in nitrogen atom concentration between the two layers is too large, the internal stress near the interface will increase, making it easier for cracks and fissures to occur near the interface. For this reason, it is preferable to control the difference in nitrogen atom concentration between the two layers to be within the above range.

[0014] The SiC wafer 10 preferably has a thickness of 500 μm or less, and more preferably 300 to 500 μm. The shape of the SiC wafer 10 is not particularly limited, but it is preferably disc-shaped (circular). In this specification, "circular shape" does not have to be a perfect circle, but may be a substantially circular shape that can be generally recognized as circular overall. For example, it may be a shape in which a part of the circle is cut out for the purpose of specifying the crystal orientation or for other purposes, or a shape in which a slit is provided in a part of the circle, in which case the size can be determined based on the diameter of the largest circle inscribed in the outer edge excluding the cut-out outer edge or the slit. The diameter of the SiC wafer 10 is not particularly limited, but may be 100 mm (4 inches) or more, 145 mm or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more.

[0015] Typically, the SiC seed crystal layer 12 is formed of a SiC single crystal and has a crystal growth surface. In this case, there are no particular limitations on the polytype, off-angle, and polarity of the SiC single crystal, nor on the type and concentration of dopants that may be contained in the SiC single crystal; however, the polytype is preferably 4H, 6H, or 3C. Alternatively, a SiC single crystal formed into a film on a Si substrate may be used as the SiC seed crystal layer 12. The crystal growth surface on the SiC single crystal serving as the SiC seed crystal layer 12 may be a Si surface, a C surface, or both the Si surface and the C surface, and is preferably a Si surface. There is no particular limitation on the diameter of the SiC seed crystal layer 12, and the diameter may be 100 mm (4 inches) or more, 145 mm or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more. Further, the resistivity of the SiC seed crystal layer 12 is preferably 13 mΩ·cm or more, more preferably 13 to 28 mΩ·cm, and still more preferably 15 to 25 mΩ·cm.

[0016] As described above, when the SiC seed crystal layer 12 and the SiC growth layer 14 have a nitrogen atom concentration difference within a specific range, the nitrogen atom concentration in the SiC seed crystal layer 12 is 2.10×10 １９ atoms / cm ３ or less, more preferably 3.53×10 １８ to 2.04×10 １９ atoms / cm ３ , still more preferably 3.90×10 １８ to 1.53×10 １９ atoms / cm ３ , particularly preferably 6.50×10 １８ to 7.21×10 １８ atoms / cm ３ .

[0017] The SiC growth layer 14 includes a SiC single crystal grown from the SiC seed crystal layer 12. There are no particular limitations on the polytype, off-angle, and polarity of the SiC single crystal, nor on the type and concentration of dopants that may be contained in the SiC single crystal; however, the polytype is preferably 4H, 6H, or 3C.

[0018] The SiC growth layer 14 preferably contains rare earth elements, and examples of rare earth elements include Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, and combinations thereof. From the viewpoint of reducing cracking and fracture, the rare earth element is preferably Y or Ce. When the SiC growth layer 14 contains rare earth elements, the SiC growth layer 14 has a density of 5.00 × 10⁻¹⁶. １３ atoms / cm ３ It is preferable that the mixture contains a portion of rare earth elements at the above concentration, and more preferably this concentration is 5.00 × 10⁻⁶. １３ ~3.20 x 10 １５ atoms / cm ３ More preferably 1.50 × 10 １４ ~1.60 x 10 １５ atoms / cm ３ That is the case.

[0019] As described above, this disclosure provides a SiC wafer 10 that has a low-cost configuration that does not require a peel-promoting layer, and that can be easily separated into the device-formed portion and the unformed portion of the wafer while suppressing the occurrence of cracks and fractures after device formation on the wafer (i.e., has good peelability). The first and second embodiments of a system or process for manufacturing such a SiC wafer 10 will be described below. The descriptions of the first and second embodiments apply to the SiC wafer 10 described above insofar as they do not contradict the present invention, but the present invention is not limited to them. Therefore, in the following description, the SiC wafer 40, seed crystal 114, and grown SiC crystal 115 may correspond to the SiC wafer 10, SiC seed crystal layer 12, and SiC growth layer 14 described above, respectively.

[0020] In the descriptions of the first and second embodiments, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the embodiments in order to make the explanation clearer. However, these are merely examples and do not limit the interpretation of this disclosure.

[0021] In the descriptions of the first and second embodiments, the semiconductor wafer is a SiC (silicon carbide) wafer, but the method can also be applied to semiconductor wafers other than SiC wafers. Examples of semiconductor wafers other than SiC wafers include GaN (gallium nitride) wafers, AlN (aluminum nitride) wafers, or diamond wafers.

[0022] [First Embodiment] Figure 2 shows an example of the overall system configuration according to the first embodiment of this disclosure.

[0023] In the second entity, a surface device step and a wafer splitting step are performed. The second entity may be a company acting as a device manufacturer that extracts SiC chips from the SiC wafer 40 and provides SiC chips or devices having SiC chips. The SiC wafer 40 is broadly divided into a layer as a base SiC crystal and a layer as a grown SiC crystal (oriented SiC crystal).

[0024] In the surface device step, a device is formed on the first main surface (surface) of the SiC wafer 40 (corresponding to the surface of the SiC wafer 10 on the SiC growth layer 14 side). The device may include electrodes and wiring patterns.

[0025] In the wafer splitting step, the SiC wafer 40 having the device is split along the planar direction (a direction perpendicular to the thickness direction, in other words, a direction parallel to the first main surface). In this wafer splitting step, the SiC wafer 40 is split along the planar direction by a method called laser slicing using a laser device, for example. Specifically, for example, the laser device irradiates laser light (e.g., a pulsed laser) from the second main surface (back side) of the SiC wafer 40 (corresponding to the surface of the SiC seed crystal layer 12 of the SiC wafer 10) to the vicinity of the interface between the seed crystal 114 (corresponding to the SiC seed crystal layer 12) and the grown SiC crystal 115 (corresponding to the SiC growth layer 14) inside the SiC wafer 40. As a result, starting from the vicinity of the interface, the SiC wafer 40 is split into a main wafer portion 111, which is the SiC wafer portion having the first main surface, and a remaining wafer portion 112, which is the SiC wafer portion having the second main surface.

[0026] In addition, during the wafer splitting step, the SiC wafer 40 may be split into the main wafer 111 and the remaining wafer 112 by a method other than laser slicing. For example, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 by etching away the area near the interface. In this case, electrolytic etching, chemical etching, thermal etching, etc., can be used for etching. By performing the wafer splitting step by etching in this way, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 without using a laser device. Furthermore, ultrasonic delamination called sonic lift-off can also be performed. Specifically, by using sound waves to split the SiC wafer 40 into the main wafer 111 and the remaining wafer 112, the delamination surfaces of the main wafer 111 and the remaining wafer 112 can be made flat and smooth, thus eliminating material waste and allowing the remaining wafer 112 to be reused, thereby reducing wafer manufacturing costs. In addition to the above, it is possible to divide the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 by processing the area near the interface formed within the SiC wafer 40 using any method.

[0027] In the first entity, the acquisition step, processing step, optional pre-processing step, growth step, and wafer provision step are performed (in this embodiment, an inspection step is also performed between the acquisition step and the processing step, as will be described later). The first entity is a company that provides a new service, that is, a company that acquires (recovers) the remaining wafer 112 of the SiC wafer 40 from the second entity, grows a grown SiC crystal on the remaining wafer 112 to regenerate the SiC wafer 40, and provides the regenerated SiC wafer 40 to the same or a different second entity. There is one or more second entities for each first entity. Note that the wafer splitting step described above may be performed in the first entity instead of the second entity.

[0028] In the acquisition step, the remaining wafer 112 is acquired from the second entity. In the processing step, the slice surface of the remaining wafer 112 is processed to acquire a seed crystal 113a made of SiC single crystal material.

[0029] In the pretreatment step, an inhibitory region can be formed on or near the surface of the seed crystal 113a obtained in the processing step, or a seed crystal 113b made of newly prepared SiC single crystal material, which partially disrupts or inhibits the SiC crystal structure. This allows for the formation of a peel-promoting layer on the seed crystals 113a and 113b. However, in the manufacturing of the SiC wafers 10 and 40 of this disclosure, the pretreatment step can be omitted from the viewpoint of reducing manufacturing costs. Therefore, the seed crystals 113a and 113b can be used as seed crystals 114 as they are.

[0030] In the growth step, a new SiC wafer 40 is manufactured by growing a growth SiC crystal (an example of a semiconductor crystal layer) 115 on the surface of a seed crystal 114. In the SiC wafer 40 manufactured here, a seed crystal 114 and a growth SiC crystal 115 with different nitrogen atom concentrations are formed.

[0031] In the wafer supply step, the SiC wafer 40 obtained in the growth step is provided to a second entity that is the same as or different from the source from which the remaining wafer 112 was obtained.

[0032] In conventional processes not to which this disclosure applies, the portion of the SiC wafer 40 corresponding to the remaining wafer 112 is ground without separating it from the main wafer 111, and the resulting grinding waste is discarded. In contrast, in this embodiment, the remaining wafer 112 is separated from the main wafer 111 and recovered without being discarded as grinding waste, and this is recycled into a new semiconductor wafer by the first entity and provided to the second entity. The second entity forms a device on the semiconductor wafer provided by the first entity (SiC wafer 40 recycled from the remaining wafer 112), and then separates it into the main wafer 111 and the remaining wafer 112. The remaining wafer 112 is recovered by the first entity and used as a seed crystal 114 to form a grown SiC crystal, and is then used again as SiC wafer 40. By repeating this process, the portion of the SiC wafer 40 that was conventionally ground or discarded, namely the remaining wafer 112, can be reused. In this disclosure, the reuse of expensive SiC wafers is made possible, thereby reducing the manufacturing cost of devices. Furthermore, since waste can be significantly reduced throughout the entire SiC wafer manufacturing process, including high-temperature processes, it is also possible to reduce the environmental impact.

[0033] The processing step may be performed by the processing device 172, the pretreatment step may be performed by the pretreatment device 173, and the growth step may be performed by the growth device 174 (the inspection step described later may be performed by the inspection device 171).

[0034] Below, we will first describe the acquisition step, processing step, pretreatment step, growth step, and wafer supply step among the steps in the first entity, and then describe the inspection step.

[0035] <Acquisition Step> In the acquisition step, the remaining wafers 112 are acquired from one or more second entities. Any number of remaining wafers 112 may be sent to the first entity at any time the second entity has chosen, or an acquisition schedule, including the number of remaining wafers 112 to be acquired from each of the one or more second entities and the acquisition timing, may be shared between the second entity and the first entity, and the remaining wafers 112 may be acquired from the second entity according to the acquisition schedule. Note that if the wafer splitting step is performed by the first entity, the acquisition step is unnecessary.

[0036] <Processing Step> The processing in the processing step includes removing the slice surface (typically grinding and / or polishing) and removing the processed altered layer including the removed slice surface. The processing apparatus 172 may include, for example, an apparatus for grinding and / or polishing the slice surface (e.g., a grinder) and an apparatus for removing the processed altered layer, and these apparatuses may be a single apparatus (i.e., grinding and removal may be performed by one apparatus). For example, the processing apparatus 172 may be an apparatus for grinding and polishing such as the CMP (Chemical Mechanical Polishing) method.

[0037] In the processing step, a seed crystal 113a is obtained as a result of processing the remaining wafer 112. The seed crystal 113a may be composed mainly of the underlying SiC crystal, or it may be composed of the underlying SiC crystal and some oriented SiC crystal. Alternatively, instead of the seed crystal 113a, a new SiC single crystal material may be prepared and used as the seed crystal 113b.

[0038] <Pre-treatment step> In the pre-treatment apparatus 173, an inhibitory region can be formed on or near the surface of the seed crystals 113a and 113b, which partially disrupts or inhibits the formation of the crystal structure when growing the SiC crystal in the next growth step. Due to the presence of this inhibitory region, a peel-promoting layer that is easier to peel off than other parts is formed inside the SiC wafer 40 manufactured from the seed crystals 113a and 113b in the growth step. However, in the manufacturing of the SiC wafers 10 and 40 of this disclosure, the pre-treatment step can be omitted from the viewpoint of reducing manufacturing costs. Therefore, the seed crystals 113a and 113b can be used as seed crystals 114 as they are.

[0039] <Growth Step> In the growth apparatus 174, a grown SiC crystal (oriented SiC crystal) 115 is grown on the seed crystal 114 to a thickness of 50 μm or more. Such crystal growth may be carried out by sublimation or CVD (Chemical Vapor Deposition), or by other methods. As a result, a new SiC wafer 40 is obtained, which consists of a seed crystal 114, which is a crystalline layer made of SiC single crystal material, and a grown SiC crystal 115, which is a crystalline layer of SiC formed on the seed crystal 114. The method for controlling the nitrogen atom concentration difference between the two layers (SiC seed crystal layer 12 and SiC growth layer 14) is not particularly limited, but it can be controlled by controlling the atmosphere during crystal growth, the resistivity of the SiC seed crystal layer 12 used, etc. For example, the nitrogen atom concentration difference can be controlled by performing crystal growth in a mixed gas atmosphere containing nitrogen while appropriately controlling the partial pressure of nitrogen gas.

[0040] <Wafer Provision Step> A new SiC wafer 40, composed of a seed crystal 114 and a grown SiC crystal 115, is provided to a second entity that is the same as or different from the source from which the remaining wafer that forms the basis of the SiC wafer was obtained. In this way, the acquired remaining wafer 112 is regenerated into such a new SiC wafer 40 and provided to the second entity, so the second entity can obtain a main wafer from that SiC wafer 40.

[0041] The above describes the acquisition step, processing step, pretreatment step, growth step, and wafer supply step.

[0042] In this embodiment, an inspection step is included between the acquisition step and the processing step to inspect the slice surface of the acquired remaining wafer 112. The inspection step is, for example, as follows:

[0043] <Inspection Step> The inspection step includes measuring at least one of the following: the height difference of the slice surface and the thickness of the processed altered layer having the slice surface. In this embodiment, both are measured. The height difference of the slice surface is the height difference caused by the surface irregularities resulting from the laser irradiation or the separation of the main wafer 111 and the remaining wafer 112 in the wafer splitting step.

[0044] The inspection step is performed by the inspection device 171. The inspection device 171 may include a laser microscope and a Raman spectrometer. The height difference of the slice surface may be measured using the laser microscope. The thickness of the processed altered layer may be measured using the Raman spectrometer. The measurement methods for both the height difference of the slice surface and the thickness of the processed altered layer are not limited to this example. For example, the height difference of the slice surface may be measured using a white light interferometer or a contact-type shape measuring instrument.

[0045] At least one of the following (x) and (y) may be performed. (x) The processing in the processing step includes determining the amount to remove from the slice surface based on at least one of the measured height difference of the slice surface of the acquired remaining wafer 112 and the measured thickness of the processed altered layer, and removing material from the slice surface according to the determined amount. This allows for appropriate (with minimal excess or deficiency) slicing of the slice surface according to the quality (condition) of the acquired remaining wafer 112. For example, if the PV value (maximum valley depth) is measured as an example of the height difference of the slice surface, and the processing altered layer depth is measured as an example of the thickness of the processed altered layer, then the amount to remove = PV value + (processed altered layer depth × N). N may be any value greater than 0 (for example, any natural number). A processing command associated with information representing the amount to remove may be input to the processing device 172 (or the control device of the processing device 172), and the processing device 172 may perform slicing according to that amount. The "amount of material removed" may be defined by parameter values ​​for each of one or more parameter items. Examples of parameter items include the processing time and processing power (e.g., temperature and pressure) of the processing apparatus 172. (y) In the growth step, the thickness of the growing SiC crystal to be grown is determined based on at least one of the measured height difference of the slice surface of the remaining wafer 112 and the measured thickness of the processed altered layer, and the growing SiC crystal is grown to the determined thickness. This allows for appropriate (with minimal excess or deficiency) crystal growth according to the quality (condition) of the acquired remaining wafer 112. For example, the thickness to be grown may be determined based on at least one of X, Y, Z, and α. Specifically, for example, the thickness to be grown may be X - Y + Z + α. X may be the thickness required at the start of the surface device step or wafer splitting step in the second entity (the thickness requested by the second entity). Y may be the thickness of the growing SiC crystal when received by the first entity. Z can be the amount of material removed as determined in (x) above. α can be any value determined as the machining margin (for example, about 50 μm) to remove the irregularities after growth and flatten the surface.A crystal growth command, associated with information indicating the thickness to be grown, may be input to the growth apparatus 174 (or the control device for the growth apparatus 174), thereby causing the growth apparatus 174 to grow a SiC crystal of that thickness on the seed crystal.

[0046] [Second Embodiment] The second embodiment will now be described. In this description, the differences from the first embodiment will be explained, and the similarities with the first embodiment will be omitted or simplified.

[0047] In the second embodiment, crystal growth in the growth step is carried out using the method disclosed in the prior application Patent Document 2 (WO2023 / 067736A1) by the same applicant as the present application (hereinafter, this method will be conveniently referred to as the "NGK method" based on the applicant's notation). That is, in the growth step, a SiC single crystal as a seed crystal and a SiC powder layer are placed in a container in contact with each other, and the container is placed in a firing furnace and heat treatment is performed, thereby growing a SiC single crystal on the seed crystal. According to the NGK method, it is possible to obtain a SiC single crystal (grown SiC crystal) with a lower BPD density than the sublimation method and a BPD density of about the same as that of the CVD method. The second embodiment can utilize all or part of the technology disclosed in Patent Document 2.

[0048] Furthermore, when crystal growth is performed using the NGK method, the flatness of the processed surface does not need to be as high as when crystal growth is performed using the sublimation or CVD methods, and the processed surface does not need to be perfectly flat. Specifically, for example, the following applies:

[0049] When homoepitaxial growth is performed on a seed crystal using sublimation or CVD, it is usually essential that the growth surface is atomically flat and that there is no processed or altered layer. This is because irregularities can form on the epitaxial growth surface, or defects such as dislocations can be introduced into the crystal.

[0050] On the other hand, because SiC wafers are hard and stable against heat and chemicals, surface planarization and removal of processing damage using the CMP method after slicing or grinding is extremely time-consuming, and the consumption of polishing slurry and polishing pads is also high.

[0051] Therefore, in this embodiment, in the processing step, the removal of the processed altered layer is performed by a thermal etching process, a surface oxidation process, or a plasma etching process (i.e., any process that results in a lower degree of flatness after etching than etching by the CMP method). Below, examples of each process for removing the processed altered layer in the processing step of the second embodiment will be described. In this embodiment, etching other than the thermal etching process, surface oxidation process, and plasma etching process, such as etching by the CMP method, or etching by other etching processes (e.g., hydrogen etching) may be performed.

[0052] Figure 3 schematically illustrates the thermal etching process.

[0053] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a thermal etching process. This apparatus is illustrated in Figure 3. In the thermal etching process, the surface of the remaining wafer (including the processed altered layer) heated and processed in the electric furnace 302 is sublimated to a thickness of several micrometers.

[0054] For example, gas (such as nitrogen or argon, an inert gas) is introduced into an electric furnace 302, which is made of insulating material and equipped with a heater 301, through a gas pipe 305, creating an inert gas atmosphere inside the electric furnace 302. The electric furnace 302 may also be under vacuum.

[0055] The material is heated by heater 301, but the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 1000 to 2000°C), and may be set taking into account the required amount of etching (for example, 1800°C may be set). The holding time at the maximum temperature is a time within a certain time range (for example, 1 minute to 5 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0056] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 303 (for example, graphite) on a spacer 304 (for example, graphite), or it may be placed using a sheath or the like made of a heat-resistant material.

[0057] If the surface of the remaining wafer 112 is carbonized after this thermal etching process, the carbonized layer on the surface may be removed by annealing in an atmospheric furnace or the like, or by polishing or other processing. To prevent surface carbonization, a carbon getter material such as Ta may be placed inside the electric furnace 302.

[0058] Figure 4 schematically illustrates the surface oxidation process.

[0059] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a surface oxidation process. This apparatus is illustrated in Figure 4. In the surface oxidation process, the surface of the remaining wafer (including the processed altered layer) that has been heated in an oxidizing atmosphere (including an air atmosphere) in an electric furnace 402 is oxidized to a thickness of several micrometers. The oxide film may be removed by processing such as polishing, or it may be volatilized or melted (reacted with the raw material powder) during crystal growth.

[0060] For example, in an electric furnace 402 made of insulating material and equipped with a heater 401, the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 800 to 2000°C), and may be set taking into account the required amount of etching (for example, 1400°C may be set). Also, the holding time at the maximum temperature is a time within a certain time range (for example, 5 minutes to 50 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0061] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 403 (for example, alumina) on a spacer 404 (for example, alumina).

[0062] Figure 5 schematically illustrates the plasma etching process.

[0063] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a plasma etching process. This apparatus is illustrated in Figure 5. In the plasma etching process, the surface of the remaining processed wafer (including the processed altered layer) is etched to a thickness of several micrometers.

[0064] Plasma etching includes methods such as RIE (Reactive Ion Etching), ECR (Electron Cyclotron Resonance), ICP (Inductively Coupled Plasma), and CCP (Capacitively Coupled Plasma), but there are no particular limitations; for example, RIE can be applied.

[0065] The substrate temperature, gas type, processing time, and apparatus configuration may be set as appropriate depending on the desired etching rate and surface condition. The remaining wafer surface may be pre-treated by ashing or other methods to remove any surface deposits.

[0066] An upper electrode 501 and a lower electrode 503 are located in the chamber 502. Gas is introduced from the gas introduction pipe 505 and exhausted from the gas exhaust pipe 504, and plasma is generated between electrodes 501 and 503 by the high-frequency power supply 509s.

[0067] The above is an explanation of examples of each process related to the removal of the processed altered layer in the processing step according to the second embodiment. Furthermore, there are differences between the sublimation method, CVD method and the NGK method regarding crystal growth, for example, as follows.

[0068] In other words, while sublimation and CVD methods require precise cleaning after CMP polishing and before epitaxial layer formation, the NGK method does not require such cleaning.

[0069] Furthermore, in sublimation and CVD methods, the rapid heating rate increases the likelihood of seed crystal warping and subsequent breakage. Also, in sublimation and CVD methods, multiple seed crystals can be placed in the growth chamber, but if even one seed crystal is damaged, it will affect the others. On the other hand, in the NGK method, the heating rate is slower than in sublimation and CVD methods, so even if the seed crystal is slightly warped, the likelihood of breakage due to that warping is low. In addition, in the NGK method, one seed crystal is stored in each container, so even if one seed crystal is damaged, it will not affect the others.

[0070] Furthermore, in both the second and first embodiments, the diameter of the remaining wafer 112 acquired in the acquisition step may be 6 inches or more, and for example, the diameter of the remaining wafer may be 8 inches or more (for example, in the second embodiment). For example, in both cases where the diameter is 6 inches or 8 inches, the thickness of the main wafer 111 may be about 100 μm, but in the case of a 6-inch diameter, the thickness of the remaining wafer 112 may be about 250 μm, and in the case of an 8-inch diameter, the thickness of the remaining wafer 112 may be about 400 μm.

[0071] The present invention will be further described in detail by the following examples. However, the present invention is not limited to the following examples.

[0072] Example 1 (1) Preparation of SiC mixed powder Commercially available β-SiC powder (volume-based D50 particle size: 65.0 μm) and an oxide (SiO₂) which is a liquid phase formation aid ２ The oxides (D50 particle size based on volume: 0.5 μm) were weighed so that the oxide content relative to the SiC powder content was 8.1% by weight, and then placed in a polypropylene container along with pebbles and water. After placing the polypropylene container on a pot stand, the container was rotated at a speed of 50 rpm to mix the raw materials. The slurry obtained by mixing the raw materials was dried in a dryer and collected to obtain SiC mixed powder.

[0073] (2) A commercially available SiC single crystal substrate (4H-SiC, 150 mm diameter (6 inches), off-angle 4°, thickness 0.35 mm, resistivity 13 mΩ·cm) to serve as the seed crystal for the SiC mixed powder and SiC single crystal was placed in a graphite container. At this time, the seed crystal was placed on the SiC mixed powder so that only the Si side of the seed crystal was in contact with the SiC mixed powder. Several such graphite containers were prepared.

[0074] (3) Heat treatment The graphite containers prepared in (2) above were placed in a resistance furnace (firing furnace) in a location where the temperature range was within ±75°C of the set temperature, and heat treatment was performed for 20 hours at a set temperature of 2450°C in a mixed gas atmosphere of argon and nitrogen with controlled nitrogen gas partial pressure. As a result, SiC single crystals were grown on seed crystals in all graphite containers, and SiC wafers 10 having a SiC growth layer 14 on a SiC seed crystal layer 12 were obtained. Since this SiC wafer 10 does not require a process to form a peel-promoting layer, the wafer manufacturing cost can be reduced.

[0075] (4) Measurement of crystal growth thickness on SiC wafers The thickness of 25 arbitrary locations on the SiC wafer 10 obtained in (3) above was measured with a micrometer, and the arithmetic mean was calculated. The thickness of the seed crystal was also calculated at the time of (2) above using the same method. Then, the crystal growth thickness (μm) was calculated by subtracting the arithmetic mean of the seed crystal thickness from the arithmetic mean of the thickness of the SiC wafer 10. It was confirmed that the crystal growth thickness on all SiC wafers 10 was 200 μm or more.

[0076] (5) Polishing The surfaces (Si surface and C surface) of all the SiC wafers 10 obtained in (3) above were polished using diamond abrasive grains, and then chemical mechanical polishing (CMP) was performed. At this time, the amount of polishing was adjusted so that the thickness of the SiC seed crystal layer 12 after polishing was 200 μm, the thickness of the SiC growth layer 14 was 150 μm, and the thickness of the SiC wafer 10 was 350 μm.

[0077] (6) Device fabrication process A SiC-MOSFET device was formed on the SiC growth layer 14 of the polished SiC wafer 10 obtained in (5) above.

[0078] (7) Delamination of SiC seed crystal layer and SiC growth layer A pulsed laser with a wavelength of 1064 nm was irradiated into the interior of the SiC wafer 10 obtained in (6) from the SiC seed crystal layer 12 side. By scanning this pulsed laser light in the in-plane direction of the SiC wafer 10, the SiC wafer 10 on which the SiC-MOSFET device was formed was divided into a main wafer 111 (SiC growth layer 14 on which the device was formed) and a remaining wafer 112 (SiC seed crystal layer 12). The laser irradiation conditions at this time were an irradiation fluence of 100 J / cm ２ The pulse width was set to 10 ns, and the laser focusing position was set to a depth of 200 μm in the thickness direction from the surface of the SiC seed crystal layer 12 on the SiC wafer 10.

[0079] (8) Evaluation of peelability (good product rate) A total of 100 SiC wafers 10 on which SiC-MOSFET devices were formed were prepared using the same procedure as in (1) to (6) above. These SiC wafers 10 were divided into 100 sets of main wafers 111 and remaining wafers 112 using the same procedure as in (7) above. The peeled surfaces of the obtained main wafers 111 and remaining wafers 112 were irradiated with a halogen lamp, and the condition of these peeled surfaces was observed visually. If there were no cracks or cracks of 1 mm or more on the peeled surface of either the main wafers 111 or the remaining wafers 112, it was considered "acceptable". If there were cracks or cracks of 1 mm or more, it was considered "unacceptable". The peelability, i.e., the good product rate (%), was calculated by counting the number of "acceptable" wafers among the 100 sets of main wafers 111 and remaining wafers 112. The results are shown in Table 1.

[0080] (9) Impurity Concentration Analysis A total of 100 SiC wafers 10 on which SiC-MOSFET devices were formed were prepared using the same procedure as in (1) to (6) above. These SiC wafers 10 were divided into 100 sets of main wafers 111 and remaining wafers 112 using the same procedure as in (7) above. The impurity (nitrogen atoms and rare earth elements) concentration was measured in one set of main wafers 111 (SiC growth layer 14 on which the device was formed) and remaining wafers 112 (SiC seed crystal layer 12) randomly selected from these 100 sets using the following method. Specifically, the peeled surfaces of the obtained main wafers 111 and remaining wafers 112 were CMP finished using the same method as in (5) above. The amount of polishing (i.e., the thickness reduced by polishing) at this time was 5 μm. After that, the impurity (nitrogen atoms and rare earth elements) concentration was measured in the peeled surfaces of the main wafers 111 and remaining wafers 112. For measuring the impurity concentration at this time, dynamic secondary ion mass spectrometry (D-SIMS) was used, and the measurement position was the center in the in-plane direction of the main wafer 111 and the remaining wafer 112. For the rare earth element concentration, the IMS-7f manufactured by CAMECA was used as the analytical instrument, and the primary ion species O ２ ＋ The tests were conducted under the conditions of an acceleration voltage of 11.0 kV. For nitrogen atom concentration, a CAMECA IMS-7f was used as the analyzer, and the primary ion species Cs was measured. ＋ The experiment was conducted under the conditions of an acceleration voltage of 15.0 kV. Furthermore, the impurity concentration in the central area can be considered representative of the impurity concentration across the entire delamination surface of wafers 111 and 112. The results are shown in Table 1.

[0081] (10) Calculation of Nitrogen Atom Concentration Difference From the nitrogen atom concentrations of the main wafer 111 (SiC growth layer 14 on which the device was formed) and the remaining wafer 112 (SiC seed crystal layer 12) measured in (9) above, the absolute value of the nitrogen atom concentration difference between these two layers was calculated. The results are shown in Table 1.

[0082] Example 2 In the same procedure as in Example 1, except that the nitrogen gas partial pressure being controlled was changed, the SiC wafer 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 1.

[0083] Example 3 i) In (1) above, Y as the oxide. ２ O ３ Using (volume-based D50 particle size: 5.0 μm), ii) in (2) above, a seed crystal with a resistivity of 20 mΩ·cm was used, and iii) in (3) above, the controlled nitrogen gas partial pressure was changed, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 1.

[0084] Example 4 In the same procedure as in Example 3, except that a seed crystal with a diameter of 200 mm (8 inches) was used, the SiC wafer 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 1.

[0085] Example 5 In (1) above, CeO ２ Except for using volume-based D50 particle size (5.0 μm), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 3. The results are shown in Table 1.

[0086] Example 6 In Example 6, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 3, except that the oxide content relative to the SiC powder content was set to 16.2% by weight. The results are shown in Table 1.

[0087] Example 7 In (1) above, CeO ２ Except for using volume-based D50 particle size (5.0 μm), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 6. The results are shown in Table 1.

[0088] Example 8 In the same manner as in Example 3, except that the oxide content relative to the SiC powder content was set to 0.3% by weight, a SiC wafer 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 1.

[0089] Example 9 In (1) above, CeO ２Except for using volume-based D50 particle size (5.0 μm), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 8. The results are shown in Table 1.

[0090] In Example 10, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that i) a seed crystal with a resistivity of 20 mΩ·cm was used in (2) above, and ii) the controlled nitrogen gas partial pressure was changed in (3) above. The results are shown in Table 1.

[0091] In Example 11, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that i) a seed crystal with a resistivity of 15 mΩ·cm was used in (2) above, and ii) the controlled nitrogen gas partial pressure was changed in (3) above. The results are shown in Table 1.

[0092] In Example 12, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that i) a seed crystal with a resistivity of 25 mΩ·cm was used in (2) above, and ii) the controlled nitrogen gas partial pressure was changed in (3) above. The results are shown in Table 1.

[0093] In Example 13, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that i) a seed crystal with a resistivity of 28 mΩ·cm was used in (2) above, and ii) the controlled nitrogen gas partial pressure was changed in (3) above. The results are shown in Table 1.

[0094] Example 14 In Example 14, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 13, except that the partial pressure of the nitrogen gas being controlled was changed as in (3) above. The results are shown in Table 1.

[0095] Example 15 In Example 15, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 13, except that the partial pressure of the nitrogen gas being controlled was changed as in (3) above. The results are shown in Table 1.

[0096] In Example 16, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that i) a seed crystal with a resistivity of 28 mΩ·cm was used in (2) above, and ii) the controlled nitrogen gas partial pressure was changed in (3) above. The results are shown in Table 1.

[0097] Example 17 (Comparison) Except for the following, the SiC wafer 10 and other components were manufactured and various evaluations were performed in the same manner as in Example 1: i) A seed crystal with a peel-promoting layer formed on it, obtained by pre-treating it according to the procedure shown below, was used as the seed crystal in (2) above; ii) The nitrogen gas partial pressure to be controlled in (3) above was changed; and iii) In (7) above, the laser focusing position was set to the peel-promoting layer formation portion at a depth of 200 μm in the thickness direction from the surface of the SiC seed crystal layer 12 on the SiC wafer 10. The results are shown in Table 1.

[0098] (2') Pretreatment: Hydrogen ions were implanted into a commercially available SiC seed crystal substrate (4H-SiC, 150 mm diameter (6 inches), 4° off-angle, 0.35 mm thickness, 20 mΩ·cm resistivity) as ions to form a peel-accelerating layer. The hydrogen ion implantation conditions at this time were an acceleration voltage of 170 keV and an implantation dose of 8 × 10⁻¹⁶. １５ ions / cm ２ The temperature was set to 500°C.

[0099] Example 18 (Comparison) Except for changing the nitrogen gas partial pressure being controlled as in (3) above, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 1.

[0100] Example 19 (Comparison) Except for changing the controlled nitrogen gas partial pressure as in (3) above, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 1.

[0101]

[0102] Table 1 shows that, although the cause is unclear, the difference in nitrogen atom concentration between the two layers (SiC seed crystal layer and SiC growth layer) is 1.00 × 10⁻⁶. １７ atoms / cm ３If the difference in nitrogen atom concentration between the two layers is less than 1.50 × 10⁻¹⁰, it is estimated that the formation of the modified layer by laser irradiation is often insufficient due to the lack of a clear difference in crystallinity between the SiC seed crystal layer and the SiC growth layer, leading to a higher frequency of cracks and fractures during delamination and a lower yield of good products. Conversely, if the difference in nitrogen atom concentration between the two layers is 1.50 × 10⁻¹⁰, １８ atoms / cm ３ If the value is greater than 1.00 × 10, it is estimated that the yield of good products after delamination will decrease due to factors such as increased warping of the SiC wafer and a large difference in the lattice constants between the two layers, resulting in increased internal stress at the two-layer interface. １７ ~1.50 x 10 １８ atoms / cm ３ By doing so, it was found that a yield rate of good products comparable to that when a peel-promoting layer is formed can be achieved without forming a peel-promoting layer (i.e., while reducing manufacturing costs).

[0103] 10, 40 SiC wafer 12 SiC seed crystal layer 14 SiC growth layer 111 Main wafer 112 Remaining wafer 113a, 113b Seed crystal 114 Seed crystal 115 Grown SiC crystal 171 Inspection device 172 Processing device 173 Pretreatment device 174 Growth device

Claims

1. A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer formed on the first crystal layer containing a SiC single crystal, wherein the difference between the nitrogen atom concentration in the first crystal layer and the nitrogen atom concentration in the second crystal layer is 1.00 × 10⁻¹⁰. １７ ~1.50 x 10 １８ atoms / cm ３ This is a SiC wafer.

2. The SiC wafer according to claim 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer.

3. The nitrogen atom concentration in the first crystal layer is 3.90 × 10⁻⁶ １８ ~1.53 x 10 １９ atoms / cm ３ The SiC wafer according to claim 1 or 2.

4. The second crystal layer is 5.00 × 10 １３ atoms / cm ３ A SiC wafer according to claim 1 or 2, having a portion containing rare earth elements at the above concentration.

5. The second crystal layer has a concentration of 5.00×10 １３ to 3.20×10 １５ atoms / cm ３ for the rare earth element contained in a portion thereof, which is the SiC wafer according to claim 4.

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