SiC WAFER

Abstract

Provided is an SiC wafer having a low basal plane dislocation (BPD) density. This SiC wafer comprises an SiC seed crystal layer and an SiC growth layer including an SiC single crystal grown from the SiC seed crystal layer, wherein, in a Raman spectroscopic measurement in the cross section of the SiC wafer, the peak intensity of an optical folding peak of an E2-mode transverse wave has a maximum value in the vicinity of the interface between the two layers (the SiC seed crystal layer and the SiC growth layer) in the thickness direction and satisfies a prescribed condition.

Description

SiC wafer

[0001] This disclosure relates to SiC wafers.

[0002] Silicon carbide (SiC) is attracting attention as a wide-bandgap material that can control high currents and high voltages with low loss. In particular, power semiconductor devices using SiC material (SiC power devices) have recently been expected to be used in a variety of applications because they are superior to those using Si semiconductors in terms of miniaturization, low power consumption, and high efficiency. For example, by adopting SiC power devices, converters, inverters, and on-board chargers for electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs) can be miniaturized and their efficiency improved. For this reason, the development of SiC wafers, which form the core of SiC power devices, is attracting considerable attention.

[0003] To fabricate SiC power devices, it is necessary to epitaxially grow a SiC single crystal on a SiC single crystal substrate. The resulting SiC single crystal substrate contains many dislocations, which can be broadly classified into three types: basal plane dislocations (BPDs), helical dislocations (TSDs), and edge dislocations (TEDs). Of these dislocations, basal plane dislocations are inherited by the epitaxially grown film, and if they are present in the drive region of the device, current application causes the basal plane dislocations to expand into stacking faults, adversely affecting the reliability of the SiC device. Regarding these dislocations, Patent Document 1 (Japanese Patent No. 6192948) discloses a SiC single crystal having regions in which edge dislocations are unevenly distributed and regions in which basal plane dislocations are unevenly distributed. It is stated that such a SiC single crystal can suppress the degradation of properties caused by specific dislocation species. Patent Document 2 (Japanese Patent No. 5750363) states that the volume density of dislocations having a Burgers vector in the {0001} plane (mainly basal plane dislocations and through-type edge dislocations) is 3700 cm³ / cm³. ３ A SiC single crystal containing the following low dislocation density region is disclosed.

[0004] Patent No. 6192948 Patent No. 5750363 WO2023 / 067736A1

[0005] As mentioned above, reducing basal plane dislocations (BPDs) in SiC wafers is desired in order to improve the reliability of SiC devices.

[0006] The present inventors have now found that a SiC wafer having two layers, a first crystal layer such as a SiC seed crystal layer and a second crystal layer such as a SiC growth layer, exhibits E in a cross-sectional Raman spectroscopy measurement. ２ We have found that by configuring the mode transverse wave optical folding peak to have a maximum peak intensity near the interface of the two layers in the thickness direction and satisfying predetermined conditions, it is possible to provide a SiC wafer with a low basal plane dislocation (BPD) density.

[0007] Therefore, an object of the present invention is to provide a SiC wafer with a low basal plane dislocation (BPD) density.

[0008] The following embodiments are provided according to this disclosure: [Embodiment 1] A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein the first main surface which is the surface of the SiC wafer on the second crystal layer side, the second main surface which is the surface of the SiC wafer on the first crystal layer side, and the interface between the second crystal layer and the first crystal layer are parallel to each other. A coordinate system is assigned to the SiC wafer such that (i) the z-axis is set perpendicular to the first and second principal surfaces, and the direction from the second principal surface toward the first principal surface is considered positive (where the position of the interface is defined as z=0), and (ii) the x-axis is set in the direction obtained by rotating the z-axis 90° clockwise is considered positive (where x=0 is defined as the center point when the SiC wafer is viewed from above). For each measurement point positioned in a grid at 5 μm intervals in the cross section in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, the E of the Raman spectrum is measured. ２ When measuring the intensity of the transverse wave optical aliasing peak, with the z-coordinate as the horizontal axis, the z-coordinate corresponds to 786 cm⁻¹. －１ In a graph plotting the average peak intensity in the vicinity on the vertical axis, the maximum value I is in the range -50 μm ≤ z ≤ 50 μm. Ｍ１ There exists a region that gives the maximum value I Ｍ１, wherein a value obtained by dividing E of the Raman spectrum in the range of -80 μm ≦ z ≦ -50 μm by an average peak intensity I ２ near 786 cm －１ of the mode transverse optical folded peak, which is I Ｓ１ divided by I Ｍ１ / I Ｓ１ is 1.120 or more. [Aspect 2] The SiC wafer according to Aspect 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer. [Aspect 3] In the x-z coordinate system, for each measurement point positioned in a grid at 0.5 μm intervals in a cross-section within the range of -2.5 μm ≦ x ≦ 2.5 μm and -20.0 μm ≦ z ≦ 20.0 μm, E of the Raman spectrum ２ when measuring the intensity of the mode transverse optical folded peak, in a graph plotted with the z-coordinate as the horizontal axis and the average peak intensity near 786 cm －１ at each z-coordinate as the vertical axis, there exists a region providing a maximum value I Ｍ２ within the range of -10.0 μm ≦ z ≦ 10.0 μm, and a value obtained by dividing the maximum value I Ｍ２ by an average peak intensity I ２ near 786 cm －１ of the mode transverse optical folded peak of the Raman spectrum in the range of -20.0 μm ≦ z ≦ -10.0 μm, which is I Ｓ２ divided by I Ｍ２ / I Ｓ２ is 1.030 or more. [Aspect 4] The SiC wafer according to any one of Aspects 1 to 3, wherein the second crystal layer has a portion containing a rare earth element at a concentration of 5.0 × 10 １３ atoms / cm ３ or more, and the rare earth element includes at least one selected from the group consisting of Gd, Sm, La, Nd, Y and Ce.

[0009] It is a schematic cross-sectional view showing an example of the SiC wafer of the present disclosure. In an example of the SiC wafer of the present disclosure, the horizontal axis represents the z-coordinate, and the vertical axis represents 786 cm at each z-coordinate －１This is a graph plotting the average peak intensity in the vicinity. This is a diagram showing an example of the overall system configuration according to the first embodiment of this disclosure. This is a diagram schematically showing the thermal etching process in the first example of the processing steps according to the second embodiment of this disclosure. This is a diagram schematically showing the surface oxidation process in the second example of the processing steps according to the second embodiment of this disclosure. This is a diagram schematically showing the plasma etching process in the third example of the processing steps according to the second embodiment of this disclosure.

[0010] The SiC wafer of this disclosure comprises a first crystal layer containing a SiC single crystal and a second crystal layer containing a SiC single crystal formed on the first crystal layer. Therefore, the SiC wafer of this disclosure is mainly composed of SiC single crystals and is usable as a SiC single crystal wafer. Here, the expression "mainly composed of SiC single crystals" means that the SiC wafer is near the interface of the two layers (first crystal layer and second crystal layer) in the thickness direction. ２ The fact that the peak intensity of the mode transverse wave optical folding peak is controlled to take a maximum value and satisfy predetermined conditions means that, although the strain within the crystal is likely changing near the interface, the first and second crystal layers themselves are composed of SiC single crystals (not SiC polycrystalline). Typically, the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing a SiC single crystal grown from the SiC seed crystal layer. Therefore, the SiC wafer as a whole can be composed of a single SiC single crystal (or at least primarily composed of a SiC single crystal). Accordingly, the following explanation will be based on a SiC wafer in which the first crystal layer is a SiC seed crystal layer and the second crystal layer is a SiC growth layer.

[0011] Figure 1 conceptually shows a SiC wafer 10. The SiC wafer 10 comprises a SiC seed crystal layer 12 (first crystal layer) and a SiC growth layer 14 (second crystal layer) containing a SiC single crystal grown from the SiC seed crystal layer 12. Here, the first main surface 10a, which is the surface of the SiC wafer 10 on the SiC growth layer 14 side, the second main surface 10b, which is the surface of the SiC wafer 10 on the SiC seed crystal layer 12 side, and the interface between the SiC growth layer 14 and the SiC seed crystal layer 12 are parallel to each other. When Raman spectroscopy is performed on the cross-section of the SiC wafer 10, E is found near the interface of the two layers in the thickness direction. ２ Mode transverse wave optical aliasing peak (E ２ The peak intensity of the FTO peak is configured to reach a maximum value and satisfy predetermined conditions. This makes it possible to provide a SiC wafer 10 with a low basal plane dislocation (BPD) density. In other words, as described above, reducing basal plane dislocations (BPD) in SiC wafers is desired in order to improve the reliability of SiC devices. This problem is successfully resolved according to the present invention.

[0012] As described above, in the present invention, when Raman spectroscopy is performed on the cross-section of the SiC wafer 10, E is observed near the interface of the two layers in the thickness direction. ２ Mode transverse wave optical aliasing peak (E ２ The configuration is such that the peak intensity of the FTO peak reaches its maximum value and satisfies predetermined conditions. This configuration will be described in detail below.

[0013] A coordinate system is assigned to the SiC wafer 10 such that (i) the z-axis is set perpendicular to the first main surface 10a and the second main surface 10b, and the direction from the second main surface 10b toward the first main surface 10a is considered positive (however, the position of the above interface is defined as z=0), and (ii) the x-axis is set so that the direction obtained by rotating the z-axis clockwise by 90° is considered positive (however, the center point when the SiC wafer 10 is viewed from above is defined as x=0). In this x-z coordinate system, in the cross section of the SiC wafer 10 in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, the Raman spectrum E is measured for each measurement point positioned in a grid at 5 μm intervals. ２The peak intensity of the transverse wave optical aliasing peak is measured. Next, the z-coordinate is used as the horizontal axis, and the peak intensity at 786 cm is measured for each z-coordinate. －１ A graph is obtained by plotting the average value of the peak intensity in the vicinity (reflecting all x-coordinate values ​​on a given z-coordinate) on the vertical axis. In this graph, the SiC wafer 10 has a maximum value I in the range of -50 μm ≤ z ≤ 50 μm. Ｍ１ There exists a region that gives this value I. Ｍ１ The E of the Raman spectrum in the range -80 μm ≤ z ≤ -50 μm ２ Mode transverse wave optical folding peak 786 cm －１ Average value of peak intensity in the vicinity I Ｓ１ The value I obtained by dividing by Ｍ１ / I Ｓ１ However, it is 1.120 or higher. When Raman spectroscopy is performed on the cross-section of the SiC wafer 10, the SiC wafer 10 has these characteristics near the interface of the two layers (in the range of -50 μm ≤ z ≤ 50 μm), which makes it possible to provide a SiC wafer 10 with a low BPD density. The reason for this is not clear, but the estimated mechanism is that near the interface of the two layers of the SiC wafer 10 having the above characteristics, the strain in the crystal changes, causing the Raman peak intensity to fluctuate, and thereby changing the propagation behavior of the BPD. This change in strain in the crystal is presumed to be caused, for example, by nitrogen atoms in the atmosphere during crystal growth and / or rare earth elements in the raw materials used to manufacture the wafer, which dissolve in the SiC.

[0014] Here, the "center point," which is the point where x = 0 when the SiC wafer 10 is viewed from above, is typically defined as the center point of the largest circle inscribed in the outer edge of the wafer when the wafer is viewed from above (or from above). Alternatively, if the SiC wafer 10 is rectangular, the intersection of the diagonals of the SiC wafer 10 may be defined as the "center point." Also, "786 cm －１ "Peak intensity in the vicinity" refers to "E ２ This means "peak intensity of transverse wave optical aliasing peak." Therefore, the vertical axis of the graph above represents E at each z coordinate. ２ Mode transverse wave optical aliasing peak (E ２This can be rephrased as the average value of the peak intensity (FTO peak).

[0015] Next, with the z-coordinate as the horizontal axis, the value at each z-coordinate is 786 cm. －１ A concrete example of the process for obtaining a graph plotting the average peak intensity in the vicinity on the vertical axis will be explained. First, Raman spectral measurements are performed at 5 μm intervals in the x-z coordinate system of the cross-section of the SiC wafer 10, in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, that is, in the range of 50 μm × 160 μm of the cross-section of the SiC wafer 10. Therefore, a total of (50 / 5) × (160 / 5) = 320 Raman spectra are obtained at each measurement point. From each of these Raman spectra, 786 cm⁻¹ is obtained. －１ The peak intensity in the vicinity, i.e., E ２ - Peak intensity I of the FTO peak ｚ，ｘ We will find this I. ｚ，ｘ The "z" in I indicates the position (μm) of the z coordinate at each measurement point. ｚ，ｘ The "x" indicates the x-coordinate position (μm) at each measurement point. Therefore, there are a total of 320 I ｚ，ｘ This will result in the following: Based on this, for example, when the z-coordinate position is -80 μm, the I for all x-coordinates ｚ，ｘ The average value I ａ，－８０ Calculate the I for all x coordinates when the z coordinate position is -75 μm. ｚ，ｘ The average value I ａ，－７５ For example, the average value I at each z coordinate is calculated. ａ，ｚ Calculate the result. The result of this calculation is shown in Table 1 below.

[0016]

[0017] Based on Table 1, the z-coordinate is used as the horizontal axis, and the average value I at each z-coordinate is used. ａ，ｚ The above graph can be obtained by plotting the values ​​on the vertical axis. An example of the above graph for the SiC wafer 10 of this disclosure is shown in Figure 2.

[0018] In the graph above, the SiC wafer 10 has a maximum value I in the range of -50 μm ≤ z ≤ 50 μm. Ｍ１Where there exists a region that gives a maximum value I Ｍ１ The z-coordinate position that gives the value is preferably in the range of -30 μm ≤ z ≤ 30 μm, more preferably in the range of -20 μm ≤ z ≤ 20 μm, even more preferably in the range of -10 μm ≤ z ≤ 10 μm, and particularly preferably in the range of -5 μm ≤ z ≤ 5 μm. Here, the maximum value I Ｍ１ In Table 1, I ａ，－５０ From I ａ，５０ It can be said that it exists within the range of values ​​up to . Note that in the graph of Figure 2, the maximum value I Ｍ１ The z-coordinate position that gives this is 5 μm.

[0019] Furthermore, in the graph above, the maximum value I given in the range -50 μm ≤ z ≤ 50 μm Ｍ１ The E of the Raman spectrum in the range -80 μm ≤ z ≤ -50 μm ２ - FTO Peak: 786 cm －１ Average value of peak intensity in the vicinity I Ｓ１ The value I obtained by dividing by Ｍ１ / I Ｓ１ However, where 1.120 or more, this I Ｍ１ / I Ｓ１ The mean value is preferably 1.120 to 6.950, more preferably 1.700 to 6.950, and even more preferably 2.400 to 6.950. Here, the mean value is Ｓ１ In Table 1, I ａ，－８０ From I ａ，－５０ This represents the average value up to [a certain point]. Note that in the graph in Figure 2, I Ｍ１ / I Ｓ１ It is 6.92.

[0020] Furthermore, in the above x-z coordinate system, for each measurement point positioned in a grid pattern at 0.5 μm intervals in the cross-section of the SiC wafer 10 in the range of -2.5 μm ≤ x ≤ 2.5 μm and -20.0 μm ≤ z ≤ 20.0 μm, the E of the Raman spectrum is measured. ２ - When measuring the intensity of the FTO peak, the z-coordinate was used as the horizontal axis, and the value at each z-coordinate was 786 cm. －１ In a graph plotting the average peak intensity in the vicinity on the vertical axis, a maximum value I occurs in the range -10.0 μm ≤ z ≤ 10.0 μm. Ｍ２It is preferable that a region exists that gives this. This graph can be obtained by following a process similar to the specific example of the process for obtaining the graph described above. Maximum value I Ｍ２ The z-coordinate position that gives the value is preferably in the range of -10 μm ≤ z ≤ 10 μm, more preferably in the range of -8.0 μm ≤ z ≤ 8.0 μm, even more preferably in the range of -6.0 μm ≤ z ≤ 6.0 μm, and particularly preferably in the range of -5.0 μm ≤ z ≤ 5.0 μm. And in this graph, the maximum value I Ｍ２ The E of the Raman spectrum in the range -20.0 μm ≤ z ≤ -10.0 μm ２ - FTO Peak: 786 cm －１ Average value of peak intensity in the vicinity I Ｓ２ The value I obtained by dividing by Ｍ２ / I Ｓ２ However, it is preferably 1.030 or higher, more preferably 1.030 to 1.230, even more preferably 1.050 to 1.230, and particularly preferably 1.080 to 1.230.

[0021] As described above, when Raman spectroscopy was performed on a cross-section of the SiC wafer 10, the E near the interface of the two layers was observed. ２ - The characteristics of the peak intensity of the FTO peak were explained.

[0022] The SiC wafer 10 preferably has a thickness of 500 μm or less, and more preferably 350 to 500 μm. The shape of the SiC wafer 10 is not particularly limited, but it is preferably disc-shaped (circular). In this specification, "circular shape" does not have to be a perfect circle, but may be a substantially circular shape that can be generally recognized as circular overall. For example, it may be a shape in which a part of the circle is cut out for the purpose of specifying the crystal orientation or for other purposes, or a shape in which a slit is provided in a part of the circle, in which case the size can be determined based on the diameter of the largest circle inscribed in the outer edge excluding the cut-out outer edge or the slit. The diameter of the SiC wafer 10 is not particularly limited, but may be 100 mm (4 inches) or more, 145 mm or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more.

[0023] Typically, the SiC seed crystal layer 12 is composed of SiC single crystal and has a crystal growth surface. In this case, the polytype, off-angle, polarity of the SiC single crystal, and the type and concentration of dopants that may be contained in the SiC single crystal are not particularly limited, but 4H, 6H or 3C is preferable as the polytype. A SiC single crystal formed on a Si substrate may also be used as the SiC seed crystal layer 12. The crystal growth surface on the SiC single crystal serving as the SiC seed crystal layer 12 may be a Si surface, a C surface, or both the Si surface and the C surface, and a Si surface is preferable. The diameter of the SiC seed crystal layer 12 is not particularly limited, but it may be 100 mm (4 inches) or more in diameter, 145 mm or more in diameter, 150 mm (6 inches) or more in diameter, or 200 mm (8 inches) or more in diameter.

[0024] The SiC growth layer 14 includes a SiC single crystal grown from the SiC seed crystal layer 12. The polytype, off-angle, polarity of this SiC single crystal, and the type and concentration of dopants that may be contained in the SiC single crystal are not particularly limited, but 4H, 6H or 3C is preferable as the polytype.

[0025] The SiC growth layer 14 preferably contains a rare earth element. Examples of the rare earth element include Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc and combinations thereof; preferably Gd, Sm, La, Nd, Y, Ce and combinations thereof; more preferably Y and / or Ce. When the SiC growth layer 14 contains a rare earth element, the SiC growth layer 14 has a content of 5.0×10 １３ atoms / cm ３ It is preferable to have a portion containing the rare earth element at the above concentration, more preferably the concentration is 5.0×10 １３ to 7.0×10 １５ atoms / cm ３ , more preferably 5.0×10 １３ to 5.0×10 １５ atoms / cm ３ , particularly preferably 5.0×10 １３ to 2.0×10 １５ atoms / cm ３Furthermore, the SiC growth layer 14 may also contain Si as an element other than rare earth elements. In this case, the preferred elemental concentration range is the same as the rare earth element concentration range described above.

[0026] As described above, in this disclosure, when Raman spectroscopy is performed on a cross-section of a SiC wafer 10 having a first crystal layer such as a SiC seed crystal layer 12 and a second crystal layer such as a SiC growth layer 14, E is observed near the interface of these two layers. ２ - By controlling the peak intensity of the FTO peak to have predetermined characteristics, a SiC wafer 10 with a low basal plane dislocation (BPD) density can be provided. The first and second embodiments of a system or process for manufacturing such a SiC wafer 10 will be described below. The descriptions of the first and second embodiments apply to the SiC wafer 10 described above insofar as they do not contradict the present invention, but the present invention is not limited to them. Therefore, in the following description, the SiC wafer 40, seed crystal 114, and grown SiC crystal 115 can correspond to the SiC wafer 10, SiC seed crystal layer 12, and SiC growth layer 14 described above, respectively.

[0027] In the descriptions of the first and second embodiments, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the embodiments in order to make the explanation clearer. However, these are merely examples and do not limit the interpretation of this disclosure.

[0028] In the descriptions of the first and second embodiments, the semiconductor wafer is a SiC (silicon carbide) wafer, but the method can also be applied to semiconductor wafers other than SiC wafers. Examples of semiconductor wafers other than SiC wafers include GaN (gallium nitride) wafers, AlN (aluminum nitride) wafers, or diamond wafers.

[0029] [First Embodiment] Figure 3 shows an example of the overall system configuration according to the first embodiment of this disclosure.

[0030] In the second entity, a surface device step and a wafer splitting step are performed. The second entity may be a company acting as a device manufacturer that extracts SiC chips from the SiC wafer 40 and provides SiC chips or devices having SiC chips. The SiC wafer 40 is broadly divided into a layer as a base SiC crystal and a layer as a grown SiC crystal (oriented SiC crystal).

[0031] In the surface device step, a device is formed on the first main surface (surface) of the SiC wafer 40 (corresponding to the surface of the SiC wafer 10 on the SiC growth layer 14 side). The device may include electrodes and wiring patterns.

[0032] In the wafer splitting step, the SiC wafer 40 having the device is split along the planar direction (a direction perpendicular to the thickness direction, in other words, a direction parallel to the first main surface). In this wafer splitting step, the SiC wafer 40 is split along the planar direction by a method called laser slicing using a laser device, for example. Specifically, for example, the laser device irradiates laser light (e.g., a pulsed laser) from the second main surface (back side) of the SiC wafer 40 (corresponding to the surface of the SiC seed crystal layer 12 of the SiC wafer 10) to the vicinity of the interface between the seed crystal 114 (corresponding to the SiC seed crystal layer 12) and the grown SiC crystal 115 (corresponding to the SiC growth layer 14) inside the SiC wafer 40. As a result, starting from the vicinity of the interface, the SiC wafer 40 is split into a main wafer portion 111, which is the SiC wafer portion having the first main surface, and a remaining wafer portion 112, which is the SiC wafer portion having the second main surface.

[0033] In addition, during the wafer splitting step, the SiC wafer 40 may be split into the main wafer 111 and the remaining wafer 112 by a method other than laser slicing. For example, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 by etching away the area near the interface. In this case, electrolytic etching, chemical etching, thermal etching, etc., can be used for etching. By performing the wafer splitting step by etching in this way, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 without using a laser device. Furthermore, ultrasonic delamination called sonic lift-off can also be performed. Specifically, by using sound waves to split the SiC wafer 40 into the main wafer 111 and the remaining wafer 112, the delamination surfaces of the main wafer 111 and the remaining wafer 112 can be made flat and smooth, thus eliminating material waste and allowing the remaining wafer 112 to be reused, thereby reducing wafer manufacturing costs. In addition to the above, it is possible to divide the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 by processing the area near the interface formed within the SiC wafer 40 using any method.

[0034] In the first entity, the acquisition step, processing step, optional pre-processing step, growth step, and wafer provision step are performed (in this embodiment, an inspection step is also performed between the acquisition step and the processing step, as will be described later). The first entity is a company that provides a new service, that is, a company that acquires (recovers) the remaining wafer 112 of the SiC wafer 40 from the second entity, grows a grown SiC crystal on the remaining wafer 112 to regenerate the SiC wafer 40, and provides the regenerated SiC wafer 40 to the same or a different second entity. There is one or more second entities for each first entity. Note that the wafer splitting step described above may be performed in the first entity instead of the second entity.

[0035] In the obtaining step, the remaining wafer 112 is obtained from the second entity. In the processing step, the sliced surface of the remaining wafer 112 is processed to obtain a seed crystal 113a composed of a SiC single crystal material.

[0036] In the pretreatment step, for the seed crystal 113a obtained in the processing step, or a newly prepared seed crystal 113b composed of a SiC single crystal material, an inhibition region that partially divides or inhibits the SiC crystal structure can be formed on the surface of the seed crystal or in the vicinity thereof. Accordingly, a peeling promotion layer can be formed on the seed crystals 113a and 113b. However, in the manufacturing of the SiC wafers 10 and 40 of the present disclosure, the pretreatment step can be omitted from the viewpoint of reducing manufacturing costs. Therefore, the seed crystals 113a and 113b can be directly used as the seed crystal 114.

[0037] In the growth step, a new SiC wafer 40 is manufactured by growing a grown SiC crystal (an example of a semiconductor crystal layer) 115 on the surface of the seed crystal 114. The SiC wafer 40 manufactured herein has E near the interface between two layers (the SiC growth layer 14 and the SiC seed crystal layer 12) ２ -FTO peak whose peak intensity is controlled to have predetermined characteristics.

[0038] In the wafer providing step, the SiC wafer 40 obtained in the growth step is provided to a second entity that is the same as or different from the acquisition source of the remaining wafer 112.

[0039] In conventional processes not to which this disclosure applies, the portion of the SiC wafer 40 corresponding to the remaining wafer 112 is ground without separating it from the main wafer 111, and the resulting grinding waste is discarded. In contrast, in this embodiment, the remaining wafer 112 is separated from the main wafer 111 and recovered without being discarded as grinding waste, and this is recycled into a new semiconductor wafer by the first entity and provided to the second entity. The second entity forms a device on the semiconductor wafer provided by the first entity (SiC wafer 40 recycled from the remaining wafer 112), and then separates it into the main wafer 111 and the remaining wafer 112. The remaining wafer 112 is recovered by the first entity and used as a seed crystal 114 to form a grown SiC crystal, and is then used again as SiC wafer 40. By repeating this process, the portion of the SiC wafer 40 that was conventionally ground or discarded, namely the remaining wafer 112, can be reused. In this disclosure, the reuse of expensive SiC wafers is made possible, thereby reducing the manufacturing cost of devices. Furthermore, since waste can be significantly reduced throughout the entire SiC wafer manufacturing process, including high-temperature processes, it is also possible to reduce the environmental impact.

[0040] The processing step may be performed by the processing device 172, the pretreatment step may be performed by the pretreatment device 173, and the growth step may be performed by the growth device 174 (the inspection step described later may be performed by the inspection device 171).

[0041] Below, we will first describe the acquisition step, processing step, pretreatment step, growth step, and wafer supply step among the steps in the first entity, and then describe the inspection step.

[0042] <Acquisition Step> In the acquisition step, the remaining wafers 112 are acquired from one or more second entities. Any number of remaining wafers 112 may be sent to the first entity at any time the second entity has chosen, or an acquisition schedule, including the number of remaining wafers 112 to be acquired from each of the one or more second entities and the acquisition timing, may be shared between the second entity and the first entity, and the remaining wafers 112 may be acquired from the second entity according to the acquisition schedule. Note that if the wafer splitting step is performed by the first entity, the acquisition step is unnecessary.

[0043] <Processing Step> The processing in the processing step includes removing the slice surface (typically grinding and / or polishing) and removing the processed altered layer including the removed slice surface. The processing apparatus 172 may include, for example, an apparatus for grinding and / or polishing the slice surface (e.g., a grinder) and an apparatus for removing the processed altered layer, and these apparatuses may be a single apparatus (i.e., grinding and removal may be performed by one apparatus). For example, the processing apparatus 172 may be an apparatus for grinding and polishing such as the CMP (Chemical Mechanical Polishing) method.

[0044] In the processing step, a seed crystal 113a is obtained as a result of processing the remaining wafer 112. The seed crystal 113a may be composed mainly of the underlying SiC crystal, or it may be composed of the underlying SiC crystal and some oriented SiC crystal. Alternatively, instead of the seed crystal 113a, a new SiC single crystal material may be prepared and used as the seed crystal 113b.

[0045] <Pre-treatment step> In the pre-treatment apparatus 173, an inhibitory region can be formed on or near the surface of the seed crystals 113a and 113b, which partially disrupts or inhibits the formation of the crystal structure when growing the SiC crystal in the next growth step. Due to the presence of this inhibitory region, a peel-promoting layer that is easier to peel off than other parts is formed inside the SiC wafer 40 manufactured from the seed crystals 113a and 113b in the growth step. However, in the manufacturing of the SiC wafers 10 and 40 of this disclosure, the pre-treatment step can be omitted from the viewpoint of reducing manufacturing costs. Therefore, the seed crystals 113a and 113b can be used as seed crystals 114 as they are.

[0046] <Growth Step> In the growth apparatus 174, a grown SiC crystal (oriented SiC crystal) 115 is grown on the seed crystal 114 with a thickness of 50 μm or more. Such crystal growth may be carried out by sublimation or CVD (Chemical Vapor Deposition), or by other methods. As a result, a new SiC wafer 40 is obtained, which consists of a seed crystal 114, which is a crystalline layer made of SiC single crystal material, and a grown SiC crystal 115, which is a crystalline layer of SiC formed on the seed crystal 114. Note that near the interface of the two layers (SiC seed crystal layer 12 and SiC growth layer 14) E ２ - The method for controlling the peak intensity of the FTO peak to have predetermined characteristics is not particularly limited, but it can be controlled by controlling conditions such as the nitrogen concentration in the heat treatment atmosphere.

[0047] <Wafer Provision Step> A new SiC wafer 40, composed of a seed crystal 114 and a grown SiC crystal 115, is provided to a second entity that is the same as or different from the source from which the remaining wafer that forms the basis of the SiC wafer was obtained. In this way, the acquired remaining wafer 112 is regenerated into such a new SiC wafer 40 and provided to the second entity, so the second entity can obtain a main wafer from that SiC wafer 40.

[0048] The above describes the acquisition step, processing step, pretreatment step, growth step, and wafer supply step.

[0049] In this embodiment, an inspection step is included between the acquisition step and the processing step to inspect the slice surface of the acquired remaining wafer 112. The inspection step is, for example, as follows:

[0050] <Inspection Step> The inspection step includes measuring at least one of the following: the height difference of the slice surface and the thickness of the processed altered layer having the slice surface. In this embodiment, both are measured. The height difference of the slice surface is the height difference caused by the surface irregularities resulting from the laser irradiation or the separation of the main wafer 111 and the remaining wafer 112 in the wafer splitting step.

[0051] The inspection step is performed by the inspection device 171. The inspection device 171 may include a laser microscope and a Raman spectrometer. The height difference of the slice surface may be measured using the laser microscope. The thickness of the processed altered layer may be measured using the Raman spectrometer. The measurement methods for both the height difference of the slice surface and the thickness of the processed altered layer are not limited to this example. For example, the height difference of the slice surface may be measured using a white light interferometer or a contact-type shape measuring instrument.

[0052] At least one of the following (x) and (y) may be performed. (x) The processing in the processing step includes determining the amount to remove from the slice surface based on at least one of the measured height difference of the slice surface of the acquired remaining wafer 112 and the measured thickness of the processed altered layer, and removing material from the slice surface according to the determined amount. This allows for appropriate (with minimal excess or deficiency) slicing of the slice surface according to the quality (condition) of the acquired remaining wafer 112. For example, if the PV value (maximum valley depth) is measured as an example of the height difference of the slice surface, and the processing altered layer depth is measured as an example of the thickness of the processed altered layer, then the amount to remove = PV value + (processed altered layer depth × N). N may be any value greater than 0 (for example, any natural number). A processing command associated with information representing the amount to remove may be input to the processing device 172 (or the control device of the processing device 172), and the processing device 172 may perform slicing according to that amount. The "amount of material removed" may be defined by parameter values ​​for each of one or more parameter items. Examples of parameter items include the processing time and processing power (e.g., temperature and pressure) of the processing apparatus 172. (y) In the growth step, the thickness of the growing SiC crystal to be grown is determined based on at least one of the measured height difference of the slice surface of the remaining wafer 112 and the measured thickness of the processed altered layer, and the growing SiC crystal is grown to the determined thickness. This allows for appropriate (with minimal excess or deficiency) crystal growth according to the quality (condition) of the acquired remaining wafer 112. For example, the thickness to be grown may be determined based on at least one of X, Y, Z, and α. Specifically, for example, the thickness to be grown may be X - Y + Z + α. X may be the thickness required at the start of the surface device step or wafer splitting step in the second entity (the thickness requested by the second entity). Y may be the thickness of the growing SiC crystal when received by the first entity. Z can be the amount of material removed as determined in (x) above. α can be any value determined as the machining margin (for example, about 50 μm) to remove the irregularities after growth and flatten the surface.A crystal growth command, associated with information indicating the thickness to be grown, may be input to the growth apparatus 174 (or the control device for the growth apparatus 174), thereby causing the growth apparatus 174 to grow a SiC crystal of that thickness on the seed crystal.

[0053] [Second Embodiment] The second embodiment will now be described. In this description, the differences from the first embodiment will be explained, and the similarities with the first embodiment will be omitted or simplified.

[0054] In the second embodiment, crystal growth in the growth step is carried out using the method disclosed in the prior application Patent Document 3 (WO2023 / 067736A1) by the same applicant as the present application (hereinafter, this method will be conveniently referred to as the "NGK method" based on the applicant's notation). That is, in the growth step, a SiC single crystal as a seed crystal and a SiC powder layer are placed in a container in contact with each other, and the container is placed in a firing furnace and heat treatment is performed, thereby growing a SiC single crystal on the seed crystal. According to the NGK method, it is possible to obtain a SiC single crystal (grown SiC crystal) with a lower BPD density than the sublimation method and a BPD density of about the same as the CVD method. The second embodiment can utilize all or part of the technology disclosed in Patent Document 3.

[0055] Furthermore, when crystal growth is performed using the NGK method, the flatness of the processed surface does not need to be as high as when crystal growth is performed using the sublimation or CVD methods, and the processed surface does not need to be perfectly flat. Specifically, for example, the following applies:

[0056] When homoepitaxial growth is performed on a seed crystal using sublimation or CVD, it is usually essential that the growth surface is atomically flat and that there is no processed or altered layer. This is because irregularities can form on the epitaxial growth surface, or defects such as dislocations can be introduced into the crystal.

[0057] On the other hand, because SiC wafers are hard and stable against heat and chemicals, surface planarization and removal of processing damage using the CMP method after slicing or grinding is extremely time-consuming, and the consumption of polishing slurry and polishing pads is also high.

[0058] Therefore, in this embodiment, in the processing step, the removal of the processed altered layer is performed by a thermal etching process, a surface oxidation process, or a plasma etching process (i.e., any process that results in a lower degree of flatness after etching than etching by the CMP method). Below, examples of each process for removing the processed altered layer in the processing step of the second embodiment will be described. In this embodiment, etching other than the thermal etching process, surface oxidation process, and plasma etching process, such as etching by the CMP method, or etching by other etching processes (e.g., hydrogen etching) may be performed.

[0059] Figure 4 schematically illustrates the thermal etching process.

[0060] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a thermal etching process. This apparatus is illustrated in Figure 4. In the thermal etching process, the surface of the remaining wafer (including the processed altered layer) that has been heated and processed in the electric furnace 302 is sublimated to a thickness of several micrometers.

[0061] For example, gas (such as nitrogen or argon, an inert gas) is introduced into an electric furnace 302, which is made of insulating material and equipped with a heater 301, through a gas pipe 305, creating an inert gas atmosphere inside the electric furnace 302. The electric furnace 302 may also be under vacuum.

[0062] The material is heated by heater 301, but the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 1000 to 2000°C), and may be set taking into account the required amount of etching (for example, 1800°C may be set). The holding time at the maximum temperature is a time within a certain time range (for example, 1 minute to 5 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0063] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 303 (for example, graphite) on a spacer 304 (for example, graphite), or it may be placed using a sheath or the like made of a heat-resistant material.

[0064] If the surface of the remaining wafer 112 is carbonized after this thermal etching process, the carbonized layer on the surface may be removed by annealing in an atmospheric furnace or the like, or by polishing or other processing. To prevent surface carbonization, a carbon getter material such as Ta may be placed inside the electric furnace 302.

[0065] Figure 5 schematically illustrates the surface oxidation process.

[0066] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a surface oxidation process. This apparatus is illustrated in Figure 5. In the surface oxidation process, the surface of the remaining wafer (including the processed altered layer) that has been heated in an oxidizing atmosphere (including an atmospheric atmosphere) in an electric furnace 402 is oxidized to a thickness of several micrometers. The oxide film may be removed by processing such as polishing, or it may be volatilized or melted (reacted with the raw material powder) during crystal growth.

[0067] For example, in an electric furnace 402 made of insulating material and equipped with a heater 401, the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 800 to 2000°C), and may be set taking into account the required amount of etching (for example, 1400°C may be set). Also, the holding time at the maximum temperature is a time within a certain time range (for example, 5 minutes to 50 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0068] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 403 (for example, alumina) on a spacer 404 (for example, alumina).

[0069] Figure 6 schematically illustrates the plasma etching process.

[0070] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a plasma etching process. This apparatus is illustrated in Figure 6. In the plasma etching process, the surface of the remaining processed wafer (including the processed altered layer) is etched to a thickness of several micrometers.

[0071] Plasma etching includes methods such as RIE (Reactive Ion Etching), ECR (Electron Cyclotron Resonance), ICP (Inductively Coupled Plasma), and CCP (Capacitively Coupled Plasma), but there are no particular limitations; for example, RIE can be applied.

[0072] The substrate temperature, gas type, processing time, and apparatus configuration may be set as appropriate depending on the desired etching rate and surface condition. The remaining wafer surface may be pre-treated by ashing or other methods to remove any surface deposits.

[0073] An upper electrode 501 and a lower electrode 503 are located in the chamber 502. Gas is introduced from the gas introduction pipe 505 and exhausted from the gas exhaust pipe 504, and plasma is generated between electrodes 501 and 503 by the high-frequency power supply 509s.

[0074] The above is an explanation of examples of each process related to the removal of the processed altered layer in the processing step according to the second embodiment. Furthermore, there are differences between the sublimation method, CVD method and the NGK method regarding crystal growth, for example, as follows.

[0075] In other words, while sublimation and CVD methods require precise cleaning after CMP polishing and before epitaxial layer formation, the NGK method does not require such cleaning.

[0076] Furthermore, in sublimation and CVD methods, the rapid heating rate increases the likelihood of seed crystal warping and subsequent breakage. Also, in sublimation and CVD methods, multiple seed crystals can be placed in the growth chamber, but if even one seed crystal is damaged, it will affect the others. On the other hand, in the NGK method, the heating rate is slower than in sublimation and CVD methods, so even if the seed crystal is slightly warped, the likelihood of breakage due to that warping is low. In addition, in the NGK method, one seed crystal is stored in each container, so even if one seed crystal is damaged, it will not affect the others.

[0077] Furthermore, in both the second and first embodiments, the diameter of the remaining wafer 112 acquired in the acquisition step may be 6 inches or more, and for example, the diameter of the remaining wafer may be 8 inches or more (for example, in the second embodiment). For example, in both cases where the diameter is 6 inches or 8 inches, the thickness of the main wafer 111 may be about 100 μm, but in the case of a 6-inch diameter, the thickness of the remaining wafer 112 may be about 250 μm, and in the case of an 8-inch diameter, the thickness of the remaining wafer 112 may be about 400 μm.

[0078] The present invention will be further described in detail by the following examples. However, the present invention is not limited to the following examples.

[0079] Example 1 (1) Preparation of SiC mixed powder Commercially available β-SiC powder (volume-based D50 particle size: 65.0 μm) and an oxide (SiO₂) which is a liquid phase formation aid ２ The oxides (D50 particle size based on volume: 0.5 μm) were weighed so that the oxide content relative to the SiC powder content was 8.1% by weight, and then placed in a polypropylene container along with pebbles and water. After placing the polypropylene container on a pot stand, the container was rotated at a speed of 50 rpm to mix the raw materials. The slurry obtained by mixing the raw materials was dried in a dryer and collected to obtain SiC mixed powder.

[0080] (2) Arrangement of SiC mixed powder and seed crystal A commercially available SiC single crystal substrate (4H-SiC, 150 mm diameter (6 inches), off-angle 4°, thickness 0.35 mm) to be used as the seed crystal, and the SiC mixed powder obtained in (1) above were placed in a graphite container.

[0081] (3) Heat treatment The graphite container prepared in (2) above was placed in a location in the resistance furnace (firing furnace) where the temperature range was within ±75°C of the set temperature, and heat treatment was performed in an argon gas atmosphere at the set temperature of 2450°C for 20 hours. As a result, as shown in Figure 1, a SiC single crystal was grown on the SiC single crystal substrate, and a SiC wafer 10 having a SiC growth layer 14 on the SiC seed crystal layer 12 was obtained.

[0082] (4) Polishing The surface (Si side and C side) of the SiC wafer 10 obtained in (3) above was polished using diamond abrasive grains, and then chemical mechanical polishing (CMP) was performed.

[0083] (5) Measurement of basal plane dislocation density of SiC wafer The SiC wafer 10 obtained in (4) above was placed in a nickel crucible together with a KOH crystal. This crucible was etched in an electric furnace at 500°C for 10 minutes. After etching, the sample (SiC wafer 10) was cleaned, and its surface was observed with an optical microscope to determine the types of defects from the shape of the pits. The number of basal plane dislocations was measured, and the number of basal plane dislocations (number of dislocations) was measured over the area (cm²) of the observation region. ２ By dividing by ), the basal plane dislocation (BPD) density (cm －２ The BPD was calculated as follows: Specifically, 100 fields of view of 2.8 mm vertically x 3.6 mm horizontally were photographed at 20x magnification for any point on the sample surface, and the total number of BPDs was measured. This total was then used to calculate the total area of ​​the 100 fields of view, which is 10.1 cm². ２ The BPD density was calculated by dividing by [a certain factor].

[0084] The SiC wafer 10, whose BPD density was determined by the method described above, was graded according to the evaluation criteria shown below. The results are shown in Table 2. <Evaluation Criteria> - Evaluation A: SiC wafer with a BPD density of 80 cm² －２ Below - Evaluation B: SiC wafer BPD density is 80 cm －２ Over 100 cm －２ Below - Evaluation C: SiC wafer BPD density is 100 cm －２ exceed

[0085] (6) Cutting the SiC wafer A small piece of SiC wafer measuring 5 mm wide x 5 mm long was cut from the center of the SiC wafer 10 that had been etched in (6) above.

[0086] (7) Cross-sectional polishing of SiC wafer pieces The cross-section of the SiC wafer pieces obtained in (6) above was polished using diamond abrasive grains, and then chemical mechanical polishing (CMP) was performed.

[0087] (8) Fluorescence Microscope Observation The cross-section of the SiC wafer piece obtained in (7) above was observed at 10x magnification using a fluorescence microscope (Nikon Corporation, ECLIPSE LV100D), and the distance d from the surface of the SiC seed crystal layer 12 (second main surface 10b) to the interface between the SiC seed crystal layer 12 and the SiC growth layer 14 was determined. １ (μm) was measured.

[0088] (9) First Raman spectroscopy measurement (E ２ -FTO peak intensity) The cross-section of the SiC wafer fragment obtained in (7) above was analyzed using a micro-laser Raman spectrometer (Horiba, LabRAM ARAMIS). The optical system was a Zernite-Turner type spectrometer, backscattering method, and a semiconductor-pumped solid-state laser (DPSS, 532 nm) was used as the light source. Calibration was performed using a Si wafer before measuring the sample. First, the measurement conditions were determined by point analysis of the vicinity of the surface of the SiC seed crystal layer 12 in the cross-section of the SiC wafer fragment. Specifically, the laser output was adjusted to 100 mW, the Hole (confocal hole diameter) was set to 100 μm, Slit was set to "none", the grating was set to 1800 gr / mm, and the objective lens was set to 10x, and the analysis was performed in point analysis mode. The exposure time was 1 second, the number of integrations was 2, and the wavenumber range was 700 to 1100 cm⁻¹. －１ The values ​​of the light-reducing filter were determined so that the count of the strongest peak was between 1000 and 10000. Next, for the SiC wafer piece, the (i) z axis was set perpendicular to the first main surface 10a (surface of the SiC growth layer 14) and the second main surface 10b (surface of the SiC seed crystal layer 12), and the direction from the second main surface 10b toward the first main surface 10a was considered positive (however, the position of the above interface (distance d from the second main surface 10b) １(ii) The x-z coordinate system was assigned by defining z=0 at a distance of (i) and setting the x-axis to be positive in the direction obtained by rotating the z-axis 90° clockwise (however, the center point when viewing the SiC wafer piece in plan view is defined as x=0). Here, the center point means the intersection of the diagonals in the SiC wafer piece. Next, for each measurement point positioned in a grid at 5 μm intervals in the cross section of the SiC wafer piece in the range of -25 μm ≤ x ≤ 25 μm and -80 μm ≤ z ≤ 80 μm, the E of the Raman spectrum was measured. ２ Mode transverse wave optical aliasing peak (E ２ The intensity of the FTO peak was measured. An Ne lamp was used as the measurement standard, with the peak intensity due to the Ne lamp set to 300, and the peak (808.21–828.21 cm) caused by the Ne lamp emission line was measured. －１ The wavenumber at the peak top of the peak (within the range) is 818.21 cm. －１ The spectral position was corrected accordingly. Baseline correction was performed using the LabSpec6 software (manufactured by Horiba, Ltd.) with "Type" set to "Poly", "Degree" set to "2", and "Attach" set to "No". 818.21 cm －１ The peak of the Ne-Lamp emission line was peak-fitted with a Gauss-Lorentz function, resulting in 786 cm. －１ E of SiC appearing nearby ２ Mode transverse wave optical aliasing peak (E ２ The FTO peak was peak-fitted using the Lorentz function. Next, in this measurement, the z-coordinate was used as the horizontal axis, and 786 cm was used for each z-coordinate. －１ A graph was obtained by plotting the average value of the peak intensity in the vicinity (reflecting all x-coordinate values ​​on a given z-coordinate) on the vertical axis. Then, in this graph, the local maximum value I Ｍ１ The z-coordinate position (μm) that gives the result was determined. Also, in this graph, the E of the Raman spectrum in the range -80 μm ≤ z ≤ -50 μm was determined. ２ - FTO Peak: 786 cm －１ Average value of peak intensity in the vicinity I Ｓ１ Calculate I Ｍ１ / I Ｓ１The following was determined. The results are shown in Table 2. Although the above measurements were performed on a small piece of SiC wafer cut from the center of the SiC wafer 10, the evaluation results from this center can be considered representative of the entire SiC wafer 10.

[0089] (10) Second Raman spectroscopy measurement (E ２ -FTO peak intensity) The cross-section of the SiC wafer fragment obtained in (7) above was analyzed using a micro-laser Raman spectrometer (Horiba, Ltd., LabRAM ARAMIS). The optical system was a Zernite-Turner type spectrometer, backscattering method, and a semiconductor-pumped solid-state laser (DPSS, 532 nm) was used as the light source. Calibration was performed using a Si wafer before measuring the sample. First, the measurement conditions were determined by point analysis of the vicinity of the surface of the SiC seed crystal layer 12 in the cross-section of the SiC wafer fragment. Specifically, the laser output was adjusted to 100 mW, the Hole (confocal hole diameter) was set to 100 μm, Slit was set to "none", the grating was set to 1800 gr / mm, and the objective lens was set to 100x (higher magnification than the first Raman spectroscopic measurement), and the analysis was performed in point analysis mode. The exposure time was 1 second, the number of integrations was 2, and the wavenumber range was 700 to 1100 cm⁻¹. －１ The values ​​of the light-reducing filter were determined so that the count of the strongest peak was between 1000 and 10000. Next, for the SiC wafer piece, the (i) z axis was set perpendicular to the first main surface 10a (surface of the SiC growth layer 14) and the second main surface 10b (surface of the SiC seed crystal layer 12), and the direction from the second main surface 10b toward the first main surface 10a was considered positive (however, the position of the above interface (distance d from the second main surface 10b) １ (ii) The x-z coordinate system was assigned by defining z=0 at a distance of (i) and setting the x-axis to be positive in the direction obtained by rotating the z-axis clockwise by 90° (however, the center point when viewing the SiC wafer piece in plan view is defined as x=0). Here, the center point means the intersection of the diagonals in the SiC wafer piece. Next, for each measurement point positioned in a grid at 0.5 μm intervals in the cross section of the SiC wafer piece in the range of -2.5 μm ≤ x ≤ 2.5 μm and -20.0 μm ≤ z ≤ 20.0 μm, the E of the Raman spectrum was measured. ２Mode transverse wave optical aliasing peak (E ２ The intensity of the FTO peak was measured. An Ne lamp was used as the measurement standard, with the peak intensity due to the Ne lamp set to 300, and the peak (808.21–828.21 cm) caused by the Ne lamp emission line was measured. －１ The wavenumber at the peak top of the peak (within the range) is 818.21 cm. －１ The spectral position was corrected accordingly. Baseline correction was performed using the LabSpec6 software (manufactured by Horiba, Ltd.) with "Type" set to "Poly", "Degree" set to "2", and "Attach" set to "No". 818.21 cm －１ The peak of the Ne-Lamp emission line was peak-fitted with a Gauss-Lorentz function, resulting in 786 cm. －１ E of SiC appearing nearby ２ Mode transverse wave optical aliasing peak (E ２ The FTO peak was peak-fitted using the Lorentz function. Next, in this measurement, the z-coordinate was used as the horizontal axis, and 786 cm was used for each z-coordinate. －１ A graph was obtained by plotting the average value of the peak intensity in the vicinity (reflecting all x-coordinate values ​​on a given z-coordinate) on the vertical axis. Then, in this graph, the local maximum value I Ｍ２ The z-coordinate position (μm) that gives the result was determined. Also, in this graph, the E of the Raman spectrum in the range -20.0 μm ≤ z ≤ -10.0 μm was determined. ２ - FTO Peak: 786 cm －１ Average value of peak intensity in the vicinity I Ｓ２ Calculate I Ｍ２ / I Ｓ２ The following was determined. The results are shown in Table 2. Although the above measurements were performed on a small piece of SiC wafer cut from the center of the SiC wafer 10, the evaluation results from this center can be considered representative of the entire SiC wafer 10.

[0090] (11) Measurement of rare earth element concentration The SiC wafer fragment obtained in (7) above was used as an evaluation sample. Dynamic secondary ion mass spectrometry (D-SIMS) was performed on the polished surface (0001) of this evaluation sample to determine the rare earth element concentration CＬ (atoms / cm ３ The concentration of rare earth elements was measured using a CAMECA IMS-7f analyzer, and the primary ion species O was measured. ２＋ Measurements were also performed at an acceleration voltage of 11.0 kV. The results are shown in Table 2. Although the above measurements were performed on a small SiC wafer piece cut from the center of the SiC wafer 10, the evaluation results from this center can be considered representative of the entire SiC wafer 10.

[0091] Example 2 In the same manner as in Example 1, except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.90%) and nitrogen (mixing ratio: 0.10%) as described in (3) above, SiC wafers 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 2.

[0092] Example 3 In the same manner as in Example 1, except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.80%) and nitrogen (mixing ratio: 0.20%) as described in (3) above, SiC wafers 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 2.

[0093] Example 4 In the same procedure as in Example 1, except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as described in (3) above, SiC wafers 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 2.

[0094] Example 5 In the same procedure as in Example 1, except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.40%) and nitrogen (mixing ratio: 0.60%) as described in (3) above, SiC wafers 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 2.

[0095] Example 6 In the same manner as in Example 1, except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.20%) and nitrogen (mixing ratio: 0.80%) as described in (3) above, SiC wafers 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 2.

[0096] Example 7 In the same procedure as in Example 1, except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.0%) and nitrogen (mixing ratio: 1.0%) as described in (3) above, SiC wafers 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 2.

[0097] Example 8 In the above (3), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that the heat treatment was carried out in a mixed gas atmosphere of argon (mixing ratio: 98.8%) and nitrogen (mixing ratio: 1.2%). The results are shown in Table 2.

[0098] Example 9 (Comparison) In the same manner as in Example 1, except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 98.6%) and nitrogen (mixing ratio: 1.4%), the SiC wafer 10 and other components were fabricated and various evaluations were performed. The results are shown in Table 2.

[0099] Example 10 In (1) above, the oxide (Gd ２ O ３ Except for adding (volume-based D50 particle size: 5.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0100] Example 11 In (1) above, the oxide (Gd ２ O ３ (Volume-based D50 particle size: 5.0 μm) was weighed so that the oxide content relative to the SiC powder content was 4.0% by weight. Except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other products were manufactured and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0101] Example 12 In (1) above, the oxide (Gd ２ O ３(Volume-based D50 particle size: 5.0 μm) was weighed so that the oxide content relative to the SiC powder content was 2.0% by weight. Except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other items were manufactured and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0102] Example 13 In (1) above, the oxide (Gd ２ O ３ A volume-based D50 particle size of 5.0 μm was weighed out so that the oxide content relative to the SiC powder content was 1.0% by weight. Except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other materials were manufactured and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0103] Example 14 In (1) above, the oxide (Gd ２ O ３ A volume-based D50 particle size of 5.0 μm was weighed out so that the oxide content relative to the SiC powder content was 0.50% by weight. Except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other materials were manufactured and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0104] Example 15 In (1) above, the oxide (Gd ２ O ３ (Volume-based D50 particle size: 5.0 μm) was weighed so that the oxide content relative to the SiC powder content was 16.2% by weight. Except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other materials were manufactured and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0105] Example 16 In (1) above, the oxide (Gd２ O ３ (Volume-based D50 particle size: 5.0 μm) was weighed so that the oxide content relative to the SiC powder content was 40.0% by weight. Except that the heat treatment was performed in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other products were manufactured and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0106] Example 17 In (1) above, the oxide (Sm) is a liquid phase formation aid. ２ O ３ Except for adding (volume-based D50 particle size: 5.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0107] Example 18 In (1) above, the oxide (La) is a liquid phase generating aid. ２ O ３ Except for adding (volume-based D50 particle size: 5.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0108] Example 19 In (1) above, the oxide (Nd ２ O ３ Except for adding (volume-based D50 particle size: 4.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0109] Example 20 In (1) above, the oxide (Y) is a liquid phase formation aid. ２ O ３Except for adding (volume-based D50 particle size: 5.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0110] Example 21 In (1) above, the oxide (CeO) is a liquid phase formation aid. ２ Except for adding (volume-based D50 particle size: 5.0 μm) and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) as in (3) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0111] Example 22 In (1) above, the oxide (Gd ２ O ３ Except for adding (volume-based D50 particle size: 5.0 μm) in (2) above, using a commercially available SiC single crystal substrate (4H-SiC, diameter 200 mm (8 inches), off-angle 4°, thickness 0.35 mm) as the seed crystal, and performing heat treatment in a mixed gas atmosphere of argon (mixing ratio: 99.60%) and nitrogen (mixing ratio: 0.40%) in (3) above, SiC wafers 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Table 2.

[0112]

[0113] From Table 2, although the cause is unclear, by changing conditions such as the nitrogen concentration in the heat treatment atmosphere, the maximum value I Ｍ１ The z-coordinate position that gives I Ｍ１ / I Ｓ１ , maximum value I Ｍ２ The z coordinate position that gives, and I Ｍ２ / I Ｓ２ It was found that it is possible to control I Ｍ１ / I Ｓ１ (and I Ｍ２ / I Ｓ２It was found that by controlling the ) a SiC wafer 10 with a lower basal plane dislocation density can be obtained. The estimated mechanism is not clear, but it is presumed that nitrogen in the heat treatment atmosphere and / or rare earth elements in the mixed powder used as raw materials dissolved in the SiC, causing a change in the strain within the crystal.

[0114] 10, 40 SiC wafer 10a First main surface 10b Second main surface 12 SiC seed crystal layer 14 SiC growth layer 111 Main wafer 112 Remaining wafer 113a, 113b Seed crystal 114 Seed crystal 115 Grown SiC crystal 171 Inspection device 172 Processing device 173 Pretreatment device 174 Growth device

Claims

1. A SiC wafer, comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein a first main surface that is the surface of the SiC wafer on the second crystal layer side, a second main surface that is the surface of the SiC wafer on the first crystal layer side, and an interface between the second crystal layer and the first crystal layer are parallel to each other, for the SiC wafer, (i) a z-axis is set such that it is perpendicular to the first main surface and the second main surface, and a direction from the second main surface toward the first main surface is positive (provided that the position of the interface is defined as z=0), and (ii) an x-axis is set such that a direction obtained by rotating the z-axis 90° clockwise is positive (provided that a center point when the SiC wafer is viewed in plan is defined as x=0), an x-z coordinate system is assigned, for each measurement point positioned in a grid at 5 μm intervals in a cross-section within the range of -25 μm≤x≤25 μm and -80 μm≤z≤80 μm, E of Raman spectrum ２ When measuring the intensity of the mode transverse optical folding peak, taking the z-coordinate as the horizontal axis, 786 cm at each z-coordinate －１ In a graph plotted by corresponding the average value of peak intensities in the vicinity to the vertical axis, there is a region giving a maximum value I Ｍ１ within a range of -50 μm≤z≤50 μm, and the maximum value I Ｍ１ is E of Raman spectrum in the range of -80 μm≤z≤-50 μm ２ 786 cm of the mode transverse optical folding peak －１ average value I of peak intensities in the vicinity Ｓ１ value I divided by Ｍ１ / I Ｓ１ is 1.120 or more. A SiC wafer.

2. The SiC wafer according to claim 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer.

3. In the x-z coordinate system, for each measurement point positioned in a grid at 0.5 μm intervals in the cross section within the ranges of -2.5 μm ≤ x ≤ 2.5 μm and -20.0 μm ≤ z ≤ 20.0 μm, the E of the Raman spectrum is measured. ２ When measuring the intensity of the transverse wave optical aliasing peak, with the z-coordinate as the horizontal axis, the z-coordinate corresponds to 786 cm⁻¹. －１ In a graph plotting the average peak intensity in the vicinity on the vertical axis, a maximum value I occurs in the range -10.0 μm ≤ z ≤ 10.0 μm. Ｍ２ There exists a region that gives the maximum value I Ｍ２ The E of the Raman spectrum in the range -20.0 μm ≤ z ≤ -10.0 μm ２ Mode transverse wave optical folding peak 786 cm －１ Average value of peak intensity in the vicinity I Ｓ２ The value I obtained by dividing by Ｍ２ / I Ｓ２ The SiC wafer according to claim 1, wherein the coefficient is 1.030 or higher.

4. The second crystal layer is 5.0 × 10 １３ atoms / cm ３ A SiC wafer according to any one of claims 1 to 3, having a portion containing rare earth elements at the above concentration, wherein the rare earth element includes at least one selected from the group consisting of Gd, Sm, La, Nd, Y, and Ce.

Images