SiC WAFER

Abstract

The present invention provides a SiC wafer that, when a device formation part and a device non-formation part are divided after formation of a device on a wafer, can improve the flatness of the separation surfaces of said parts. The SiC wafer comprises a first crystal layer that includes a SiC single crystal and a second crystal layer that includes a SiC single crystal formed on the first crystal layer, wherein a linear crystal defect exists in the vicinity of the interface between the first crystal layer and the second crystal layer, and the second crystal layer has a part which includes nitrogen atoms at a concentration of not less than 1.00×1018 atoms / cm3.

Description

SiC wafer

[0001] This disclosure relates to SiC wafers.

[0002] Silicon carbide (SiC) is attracting attention as a wide-bandgap material that can control high currents and high voltages with low loss. In particular, power semiconductor devices using SiC material (SiC power devices) have recently been expected to be used in a variety of applications because they are superior to those using Si semiconductors in terms of miniaturization, low power consumption, and high efficiency. For example, by adopting SiC power devices, converters, inverters, and on-board chargers for electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs) can be miniaturized and their efficiency improved.

[0003] Incidentally, after forming devices (e.g., electrodes and wiring patterns) on the surface of a semiconductor wafer, the semiconductor wafer is generally divided into a device-formed portion and an unformed portion (the back surface portion of the wafer). At this time, the unformed portion is considered an unnecessary part of the wafer and is often ground and / or removed. Several wafer slicing technologies have been proposed as methods to reduce the costs associated with grinding and / or removing the back surface portion of the wafer. For example, Patent Document 1 (JP 2022-169468 A) discloses a method of forming a modified zone in a semiconductor wafer by laser irradiation and peeling the wafer along the modified zone. Patent Document 2 (JP 2020-10020 A) discloses a method of peeling a wafer by laser lift-off.

[0004] Japanese Patent Publication No. 2022-169468, Japanese Patent Publication No. 2020-10020, WO2023 / 067736A1

[0005] However, conventional methods for delaminating semiconductor wafers tend to result in significant unevenness on the delamination surface after slicing, requiring grinding and / or polishing after slicing, which is wasteful in terms of cost and environmental impact. For example, in the method disclosed in Patent Document 1, the modification of the wafer's interior by laser irradiation causes long cracks to propagate along the off-angle (e.g., about 4°), resulting in significant unevenness on the delamination surface and requiring grinding and / or polishing after slicing. While it is conceivable to introduce a delamination-promoting layer into the semiconductor wafer to suppress crack formation during slicing, this alone still leaves the problem of significant unevenness on the delamination surface. Therefore, it is desirable to improve the flatness of the delamination surfaces when a semiconductor wafer is divided into a device-formed portion and an unformed portion after device formation.

[0006] The present inventors have now discovered that by forming linear crystal defects near the interface between a first crystal layer, such as a SiC seed crystal layer, and a second crystal layer, such as a SiC growth layer, in a SiC wafer, the flatness of the delamination surface can be improved when the wafer is divided into a device-formed portion and an unformed portion after device formation.

[0007] Therefore, an object of the present invention is to provide a SiC wafer that can improve the flatness of the peeled surfaces when the wafer is divided into a device-formed portion and an unformed portion after device formation.

[0008] The following embodiments are provided according to this disclosure: [Embodiment 1] A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer containing a SiC single crystal formed on the first crystal layer, wherein linear crystal defects exist near the interface between the first crystal layer and the second crystal layer, and the second crystal layer has a density of 1.00 × 10 １８ atoms / cm ３A SiC wafer having a portion containing nitrogen atoms at the above concentration. [Aspect 2] The SiC wafer according to aspect 1, wherein the first crystal layer is a SiC seed crystal layer and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer. [Aspect 3] The SiC wafer according to aspect 1 or 2, wherein the average length of the crystal defects is 0.30 to 5.00 μm. [Aspect 4] The second crystal layer has a thickness of 25 μm or more, and the nitrogen atom concentration of the second crystal layer at a depth position of 25 μm in the thickness direction of the SiC wafer from the surface of the SiC wafer on the second crystal layer side is 1.00 × 10 １８ atoms / cm ３ The above is the SiC wafer according to any one of embodiments 1 to 3. [Embodiment 5] The second crystal layer has a thickness of 55 μm or more, and the nitrogen atom concentration of the second crystal layer at a depth of 55 μm in the thickness direction of the SiC wafer from the surface of the SiC wafer on the second crystal layer side is 1.00 × 10 １８ atoms / cm ３ The above is the SiC wafer according to any one of embodiments 1 to 4. [Embodiment 6] The second crystal layer is 5.00 × 10 １３ atoms / cm ３ A SiC wafer according to any one of embodiments 1 to 5, having a portion containing rare earth elements at the above concentration. [Embodiment 7] A SiC wafer according to any one of embodiments 1 to 6, wherein an ion-containing layer containing ions is formed near the interface between the first crystal layer and the second crystal layer. [Embodiment 8] A SiC wafer according to embodiment 7, wherein the ions are at least one selected from the group consisting of Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements.

[0009] This is a schematic cross-sectional view showing an example of a SiC wafer according to the present disclosure. This is a diagram showing an example of the overall system configuration according to the first embodiment of the present disclosure. This is an explanatory diagram of the pretreatment for forming a portion containing linear crystal defects (exfoliation aid layer). This is a diagram showing an example of the appearance of the cut surface when a SiC wafer is cut along a plane passing through the exfoliation aid layer. This is a diagram showing another example of the appearance of the cut surface when a SiC wafer is cut along a plane passing through the exfoliation aid layer. This is a diagram showing yet another example of the appearance of the cut surface when a SiC wafer is cut along a plane passing through the exfoliation aid layer. This is a schematic diagram showing the thermal etching process in a first example of the processing step according to the second embodiment of the present disclosure. This is a schematic diagram showing the surface oxidation process in a second example of the processing step according to the second embodiment of the present disclosure. This is a schematic diagram showing the plasma etching process in a third example of the processing step according to the second embodiment of the present disclosure.

[0010] The SiC wafer of this disclosure comprises a first crystal layer containing a SiC single crystal and a second crystal layer containing a SiC single crystal formed on the first crystal layer. Therefore, the SiC wafer of this disclosure is mainly composed of a SiC single crystal and is usable as a SiC single crystal wafer. Here, the expression "mainly composed of a SiC single crystal" means that even if the SiC wafer contains linear crystal defects as described later, the main part of the SiC wafer other than the linear crystal defects is composed of a SiC single crystal (not a SiC polycrystalline material). Furthermore, the above expression also means that regardless of whether the ion-containing layer described later maintains the form of a SiC single crystal or not, the main part of the SiC wafer other than the ion-containing layer is composed of a SiC single crystal (not a SiC polycrystalline material). Typically, the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing a SiC single crystal grown from the SiC seed crystal layer. Therefore, the SiC wafer can be composed of a single SiC single crystal as a whole, excluding the linear crystal defects and the ion-containing layer (or even if not, it can be mainly composed of a SiC single crystal). Therefore, the following explanation will be based on a SiC wafer in which the first crystal layer is a SiC seed crystal layer and the second crystal layer is a SiC growth layer.

[0011] Fig. 1 conceptually shows an SiC wafer 10. The SiC wafer 10 includes an SiC seed crystal layer 12 (first crystal layer) and an SiC growth layer 14 (second crystal layer) containing an SiC single crystal grown from the SiC seed crystal layer 12. Further, linear crystal defects exist near the interface between the SiC seed crystal layer 12 and the SiC growth layer 14. The SiC growth layer 14 contains 1.00×10 １８ atoms / cm ３ or higher concentration of nitrogen atoms in a portion thereof. This makes it possible to provide the SiC wafer 10 capable of improving the flatness of the separation surfaces when the wafer is divided into a device-formed portion and a device-non-formed portion after device formation on the wafer.

[0012] That is, as described above, in the conventional method for separating a semiconductor wafer, unevenness of the separation surface of the wafer after slicing tends to be large, and grinding and / or polishing after slicing are required, so it can be said that there is much waste in terms of cost and environment. For example, in the method disclosed in Patent Document 1, cracks extending along an off-angle (for example, about 4°) progress long due to modification inside the wafer by laser irradiation, so that unevenness of the separation surface becomes large, and grinding and / or polishing after slicing are required. It is also conceivable to introduce a separation promoting layer inside the semiconductor wafer for the purpose of suppressing the occurrence of cracks during wafer slicing, but this alone still leaves the problem that unevenness of the separation surface becomes large. Therefore, when a semiconductor wafer is divided into a device-formed portion and a device-non-formed portion after device formation, it is desired to improve the flatness of these separation surfaces. Such a problem is successfully solved by the present invention. Further, in the conventional method for separating a semiconductor wafer, cleavage propagating along a specific crystal plane is likely to occur at the interface between the device-formed portion and the device-non-formed portion, whereas in the present invention, the presence of linear crystal defects near the interface between the two layers (the SiC seed crystal layer 12 and the SiC growth layer 14) prevents cleavage from occurring near the interface or suppresses (or stops) the propagation of cleavage (for example, the length of cleavage is shortened), so it is presumed that the flatness of the separation surface can be improved.

[0013] The SiC wafer 10 preferably has a thickness of 500 μm or less, and more preferably 300 to 500 μm. The shape of the SiC wafer 10 is not particularly limited, but it is preferably disc-shaped (circular). In this specification, "circular shape" does not have to be a perfect circle, but may be a substantially circular shape that can be generally recognized as circular overall. For example, it may be a shape in which a part of the circle is cut out for the purpose of specifying the crystal orientation or for other purposes, or a shape in which a slit is provided in a part of the circle, in which case the size can be determined based on the diameter of the largest circle inscribed in the outer edge excluding the cut-out outer edge or the slit. The diameter of the SiC wafer 10 is not particularly limited, but may be 100 mm (4 inches) or more, 145 mm or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more.

[0014] The SiC seed crystal layer 12 is typically composed of a SiC single crystal and has a crystal growth surface. In this case, the polymorph (polytype), off-angle and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal, are not particularly limited, but the polymorph is preferably 4H, 6H, or 3C. Alternatively, a SiC single crystal deposited on a Si substrate may be used as the SiC seed crystal layer 12. The crystal growth surface on the SiC single crystal as the SiC seed crystal layer 12 may be a Si plane or a C plane, or both the Si plane and the C plane, but it is preferably a Si plane. Therefore, it is preferable that linear crystal defects are formed near this Si plane. The diameter of the SiC seed crystal layer 12 is not particularly limited, but it may be 100 mm (4 inches) or larger, 145 mm or larger, 150 mm (6 inches) or larger, or 200 mm (8 inches) or larger.

[0015] The SiC growth layer 14 contains SiC single crystals grown from the SiC seed crystal layer 12. The polymorph (polytype), off-angle and polarity of the SiC single crystal, as well as the type and concentration of dopants that may be contained in the SiC single crystal, are not particularly limited, but the polymorph is preferably 4H, 6H, or 3C.

[0016] The SiC growth layer 14 is 1.00 × 10 １８ atoms / cm ３The above concentration contains a portion containing nitrogen atoms, and this concentration is 1.00 × 10⁻⁶ １８ ~1.50 x 10 １９ atoms / cm ３ Preferably, it is 1.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ More preferably 2.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ Particularly preferred is 2.00 × 10 １８ ~8.00 x 10 １８ atoms / cm ３ That is the case.

[0017] The SiC growth layer 14 has a thickness of 5 μm or more, and the nitrogen atom concentration of the SiC growth layer 14 at a depth of 5 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC growth layer 14 on the SiC growth layer 14 side of the SiC wafer 10 is 1.00 × 10 １８ atoms / cm ３ Preferably, it is 1.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ More preferably 2.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ Particularly preferred is 2.00 × 10 １８ ~8.00 x 10 １８ atoms / cm ３ That is the case.

[0018] The SiC growth layer 14 has a thickness of 10 μm or more, and the nitrogen atom concentration of the SiC growth layer 14 at a depth of 10 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC growth layer 14 on the SiC wafer 10 side is 1.00 × 10 １８ atoms / cm ３ Preferably, it is 1.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ More preferably 2.00 × 10 １８ ~1.00 x 10 １９ atoms / cm３ Particularly preferred is 2.00 × 10 １８ ~8.00 x 10 １８ atoms / cm ３ That is the case.

[0019] The SiC growth layer 14 has a thickness of 25 μm or more, and the nitrogen atom concentration of the SiC growth layer 14 at a depth of 25 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC growth layer 14 on the SiC wafer 10 side is 1.00 × 10⁻¹⁴ １８ atoms / cm ３ Preferably, it is 1.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ More preferably 2.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ Particularly preferred is 2.00 × 10 １８ ~8.00 x 10 １８ atoms / cm ３ That is the case.

[0020] The SiC growth layer 14 has a thickness of 55 μm or more, and the nitrogen atom concentration of the SiC growth layer 14 at a depth of 55 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC growth layer 14 on the SiC growth layer 14 side of the SiC wafer 10 is 1.00 × 10 １８ atoms / cm ３ Preferably, it is 1.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ More preferably 2.00 × 10 １８ ~1.00 x 10 １９ atoms / cm ３ Particularly preferred is 2.00 × 10 １８ ~8.00 x 10 １８ atoms / cm ３ That is the case.

[0021] The SiC growth layer 14 preferably contains a rare earth element. Examples of the rare earth element include Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, and combinations thereof. From the viewpoint of improving the flatness of the peeled surface during wafer dicing, the rare earth element is preferably Y and / or Ce. When the SiC growth layer 14 contains a rare earth element, the SiC growth layer 14 has 5.00×10 １３ atoms / cm ３ or higher concentration of the rare earth element in a portion thereof. This concentration is more preferably 5.00×10 １３ to 8.00×10 １５ atoms / cm ３ , more preferably 3.00×10 １４ to 8.00×10 １５ atoms / cm ３ , particularly preferably 3.00×10 １４ to 3.20×10 １５ atoms / cm ３ .

[0022] The SiC growth layer 14 has a thickness of 5 μm or more, and the rare earth element concentration of the SiC growth layer 14 at a depth position of 5 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC wafer 10 on the SiC growth layer 14 side is 5.00×10 １３ atoms / cm ３ or higher, more preferably 5.00×10 １３ to 8.00×10 １５ atoms / cm ３ , more preferably 3.00×10 １４ to 8.00×10 １５ atoms / cm ３ , particularly preferably 3.00×10 １４ to 3.20×10 １５ atoms / cm ３ .

[0023] The SiC growth layer 14 has a thickness of 10 μm or more, and the rare earth element concentration of the SiC growth layer 14 at a depth position of 10 μm in the thickness direction of the SiC wafer 10 from the surface of the SiC wafer 10 on the SiC growth layer 14 side is 5.00×10 １３atoms / cm ３ preferably at least, more preferably 5.00×10 １３ to 8.00×10 １５ atoms / cm ３ , still more preferably 3.00×10 １４ to 8.00×10 １５ atoms / cm ３ , particularly preferably 3.00×10 １４ to 3.20×10 １５ atoms / cm ３ .

[0024] The SiC growth layer 14 has a thickness of 25 µm or more, and the rare earth element concentration of the SiC growth layer 14 at a depth position of 25 µm in the thickness direction of the SiC wafer 10 from the surface on the SiC growth layer 14 side of the SiC wafer 10 is 5.00×10 １３ atoms / cm ３ preferably at least, more preferably 5.00×10 １３ to 8.00×10 １５ atoms / cm ３ , still more preferably 3.00×10 １４ to 8.00×10 １５ atoms / cm ３ , particularly preferably 3.00×10 １４ to 3.20×10 １５ atoms / cm ３ .

[0025] The SiC growth layer 14 has a thickness of 55 µm or more, and the rare earth element concentration of the SiC growth layer 14 at a depth position of 55 µm in the thickness direction of the SiC wafer 10 from the surface on the SiC growth layer 14 side of the SiC wafer 10 is 5.00×10 １３ atoms / cm ３ preferably at least, more preferably 5.00×10 １３ to 8.00×10 １５ atoms / cm ３ , still more preferably 3.00×10 １４ to 8.00×10 １５ atoms / cm ３ , particularly preferably 3.00×10 １４ to 3.20×10 １５atoms / cm ３ That is the case.

[0026] Linear crystal defects exist near the interface between the two layers (SiC seed crystal layer 12 and SiC growth layer 14). Here, "linear crystal defects" refers to crystal defects with a length of 0.10 μm or more. The length of these linear crystal defects is typically 0.10 to 5.00 μm. Furthermore, the average length of the linear crystal defects is preferably 0.30 to 5.00 μm, more preferably 0.30 to 4.50 μm, even more preferably 0.30 to 4.00 μm, and particularly preferably 0.30 to 3.50 μm. Note that the "near the interface" of the two layers typically refers to a range of ±2 μm in the thickness direction of the SiC wafer 10 from the interface. Specifically, it refers to the region of -2 μm ≤ z ≤ 2 μm when the z-coordinate is taken with the interface of the SiC wafer 10 as the origin and the direction from the surface on the SiC seed crystal layer 12 side to the surface on the SiC growth layer 14 side of the SiC wafer 10 as positive.

[0027] The portion near the interface of the two layers in which linear crystal defects exist is preferably formed by implanting ions into at least one of the SiC seed crystal layer 12 and the SiC growth layer 14, and then applying ultrasonic vibrations to the ion-implanted portion. Therefore, it is preferable that an ion-containing layer containing ions is formed near the interface of the SiC seed crystal layer 12 and the SiC growth layer 14. In other words, it is preferable that the SiC wafer 10 has an ion-containing layer near the interface of the SiC seed crystal layer 12 and the SiC growth layer 14. Linear crystal defects are formed in the ion-containing layer by the subsequent application of ultrasonic vibrations, and the portion in which linear crystal defects exist (the portion originating from the ion-containing layer) is a SiC-derived layer (for example, a SiC-based layer) that assists in dividing the SiC wafer 10 into an upper portion and a lower portion with that portion as the starting point or boundary. Such a portion is, for example, a layer in which the SiC crystal structure is incomplete compared to other portions, or a layer in which delamination or splitting is more likely to occur due to other causes. The term "SiC-derived layer" typically refers to a layer formed by subjecting the SiC crystal (especially the SiC single crystal) constituting the SiC seed crystal layer 12 and / or the SiC growth layer 14 to some modification (for example, a SiC-based layer), and may be a layer in which the SiC crystal has been modified.

[0028] The frequency of the applied ultrasonic vibration is typically 20–60 kHz, more typically 30–50 kHz, and even more typically 35–45 kHz. Examples of fluids to be filled into the container in which the SiC seed crystal layer 12 and / or SiC growth layer 14 are placed when ultrasonic vibration is applied include pure water, deionized water, general solvents, dimethylformamide, isopropyl alcohol, methanol, ethanol, etc. Ultrasound can also be applied to the SiC seed crystal layer 12 and / or SiC growth layer 14 using a device similar to that of an ultrasonic cleaning apparatus.

[0029] The ions contained in the ion-containing layer are preferably Si, C, Al, B, P, N, O, H, noble gas elements, rare earth elements, or combinations thereof; more preferably Si, C, B, P, N, H, noble gas elements, rare earth elements, or combinations thereof; and even more preferably Si, C, B, P, noble gas elements, or combinations thereof.

[0030] As described above, this disclosure provides a SiC wafer 10 that can improve the flatness of the peeled surfaces when the wafer is divided into a device-formed portion and an unformed portion after device formation. The first and second embodiments of a system or process for manufacturing such a SiC wafer 10 will be described below. The descriptions of the first and second embodiments apply to the SiC wafer 10 described above insofar as they do not contradict the present invention, but the present invention is not limited thereto. Therefore, in the following description, the SiC wafer 40, the pre-treated seed crystal 114, the grown SiC crystal 115, and the peeling auxiliary layer 116 can correspond to the SiC wafer 10, the SiC seed crystal layer 12, the SiC growth layer 14, and the portion containing linear crystal defects, respectively.

[0031] In the descriptions of the first and second embodiments, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the embodiments in order to make the explanation clearer. However, these are merely examples and do not limit the interpretation of this disclosure.

[0032] In the descriptions of the first and second embodiments, the semiconductor wafer is a SiC (silicon carbide) wafer, but the method can also be applied to semiconductor wafers other than SiC wafers. Examples of semiconductor wafers other than SiC wafers include GaN (gallium nitride) wafers, AlN (aluminum nitride) wafers, or diamond wafers.

[0033] [First Embodiment] Figure 2 shows an example of the overall system configuration according to the first embodiment of this disclosure.

[0034] In the second entity, a surface device step and a wafer splitting step are performed. The second entity may be a company acting as a device manufacturer that extracts SiC chips from the SiC wafer 40 and provides SiC chips or devices having SiC chips. The SiC wafer 40 is broadly divided into a layer as a base SiC crystal and a layer as a grown SiC crystal (oriented SiC crystal).

[0035] In the surface device step, a device is formed on the first main surface (surface) of the SiC wafer 40 (corresponding to the surface of the SiC wafer 10 on the SiC growth layer 14 side). The device may include electrodes and wiring patterns.

[0036] In the wafer splitting step, the SiC wafer 40 having the device is split along the planar direction (a direction perpendicular to the thickness direction, in other words, a direction parallel to the first main surface). In this wafer splitting step, the SiC wafer 40 is split along the planar direction by a method called laser slicing using a laser device, for example. Specifically, for example, the laser device irradiates a peeling auxiliary layer 116 (corresponding to a portion containing linear crystal defects) that has been pre-formed inside the SiC wafer 40 from the second main surface (back side) of the SiC wafer 40 (corresponding to the surface of the SiC seed crystal layer 12 of the SiC wafer 10) with laser light (for example, a pulsed laser). As a result, a modified layer is formed in the peeling auxiliary layer 116, and starting from this modified layer, the SiC wafer 40 is split into a main wafer portion 111, which is the SiC wafer portion having the first main surface, and a remaining wafer portion 112, which is the SiC wafer portion having the second main surface.

[0037] In laser slicing, the peeling assist layer 116 within the SiC wafer 40 irradiated with laser light is a layer that is easier to peel off due to an incomplete SiC crystal structure compared to other parts, or for other reasons. By irradiating this peeling assist layer 116 with laser light to create a modified layer, and then dividing the SiC wafer 40 into the main wafer 111 and the remaining wafer 112 along the peeling assist layer 116, the division (peeling) can be performed more easily than when other parts are used as the modified layer. Possible reasons for this include, for example, the peeling assist layer 116 having an incomplete crystal structure compared to other parts and having weak interatomic bonding forces. It is also possible that the peeling assist layer 116 easily absorbs laser light, thus facilitating the formation of a modified layer. Various other factors may also be considered, but in any case, by peeling off the portion including the first main surface from the SiC wafer 40 starting from the peeling assist layer 116, the SiC wafer 40 can be divided into the main wafer 111 and the remaining wafer 112 with less force. This makes it possible to suppress the generation of distortion during peeling in the device formation portion of the main wafer 111, thereby preventing the occurrence of cracks and fractures.

[0038] The peeling aid layer 116 is formed within the SiC wafer 40 when the SiC wafer 40 is manufactured in a first entity different from the second entity. This method will be described later.

[0039] In addition, during the wafer splitting step, the SiC wafer 40 may be split into the main wafer 111 and the remaining wafer 112 by a method other than laser slicing. For example, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 by etching away the peeling auxiliary layer 116 on the SiC wafer 40. In this case, electrolytic etching, chemical etching, thermal etching, etc., can be used for etching. By performing the wafer splitting step by etching in this way, the SiC wafer 40 can be split into the main wafer 111 and the remaining wafer 112 without using a laser device. Furthermore, peeling can also be performed using ultrasound, known as sonic lift-off. Specifically, by splitting the SiC wafer 40 into the main wafer 111 and the remaining wafer 112 using sound waves, the peeled surfaces of the main wafer 111 and the remaining wafer 112 can be made flat and smooth, thus eliminating material waste and allowing the remaining wafer 112 to be reused, thereby reducing wafer manufacturing costs. In addition to the above, it is possible to divide the SiC wafer 40 into a main wafer 111 and a remaining wafer 112 by processing the peeling assist layer 116 formed in the SiC wafer 40 using any method.

[0040] In the first entity, the acquisition step, processing step, pre-processing step, growth step, and wafer provision step are performed (in this embodiment, an inspection step is also performed between the acquisition step and the processing step, as will be described later). The first entity is a company that provides a new service, that is, a company that acquires (recovers) the remaining wafer 112 of the SiC wafer 40 from the second entity, grows a grown SiC crystal on the remaining wafer 112 to regenerate the SiC wafer 40, and provides the regenerated SiC wafer 40 to the same or a different second entity. There is one or more second entities for each first entity. Note that the wafer splitting step described above may be performed in the first entity instead of the second entity.

[0041] In the acquisition step, the remaining wafer 112 is acquired from the second entity. In the processing step, the slice surface of the remaining wafer 112 is processed to acquire a seed crystal 113a made of SiC single crystal material.

[0042] In the pretreatment step, an inhibitory region is formed on or near the surface of the seed crystal 113a obtained in the processing step, or a seed crystal 113b made of newly prepared SiC single crystal material, which partially disrupts or inhibits the SiC crystal structure. This pretreatment is performed on the seed crystals 113a and 113b to form the aforementioned peeling auxiliary layer 116, and a pretreated seed crystal 114 is obtained. Details of the pretreatment step will be described later.

[0043] In the growth step, a new SiC wafer 40 is manufactured by growing a growth SiC crystal (an example of a semiconductor crystal layer) 115 on the surface of the seed crystal 114 obtained in the pretreatment step. Inside the SiC wafer 40 manufactured here, a peeling aid layer 116 is formed by the inhibition region formed on the seed crystal 114 in the pretreatment step.

[0044] In the wafer supply step, the SiC wafer 40 obtained in the growth step is provided to a second entity that is the same as or different from the source from which the remaining wafer 112 was obtained.

[0045] In conventional processes not to which this disclosure applies, the portion of the SiC wafer 40 corresponding to the remaining wafer 112 is ground without separating it from the main wafer 111, and the resulting grinding waste is discarded. In contrast, in this embodiment, the remaining wafer 112 is separated from the main wafer 111 and recovered without being discarded as grinding waste, and this is recycled into a new semiconductor wafer by the first entity and provided to the second entity. The second entity forms a device on the semiconductor wafer provided by the first entity (SiC wafer 40 recycled from the remaining wafer 112), and then separates it into the main wafer 111 and the remaining wafer 112. The remaining wafer 112 is recovered by the first entity and used as a seed crystal 114 to form a grown SiC crystal together with the peeling auxiliary layer 116, and is then used again as SiC wafer 40. By repeating this process, the portion of the SiC wafer 40 that was conventionally ground or discarded, namely the remaining wafer 112, can be reused. In this disclosure, the reuse of expensive SiC wafers is made possible, thereby reducing the manufacturing cost of devices. Furthermore, since waste can be significantly reduced throughout the entire SiC wafer manufacturing process, including high-temperature processes, it is also possible to reduce the environmental impact.

[0046] The processing step may be performed by the processing device 172, the pretreatment step may be performed by the pretreatment device 173, and the growth step may be performed by the growth device 174 (the inspection step described later may be performed by the inspection device 171).

[0047] Below, we will first describe the acquisition step, processing step, pretreatment step, growth step, and wafer supply step among the steps in the first entity, and then describe the inspection step.

[0048] <Acquisition Step> In the acquisition step, the remaining wafers 112 are acquired from one or more second entities. Any number of remaining wafers 112 may be sent to the first entity at any time the second entity has chosen, or an acquisition schedule, including the number of remaining wafers 112 to be acquired from each of the one or more second entities and the acquisition timing, may be shared between the second entity and the first entity, and the remaining wafers 112 may be acquired from the second entity according to the acquisition schedule. Note that if the wafer splitting step is performed by the first entity, the acquisition step is unnecessary.

[0049] <Processing Step> The processing in the processing step includes removing the slice surface (typically grinding and / or polishing) and removing the processed altered layer including the removed slice surface. The processing apparatus 172 may include, for example, an apparatus for grinding and / or polishing the slice surface (e.g., a grinder) and an apparatus for removing the processed altered layer, and these apparatuses may be a single apparatus (i.e., grinding and removal may be performed by one apparatus). For example, the processing apparatus 172 may be an apparatus for grinding and polishing such as the CMP (Chemical Mechanical Polishing) method.

[0050] In the processing step, a seed crystal 113a is obtained as a result of processing the remaining wafer 112. The seed crystal 113a may be composed mainly of the underlying SiC crystal, or it may be composed of the underlying SiC crystal and some oriented SiC crystal. Alternatively, instead of the seed crystal 113a, a new SiC single crystal material may be prepared and used as the seed crystal 113b.

[0051] <Pre-treatment step> In the pre-treatment apparatus 173, inhibition regions are formed on or near the surface of the seed crystals 113a and 113b, which partially disrupt or inhibit the formation of the crystal structure when growing the SiC crystal in the next growth step. Due to the presence of these inhibition regions, a peeling assist layer 116 that is easier to peel off than other parts is formed inside the SiC wafer 40 manufactured from the seed crystals 113a and 113b in the growth step. Specifically, for example, the pre-treatment apparatus 173 forms inhibition regions on the seed crystals 113a and 113b by performing one of the processing treatments described in Figure 3 below as a pre-treatment.

[0052] Figure 3 is an explanatory diagram of the pretreatment for forming a portion containing linear crystal defects (exfoliation aid layer 116). In Figure 3, (a) shows a schematic diagram of the seed crystal 113a before processing, (b) shows the processing of the seed crystal 113a in the pretreatment, and (c) shows a schematic diagram of the SiC wafer 40 manufactured using the pretreated seed crystal 114. In these figures, the upper row shows a perspective view, and the lower row shows a magnified cross-sectional view.

[0053] In the pretreatment step, ions 221 are injected into the seed crystal 113a from the surface, as shown in Figure 3(b). Specifically, ions 221 generated by an ion source are accelerated and injected from the outside toward the surface of the seed crystal 113a, thereby injecting and dispersing the ions 221 near the surface of the seed crystal 113a. This forms an ion-containing layer. Next, linear crystal defects are formed on the surface of the seed crystal 113a into which the ions 221 have been injected by applying ultrasonic vibrations. In the subsequent growth step, the seed crystal 113a with these linear crystal defects is used as the pretreated seed crystal 114, and SiC crystals are grown on its surface (for example, to a thickness of 50 μm or more) to form the grown SiC crystal 115. As a result, as shown in Figure 3(c), linear crystal defects are formed in places near the boundary between the seed crystal 114 and the grown SiC crystal 115, and the formation of the crystal structure is inhibited by these linear crystal defects, resulting in the formation of a peeling auxiliary layer 116 with an incomplete crystal structure. In this way, a SiC wafer 40 having a peeling assist layer 116 between the first main surface 40a on the front side (the side with the growing SiC crystal 115) and the second main surface 40b on the back side (the side with the seed crystal 114) is manufactured. In the subsequent wafer splitting step, if the peeling assist layer 116 in the SiC wafer 40 is removed by etching as described above, it is preferable to form the peeling assist layer 116 using the method described in Figure 3.

[0054] Furthermore, it is preferable to use one or more ions from among Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements as the ions 221 implanted into the seed crystal 113a in the pretreatment step. In this way, it is possible to form a peeling auxiliary layer 116 in the region containing the ions 221 while sufficiently growing the SiC crystal in the growth step.

[0055] In the pretreatment step, seed crystal 114 is obtained by performing one of the pretreatments described above on seed crystals 113a and 113b using the pretreatment apparatus 173. Although Figure 3 illustrates an example of performing pretreatment on seed crystal 113a obtained in the processing step, the same pretreatment can be performed on a newly prepared seed crystal 113b to obtain seed crystal 114.

[0056] <Growth Step> In the growth apparatus 174, a grown SiC crystal (oriented SiC crystal) 115 is grown on the seed crystal 114 to a thickness of 50 μm or more. Such crystal growth may be carried out by sublimation or CVD (Chemical Vapor Deposition), or by other methods. As a result, as explained in Figure 3, a new SiC wafer 40 is obtained, which consists of a seed crystal 114, which is a crystalline layer made of a single-crystal material of SiC, and a grown SiC crystal 115, which is a crystalline layer of SiC formed on the seed crystal 114, and has a peeling auxiliary layer 116 between the first main surface 40a on the grown SiC crystal 115 side and the second main surface 40b on the seed crystal 114 side. In this SiC wafer 40, the portion where linear crystal defects exist, formed near the interface between the seed crystal 114 and the grown SiC crystal 115, contains an incomplete crystalline structure originating from ions 221.

[0057] Preferably, the peeling assist layer 116 is formed within a range of 10 μm or less in the thickness direction (up and down direction in Figure 3) perpendicular to the first main surface 40a and the second main surface 40b. Specifically, when observing a cross-section of the SiC wafer 40 in the thickness direction at any position including the peeling assist layer 116, it is preferable that the thickness of the peeling assist layer 116 in that cross-section is 10 μm or less. In this way, the thickness of the peeling assist layer 116 can be made thinner than the height of the unevenness of the slice surface that occurs when a conventional SiC wafer without a peeling assist layer 116 is divided by laser slicing (generally about 20 to 50 μm), thereby reducing the amount of grinding debris generated in the processing step and reducing the amount of SiC waste. As shown in Figure 3, the peeling assist layer 116 is a part of the seed crystal 114 or the grown SiC crystal 115.

[0058] Furthermore, it is preferable that in the peeling assist layer 116, the portions containing linear crystal defects are distributed at intervals of 200 μm or less and over a range of at least 500 μm in the planar direction parallel to the first main surface 40a and the second main surface 40b. In this way, when the first entity divides the SiC wafer 40 into the main wafer 111 and the remaining wafer 112 in the wafer splitting step, it is possible to form a peeling assist layer 116 that can be easily peeled off with little force.

[0059] Figures 4A to 4C show examples of cross-sections when the SiC wafer 40 shown in Figure 3(c) is cut along a plane parallel to the first main surface 40a and passing through at least a portion of the peeling assist layer 116. Figure 4A shows an example of a cross-section when the peeling assist layer 116 is formed over the entire surface in the planar direction at a predetermined depth within the SiC wafer 40. Figure 4B shows an example of a cross-section when the peeling assist layer 116 is formed over the entire circumference of the region near the outer periphery within the SiC wafer 40. Figure 4C shows an example of a cross-section when the peeling assist layer 116 is partially formed in the region near the outer periphery within the SiC wafer 40. Note that the peeling assist layer 116 may be formed in arrangements other than those shown.

[0060] As shown in the examples above, the peeling assist layer 116 may be formed over the entire surface in the planar direction when the SiC wafer 40 is viewed from the direction of the first main surface 40a, or it may be formed only in a part of the surface. As long as the peeling assist layer 116 is distributed over a certain range in the planar direction, for example, a range of 500 μm or more, the peeling assist layer 116 can be formed in any region within the SiC wafer 40.

[0061] <Wafer Provision Step> A new SiC wafer 40, composed of a seed crystal 114 and a grown SiC crystal 115, is provided to a second entity that is the same as or different from the source from which the remaining wafer that forms the basis of the SiC wafer was obtained. In this way, the acquired remaining wafer 112 is regenerated into such a new SiC wafer 40 and provided to the second entity, so the second entity can obtain a main wafer from that SiC wafer 40.

[0062] The above describes the acquisition step, processing step, pretreatment step, growth step, and wafer supply step.

[0063] In this embodiment, an inspection step is included between the acquisition step and the processing step to inspect the slice surface of the acquired remaining wafer 112. The inspection step is, for example, as follows:

[0064] <Inspection Step> The inspection step includes measuring at least one of the following: the height difference of the slice surface and the thickness of the processed altered layer having the slice surface. In this embodiment, both are measured. The height difference of the slice surface is the height difference caused by the surface irregularities resulting from the laser irradiation or the separation of the main wafer 111 and the remaining wafer 112 in the wafer splitting step.

[0065] The inspection step is performed by the inspection device 171. The inspection device 171 may include a laser microscope and a Raman spectrometer. The height difference of the slice surface may be measured using the laser microscope. The thickness of the processed altered layer may be measured using the Raman spectrometer. The measurement methods for both the height difference of the slice surface and the thickness of the processed altered layer are not limited to this example. For example, the height difference of the slice surface may be measured using a white light interferometer or a contact-type shape measuring instrument.

[0066] [Second Embodiment] The second embodiment will now be described. In this description, the differences from the first embodiment will be explained, and the similarities with the first embodiment will be omitted or simplified.

[0067] In the second embodiment, crystal growth in the growth step is carried out using the method disclosed in the prior application Patent Document 3 (WO2023 / 067736A1) by the same applicant as the present application (hereinafter, this method will be conveniently referred to as the "NGK method" based on the applicant's notation). That is, in the growth step, a SiC single crystal as a seed crystal and a SiC powder layer are placed in a container in contact with each other, and the container is placed in a firing furnace and heat treatment is performed, thereby growing a SiC single crystal on the seed crystal. According to the NGK method, it is possible to obtain a SiC single crystal (grown SiC crystal) with a lower BPD density than the sublimation method and a BPD density of about the same as the CVD method. The second embodiment can utilize all or part of the technology disclosed in Patent Document 3.

[0068] Furthermore, when crystal growth is performed using the NGK method, the flatness of the processed surface does not need to be as high as when crystal growth is performed using the sublimation or CVD methods, and the processed surface does not need to be perfectly flat. Specifically, for example, the following applies:

[0069] When homoepitaxial growth is performed on a seed crystal using sublimation or CVD, it is usually essential that the growth surface is atomically flat and that there is no processed or altered layer. This is because irregularities can form on the epitaxial growth surface, or defects such as dislocations can be introduced into the crystal.

[0070] On the other hand, because SiC wafers are hard and stable against heat and chemicals, surface planarization and removal of processing damage using the CMP method after slicing or grinding is extremely time-consuming, and the consumption of polishing slurry and polishing pads is also high.

[0071] Therefore, in this embodiment, in the processing step, the removal of the processed altered layer is performed by a thermal etching process, a surface oxidation process, or a plasma etching process (i.e., any process that results in a lower degree of flatness after etching than etching by the CMP method). Below, examples of each process for removing the processed altered layer in the processing step of the second embodiment will be described. In this embodiment, etching other than the thermal etching process, surface oxidation process, and plasma etching process, such as etching by the CMP method, or etching by other etching processes (e.g., hydrogen etching) may be performed.

[0072] Figure 5 schematically illustrates the thermal etching process.

[0073] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a thermal etching process. This apparatus is illustrated in Figure 5. In the thermal etching process, the surface of the remaining wafer (including the processed altered layer) that has been heated and processed in the electric furnace 302 is sublimated to a thickness of several micrometers.

[0074] For example, gas (such as nitrogen or argon, an inert gas) is introduced into an electric furnace 302, which is made of insulating material and equipped with a heater 301, through a gas pipe 305, creating an inert gas atmosphere inside the electric furnace 302. The electric furnace 302 may also be under vacuum.

[0075] The material is heated by heater 301, but the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 1000 to 2000°C), and may be set taking into account the required amount of etching (for example, 1800°C may be set). The holding time at the maximum temperature is a time within a certain time range (for example, 1 minute to 5 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0076] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 303 (for example, graphite) on a spacer 304 (for example, graphite), or it may be placed using a sheath or the like made of a heat-resistant material.

[0077] If the surface of the remaining wafer 112 is carbonized after this thermal etching process, the carbonized layer on the surface may be removed by annealing in an atmospheric furnace or the like, or by polishing or other processing. To prevent surface carbonization, a carbon getter material such as Ta may be placed inside the electric furnace 302.

[0078] Figure 6 schematically illustrates the surface oxidation process.

[0079] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a surface oxidation process. This apparatus is illustrated in Figure 6. In the surface oxidation process, the surface of the remaining wafer (including the processed altered layer) that has been heated in an oxidizing atmosphere (including an air atmosphere) in an electric furnace 402 is oxidized to a thickness of several micrometers. The oxide film may be removed by processing such as polishing, or it may be volatilized or melted (reacted with the raw material powder) during crystal growth.

[0080] For example, in an electric furnace 402 made of insulating material and equipped with a heater 401, the maximum heat treatment temperature is a temperature within a certain temperature range (for example, 800 to 2000°C), and may be set taking into account the required amount of etching (for example, 1400°C may be set). Also, the holding time at the maximum temperature is a time within a certain time range (for example, 5 minutes to 50 hours), and may be set taking into account the required amount of etching (for example, 1 hour may be set). The "required amount of etching," "maximum heat treatment temperature," and "holding time at the maximum temperature" may each be examples of at least one element of the amount of material removed, and may be determined based on the measured thickness of the processed altered layer.

[0081] The remaining wafer 112 (for example, the remaining wafer 112 whose surface has been ground) may be placed on a setter 403 (for example, alumina) on a spacer 404 (for example, alumina).

[0082] Figure 7 schematically illustrates the plasma etching process.

[0083] The processing apparatus 172 may include an apparatus for removing the processed altered layer by a plasma etching process. This apparatus is illustrated in Figure 7. In the plasma etching process, the surface of the remaining processed wafer (including the processed altered layer) is etched to a thickness of several micrometers.

[0084] Plasma etching includes methods such as RIE (Reactive Ion Etching), ECR (Electron Cyclotron Resonance), ICP (Inductively Coupled Plasma), and CCP (Capacitively Coupled Plasma), but there are no particular limitations; for example, RIE can be applied.

[0085] The substrate temperature, gas type, processing time, and apparatus configuration may be set as appropriate depending on the desired etching rate and surface condition. The remaining wafer surface may be pre-treated by ashing or other methods to remove any surface deposits.

[0086] An upper electrode 501 and a lower electrode 503 are located in the chamber 502. Gas is introduced from the gas introduction pipe 505 and exhausted from the gas exhaust pipe 504, and plasma is generated between electrodes 501 and 503 by the high-frequency power supply 509s.

[0087] The above is an explanation of examples of each process related to the removal of the processed altered layer in the processing step according to the second embodiment. Furthermore, there are differences between the sublimation method, CVD method and the NGK method regarding crystal growth, for example, as follows.

[0088] In other words, while sublimation and CVD methods require precise cleaning after CMP polishing and before epitaxial layer formation, the NGK method does not require such cleaning.

[0089] Furthermore, in sublimation and CVD methods, the rapid heating rate increases the likelihood of seed crystal warping and subsequent breakage. Also, in sublimation and CVD methods, multiple seed crystals can be placed in the growth chamber, but if even one seed crystal is damaged, it will affect the others. On the other hand, in the NGK method, the heating rate is slower than in sublimation and CVD methods, so even if the seed crystal is slightly warped, the likelihood of breakage due to that warping is low. In addition, in the NGK method, one seed crystal is stored in each container, so even if one seed crystal is damaged, it will not affect the others.

[0090] Furthermore, in both the second and first embodiments, the diameter of the remaining wafer 112 acquired in the acquisition step may be 6 inches or more, and for example, the diameter of the remaining wafer may be 8 inches or more (for example, in the second embodiment). For example, in both cases where the diameter is 6 inches or 8 inches, the thickness of the main wafer 111 may be about 100 μm, but in the case of a 6-inch diameter, the thickness of the remaining wafer 112 may be about 250 μm, and in the case of an 8-inch diameter, the thickness of the remaining wafer 112 may be about 400 μm.

[0091] The present invention will be further described in detail by the following examples. However, the present invention is not limited to the following examples.

[0092] Example 1 (1) Pretreatment As shown in Figure 3(a), a commercially available disc-shaped SiC single crystal substrate (4H-SiC, diameter 150 mm (6 inches), off-angle 4°, thickness 0.35 mm) was prepared as the seed crystal 113a. As shown in Figure 3(b), hydrogen ions were first implanted as ions 221 into the SiC single crystal substrate in order to form a portion containing linear crystal defects (exfoliation aid layer 116). The hydrogen ion implantation conditions at this time were an acceleration voltage of 170 keV and an implantation dose of 8 × 10⁻⁶ １５ ions / cm ２ The temperature was 500°C. Subsequently, a SiC single crystal substrate was placed in a container filled with pure water, and linear crystal defects were formed by applying ultrasonic vibrations at a frequency of 48 kHz.

[0093] (2) Preparation of SiC mixed powder Commercially available β-SiC powder (volume-based D50 particle size: 65.0 μm) and an oxide (SiO₂) which is a liquid phase formation aid ２The oxides (D50 particle size based on volume: 0.5 μm) were weighed so that the oxide content relative to the SiC powder content was 8.1% by weight, and then placed in a polypropylene container along with pebbles and water. After placing the polypropylene container on a pot stand, the container was rotated at a speed of 50 rpm to mix the raw materials. The slurry obtained by mixing the raw materials was dried in a dryer and collected to obtain SiC mixed powder.

[0094] (3) Arrangement of SiC mixed powder and seed crystal The SiC single crystal substrate, which serves as the seed crystal 113a pretreated in (1) above, and the SiC mixed powder prepared in (2) above were placed in a graphite container.

[0095] (4) Heat treatment The graphite container prepared in (3) above was placed in a resistance furnace (sintering furnace) in a location where the temperature range was within ±75°C of the set temperature, and heat treatment was performed for 20 hours at a set temperature of 2450°C in a mixed gas atmosphere of argon and nitrogen (partial pressure of nitrogen gas of 0.0025 atm). As a result, as shown in Figure 1 (see also Figure 3(c)), a SiC single crystal was grown on a SiC single crystal substrate, and a SiC growth layer 14 was provided on the SiC seed crystal layer 12, and a SiC wafer 10 was obtained in which linear crystal defects exist near the interface between the SiC seed crystal layer 12 and the SiC growth layer 14. It should be noted that the parts in which linear crystal defects exist are parts originating from the ion-containing layer.

[0096] (5) Measurement of the crystal growth thickness of the SiC wafer The thickness of 25 arbitrary locations on the SiC wafer 10 obtained in (4) above was measured with a micrometer, and the arithmetic mean was calculated. The thickness of the seed crystal 113a was also calculated at the time of (3) above using the same method. Then, the crystal growth thickness (μm) of the SiC growth layer 14 was calculated by subtracting the arithmetic mean of the thickness of the seed crystal 113a from the arithmetic mean of the thickness of the SiC wafer 10. As a result, it was confirmed that the crystal growth thickness of the SiC growth layer 14 was 100 μm or more.

[0097] (6) Polishing The surface (Si surface and C surface) of the SiC wafer 10 obtained in (4) above was polished using diamond abrasive grains, and then chemical mechanical polishing (CMP) was performed.

[0098] (7) Device fabrication process A SiC-MOSFET device was formed on the SiC growth layer 14 of the polished SiC wafer 10 obtained in (6) above.

[0099] (8) Confirmation of linear crystal defects A 5 mm wide x 5 mm long SiC wafer piece was cut from the center of the SiC wafer 10 obtained in (7) above after device formation. The cross-section of the cut SiC wafer piece in the thickness direction was fractured so that cleavage occurred on the (-1100) plane. The (-1100) plane of the SiC wafer piece exposed by the fracture was observed using a plasma focused ion beam scanning electron microscope (Thermo Fisher, manufactured by Sientific, Helios5 Hydra) at an acceleration voltage of 5.00 kV, and the distance d from the surface of the SiC seed crystal layer 12 (second main surface 40b) to the interface between the SiC growth layer 14 and the SiC seed crystal layer 12 was determined. １ The (μm) was measured. Using a focused ion beam device attached to a plasma focused ion beam scanning electron microscope, the distance d in the thickness direction from the second main surface 40b was measured at an arbitrary location on the (-1100) plane of a SiC wafer piece. １ Taking a point separated by (μm) (i.e., the position of the interface) as the origin, and taking a z-coordinate with the direction toward the surface on the SiC growth layer 14 side (first main surface 40a) from the second main surface 40b as positive, a thin section of the SiC wafer was cut out (cut) in a cross-sectional area of ​​approximately 12 μm horizontally × approximately 12 μm vertically, including the region -5 μm ≤ z ≤ 5 μm, to prepare a thin section sample for transmission electron microscope observation. Here, during the preparation of the thin section sample, the distance d from the second main surface 40b at the edge of the thin section sample １ A focused ion beam was used to mark a point a certain distance away. The exposed (-1100) plane of this thin section was observed using a transmission electron microscope (JEOL Ltd., JEM-F200) at an acceleration voltage of 200 kV. At this time, the observation range was defined as the region -2 μm ≤ z ≤ 2 μm in the z-coordinate. Within this observation range, linear crystal defects with a length of 0.10 μm or more were identified, and the average length L of these linear crystal defects was determined. １ The (μm) value was calculated. The results are shown in Table 1B.

[0100] (9) Peeling off the SiC seed crystal layer A pulsed laser with a wavelength of 1064 nm was irradiated as incident light from the SiC seed crystal layer 12 side of the SiC wafer 10 obtained in (7) above, near the interface between the SiC growth layer 14 and the SiC seed crystal layer 12. By scanning this pulsed laser light in the in-plane direction of the SiC wafer 10, the SiC seed crystal layer 12 was peeled off from the SiC wafer 10 along the vicinity of the interface. The laser irradiation conditions at this time were an irradiation fluence of 100 J / cm ２ The pulse width was set to 10 ns, and the laser focusing position was set to a depth of 200 μm in the thickness direction from the surface of the SiC wafer 10 on the SiC seed crystal layer 12 side. As a result, the SiC wafer 10 on which the SiC-MOSFET device was formed was divided into a main wafer 111 (SiC growth layer 14 on which the device was formed) and a remaining wafer 112 (SiC seed crystal layer 12).

[0101] (10) Evaluation of flatness after peeling The peeled surface of the remaining wafer 112 (SiC seed crystal layer 12) obtained in (9) above was observed with a laser microscope (manufactured by Keyence Corporation, model number: VK-X-1000) in accordance with ISO 25178, and the maximum height Sz and arithmetic mean height Sa were measured. The measurement location was near the center of the peeled surface of the wafer, and the measurement range was a region of 2 mm × 0.5 mm. The values ​​of the maximum height Sz and arithmetic mean height Sa near the center of the peeled surface of the wafer can be considered representative values ​​(surface roughness) of the entire peeled surface of the wafer. If the maximum height Sz of the wafer for which surface roughness was measured is 25.0 μm or less and the arithmetic mean height Sa is 3.0 μm or less, it can be said that the flatness of the peeled surface of the wafer has improved. The results are shown in Table 1B.

[0102] (11) Analysis of impurity concentration In the SiC wafer 10 on which the SiC-MOSFET device obtained in (7) above is formed, the layer of the SiC-MOSFET device is removed from the surface on the SiC growth layer 14 side (first main surface 40a), and the first main surface 40a is polished to a predetermined thickness, thereby determining the nitrogen atom concentration (atoms / cm³) at a depth position corresponding to that thickness. ３ ) and rare earth element concentration (atoms / cm ３The following measurements were taken. These measurements were performed at depths of 5 μm, 10 μm, 25 μm, and 55 μm in the thickness direction from the first main surface 40a after the device layer removal, thereby confirming the nitrogen atom concentration and rare earth element concentration at each depth in the SiC growth layer 14. Dynamic secondary ion mass spectrometry (D-SIMS) was used for the concentration measurements. For the rare earth element concentration, the IMS-7f manufactured by CAMECA was used as the analyzer, and the primary ion species O ２ ＋ The tests were conducted under the conditions of an acceleration voltage of 11.0 kV. For nitrogen atom concentration, a CAMECA IMS-7f was used as the analyzer, and the primary ion species Cs was measured. ＋ The experiment was conducted under the conditions of an acceleration voltage of 15.0 kV. The results are shown in Table 1A.

[0103] Examples 2-6 In the above (1), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that the frequency of ultrasonic vibration was changed as shown in Table 1B. The results are shown in Tables 1A and 1B.

[0104] In Example 7, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 1, except that i) the frequency of ultrasonic vibration was changed to 50 kHz in (1) above, and ii) the partial pressure of nitrogen gas was changed to 0.0000003 atm in (4) above. The results are shown in Tables 1A and 1B.

[0105] Examples 8 and 9 i) In (1) above, the frequency of ultrasonic vibration was changed to 50 kHz, ii) In (2) above, the oxide (Y) which is the liquid phase generation aid ２ O ３ Except for weighing the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 6.4% by weight (Example 8) or 0.3% by weight (Example 9), SiC wafers 10 and other materials were prepared and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 1A and 1B.

[0106] Example 10 In (2) above, the oxide (CeO) is a liquid phase formation aid. ２Except for weighing out the (volume-based D50 particle size: 5.0 μm) so that the oxide content relative to the SiC powder content was 10.2% by weight, SiC wafers 10 and other components were prepared and various evaluations were performed in the same manner as in Example 8. The results are shown in Tables 1A and 1B.

[0107] In Example 11, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 8, except that, in (4) above, the heat treatment was carried out in an argon gas atmosphere without introducing nitrogen gas until 12 hours had elapsed after the set temperature in the resistance furnace was maintained at 2450°C, and thereafter the nitrogen gas flow rate was adjusted so that the partial pressure of nitrogen gas in the furnace was calculated to be 0.0025 atm, and the heat treatment was carried out at the set temperature of 2450°C for 8 hours. The results are shown in Tables 1A and 1B.

[0108] Example 12 In Example 12, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 8, except that, in (4) above, the heat treatment was carried out in an argon gas atmosphere without introducing nitrogen gas until 9 hours had elapsed after the set temperature in the resistance furnace was maintained at 2450°C, and thereafter the nitrogen gas flow rate was adjusted so that the partial pressure of nitrogen gas in the furnace was calculated to be 0.0025 atm, and the heat treatment was carried out at the set temperature of 2450°C for 11 hours. The results are shown in Tables 1A and 1B.

[0109] Examples 13-15 In the above (1), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 8, except that the frequency of ultrasonic vibration was changed as shown in Table 1B. The results are shown in Tables 1A and 1B.

[0110] Example 16 In Example 16, the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 13, except that a commercially available disc-shaped SiC single crystal substrate (4H-SiC, 200 mm diameter (8 inches), off-angle 4°, thickness 0.35 mm) was used as the seed crystal 113a in (1) above. The results are shown in Tables 1A and 1B.

[0111] Examples 17-22 In the above (1), the SiC wafer 10 and other components were fabricated and various evaluations were performed in the same manner as in Example 8, except that the ion implantation conditions (ion species and implantation dose) were changed as shown in Table 1B. The results are shown in Tables 1A and 1B.

[0112] Example 23 (Comparison) Except for i) not performing the pretreatment described in (1) above (i.e., not forming linear crystal defects of 0.10 μm or more) and ii) performing the heat treatment in an argon gas atmosphere without introducing nitrogen gas in (4) above, the SiC wafer 10 and other materials were fabricated and various evaluations were performed in the same manner as in Example 1. The results are shown in Tables 1A and 1B.

[0113]

[0114]

[0115] 10, 40 SiC wafer 12 SiC seed crystal layer 14 SiC growth layer 111 Main wafer 112 Remaining wafer 113a, 113b Seed crystal 114 Pre-treated seed crystal 115 Grown SiC crystal 116 Peeling aid layer 171 Inspection device 172 Processing device 173 Pre-treatment device 174 Growth device I Ion

Claims

1. A SiC wafer comprising: a first crystal layer containing a SiC single crystal; and a second crystal layer formed on the first crystal layer containing a SiC single crystal, wherein linear crystal defects exist near the interface between the first and second crystal layers, and the second crystal layer has a density of 1.00 × 10⁻¹⁶. １８ atoms / cm ３ A SiC wafer having a portion containing nitrogen atoms at the above concentration.

2. The SiC wafer according to claim 1, wherein the first crystal layer is a SiC seed crystal layer, and the second crystal layer is a SiC growth layer containing the SiC single crystal grown from the SiC seed crystal layer.

3. The SiC wafer according to claim 1 or 2, wherein the average length of the crystal defects is 0.30 to 5.00 μm.

4. The second crystal layer has a thickness of 25 μm or more, and the nitrogen atom concentration of the second crystal layer at a depth of 25 μm in the thickness direction of the SiC wafer from the surface of the SiC wafer on the second crystal layer side is 1.00 × 10 １８ atoms / cm ３ The SiC wafer according to claim 1 or 2.

5. The second crystal layer has a thickness of 55 μm or more, and the nitrogen atom concentration of the second crystal layer at a depth of 55 μm in the thickness direction of the SiC wafer from the surface of the SiC wafer on the second crystal layer side is 1.00 × 10 １８ atoms / cm ３ The SiC wafer according to claim 1 or 2.

6. The second crystal layer is 5.00 × 10 １３ atoms / cm ３ A SiC wafer according to claim 1 or 2, having a portion containing rare earth elements at the above concentration.

7. The SiC wafer according to claim 1 or 2, wherein an ion-containing layer containing ions is formed near the interface between the first crystal layer and the second crystal layer.

8. The SiC wafer according to claim 7, wherein the ion is at least one selected from the group consisting of Si, C, Al, B, P, N, O, H, noble gas elements, and rare earth elements.

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