Multilayer substrate module and method for manufacturing same

Abstract

[Problem] To provide a multilayer substrate module in which transmission loss and radiation noise are reduced and a method for manufacturing the same. [Solution] A multilayer substrate module 1 comprises: a build-up layer 20 obtained by alternately layering a plurality of wiring layers 21 and a plurality of insulating layers 22; and a first through via conductor 26 formed in the build-up layer 20. The first through via conductor 26 includes a straight portion 26a having a constant diameter from an upper end to a lower end with no land present therealong, and a tapered portion 26b connected to the lower end of the straight portion 26a and having a diameter that decreases downward. The straight portion 26a is longer than the tapered portion 26b.

Description

Multilayer Substrate Module and Method for Manufacturing the Same

[0001] The present disclosure relates to a multilayer substrate module and a method for manufacturing the same, and particularly relates to a multilayer substrate module suitable for embedding a semiconductor IC chip and a method for manufacturing the same.

[0002] Multilayer substrates are widely used as interposer substrates for semiconductor IC chips. For example, Patent Document 1 describes a wiring substrate in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated, and upper and lower wiring layers are connected to each other via via conductors. A semiconductor IC chip mounted on the upper surface of the wiring substrate is connected to each wiring layer via a stacked via conductor in which via conductors are stacked in multiple stages.

[0003] Japanese Unexamined Patent Application Publication No. 2024-11472

[0004] However, when a stacked via conductor is used for a signal transmission line that electrically connects an antenna pattern provided on a multilayer substrate and a semiconductor IC chip, there is a problem that transmission loss and radiation noise increase.

[0005] Accordingly, an object of the present disclosure is to provide a multilayer substrate module with reduced transmission loss and radiation noise and a method for manufacturing the same.

[0006] In order to solve the above problem, a multilayer substrate module according to the present disclosure includes: a build-up layer in which a plurality of wiring layers and a plurality of insulating layers are alternately laminated; and a first through-via conductor formed in the build-up layer, wherein the first through-via conductor has a constant diameter from an upper end to a lower end, includes a straight portion having no land in the middle, and a tapered portion connected to a lower end of the straight portion and having a diameter decreasing downward, and the straight portion is longer than the tapered portion.

[0007] Furthermore, the manufacturing method of a multilayer substrate module according to this disclosure is characterized by comprising the steps of: forming a build-up layer by alternately stacking a plurality of wiring layers and a plurality of insulating layers; forming straight holes having a certain diameter in the build-up layer by drilling; forming tapered holes below the straight holes by laser processing to excavate the bottom of the straight holes; and forming through-via conductors by embedding a conductive material inside the through-holes consisting of the straight holes and the tapered holes.

[0008] Thus, according to this disclosure, it is possible to provide a multilayer substrate module with reduced transmission loss and radiated noise, and a method for manufacturing the same.

[0009] Figure 1 is a schematic cross-sectional view showing the structure of a multilayer substrate module according to an embodiment of the present disclosure. Figure 2 is a schematic cross-sectional view showing the structure of a through-via conductor in comparison with a stacked via conductor. Figure 3 is a schematic diagram showing the manufacturing process of a multilayer substrate module. Figure 4 is a schematic diagram showing the manufacturing process of a multilayer substrate module. Figure 5 is a schematic diagram showing the manufacturing process of a multilayer substrate module. Figure 6 is a schematic diagram showing the manufacturing process of a multilayer substrate module. Figure 7 is a schematic diagram showing the manufacturing process of a multilayer substrate module. Figure 8 is a schematic diagram showing the manufacturing process of a multilayer substrate module. Figure 9 is a schematic diagram showing the manufacturing process of a multilayer substrate module. Figure 10 is a schematic diagram showing the manufacturing process of a multilayer substrate module. Figure 11 is a schematic diagram showing the manufacturing process of a multilayer substrate module. Figures 12(a) to (c) are cross-sectional views showing variations in the shape of a through-via conductor and methods for forming them. Figures 13(a) and (b) are cross-sectional views showing variations in the shape of a through-via conductor and methods for forming them. Figures 14(a) and (b) are cross-sectional views showing variations in the shape of a through-via conductor and methods for forming them. Figure 15 is a schematic cross-sectional view showing the structure of a multilayer substrate module according to a second embodiment of the present disclosure. Figure 16 is a schematic cross-sectional view showing the structure of a multilayer substrate module according to a third embodiment of the present disclosure. Figure 17 is a schematic cross-sectional view showing the structure of a multilayer substrate module according to a fourth embodiment of the present disclosure. Figure 18 is a schematic cross-sectional view showing the structure of a multilayer substrate module according to a fifth embodiment of the present disclosure. Figure 19 is a schematic cross-sectional view showing the structure of a multilayer substrate module according to a sixth embodiment of the present disclosure. Figure 20 is a schematic cross-sectional view showing the structure of a multilayer substrate module according to a seventh embodiment of the present disclosure.

[0010] Preferred embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0011] Figure 1 is a substantially cross-sectional view showing the structure of a multilayer substrate module according to the first embodiment of the present disclosure.

[0012] As shown in Figure 1, this multilayer substrate module 1 comprises a semiconductor IC embedded substrate 10 (SESUB), a multilayer build-up layer 20 stacked on the upper surface of the semiconductor IC embedded substrate 10, a protective layer 30A covering the upper surface of the build-up layer 20, and a protective layer 30B covering the lower surface of the semiconductor IC embedded substrate 10.

[0013] The semiconductor IC embedded substrate 10 comprises a core substrate 11 and an embedded resin layer 12 formed on the upper surface of the core substrate 11, with a semiconductor IC chip 40 embedded within the embedded resin layer 12.

[0014] The core substrate 11 comprises an insulating substrate 11a such as a glass epoxy substrate, a first core wiring layer 11b formed on the upper surface of the insulating substrate 11a, a second core wiring layer 11c formed on the lower surface of the insulating substrate 11a, and a via conductor 13 that penetrates the insulating substrate 11a and connects the second core wiring layer 11c and the first core wiring layer 11b. The lower surface of the second core wiring layer 11c is covered with a protective layer 30B, and bump electrodes 33 such as solder bumps are provided on the lower surface of the protective layer 30B. The bump electrodes 33 penetrate the protective layer 30B and are connected to the circuit pattern of the second core wiring layer 11c.

[0015] The embedded resin layer 12 comprises a base resin layer 12a and an upper resin layer 12b formed on the upper surface of the base resin layer 12a. The semiconductor IC chip 40 is placed on the upper surface of the base resin layer 12a with its pad-forming surface facing upward and is covered by the upper resin layer 12b. A first wiring layer 21-1, which is the lowest wiring layer of the build-up layer 20, is formed on the upper surface of the upper resin layer 12b.

[0016] Via conductors 42a and 42b are provided on the surface of the embedded resin layer 12. The upper ends of the via conductors 42a and 42b are connected to the circuit pattern of the first wiring layer 21-1, and the lower ends of the via conductors 42a and 42b are connected to the pads 41a and 41b of the semiconductor IC chip 40, respectively. As will be described in detail later, via conductor 42a is part of the stacked via conductor 24S.

[0017] The embedded resin layer 12 is provided with a through-via conductor 16 (second through-via conductor) that penetrates its upper and lower surfaces. As will be described in detail later, the through-via conductor 16 in this embodiment is a so-called pencil-shaped interlayer connection conductor, having a straight portion 16a with a constant diameter and a tapered portion 16b provided at the lower end of the straight portion 16a, with the diameter decreasing downwards. The upper end (base end) of the through-via conductor 16 is connected to the circuit pattern of the first wiring layer 21-1, and the lower end (tip) of the through-via conductor 16 is connected to the circuit pattern of the first core wiring layer 11b.

[0018] The build-up layer 20 has a multilayer structure in which a plurality of wiring layers 21 and a plurality of insulating layers 22 are alternately stacked. More specifically, it has first to sixth wiring layers 21-1 to 21-6 and first to fifth insulating layers 22-1 to 22-5 provided between the first to sixth wiring layers 21-1 to 21-6, respectively. The second to sixth wiring layers 21-2 to 21-6 are formed on the upper surfaces of the first to fifth insulating layers 22-1 to 22-5, respectively, and the first wiring layer 21-1 is formed on the upper surface of the embedded resin layer 12. Preferably, the first to fifth insulating layers 22-1 to 22-5 are made of an insulating substrate in which glass cloth is impregnated with a thermosetting resin. Each of the first to sixth wiring layers 21-1 to 21-6 has a circuit pattern, and in particular the uppermost sixth wiring layer 21-6 includes an antenna pattern 21a that functions as an antenna. Thus, the build-up layer 20 in this embodiment is an antenna substrate mounted on a semiconductor IC-embedded substrate 10.

[0019] Via conductors 24 are formed at appropriate locations in the first to fifth insulating layers 22-1 to 22-5 that constitute the build-up layer 20. The via conductors 24 may be single-layer via conductors that are not continuous in the stacking direction, or they may be stacked via conductors consisting of multiple via conductors that are continuous in the stacking direction. The stacked via conductor 24S in the figure is a full-stack via conductor formed to penetrate the first to fifth insulating layers 22-1 to 22-5. The lower end of the stacked via conductor 24S is connected to the pad 41a of the semiconductor IC chip 40 via a via conductor 42a.

[0020] Furthermore, a through-via conductor 26 (first through-via conductor) is formed in the build-up layer 20, penetrating the first to fifth insulating layers 22-1 to 22-5. The upper end (base end) of the through-via conductor 26 is connected to the antenna pattern 21a provided on the sixth wiring layer 21-6, and the lower end (tip) of the through-via conductor 26 penetrates the surface layer of the embedded resin layer 12 and is connected to the pad 41c of the semiconductor IC chip 40.

[0021] Figure 2 is a schematic cross-sectional view showing the structure of the through-via conductor 26 in comparison with that of a stacked via conductor.

[0022] As shown in Figure 2, the through-via conductor 26 according to this embodiment is a so-called pencil-shaped interlayer connection conductor, having a straight portion 26a with a constant diameter (width) and a tapered portion 26b provided at the lower end of the straight portion 26a, the tapered portion having a smaller diameter towards the bottom. The diameter of the lower end of the tapered portion 26b is smaller than the diameter of the straight portion 26a.

[0023] As will be described in detail later, the straight portion 26a of the through-via conductor 26 is formed by drilling, and the tapered portion 26b is formed by laser processing. The through-via conductor 26 is composed of a metal film 28 such as Cu that covers the inner surface of the through-hole, and a filler material 29 that fills the hollow portion inside the metal film 28. The filler material 29 may be a conductive resin, or it may be the same metal material as the metal film 28. The filler material 29 may also be an insulating material such as a prepreg or solder resist.

[0024] Depending on the thickness (number of layers) of the build-up layer 20, the through-via conductor 26 consists mostly of a straight section 26a, with the tapered section 26b being only a small part of the lower end of the through-via conductor 26. The straight section 26a is longer than the tapered section 26b, and it is preferable that the length La of the straight section 26a is at least twice the length Lb of the tapered section 26b. Furthermore, it is preferable that the length Lb (height) of the tapered section 26b is between 0.01 mm and 10 mm.

[0025] The through-via conductor 26 in this embodiment is a bottomed via conductor whose lower end (tip) of the tapered portion 26b is terminated on a conductor surface such as a pad 41c. However, there are no lands between the upper and lower ends of the straight portion 26a, and the outer circumferential surface of the through-via conductor 26 is formed straight in the vertical direction.

[0026] As shown in Figure 2, in a stacked via conductor 24S in which multiple via conductors 24 are stacked in a continuous manner, there are several lands 21b along the extension direction from the top end to the bottom end, and because the diameter variation in the vertical direction is large, the current I flowing through the surface of the stacked via conductor 24S ２ The path of the current travels meanders vertically due to the skin effect. In contrast, the through-via conductor 26 in this embodiment has no lands in the middle of its extension direction, and its diameter is almost constant from the upper end to the lower end, so the current I flowing through the surface of the through-via conductor 26 １ The path travels straight in the vertical direction. Therefore, it has low transmission loss and radiation noise, making it suitable as an interlayer connecting conductor for connecting the antenna pattern 21a and the pad 41c of the semiconductor IC chip 40.

[0027] Furthermore, as the semiconductor IC chip 40 is miniaturized, the area of ​​the pad 41c is also small, making it difficult to connect the straight portion 26a of the through-via conductor 26 directly to the pad 41c. However, since a tapered portion 26b is formed at the lower end of the through-via conductor 26, the lower end of the through-via conductor 26 can be reliably connected to the pad 41c of the semiconductor IC chip 40.

[0028] If a semiconductor IC chip 40 already exists below the location where the through-via conductor 26 is to be formed, it is not possible to drill to the predetermined depth to which the through-via conductor 26 should be formed. This is because if the tip of the drill comes into contact with the semiconductor IC chip 40, the semiconductor IC chip 40 will be destroyed. However, if a drill hole is formed to a position slightly shallower than the desired depth, and then further drilled using laser processing, damage to the semiconductor IC chip 40 can be prevented. Furthermore, since the pad 41c of the semiconductor IC chip 40 prevents laser etching and the lower end of the through-hole stops at the surface of the pad 41c, the through-hole can be safely and reliably formed up to the height of the surface of the pad 41c of the semiconductor IC chip 40.

[0029] In a stacked via conductor where via conductors 24 are stacked in multiple layers, tensile stress from the outside may cause cracks to form at the boundary between the upper and lower via conductors 24, and there is a particular risk of breakage of the via conductor 24 near the surface. However, the through via conductor 26 according to this embodiment has no diameter variation in the vertical direction and no boundary between the upper and lower layers, so breakage due to cracking can be prevented.

[0030] The pencil-shaped through-via conductor 26 according to this embodiment is suitable for electrically connecting the antenna pattern 21a and the semiconductor IC chip 40, but is not limited to this use and can be preferably used as a transmission path for high-frequency signals. Therefore, as shown in the figure, a pencil-shaped through-via conductor may be applied to the through-via conductor 16 that penetrates the embedded resin layer 12.

[0031] Next, the manufacturing method of the multilayer substrate module 1 will be described in detail with reference to Figures 3 to 11.

[0032] In the manufacturing of the multilayer substrate module 1 according to this embodiment, first a core substrate 11 made of a double-sided copper-clad substrate is prepared (Figure 3(a)). The core substrate 11 has an insulating substrate 11a, a first core wiring layer 11b formed on the upper surface of the insulating substrate 11a, and a second core wiring layer 11c formed on the lower surface of the insulating substrate 11a. Next, the first core wiring layer 11b on the upper surface side of the core substrate 11 is patterned to form a circuit pattern (Figure 3(b)).

[0033] Next, a base resin layer 12a is formed on the upper surface of the core substrate 11, and the semiconductor IC chip 40 is mounted on the upper surface of the base resin layer 12a with its pad-forming surface facing upward (Figure 3(c)). Subsequently, an upper resin layer 12b is formed on the upper surface of the base resin layer 12a to form an embedded resin layer 12 in which the semiconductor IC chip 40 is embedded (Figure 3(d)). With the above steps, the semiconductor IC embedded substrate 10 is completed.

[0034] Next, a build-up layer 20 is formed on the upper surface of the semiconductor IC embedded substrate 10. In forming the build-up layer 20, a first wiring layer 21-1 made of copper foil or the like is formed on the upper surface of the embedded resin layer 12 (Figure 4(a)). The first wiring layer 21-1 is the lowest wiring layer of the build-up layer 20.

[0035] Next, a through-via conductor 16 is formed that penetrates the embedded resin layer 12 and connects the first wiring layer 21-1 and the first core wiring layer 11b (Figures 4(b) to 5(a)). The through-via conductor 16 according to this embodiment is pencil-shaped and can be formed by a combination of drilling and laser processing.

[0036] In forming the through-via conductor 16, a through-hole 17 is first formed by drilling downwards from the upper surface of the first wiring layer 21-1 (Figure 4(b)). The through-hole 17 is formed to a depth slightly above the upper surface of the first core wiring layer 11b. The diameter of the through-hole 17 is preferably 0.1 mm to 0.5 mm, and particularly preferably 0.15 mm to 0.30 mm. The distance from the bottom of the through-hole 17 to the upper surface of the first core wiring layer 11b is preferably 0.01 mm to 10 mm. If the distance is less than 0.01 mm, there is a high risk of damage to the first core wiring layer 11b due to processing errors, and if it exceeds 10 mm, the laser may not reach the upper surface of the first core wiring layer 11b, potentially resulting in incomplete drilling.

[0037] Subsequently, the bottom of the through-hole 17 is further excavated by laser processing. This causes the through-hole 17 to reach the upper surface of the first core wiring layer 11b (Figure 4(c)). The diameter of the lower end of the through-hole 17 thus formed is smaller than the diameter of the upper part of the through-hole 17 formed by drilling. After that, the through-via conductor 16 is completed by embedding a conductive material inside the through-hole 17 (Figure 5(a)). The method of embedding the conductive material is not particularly limited, but it is preferable to perform electroless copper plating and electrolytic copper plating in sequence, and copper sputtering may be performed instead of electroless copper plating. Alternatively, a conductive resin (conductive paste) may be injected instead of electrolytic copper plating. It is preferable to completely fill the inside of the through-hole 17 with conductive material, but an insulating material such as epoxy resin may be filled into the hollow part after the conductor has been formed on the inner surface of the through-hole 17.

[0038] Next, the first wiring layer 21-1 is processed to form an opening 21o for forming via conductors (Figure 5(b)), and via holes 43 are formed on the surface of the embedded resin layer 12 by laser processing using the first wiring layer 21-1 as a mask (Figure 5(c)). Subsequently, via conductors 42a and 42b are formed by embedding conductive material in the via holes 43 to connect the first wiring layer 21-1 and the pads 41a and 41b of the semiconductor IC chip 40 (Figure 6(a)). Subsequently, the first wiring layer 21-1 on the upper surface of the embedded resin layer 12 is patterned to form a circuit pattern (Figure 6(b)). With the above steps, the semiconductor IC embedded substrate 10 with via conductors 42a and 42b and through via conductor 16 is completed.

[0039] Next, a first insulating layer 22-1 made of prepreg or the like and a second wiring layer 21-2 made of copper foil or the like are sequentially laminated on the upper surface of the embedded resin layer 12 on which the first wiring layer 21-1 is formed (Figure 6(c)). Then, the second wiring layer 21-2 is processed to form an opening for forming a via conductor, and a via hole 25 is formed by laser processing using the second wiring layer 21-2 as a mask (Figure 7(a)). In this embodiment, the via hole 25 is formed directly above the via conductor 42a.

[0040] Thereafter, the via conductor 24 is formed by embedding a conductive material into the via hole 25 (Fig. 7(b)). Subsequently, the second wiring layer 21-2 having a circuit pattern formed thereon is completed by patterning the second wiring layer 21-2 (Fig. 7(c)). Then, by repeating the step of alternately laminating such wiring layers 21 and insulating layers 22 a plurality of times (here, 5 times), the build-up layer 20 including the first to sixth wiring layers 21-1 to 21-6 and the first to fifth insulating layers 22-1 to 22-5 is completed (Fig. 8(a)). At this stage, the sixth wiring layer 21-6 is not patterned, and substantially the entire surface of the fifth insulating layer 22-5 remains covered with the sixth wiring layer 21-6.

[0041] Next, the via conductor 13 penetrating the insulating substrate 11a is formed by laser processing and embedding of a conductive material (Fig. 8(b)).

[0042] Next, the through-via conductor 26 that penetrates the build-up layer 20 and connects the sixth wiring layer 21-6 and the pad 41c of the semiconductor IC chip 40 is formed (Figs. 9(a) to 10(a)). Similar to the through-via conductor 16, the through-via conductor 26 is pencil-shaped and can be formed by a combination of drilling and laser processing.

[0043] In forming the through-via conductor 26, first, a through hole 27 is formed downward from the upper surface of the sixth wiring layer 21-6 by drilling (Fig. 9(a)). The through hole 27 is formed to a depth position slightly above the upper surface of the pad 41c of the semiconductor IC chip 40. The distance from the bottom of the through hole 27 to the upper surface of the pad 41c is preferably 0.01 mm to 10 mm. This is because if the distance is less than 0.01 mm, there is a high risk that the semiconductor IC chip 40 will be damaged due to processing errors, and if it exceeds 10 mm, the laser cannot reach the upper surface of the pad 41c, which may result in incomplete drilling.

[0044] Thereafter, the bottom of the through hole 27 is further dug down by laser processing. Accordingly, the through hole 27 reaches the upper surface of the pad 41c (FIG. 9(b)). The diameter of the lower end of the through hole 27 formed in this way is smaller than the diameter of the upper part of the through hole 27 formed by drilling. Thereafter, a conductive material is embedded inside the through hole 27, whereby the through via conductor 26 is completed (FIG. 10(a)). The method for embedding the conductive material is not particularly limited, but it is preferable to perform electroless copper plating and electrolytic copper plating in this order, and copper sputtering may be performed instead of electroless copper plating. It is also preferable that the inside of the through hole 17 is completely filled with a conductive material such as copper, but an insulating material such as resin may be filled in the center of the through hole 17.

[0045] When laser processing is performed on an insulating layer made of a glass cloth-containing base material, the glass cloth cannot be completely removed, and the glass cloth may protrude from the inner wall of the through hole and remain on the inner wall of the through hole. Even when attempting to plate the inner wall of such a through hole, the plating solution is difficult to penetrate, and there is a risk of plating defects occurring on the inner wall of the through hole. That is, the presence of the glass cloth on the inner wall of the through hole prevents the conductor from being sufficiently embedded. However, drilling can remove the glass cloth from the inner wall of the through hole and prevent poor embedding of the conductor. In addition, since laser processing after drilling is mainly performed on the surface layer portion of the embedded resin layer 12 that does not contain glass cloth, the problem of poor conductor embedding caused by glass cloth does not occur.

[0046] Next, the sixth wiring layer 21-6 (the uppermost wiring layer) formed on the upper surface of the build-up layer 20 is patterned to form a circuit pattern including the antenna pattern 21a (FIG. 10(b)). At the same time, the second core wiring layer 11c on the lower surface side of the core substrate 11 is also patterned to form a circuit pattern (FIG. 10(b)).

[0047] Next, protective layers 30A and 30B are formed on both sides of the laminate of the semiconductor IC embedded substrate 10 and the build-up layer 20, that is, on the upper surface of the build-up layer 20 and on the lower surface of the core substrate 11, respectively (Figure 11). Subsequently, bump electrodes 33 are formed that penetrate the protective layer 30A and are connected to the circuit pattern of the first core wiring layer 11b (Figure 1). With these steps, the multilayer substrate module 1 according to this embodiment is completed.

[0048] In build-up construction, where insulating and conductive layers are stacked alternately, when via holes penetrating the insulating layer are formed by laser processing, the diameter of the via holes decreases towards the bottom. Furthermore, to prevent the insulating layer below the layer being processed from being processed, an etching stopper land must be provided directly below the via hole formation location, and the planar size of this land is larger than the via hole diameter. Via conductors embedded within such via holes and integrated with the land exhibit large vertical diameter variations. In the case of stacked via conductors, where multiple via conductors are stacked, the presence of multiple lands in between further increases the diameter variation. Current flowing across the surface of such stacked via conductors does not proceed in a straight line vertically, but rather bends repeatedly, resulting in increased transmission loss and radiated noise. This problem becomes more pronounced as the number of via conductor layers increases, and is particularly problematic in signal transmission lines connecting semiconductor IC chips embedded inside a multilayer substrate to antenna patterns formed on the top surface of the multilayer substrate.

[0049] However, in this embodiment, since most of the deep hole for forming the through-via conductor is formed by drilling and the remaining portion is formed by laser processing, the overall diameter variation of the deep hole can be significantly reduced, thereby reducing transmission loss and radiated noise in the signal transmission line. In addition, since the lower end of the deep hole is formed by laser processing, the tip of the deep hole can be tapered, allowing it to be connected to small electrode surfaces such as the pads of semiconductor IC chips.

[0050] Figures 12 to 14 are cross-sectional views showing variations in the shape of the through-via conductor 26 and the method of forming it. Since the shape and forming method of the through-via conductor 16 are the same as those of the through-via conductor 26, a detailed explanation of the through-via conductor 16 is omitted.

[0051] As described above, the through-via conductor 26 has a straight portion 26a and a tapered portion 26b provided below the straight portion 26a (see Figure 2, etc.). The straight portion 26a is formed by drilling and has a constant diameter, while the tapered portion 26b is formed by laser processing and has a diameter that decreases downwards.

[0052] As shown in Figures 12(a) to (c), the shape of the tapered portion 26b may be a normal tapered shape without any steps in the middle, or it may be a stepped tapered shape with steps in the middle, as shown in Figures 13(a) and (b) and Figures 14(a) and (b). The stepped tapered shape may have one step or two or more steps. Figures 13(a) and (b) show a stepped tapered shape with one step, and Figures 14(a) and (b) show a stepped tapered shape with two steps, respectively.

[0053] Figure 12(a) shows a case where a straight hole 27a is drilled to a depth below the upper surface of the embedded resin layer 12. Then, a laser beam B is irradiated onto the bottom of the straight hole 27a to further drill the straight hole 27a, thereby forming a tapered hole 27b below the straight hole 27a. The lower end of the tapered hole 27b penetrates the surface layer 12c of the embedded resin layer 12 and reaches the upper surface of the pad 41c. By embedding a conductor material inside the through-hole 27 thus formed, a through-via conductor 26 having a straight portion 26a and a tapered portion 26b is completed.

[0054] Figure 12(b) shows a case where the drilling is stopped at a depth above the upper surface of the embedded resin layer 12 to form a shallow straight hole 27a. Subsequently, the straight hole 27a is further excavated by irradiating it with the laser beam B to form a tapered hole 27b below the straight hole 27a. The lower end of the tapered hole 27b penetrates the first insulating layer 22-1 and the surface layer 12c of the embedded resin layer 12 to reach the upper surface of the pad 41c. By embedding a conductor material inside the through hole 27 thus formed, the through via conductor 26 is completed.

[0055] Figure 12(c) shows a case where drilling is stopped at a depth above the upper surface of the embedded resin layer 12 to form a shallow straight hole 27a, and a ring-shaped land 21c (metal mask) is provided on the first wiring layer 21-1 to limit the diameter of the tapered hole 27b. Subsequently, the bottom of the through hole 27 is further excavated by laser etching to form a tapered hole 27b below the straight hole 27a. The lower end of the tapered hole 27b penetrates the first insulating layer 22-1 and the surface layer 12c of the embedded resin layer 12 to reach the upper surface of the pad 41c. The diameter of the tapered hole 27b is also limited to less than or equal to the diameter of the opening of the land 21c, thus forming a tapered hole 27b with a diameter less than or equal to the diameter of the straight hole 27a. By embedding a conductor material inside the thus formed through hole 27, the through via conductor 26 is completed.

[0056] Figures 13(a) and (b) show a case in which laser etching is performed by irradiating with laser light having a beam diameter narrower than the diameter of the straight hole 27a formed by drilling.

[0057] Figure 13(a) shows a case where a straight hole 27a is drilled to a depth below the upper surface of the embedded resin layer 12. Then, by irradiating the bottom of the straight hole 27a with a laser beam B to further drill the straight hole 27a, a tapered hole 27b is formed below the straight hole. The lower end of the tapered hole 27b penetrates the first insulating layer 22-1 and the surface layer 12c of the embedded resin layer 12 and reaches the upper surface of the pad 41c. At this time, by irradiating with a laser beam B with a narrow beam diameter, a step 27s is formed at the boundary between the straight hole 27a and the tapered hole 27b. By embedding a conductor material inside the through-hole 27 thus formed, a through-via conductor 26 having a straight portion 26a and a stepped tapered portion 26b is completed.

[0058] Figure 13(b) shows a case where the drilling is stopped at a depth above the upper surface of the embedded resin layer 12 to form a shallow straight hole 27a. Then, similar to Figure 13(a), the bottom of the straight hole 27a is further excavated by irradiating it with the laser beam B to form a tapered hole 27b below the straight hole 27a. The lower end of the tapered hole 27b penetrates the first insulating layer 22-1 and the surface layer 12c of the embedded resin layer 12 and reaches the upper surface of the pad 41c. At this time, by irradiating with the laser beam B which has a narrow beam diameter, a step 27s is formed at the boundary between the straight hole 27a and the tapered hole 27b. By embedding a conductor material inside the through hole 27 thus formed, a through via conductor 26 having a straight portion 26a and a stepped tapered portion 26b is completed.

[0059] Figure 14(a) shows a case in which drilling is stopped at a depth above the upper surface of the embedded resin layer 12 to form a shallow straight hole 27a, and two-stage laser etching is performed by irradiating with laser light having a beam diameter narrower than the diameter of the straight hole 27a. In the first laser etching, a laser beam B1 with a beam diameter narrower than the drill diameter is irradiated, and in the second laser etching, a laser beam B2 with a beam diameter narrower than the first is irradiated. Through this laser processing, a tapered hole 27b with two steps 27s is formed at the lower end of the through hole 27. By embedding a conductive material inside the through hole 27 thus formed, a through via conductor 26 having a straight portion 26a and a stepped tapered portion 26b is completed.

[0060] Figure 14(b) shows a case in which drilling is stopped at a depth above the upper surface of the embedded resin layer 12 to form a shallow straight hole 27a, and a single laser etching is performed using a laser beam with a beam diameter narrower than the diameter of the straight hole 27a, and a ring-shaped land 21c (metal mask) is provided on the first wiring layer 21-1 to limit the diameter of the tapered hole 27b. Preferably, the outer diameter of the ring-shaped land 21c is equal to the drill diameter, and the inner diameter of the land 21c is smaller than the minimum width of the land. Through this laser processing, a tapered hole 27b having two steps 27s is formed at the lower end of the through hole 27. By embedding a conductor material inside the through hole 27 thus formed, a through via conductor 26 having a straight portion 26a and a stepped tapered portion 26b is completed.

[0061] As described above, the through-via conductor 26 can be formed in various ways. The through-via conductor 16 can also be formed in the same manner as the through-via conductor 26.

[0062] Figure 15 is a substantially cross-sectional view showing the structure of a multilayer substrate module according to a second embodiment of the present disclosure.

[0063] As shown in Figure 15, a feature of this multilayer substrate module 2 is that the lower end of the through-via conductor 26 is connected to a land 21b (first land) provided on the first wiring layer 21-1, and the land 21b is connected to the pad 41c of the semiconductor IC chip 40 via a via conductor 42c (first via conductor). Thus, the through-via conductor 26 may connect the uppermost wiring layer and the lowermost wiring layer of the build-up layer 20, or it may be connected to the pad 41c of the semiconductor IC chip 40 via a via conductor 42c. In other words, the lower end of the through-via conductor 26 does not have to be directly connected to the pad 41c of the semiconductor IC chip 40.

[0064] When the tapered portion 26b of the through-via conductor 26 is formed to penetrate the first insulating layer 22-1, the glass cloth contained in the first insulating layer 22-1 may not disappear even by laser etching, causing the glass cloth to protrude from the inner surface of the tapered hole 27b, which can lead to poor embedding of the conductor. In such cases, it is possible to prevent plating defects by using a glass cloth-less substrate for the first insulating layer 22-1.

[0065] Figure 16 is a substantially cross-sectional view showing the structure of a multilayer substrate module according to a third embodiment of the present disclosure.

[0066] As shown in Figure 16, a feature of this multilayer substrate module 3 is that the lower end of the through-via conductor 26 is connected to a land 21b (second land) provided on the second wiring layer 21-2. Furthermore, the land 21b is connected to the pad 41c of the semiconductor IC chip 40 via a via conductor 24 that penetrates the first insulating layer 22-1 and a via conductor 42c that penetrates the surface layer of the embedded resin layer 12. The via conductor 42c and the via conductor 24 (second via conductor) provided directly above it constitute a two-stage stacked via conductor. Thus, the lower end of the through-via conductor 26 may also be connected to an intermediate wiring layer (second intermediate wiring layer) between the uppermost wiring layer and the lowest wiring layer.

[0067] Figure 17 is a substantially cross-sectional view showing the structure of a multilayer substrate module according to a fourth embodiment of the present disclosure.

[0068] As shown in Figure 17, a feature of this multilayer substrate module 4 is that it is equipped with through-via conductors 26-1 and 26-2, and the pad 41a of the semiconductor IC chip 40 is connected to the non-antenna pattern 21z via the through-via conductor 26-1. The pad 41c of the semiconductor IC chip 40 is connected to the antenna pattern 21a via the through-via conductor 26-1. Thus, the application of the through-via conductor is not limited to connecting the antenna pattern 21a and the semiconductor IC chip 40, but can be used as an interlayer connection conductor for various signal transmission lines where transmission loss and radiated noise are problems.

[0069] Figure 18 is a substantially cross-sectional view showing the structure of a multilayer substrate module according to a fifth embodiment of the present disclosure.

[0070] As shown in Figure 18, a feature of this multilayer substrate module 5 is that it is equipped with through-via conductors 26-1 and 26-2, and the upper ends of the through-via conductors 26-1 and 26-2 are connected to the circuit pattern of the fifth wiring layer 21-5. The lower end of the through-via conductor 26-1 is directly connected to the pad 41c of the semiconductor IC chip 40. The lower end of the through-via conductor 26-2 is connected to a land 21b provided on the first insulating layer 22-1, and the land 21b is connected to the pad 41a of the semiconductor IC chip 40 via a via conductor 42a that penetrates the surface layer of the embedded resin layer 12.

[0071] When connecting the upper ends of through-via conductors 26-1 and 26-2 to the circuit pattern of the fifth wiring layer 21-5, it is necessary to form the through-via conductors 26-1 and 26-2 that penetrate the first to fourth insulating layers 22-1 to 22-4 before forming the fifth insulating layer 22-5. After that, the fifth insulating layer 22-5 and the sixth wiring layer 21-6 are formed in order to complete the multilayer substrate module 5. In this way, the upper ends of the through-via conductors 26 may be connected to an intermediate wiring layer (first intermediate wiring layer) between the uppermost wiring layer and the lowest wiring layer.

[0072] Figure 19 is a substantially cross-sectional view showing the structure of a multilayer substrate module according to the sixth embodiment of the present disclosure.

[0073] As shown in Figure 19, the multilayer substrate module 6 is characterized by having through-via conductors 26-1 and 26-2. The upper end of through-via conductor 26-1 is connected to the antenna pattern 21a of the sixth wiring layer 2-16, and the lower end of through-via conductor 26-1 is connected to the land 21b of the second wiring layer 21-2. The lower end of through-via conductor 26-1 is not directly connected to the semiconductor IC chip. The upper end of through-via conductor 26-2 is connected to the circuit pattern of the fifth wiring layer 21-5, and the lower end of through-via conductor 26-2 is connected to another land 21b of the second wiring layer 21-2. Thus, through-via conductor 26-2 is not directly connected to the antenna pattern 21a or the pads of the semiconductor IC chip 40. In this way, through-via conductors may be used to connect intermediate wiring layers of the build-up layer 20.

[0074] Figure 20 is a substantially cross-sectional view showing the structure of a multilayer substrate module according to the seventh embodiment of the present disclosure.

[0075] As shown in Figure 20, a feature of this multilayer substrate module 7 is that the through-via conductors 16-1 and 16-2 are formed in the opposite direction to the through-via conductor 26 that penetrates the build-up layer 20. Each of the through-via conductors 16-1 and 16-2 has a straight section 16a with a constant diameter from the bottom end to the top end and no lands in between, and a tapered section 16b connected to the upper end of the straight section 16a, with the diameter decreasing upwards.

[0076] The through-via conductor 16-1 is formed to penetrate the embedded resin layer 12, with its lower end connected to the first core wiring layer 11b and its upper end connected to the first wiring layer 21-1. The through-via conductor 16-2 is formed to penetrate not only the embedded resin layer 12 but also the insulating substrate 11a of the core substrate 11, with its lower end connected to the circuit pattern of the second core wiring layer 11c and its upper end connected to the first wiring layer 21-1. These through-via conductors 16-1 and 16-2 can be formed by embedding conductive material in straight holes and tapered holes dug from bottom to top. Thus, the through-via conductors 16-1 and 16-2 penetrating the embedded resin layer 12 may be formed facing upward from the core substrate 11 towards the build-up layer 20.

[0077] As described above, the multilayer substrate module 1 according to this embodiment comprises a build-up layer 20 in which a plurality of wiring layers 21 and a plurality of insulating layers 22 are alternately stacked, and a through-via conductor 26 formed on the build-up layer 20. The through-via conductor 26 has a straight portion 26a with a constant diameter from the top end to the bottom end and no protruding shape on the outer surface due to lands in between, and a tapered portion 26b connected to the bottom end of the straight portion 26a, with the diameter decreasing downwards. Since the straight portion 26a is longer than the tapered portion 26b, an interlayer connection conductor with low transmission loss and low radiated noise can be provided.

[0078] While preferred embodiments of this disclosure have been described above, it goes without saying that this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure, and such modifications are also included within the scope of this disclosure.

[0079] For example, in the above embodiment, a multilayer substrate module in which a build-up layer 20 is formed on a semiconductor IC embedded substrate 10 and an antenna pattern 21a is formed on the build-up layer 20 was given as an example. However, this disclosure is not limited to such a configuration and can be applied to multilayer substrate modules in which a semiconductor IC chip 40 is not mounted, and can also be applied to multilayer substrate modules in which an antenna pattern is not provided. Furthermore, it is possible to omit the through-via conductor 16 formed on the embedded resin layer 12.

[0080] In the above embodiment, a straight hole 27a is formed first, followed by a tapered hole 27b, when forming the through-via conductor 26. However, it is also possible to form the straight hole 27a after forming the tapered hole 27b.

[0081] The technology relating to this disclosure includes, but is not limited to, the following configuration examples.

[0082] The multilayer substrate module according to this disclosure comprises a build-up layer in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked, and a first through-via conductor formed on the build-up layer, wherein the first through-via conductor has a straight portion having a constant diameter from the upper end to the lower end and no lands in between, and a tapered portion connected to the lower end of the straight portion and decreasing in diameter downward, and the straight portion is longer than the tapered portion.

[0083] According to this disclosure, it is possible to provide a multilayer substrate module equipped with interlayer connecting conductors that reduce transmission loss and radiated noise.

[0084] In this disclosure, the upper end of the first through-via conductor may be connected to the uppermost wiring layer of the build-up layer. In this case, the uppermost wiring layer may include an antenna pattern, and the upper end of the first through-via conductor may be connected to the antenna pattern. This allows the first through-via conductor to be connected to the antenna pattern, thereby reducing transmission loss and radiated noise of the signal transmission line connected to the antenna pattern.

[0085] The lower end of the first through-via conductor may be connected to a first land provided on the lowest wiring layer of the build-up layer. In the lowest wiring layer of the build-up layer, wiring patterns and lands are laid out at a narrow pitch, and the size of the first land is often small. Even in such cases, because the tip of the first through-via conductor is tapered, a reliable connection can be made between the tip of the first through-via conductor and the first land.

[0086] The build-up layer includes a first intermediate wiring layer provided between the uppermost wiring layer and the lowest wiring layer, and a second intermediate wiring layer provided between the first intermediate wiring layer and the lowest wiring layer, wherein the lower end of the first through-via conductor may be connected to a second land provided on the second intermediate wiring layer. In this way, the first through-via conductor can also be used for interlayer connections between the uppermost wiring layer and the intermediate wiring layer, thereby reducing transmission loss and radiated noise in the signal transmission line.

[0087] The build-up layer includes an uppermost wiring layer, a lowermost wiring layer, a first intermediate wiring layer provided between the uppermost and lowermost wiring layers, and a second intermediate wiring layer provided between the first intermediate wiring layer and the lowermost wiring layer, wherein the upper end of the first through-via conductor may be connected to the first intermediate wiring layer. In this case, the lower end of the first through-via conductor may be connected to a first land provided on the lowermost wiring layer, or to a second land provided on the second intermediate wiring layer. In this way, the first through-via conductor can be used for interlayer connections between upper intermediate wiring layers and lower wiring layers, thereby reducing transmission loss and radiated noise in the signal transmission line.

[0088] The multilayer substrate module according to this disclosure further comprises an embedded resin layer on which a semiconductor IC chip is embedded, the build-up layer is provided on the embedded resin layer, and the lower end of the first through-via conductor may penetrate the surface layer of the embedded resin layer and be connected to a pad of the semiconductor IC chip. This makes it possible to reduce transmission loss and radiated noise in the signal transmission line connecting the antenna pattern and the semiconductor IC chip.

[0089] The multilayer substrate module according to this disclosure further comprises an embedded resin layer on which a semiconductor IC chip is embedded, the build-up layer is provided on the embedded resin layer, the lower end of the first through via conductor is connected to a first land provided on the lowest wiring layer of the build-up layer, and the first land may be connected to a pad of the semiconductor IC chip via a first via conductor that penetrates the surface layer of the embedded resin layer. This makes it possible to reduce transmission loss and radiated noise in the signal transmission line connecting the antenna pattern and the semiconductor IC chip.

[0090] The multilayer substrate module according to this disclosure further comprises an embedded resin layer on which a semiconductor IC chip is embedded, the build-up layer is provided on the embedded resin layer, the build-up layer includes the uppermost wiring layer, the lowest wiring layer, a first intermediate wiring layer provided between the uppermost wiring layer and the lowest wiring layer, and a second intermediate wiring layer provided between the first intermediate wiring layer and the lowest wiring layer, wherein a first land provided on the lowest wiring layer is connected to a pad of the semiconductor IC chip via a first via conductor penetrating the surface layer of the embedded resin layer, and a second land provided on the second intermediate wiring layer may be connected to the first land via a second via conductor penetrating the lowest insulating layer.

[0091] A step is formed in the tapered portion, and the diameter of the tapered portion at the position where the step is formed may be smaller than the diameter of the straight portion. This makes it possible to make the tip of the through-via conductor thinner and to reliably connect the tip of the through-via conductor to the small land of the semiconductor IC chip.

[0092] In this disclosure, the insulating layer through which the straight portion penetrates may be made of a glass cloth-containing substrate, while the insulating layer through which the tapered portion penetrates may be made of a glass cloth-less substrate. This prevents poor conductivity in the tapered portion caused by the glass cloth.

[0093] The multilayer substrate module according to this disclosure further comprises a second through-via conductor formed to penetrate the embedded resin layer, wherein the second through-via conductor has a straight portion having a constant diameter from its upper end to its lower end and no lands in between, and a tapered portion connected to the lower end of the straight portion, with the diameter decreasing downwards, wherein the length of the straight portion may be longer than the tapered portion, and the diameter of the tapered portion may be less than or equal to the diameter of the straight portion. In this case, the upper end of the second through-via conductor may be connected to the lowest wiring layer of the build-up layer. This makes it possible to reduce the transmission loss and radiated noise of the interlayer connection conductor penetrating the embedded resin layer.

[0094] The multilayer substrate module according to this disclosure further comprises a core substrate supporting the embedded resin layer, the core substrate having an insulating substrate, a first core wiring layer formed on the upper surface of the insulating substrate, and a second core wiring layer formed on the lower surface of the insulating substrate, the embedded resin layer being formed on the upper surface of the core substrate, and the lower end of the second through-via conductor may be connected to a land provided on the first core wiring layer. This makes it possible to reduce transmission loss and radiated noise in the signal transmission line that penetrates the embedded resin layer and connects the lowest wiring layer of the build-up layer to the wiring layer on the core substrate side.

[0095] The multilayer substrate module according to this disclosure further comprises a second through-via conductor formed to penetrate the embedded resin layer, wherein the second through-via conductor has a straight portion having a constant diameter from its lower end to its upper end and no lands in between, and a tapered portion connected to the upper end of the straight portion, with the diameter decreasing upwards, wherein the length of the straight portion may be longer than the tapered portion, and the diameter of the tapered portion may be less than or equal to the diameter of the straight portion. In this case, the upper end of the second through-via conductor may be connected to the lowest wiring layer of the build-up layer. This makes it possible to reduce the transmission loss and radiated noise of the interlayer connection conductor penetrating the embedded resin layer.

[0096] The multilayer substrate module according to this disclosure further comprises a core substrate supporting the embedded resin layer, the core substrate having an insulating substrate, a first core wiring layer formed on the upper surface of the insulating substrate, and a second core wiring layer formed on the lower surface of the insulating substrate, the embedded resin layer being formed on the upper surface of the core substrate, and the lower end of the second through-via conductor may be connected to a land provided on the first core wiring layer. This makes it possible to reduce transmission loss and radiated noise in the signal transmission line that penetrates the embedded resin layer and connects the lowest wiring layer of the build-up layer to the first core wiring layer of the core substrate.

[0097] The multilayer substrate module according to this disclosure further comprises a core substrate supporting the embedded resin layer, the core substrate having an insulating substrate, a first core wiring layer formed on the upper surface of the insulating substrate, and a second core wiring layer formed on the lower surface of the insulating substrate, the embedded resin layer being formed on the upper surface of the core substrate, the second through-via conductor being formed to penetrate the embedded resin layer and the insulating substrate, and the lower end of the second through-via conductor may be connected to a land provided on the second core wiring layer. This makes it possible to reduce transmission loss and radiated noise in the signal transmission line that penetrates the embedded resin layer and the insulating substrate and connects the lowest wiring layer of the build-up layer to the second core wiring layer of the core substrate.

[0098] Furthermore, the manufacturing method of a multilayer substrate module according to this disclosure is characterized by comprising the steps of: forming a build-up layer by alternately stacking a plurality of wiring layers and a plurality of insulating layers; forming straight holes having a certain diameter in the build-up layer by drilling; forming tapered holes below the straight holes by laser processing to excavate the bottom of the straight holes; and forming through-via conductors by embedding a conductive material inside the through-holes consisting of the straight holes and the tapered holes.

[0099] According to this disclosure, it is possible to manufacture multilayer substrate modules with interlayer connectors that reduce transmission loss and radiated noise.

[0100] The method for manufacturing a multilayer substrate module according to this disclosure further comprises a step of forming an antenna pattern on the uppermost wiring layer of the build-up layer, wherein the upper end of the through-via conductor may be connected to the antenna pattern. This makes it possible to reduce transmission loss and radiated noise of the signal transmission line connected to the antenna pattern.

[0101] The manufacturing method of a multilayer substrate module according to this disclosure further comprises the step of forming an embedded resin layer on a core substrate in which a semiconductor IC chip is embedded, wherein the build-up layer is formed on the upper surface of the embedded resin layer, the tapered holes are formed so as to penetrate the surface layer of the embedded resin layer and expose the pads of the semiconductor IC chip, and the lower end of the through via conductor may be connected to the pads of the semiconductor IC chip. This makes it possible to reduce transmission loss and radiated noise in the signal transmission line connecting the antenna pattern and the semiconductor IC chip.

[0102] This application claims the interests of Japanese Patent Application No. 2025-052918, filed on 27 March 2025, the full disclosure of which is incorporated herein by reference.

[0103] 1-7 Multilayer substrate module 10 Semiconductor IC embedded substrate 11 Core substrate 11a Insulating substrate 11b First core wiring layer 11c Second core wiring layer 12 Embedded resin layer 12a Underlay resin layer 12b Top resin layer 12c Surface layer 13 Via conductors 16, 16-1, 16-2 Through via conductors (second through via conductors) 16a Straight section 16b Tapered section 17 Through hole 20 Build-up layer 21 Wiring layer 21-1 First wiring layer 21-2 Second wiring layer 21-3 Third wiring layer 21-4 Fourth wiring layer 21-5 Fifth wiring layer 21-6 Sixth wiring layer 21a Antenna pattern 21b Land 21c Land 21o Aperture 21z Non-antenna pattern 22 Insulating layer 22-1 First insulating layer 22-2 Second insulating layer 22-3 Third insulating layer 22-4 Fourth insulating layer 22-5 Fifth insulating layer 24 Via conductor 24S Stacked via conductor 25 Via hole 26, 26-1, 26-2 Through via conductor (first through via conductor) 26a Straight section 26b Tapered section 27 Through hole 27a Straight hole 27b Tapered hole 27s Step 28 Metal film 29 Filling material 30A, 30B Protective layer 33 Bump electrode 40 Semiconductor IC chip 41a, 41b, 41c Pad 42a, 42b, 42c Via conductor 43 Via hole B, B1, B2 Laser beam I １ , I ２ current

Claims

1. A multilayer substrate module comprising a build-up layer in which multiple wiring layers and multiple insulating layers are alternately stacked, and a first through-via conductor formed on the build-up layer, wherein the first through-via conductor has a straight portion having a constant diameter from the upper end to the lower end and no lands in between, and a tapered portion connected to the lower end of the straight portion, with the diameter decreasing downwards, and the straight portion being longer than the tapered portion.

2. The multilayer substrate module according to claim 1, wherein the upper end of the first through-via conductor is connected to the uppermost wiring layer of the build-up layer.

3. The multilayer substrate module according to claim 2, wherein the uppermost wiring layer includes an antenna pattern, and the upper end of the first through-via conductor is connected to the antenna pattern.

4. The multilayer substrate module according to claim 2, wherein the lower end of the first through-via conductor is connected to a first land provided in the lowest wiring layer of the build-up layer.

5. The multilayer substrate module according to claim 2, wherein the build-up layer includes a first intermediate wiring layer provided between the uppermost wiring layer and the lowest wiring layer, and a second intermediate wiring layer provided between the first intermediate wiring layer and the lowest wiring layer, and the lower end of the first through-via conductor is connected to a second land provided in the second intermediate wiring layer.

6. The multilayer substrate module according to claim 1, wherein the build-up layer includes an uppermost wiring layer, a lowermost wiring layer, a first intermediate wiring layer provided between the uppermost wiring layer and the lowermost wiring layer, and a second intermediate wiring layer provided between the first intermediate wiring layer and the lowermost wiring layer, and the upper end of the first through-via conductor is connected to the first intermediate wiring layer.

7. The multilayer substrate module according to claim 6, wherein the lower end of the first through-via conductor is connected to a first land provided in the lowest wiring layer.

8. The multilayer substrate module according to claim 6, wherein the lower end of the first through-via conductor is connected to a second land provided in the second intermediate wiring layer.

9. The multilayer substrate module according to claim 2, further comprising an embedded resin layer in which a semiconductor IC chip is embedded, wherein the build-up layer is provided on the embedded resin layer, and the lower end of the first through-via conductor penetrates the surface layer of the embedded resin layer and is connected to a pad of the semiconductor IC chip.

10. A multilayer substrate module according to claim 2, further comprising an embedded resin layer in which a semiconductor IC chip is embedded, wherein the build-up layer is provided on the embedded resin layer, the lower end of the first through-via conductor is connected to a first land provided on the lowest wiring layer of the build-up layer, and the first land is connected to a pad of the semiconductor IC chip via a first via conductor penetrating the surface layer of the embedded resin layer.

11. A multilayer substrate module according to claim 2, further comprising an embedded resin layer in which a semiconductor IC chip is embedded, wherein the build-up layer is provided on the embedded resin layer, the build-up layer includes the uppermost wiring layer, the lowest wiring layer, a first intermediate wiring layer provided between the uppermost wiring layer and the lowest wiring layer, and a second intermediate wiring layer provided between the first intermediate wiring layer and the lowest wiring layer, wherein a first land provided on the lowest wiring layer is connected to a pad of the semiconductor IC chip via a first via conductor penetrating the surface layer of the embedded resin layer, and a second land provided on the second intermediate wiring layer is connected to the first land via a second via conductor penetrating the lowest insulating layer.

12. The multilayer substrate module according to claim 1, wherein a step is formed in the tapered portion, and the diameter of the tapered portion at the position where the step is formed is smaller than the diameter of the straight portion.

13. The multilayer substrate module according to claim 1, wherein the surface roughness of the tapered portion is greater than the surface roughness of the straight portion.

14. The multilayer substrate module according to claim 1, wherein the insulating layer through which the straight portion penetrates is made of a glass cloth-containing substrate, and the insulating layer through which the tapered portion penetrates is made of a glass cloth-less substrate.

15. A multilayer substrate module according to claim 9, further comprising a second through-via conductor formed to penetrate the embedded resin layer, wherein the second through-via conductor has a straight portion having a constant diameter from its upper end to its lower end and no lands in between, and a tapered portion connected to the lower end of the straight portion and decreasing in diameter downward, wherein the length of the straight portion is longer than the tapered portion, and the diameter of the tapered portion is less than or equal to the diameter of the straight portion.

16. The multilayer substrate module according to claim 15, wherein the upper end of the second through-via conductor is connected to the lowest wiring layer of the build-up layer.

17. A multilayer substrate module according to claim 16, further comprising a core substrate supporting the embedded resin layer, wherein the core substrate has an insulating substrate, a first core wiring layer formed on the upper surface of the insulating substrate, and a second core wiring layer formed on the lower surface of the insulating substrate, the embedded resin layer is formed on the upper surface of the core substrate, and the lower end of the second through-via conductor is connected to a land provided on the first core wiring layer.

18. A multilayer substrate module according to claim 9, further comprising a second through-via conductor formed to penetrate the embedded resin layer, wherein the second through-via conductor has a straight portion having a constant diameter from its lower end to its upper end and no lands in between, and a tapered portion connected to the upper end of the straight portion and decreasing in diameter upward, wherein the length of the straight portion is longer than the tapered portion, and the diameter of the tapered portion is less than or equal to the diameter of the straight portion.

19. The multilayer substrate module according to claim 18, wherein the upper end of the second through-via conductor is connected to the lowest wiring layer of the build-up layer.

20. A multilayer substrate module according to claim 19, further comprising a core substrate supporting the embedded resin layer, wherein the core substrate has an insulating substrate, a first core wiring layer formed on the upper surface of the insulating substrate, and a second core wiring layer formed on the lower surface of the insulating substrate, the embedded resin layer is formed on the upper surface of the core substrate, and the lower end of the second through-via conductor is connected to a land provided on the first core wiring layer.

21. A multilayer substrate module according to claim 19, further comprising a core substrate supporting the embedded resin layer, wherein the core substrate has an insulating substrate, a first core wiring layer formed on the upper surface of the insulating substrate, and a second core wiring layer formed on the lower surface of the insulating substrate, the embedded resin layer is formed on the upper surface of the core substrate, the second through-via conductor is formed to penetrate the embedded resin layer and the insulating substrate, and the lower end of the second through-via conductor is connected to a land provided on the second core wiring layer.

22. A method for manufacturing a multilayer substrate module, comprising the steps of: forming a build-up layer by alternately stacking a plurality of wiring layers and a plurality of insulating layers; forming straight holes having a certain diameter in the build-up layer by drilling; forming tapered holes below the straight holes by laser processing to excavate the bottom of the straight holes; and embedding a conductive material inside the through-holes consisting of the straight holes and the tapered holes to form through-via conductors.

23. A method for manufacturing a multilayer substrate module according to claim 22, further comprising the step of forming an antenna pattern on the uppermost wiring layer of the build-up layer, wherein the upper end of the through-via conductor is connected to the antenna pattern.

24. A method for manufacturing a multilayer substrate module according to claim 22 or 23, further comprising the step of forming an embedded resin layer on a core substrate in which a semiconductor IC chip is embedded, wherein the build-up layer is formed on the upper surface of the embedded resin layer, the tapered holes are formed to penetrate the surface portion of the embedded resin layer so as to expose the pads of the semiconductor IC chip, and the lower end of the through via conductor is connected to the pads of the semiconductor IC chip.

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