High-frequency circuit

Abstract

A high-frequency circuit (1) comprises: a power amplification circuit (10); an elastic wave filter (41) that is connected to an output end of the power amplification circuit (10); a bias circuit (21) that is configured to supply a bias current to the power amplification circuit (10); a coupler (32) that is connected between the power amplification circuit (10) and the elastic wave filter (41); a detection circuit (33) that is connected to a coupling port (321) of the coupler (32); an integration circuit (34) that is connected to an output end of the detection circuit (33); and an arithmetic circuit (36) that is configured to control the bias current on the basis of an output signal of the integration circuit (34) and a prescribed threshold value, wherein the arithmetic circuit (36) is configured to reduce the bias current when the output signal of the integration circuit (34) is larger than the prescribed threshold value.

Description

High-frequency circuit

[0001] The present invention relates to a high-frequency circuit.

[0002] Patent Document 1 discloses a transmission output control circuit that applies a correction voltage to a control voltage of a variable gain amplifying means so as to keep the transmission output constant based on an error of a transmission output value with respect to a reference detection value.

[0003] Japanese Unexamined Patent Publication No. Hei 7-264081

[0004] However, with the above conventional technology, it is difficult to suppress destruction of an elastic wave filter.

[0005] Therefore, the present invention provides a high-frequency circuit capable of suppressing destruction of an elastic wave filter.

[0006] A high-frequency circuit according to one aspect of the present invention includes a power amplifier circuit, a first elastic wave filter connected to an output end of the power amplifier circuit, a bias circuit configured to supply a bias current to the power amplifier circuit, a coupler connected between the power amplifier circuit and the first elastic wave filter, a detection circuit connected to a coupling port of the coupler, an integration circuit connected to an output end of the detection circuit, and an arithmetic circuit configured to control the bias current based on an output signal of the integration circuit and a predetermined threshold, wherein the arithmetic circuit is configured to decrease the bias current when the output signal of the integration circuit is larger than the predetermined threshold.

[0007] A high-frequency circuit according to one aspect of the present invention comprises a power amplifier circuit, an elastic wave filter connected to the output terminal of the power amplifier circuit, a bias circuit configured to supply a bias current to the power amplifier circuit, a coupler connected between the power amplifier circuit and the elastic wave filter, a detection circuit connected to the coupling port of the coupler, an integrating circuit connected to the output terminal of the detection circuit, a voltage / current conversion circuit connected to the output terminal of the integrating circuit, and an arithmetic circuit connected between the voltage / current conversion circuit and the bias circuit, wherein the arithmetic circuit has a first terminal connected to the output terminal of the voltage / current conversion circuit, a second terminal connected to the power supply terminal, and a control terminal. The device includes a first transistor, a second transistor having a first terminal short-circuited with a control terminal in the first transistor, a first terminal connected to a current source, a second terminal connected to a power supply terminal, and a control terminal connected to the control terminal of the first transistor, a third transistor having a first terminal connected to a path between the first terminal of the second transistor and the current source, a second terminal connected to ground, and a control terminal, and a fourth transistor having a first terminal short-circuited with a control terminal in the third transistor, a first terminal connected to a bias circuit, a second terminal connected to ground, and a control terminal connected to the control terminal of the third transistor.

[0008] According to one aspect of the present invention, the destruction of the elastic wave filter can be suppressed.

[0009] Figure 1 is a diagram of the communication device according to the embodiment. Figure 2 is a circuit diagram of the detection circuit, integration circuit, voltage / current conversion circuit, and arithmetic circuit according to the embodiment. Figure 3A is a graph showing the relationship between the input current and sink current of the arithmetic circuit according to the embodiment. Figure 3B is a graph showing the relationship between the input current and bias current of the arithmetic circuit according to the embodiment. Figure 4 is a layout diagram of the high-frequency circuit according to the embodiment. Figure 5 is a layout diagram of a high-frequency circuit according to a modified example of the embodiment. Figure 6A is a graph showing the relationship between the input signal and the breakdown limit of the elastic wave filter. Figure 6B is a graph showing the relationship between the input signal and the breakdown limit of the elastic wave filter. Figure 6C is a graph showing the relationship between the input signal and the breakdown limit of the elastic wave filter.

[0010] The embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement of components, and connection configurations shown in the following embodiments are examples only and are not intended to limit the present invention.

[0011] The figures are schematic diagrams that have been appropriately emphasized, omitted, or had their proportions adjusted to illustrate the present invention, and are not necessarily strictly accurate representations. Actual shapes, positional relationships, and proportions may differ. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations may be omitted or simplified.

[0012] In the following explanation, "connected" includes not only direct connections via terminals and / or wiring conductors, but also electrical connections via other circuit elements. "A is switchably connected to B" means that the connection and disconnection between A and B are switchable, and that A is connected to B via a switch. Note that "A is connected to B" includes "A is switchably connected to B".

[0013] "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, meaning that C is in series connection to the path between A and B. "C is connected between the path between A and B and ground" means that one end of C is connected to the path between A and B and the other end of C is connected to ground, meaning that C is in shunt connection to the path between A and B. "The path between A and B" means a path composed of conductors that electrically connect A to B.

[0014] A "terminal" refers to the point where a conductor within a circuit element ends. However, if the impedance of the conductors between circuit elements is sufficiently low, a terminal can be interpreted not only as a single point, but as any point on the conductor between circuit elements, or even the entire conductor.

[0015] The "passband of a filter" is the portion of the frequency spectrum transmitted by the filter, and is defined as the frequency band between two frequencies that are 3 dB greater than the minimum power insertion loss.

[0016] "Power class" is a classification of the output power of user equipment (UE) defined by its maximum output power. A lower power class value indicates a higher maximum output power that is permitted. For example, the 3GPP (registered trademark) (3rd Generation Partnership Project) defines power classes 1, 1.5, 2, and 3. Specifically, power class 1 is defined as having a maximum output power of 31 dBm. Power class 1.5 is defined as having a maximum output power of 29 dBm. Power class 2 is defined as having a maximum output power of 26 dBm. Power class 3 is defined as having a maximum output power of 23 dBm.

[0017] The maximum output power of a UE is defined as the maximum output power at the antenna terminal. The maximum output power of a UE is measured using methods defined by 3GPP, etc. For example, the maximum output power is measured by measuring the radiated power at the antenna. Alternatively, instead of measuring the radiated power, the maximum output power of the antenna can be measured by providing a terminal near the antenna and connecting a measuring instrument (such as a spectrum analyzer) to that terminal.

[0018] "Bands corresponding to a specified power class" refers to frequency bands where that power class can be used, and is defined in standards and specifications. For example, in 3GPP Release 17, n1, n3, n34, n39, n40, n41, n77, n78, n79, n95, n97, n98, and n104 are defined as bands corresponding to power class 2 for 5GNR, and n41, n77, n78, and n79 are defined as bands corresponding to power class 1.5 for 5GNR.

[0019] "Transmitting band" refers to the frequency band used for transmission in a communication device, while "receiving band" refers to the frequency band used for reception in a communication device. For example, in an FDD (Frequency Division Duplex) band, different frequency bands (uplink band and downlink band) are used as the transmitting and receiving bands. In contrast, in a TDD band, the same frequency band is used for both the transmitting and receiving bands.

[0020] "A component is placed on a substrate" includes a component being placed on the main surface of the substrate, and a component being placed within the substrate. "A component is placed on the main surface of the substrate" includes a component being placed in contact with the main surface of the substrate, as well as a component being placed above the main surface without contact with it (for example, a component being stacked on top of another component placed in contact with the main surface). Furthermore, "a component is placed on the main surface of the substrate" may also include a component being placed in a recess formed in the main surface. "A component is placed within the substrate" includes a component being encapsulated within the substrate, as well as a component being entirely placed between the two main surfaces of the substrate but with part of the component not covered by the substrate, and a component being placed within the substrate only.

[0021] Terms indicating the relationship between elements, such as "parallel" and "perpendicular," and terms indicating the shape of elements, such as "straight line," as well as numerical ranges, do not represent only the strict meaning but also include a substantially equivalent range, such as an error of a few percent. Furthermore, "constant" means not only being strictly constant but also fluctuating within a range that can be considered substantially the same as being strictly constant (a range of ±10%).

[0022] (Embodiment) An embodiment will be described below.

[0023] [1.1. Configuration of the Communication Device 5] First, the configuration of the communication device 5 according to this embodiment will be described with reference to Figure 1. Figure 1 is a configuration diagram of the communication device 5 according to this embodiment.

[0024] Figure 1 shows an exemplary configuration, and the communication device 5 can be implemented using a wide variety of circuit implementations and circuit technologies. Therefore, the description of the communication device 5 provided below should not be interpreted as restrictive.

[0025] The communication device 5 can be used to provide wireless connectivity. For example, the communication device 5 can be implemented in a UE (User Equipment) on a cellular network (also called a mobile network) such as a mobile phone, smartphone, tablet computer, or wearable device. In another example, by implementing the communication device 5, wireless connectivity can be provided to IoT (Internet of Things) sensor devices, medical / healthcare devices, cars, unmanned aerial vehicles (UAVs) (so-called drones), and automated guided vehicles (AGVs). In yet another example, by implementing the communication device 5, wireless connectivity can also be provided in a wireless access point or wireless hotspot.

[0026] The communication device 5 comprises a high-frequency circuit 1, an antenna 2, an RFIC (Radio Frequency Integrated Circuit) 3, and a BBIC (Baseband Integrated Circuit) 4.

[0027] The high-frequency circuit 1 can transmit high-frequency signals between the antenna 2 and the RFIC 3. The circuit configuration of the high-frequency circuit 1 will be described later.

[0028] Antenna 2 is connected to the high-frequency circuit 1. Antenna 2 can receive high-frequency signals from the high-frequency circuit 1 and transmit them to the outside of the communication device 5. Furthermore, antenna 2 may receive high-frequency signals from outside the communication device 5 and supply them to the high-frequency circuit 1. Note that antenna 2 does not have to be included in the communication device 5. In addition, the communication device 5 may have one or more antennas in addition to antenna 2.

[0029] RFIC3 is an example of a signal processing circuit that processes high-frequency signals. Specifically, RFIC3 processes the transmission signal input from BBIC4 by upconversion or the like, and outputs the high-frequency transmission signal generated by this signal processing to high-frequency circuit 1. Furthermore, RFIC3 may process the high-frequency reception signal input via high-frequency circuit 1 by downconversion or the like, and output the received signal generated by this signal processing to BBIC4. RFIC3 may also have a control unit that controls switches and amplifiers in high-frequency circuit 1. Note that some or all of the control unit functions of RFIC3 may be included outside of RFIC3, for example, in BBIC4 or high-frequency circuit 1.

[0030] BBIC4 is a baseband signal processing circuit that processes signals using a frequency band lower than the high-frequency signal transmitted by the high-frequency circuit 1. Examples of signals processed by BBIC4 include image signals for image display and / or voice signals for communication via a speaker. Note that BBIC4 does not necessarily have to be included in the communication device 5.

[0031] [1.2. Circuit Configuration of High-Frequency Circuit 1] Next, the circuit configuration of the high-frequency circuit 1 according to this embodiment will be described with reference to Figure 1. Note that Figure 1 shows an exemplary circuit configuration, and the high-frequency circuit 1 can be implemented using any of the many different circuit implementations and circuit technologies. Therefore, the description of the high-frequency circuit 1 provided below should not be interpreted as restrictive.

[0032] The high-frequency circuit 1 includes a power amplifier circuit 10, a bias circuit 21, switch circuits 31 and 51, a coupler 32, a detection circuit 33, an integrating circuit 34, a voltage / current conversion circuit 35, an arithmetic circuit 36, a temperature sensor 37, elastic wave filters 41, 42 and 43, matching circuits 61, 62, 63, 64, 65, 66 and 67, an antenna connection terminal 100, a high-frequency input terminal 110, and a control terminal 120.

[0033] The antenna connection terminal 100 is an external connection terminal of the high-frequency circuit 1 and is a terminal for supplying high-frequency signals to the antenna 2. The antenna connection terminal 100 is connected to the antenna 2 outside the high-frequency circuit 1 and connected to the switch circuit 51 inside the high-frequency circuit 1.

[0034] The high-frequency input terminal 110 is an external connection terminal of the high-frequency circuit 1 and is a terminal for receiving high-frequency signals from the RFIC 3. The high-frequency input terminal 110 is connected to the RFIC 3 outside the high-frequency circuit 1 and to the input terminal of the power amplifier circuit 10 inside the high-frequency circuit 1.

[0035] The control terminal 120 is an external connection terminal of the high-frequency circuit 1 and is a terminal for receiving control signals from the RFIC 3. The control terminal 120 is connected to the RFIC 3 outside the high-frequency circuit 1 and to the bias circuit 21 inside the high-frequency circuit 1.

[0036] The power amplifier circuit 10 is connected between the high-frequency input terminal 110 and the elastic wave filters 41 to 43. Specifically, the input terminal of the power amplifier circuit 10 is connected to the high-frequency input terminal 110, and the output terminal of the power amplifier circuit 10 is switchably connected to the elastic wave filters 41 to 43 via the matching circuit 61, coupler 32, and switch circuit 31.

[0037] The power amplifier circuit 10 is a multi-stage amplifier circuit and a differential amplifier type amplifier circuit. The power amplifier circuit 10 comprises power amplifiers 11, 12 and 13 and transformers 14 and 15.

[0038] The power amplifier 11 is a drive stage amplifier and is included in the semiconductor component 71. The power amplifier 11 is connected between the high-frequency input terminal 110 and the transformer 14. Specifically, the input terminal of the power amplifier 11 is connected to the high-frequency input terminal 110, and the output terminal of the power amplifier 11 is connected to the transformer 14.

[0039] Power amplifiers 12 and 13 are power stage amplifiers and are included in semiconductor component 71. Power amplifiers 12 and 13 are a pair of power amplifiers connected in parallel and are connected between transformers 14 and 15. Specifically, the input terminals of power amplifiers 12 and 13 are connected to transformer 14, and the output terminals of power amplifiers 12 and 13 are connected to transformer 15.

[0040] The transformer 14 includes a primary coil 141 and a secondary coil 142 that can be coupled with the primary coil 141. One end of the primary coil 141 is connected to the output terminal of the power amplifier 11, and the other end of the primary coil 141 is connected to ground. One end of the secondary coil 142 is connected to the input terminal of the power amplifier 12, and the other end of the secondary coil 142 is connected to the input terminal of the power amplifier 13. The transformer 14 can convert the unbalanced signal (single-ended signal) amplified by the power amplifier 11 into a balanced signal (differential signal) and supply the balanced signal to the two power amplifiers 12 and 13, respectively.

[0041] The transformer 15 includes a primary coil 151 and a secondary coil 152 that can be coupled with the primary coil 151. One end of the primary coil 151 is connected to the output terminal of the power amplifier 12, and the other end of the primary coil 151 is connected to the output terminal of the power amplifier 13. One end of the secondary coil 152 is connected to the matching circuit 61, and the other end of the secondary coil 152 is connected to ground. The transformer 15 can convert the balanced signals amplified by the power amplifiers 12 and 13 into unbalanced signals.

[0042] It should be noted that the circuit configuration of the power amplifier circuit 10 is not limited to the configuration shown in FIG. 1. For example, the power amplifier circuit 10 does not need to be a multistage amplifier circuit, and may be a single-stage amplifier circuit. In this case, the power amplifier circuit 10 does not need to include the power amplifier 11. Also, for example, the power amplifier circuit 10 does not need to be a differential amplification type amplifier circuit. In this case, the power amplifier circuit 10 does not need to include the power amplifier 13 and the transformers 14 and 15. Also, for example, in the power amplifier circuit 10, the two high-frequency signals amplified by the power amplifiers 12 and 13 do not need to be balanced signals, and may be two signals having a phase difference of 90 degrees. In this case, each of the transformers 14 and 15 may be replaced with a quadrature hybrid circuit. Also, the power amplifier circuit 10 may be a Doherty amplifier circuit.

[0043] The bias circuit 21 is included in the semiconductor component 72 and can supply a bias current to the power amplifier circuit 10.

[0044] The switch circuit 31 is included in the semiconductor component 73 and connected between the power amplifier circuit 10 and the elastic wave filters 41 to 43. Specifically, the switch circuit 31 includes a common terminal 310 and selection terminals 311, 312, and 313. The common terminal 310 is connected to the output terminal of the power amplifier circuit 10 via the coupler 32 and the matching circuit 61. The selection terminal 311 is an example of a first selection terminal, and connected to the elastic wave filter 41 via the matching circuit 62. The selection terminal 312 is an example of a second selection terminal, and connected to the elastic wave filter 42 via the matching circuit 63. The selection terminal 313 is connected to the elastic wave filter 43 via the matching circuit 64. In such a connection configuration, the switch circuit 31 can selectively connect the common terminal 310 to the selection terminals 311 to 313, for example, based on a control signal from the RFIC 3. The switch circuit 31 is configured by, for example, an SP3T (Single-Pole Triple-Throw) type switch circuit. It should be noted that the switch circuit 31 does not need to be included in the high-frequency circuit 1.

[0045] The coupler 32 is included in the semiconductor component 73 and connected between the power amplifier circuit 10 and the switch circuit 31. Specifically, the input port of the coupler 32 is connected to one end of the secondary coil 152 of the transformer 15 via the matching circuit 61. The output port of the coupler 32 is connected to the common terminal 310 of the switch circuit 31. The coupled port 321 of the coupler 32 is connected to the detection circuit 33. The coupler 32 can output a part of the high-frequency signal flowing from the secondary coil 152 of the transformer 15 to the common terminal 310 of the switch circuit 31 as a voltage signal from the coupled port 321.

[0046] The detection circuit 33 is included in the semiconductor component 73 and connected between the coupler 32 and the integration circuit 34. Specifically, the input end of the detection circuit 33 is connected to the coupled port 321 of the coupler 32, and the output end of the detection circuit 33 is connected to the input end of the integration circuit 34. The detection circuit 33 can detect the envelope of the output signal of the coupler 32. The circuit configuration of the detection circuit 33 will be described later with reference to FIG. 2.

[0047] The integration circuit 34 is included in the semiconductor component 73 and connected between the detection circuit 33 and the voltage / current conversion circuit 35. Specifically, the input end of the integration circuit 34 is connected to the output end of the detection circuit 33, and the output end of the integration circuit 34 is connected to the input end of the voltage / current conversion circuit 35. The integration circuit 34 can convert the output signal of the detection circuit 33 into an integrated signal per unit time (moving average signal). The circuit configuration of the integration circuit 34 will be described later with reference to FIG. 2.

[0048] The voltage / current conversion circuit 35 is included in the semiconductor component 73 and connected between the integration circuit 34 and the arithmetic circuit 36. Specifically, the input end of the voltage / current conversion circuit 35 is connected to the output end of the integration circuit 34, and the output end of the voltage / current conversion circuit 35 is connected to the input end of the arithmetic circuit 36. The voltage / current conversion circuit 35 can convert the output signal of the integration circuit 34 from a voltage signal to a current signal. Note that the voltage / current conversion circuit 35 does not have to be included in the high-frequency circuit 1. The circuit configuration of the voltage / current conversion circuit 35 will be described later with reference to FIG. 2.

[0049] The arithmetic circuit 36 ​​is included in the semiconductor component 73 and is connected between the voltage / current conversion circuit 35 and the bias circuit 21. Specifically, the input terminal of the arithmetic circuit 36 ​​is connected to the output terminal of the voltage / current conversion circuit 35, and the output terminal of the arithmetic circuit 36 ​​is connected to the bias circuit 21. The arithmetic circuit 36 ​​can control the bias current based on the output signal of the integration circuit 34 and a predetermined threshold. Specifically, the arithmetic circuit 36 ​​can reduce the bias current when the output signal of the integration circuit 34 is greater than the predetermined threshold. For example, the arithmetic circuit 36 ​​may reduce the bias current according to the difference between the output signal and the predetermined threshold when the output signal of the integration circuit 34 is greater than the predetermined threshold. In this case, the arithmetic circuit 36 ​​may gradually reduce the bias current or reduce it in a step function manner. Alternatively, for example, the arithmetic circuit 36 ​​may maintain a constant bias current when the output signal of the integration circuit 34 is below the predetermined threshold. Furthermore, the arithmetic circuit 36 ​​may maintain a first bias current when the output signal of the integrating circuit 34 is below a predetermined threshold, and may maintain a second bias current (including 0) that is smaller than the first bias current when the output signal of the integrating circuit 34 is greater than the predetermined threshold.

[0050] The predetermined threshold used in the arithmetic circuit 36 ​​may be changed according to the power class. For example, the predetermined threshold may be changed so that the second power class (e.g., power class 3), which is defined by a second maximum output power lower than the first maximum output power, is smaller than the first power class (e.g., power class 2, power class 1.5, power class 1, etc.), which is defined by a first maximum output power.

[0051] Furthermore, the predetermined threshold used in the calculation circuit 36 ​​may be changed according to the elastic wave filter connected to the power amplification circuit 10 by the switch circuit 31. For example, when the common terminal 310 is connected to the selection terminal 311, a predetermined threshold suitable for the elastic wave filter 41 may be used. Also, for example, when the common terminal 310 is connected to the selection terminal 312, a predetermined threshold suitable for the elastic wave filter 42 may be used. Also, for example, when the common terminal 310 is connected to the selection terminal 313, a predetermined threshold suitable for the elastic wave filter 43 may be used.

[0052] Furthermore, the predetermined threshold used in the calculation circuit 36 ​​may be changed according to the temperature detected by the temperature sensor 37. For example, the predetermined threshold may be changed so that the threshold decreases as the detected temperature increases. Alternatively, for example, a smaller threshold may be used as the predetermined threshold when the detected temperature is higher than the threshold temperature, and a larger threshold may be used as the predetermined threshold when the detected temperature is lower than the threshold temperature.

[0053] The temperature sensor 37 is included in the semiconductor component 73 and can detect temperature. Note that the temperature sensor 37 does not necessarily have to be included in the high-frequency circuit 1.

[0054] The elastic wave filter 41 is an example of a first elastic wave filter and is a bandpass filter having a passband that includes the transmission band of band A. The elastic wave filter 41 is connected between the switch circuits 31 and 51. Specifically, one end of the elastic wave filter 41 is connected to the select terminal 311 of the switch circuit 31 via a matching circuit 62, and the other end of the elastic wave filter 41 is connected to the select terminal 511 of the switch circuit 51 via a matching circuit 65. The elastic wave filter 41 has power withstand capability corresponding to the first power class.

[0055] The elastic wave filter 42 is an example of a second elastic wave filter and is a bandpass filter having a passband that includes the transmission bandwidth of band B. The elastic wave filter 42 is connected between the switch circuits 31 and 51. Specifically, one end of the elastic wave filter 42 is connected to the select terminal 312 of the switch circuit 31 via a matching circuit 63, and the other end of the elastic wave filter 42 is connected to the select terminal 512 of the switch circuit 51 via a matching circuit 66. The elastic wave filter 42 has power withstand capability corresponding to the second power class, but does not have power withstand capability corresponding to the first power class. Note that the elastic wave filter 42 does not necessarily have to be included in the high-frequency circuit 1.

[0056] The elastic wave filter 43 is a bandpass filter having a passband that includes the transmission bandwidth of band C. The elastic wave filter 43 is connected between the switch circuits 31 and 51. Specifically, one end of the elastic wave filter 43 is connected to the select terminal 313 of the switch circuit 31 via a matching circuit 64, and the other end of the elastic wave filter 43 is connected to the select terminal 513 of the switch circuit 51 via a matching circuit 67. The elastic wave filter 43 has power withstand capability corresponding to the first power class. Note that the elastic wave filter 43 does not necessarily have to be included in the high-frequency circuit 1.

[0057] Bands A to C are frequency bands for communication systems built using Radio Access Technology (RAT). Bands A to C are predefined by standardization bodies (e.g., 3GPP and IEEE (Institute of Electrical and Electronics Engineers)). Examples of communication systems include 5GNR (5th Generation New Radio) systems, 4GLTE (4th Generation Long Term Evolution) systems, and 2GGSM (2nd Generation Global System for Mobile communications). In this embodiment, bands A and C correspond to power class 2. On the other hand, band B corresponds to power class 3 but not power class 2.

[0058] The switch circuit 51 is included in the semiconductor component 75 and is connected between the elastic wave filters 41-43 and the antenna connection terminal 100. Specifically, the switch circuit 51 includes a common terminal 510 and select terminals 511, 512, and 513. The common terminal 510 is connected to the antenna connection terminal 100. The select terminal 511 is connected to the elastic wave filter 41 via a matching circuit 65. The select terminal 512 is connected to the elastic wave filter 42 via a matching circuit 66. The select terminal 513 is connected to the elastic wave filter 43 via a matching circuit 67. In this connection configuration, the switch circuit 51 can selectively connect the common terminal 510 to the select terminals 511-513, for example, based on a control signal from the RFIC 3. The switch circuit 51 is composed of, for example, an SP3T type switch circuit. Note that the switch circuit 51 does not necessarily have to be included in the high-frequency circuit 1.

[0059] The matching circuits (matching networks) 61 to 67 can convert impedance and achieve impedance matching. Matching circuit 61 is connected between the transformer 15 and the switch circuit 31. Matching circuits 62 to 64 are connected between the select terminals 311 to 313 of the switch circuit 31 and the elastic wave filters 41 to 43, respectively. Matching circuits 65 to 67 are connected between the elastic wave filters 41 to 43 and the select terminals 511 to 513 of the switch circuit 51, respectively. Note that some or all of the matching circuits 61 to 67 do not need to be included in the high-frequency circuit 1.

[0060] [1.3. Circuit Configuration of Detection Circuit 33, Integrating Circuit 34, Voltage / Current Conversion Circuit 35, and Calculation Circuit 36] Next, the circuit configuration of the detection circuit 33, integrating circuit 34, voltage / current conversion circuit 35, and calculation circuit 36 ​​will be described with reference to Figure 2. Figure 2 is a circuit diagram of the detection circuit 33, integrating circuit 34, voltage / current conversion circuit 35, and calculation circuit 36 ​​according to this embodiment.

[0061] Figure 2 shows an exemplary circuit configuration, and the detection circuit 33, integration circuit 34, voltage / current conversion circuit 35, and arithmetic circuit 36 ​​can be implemented using a wide variety of circuit implementations and circuit technologies. Therefore, the descriptions of the detection circuit 33, integration circuit 34, voltage / current conversion circuit 35, and arithmetic circuit 36 ​​provided below should not be interpreted as restrictive.

[0062] The detection circuit 33 includes a diode D31 and a capacitor C31. Diode D31 is connected between the input terminal and the output terminal of the detection circuit 33. Capacitor C31 is connected between the path connecting diode D31 and the output terminal of the detection circuit 33 and ground.

[0063] The integrating circuit 34 includes a resistor R41 and capacitors C41 and C42. Resistor R41 is connected between the input terminal and output terminal of the integrating circuit 34. Capacitor C41 is connected between the path connecting resistor R41 and the input terminal of the integrating circuit 34 and ground. Capacitor C42 is connected between the path connecting resistor R41 and the output terminal of the integrating circuit 34 and ground. Note that capacitor C41 does not necessarily have to be included in the integrating circuit 34.

[0064] The voltage / current conversion circuit 35 includes an operational amplifier U51, transistors M51, M52, M53, and M54, and a resistor R51. The inverting input terminal of operational amplifier U51 is connected to the input terminal of the voltage / current conversion circuit 35. The non-inverting input terminal of operational amplifier U51 is connected to the drain terminal of transistor M51. The output terminal of operational amplifier U51 is connected to the gate terminals of transistors M51 and M52. The drain terminal of transistor M51 is connected to the non-inverting input terminal of operational amplifier U51. A power supply terminal is connected to the source terminal of transistor M51, and a power supply voltage is applied. The gate terminal of transistor M51 is connected to the output terminal of operational amplifier U51 and the gate terminal of transistor M52. The drain terminal of transistor M52 is connected to the source terminal of transistor M53. A power supply terminal is connected to the source terminal of transistor M52, and a power supply voltage is applied. The gate terminal of transistor M52 is connected to the output terminal of op-amp U51 and the gate terminal of transistor M51. Resistor R51 is connected between the path between the non-inverting input terminal of op-amp U51 and the drain terminal of transistor M51 and ground. The drain terminal of transistor M53 is connected to ground. The source terminal of transistor M53 is connected to the drain terminal of transistor M52. The gate terminal of transistor M53 is connected to the gate terminal of transistor M54. In transistor M53, the source terminal is short-circuited (connected) to the gate terminal. The drain terminal of transistor M54 is connected to ground. The source terminal of transistor M54 is connected to the output terminal of the voltage / current conversion circuit 35. The gate terminal of transistor M54 is connected to the gate terminal of transistor M53.

[0065] The arithmetic circuit 36 ​​includes transistors M61, M62, M63, and M64 and a current source I61.

[0066] Transistor M61 is an example of a first transistor and is a p-channel FET (Field Effect Transistor). The drain terminal (an example of the first terminal) of transistor M61 is connected to the input terminal of the arithmetic circuit 36. The source terminal (an example of the second terminal) of transistor M61 is connected to the power supply terminal and the power supply voltage is applied. The gate terminal (an example of the control terminal) of transistor M61 is connected to the gate terminal of transistor M62. In addition, in transistor M61, the drain terminal is short-circuited (connected) to the gate terminal.

[0067] Transistor M62 is an example of a second transistor and is a p-channel FET. The drain terminal (an example of the first terminal) of transistor M62 is connected to the current source I61. The source terminal (an example of the second terminal) of transistor M62 is connected to the power supply terminal and the power supply voltage is applied. The gate terminal (an example of the control terminal) of transistor M62 is connected to the gate terminal of transistor M61.

[0068] Transistor M63 is an example of a third transistor and is an n-channel FET. The drain terminal (an example of the first terminal) of transistor M63 is connected to the path between the drain terminal of transistor M62 and the current source I61. The source terminal (an example of the second terminal) of transistor M63 is connected to ground. The gate terminal (an example of the control terminal) of transistor M63 is connected to the gate terminal of transistor M64. In addition, in transistor M63, the drain terminal is short-circuited (connected) to the gate terminal.

[0069] Transistor M64 is an example of a fourth transistor and is an n-channel FET. The drain terminal (an example of the first terminal) of transistor M64 is connected to the output terminal of the arithmetic circuit 36. The source terminal (an example of the second terminal) of transistor M64 is connected to ground. The gate terminal (an example of the control terminal) of transistor M64 is connected to the gate terminal of transistor M63.

[0070] Note that transistors M61 to M64 are not limited to FETs. For example, transistors M61 to M64 may be bipolar transistors. In this case, the drain, source, and gate terminals are replaced by the collector, emitter, and base terminals.

[0071] The current source I61 is connected between the drain terminal of transistor M62 and ground, and can supply a threshold current Ith.

[0072] Here, we will explain the operation of the arithmetic circuit 36 ​​when the current mirror ratio of the current mirror circuit composed of transistors M61 and M62 and the current mirror circuit composed of transistors M63 and M64 are both 1:1.

[0073] The input current Iin of the arithmetic circuit 36 ​​is copied to the Miller current Imr (Imr = Iin) by transistors M61 and M62. If the Miller current Imr is greater than the threshold current Ith, the difference between the Miller current Imr and the threshold current Ith flows to the drain terminal of transistor M63 as a shunt current Iout (= Imr - Ith) and is copied to the sink current Isink. On the other hand, if the Miller current Imr is less than or equal to the threshold current Ith, the shunt current Iout becomes 0 and the sink current Isink also becomes 0. Then, the difference between the supply current IB0 of the bias circuit 21 and the sink current Isink of the arithmetic circuit 36 ​​is supplied to the power amplifiers 11, 12 and 13 as a bias current IB (IB0 - Isink).

[0074] As a result, as shown in Figures 3A and 3B, when the input current Iin is greater than the threshold current Ith, the difference between the input current Iin and the threshold current Ith is supplied as the sink current Isink, and the bias current IB decreases in accordance with the sink current Isink. On the other hand, when the input current Iin is less than or equal to the threshold current Ith, the sink current Isink becomes 0, and the bias current IB is maintained at a constant level.

[0075] In such an arithmetic circuit 36, the threshold current Ith may be changed according to the power class. For example, a larger threshold current Ith may be used in the first power class (e.g., power class 2, power class 1.5, power class 1, etc.), and a smaller threshold current Ith may be used in the second power class (e.g., power class 3). More specifically, the threshold current Ith may be changed as shown in Table 1 below.

[0076]

[0077] Thus, in bands A and C, which correspond to power class 2, a larger threshold current is used than in band B, which corresponds to power class 3. As a result, elastic wave filters 41 and 43 are allowed to handle higher integrated power, while elastic wave filter 42 is only allowed to handle lower integrated power. Therefore, the input integrated power is limited according to the breakdown limit (power withstand capability) of elastic wave filters 41 to 43, suppressing distortion of the transmitted signal while preventing the breakdown of elastic wave filters 41 to 43.

[0078] In addition, bands A and C may also be used in power class 3. In such cases, a smaller threshold current Ith may be used. In other words, in power class 3, a smaller threshold current Ith may also be used for elastic wave filters 41 and 43. This allows for limiting the power of the transmitted signal when an unnecessarily high integrated power is input to elastic wave filters 41 and 43 in power class 3, thereby suppressing the degradation of elastic wave filters 41 and 43.

[0079] Furthermore, the current mirror ratio of transistors M61 and M62 in the arithmetic circuit 36 ​​may be variable. In this case, the current mirror ratio may be changed according to the power class, similar to the threshold current Ith. For example, with the threshold current Ith fixed at 100 μA, the same effect as changing the threshold current Ith can be obtained by changing the current mirror ratio as shown in Table 2 below.

[0080]

[0081] [1.4. Implementation Example of High-Frequency Circuit 1] Next, an implementation example of the high-frequency circuit 1 will be described with reference to Figure 4. Figure 4 is a layout diagram of the high-frequency circuit 1 according to this embodiment. In Figure 4, each component is labeled so that the arrangement of each component can be easily understood, but in reality, each component does not need to be labeled.

[0082] Note that Figure 4 shows an exemplary layout, and the high-frequency circuit 1 can be implemented using a wide variety of circuit implementations and circuit technologies. Therefore, the description of the high-frequency circuit 1 provided below should not be interpreted as restrictive.

[0083] The semiconductor component 71 (PA) is a semiconductor integrated circuit including power amplifiers 11-13 and a transformer 14, and is arranged on the main surface 90a of the module substrate 90. For example, silicon germanium (SiGe) or gallium arsenide (GaAs) can be used as the semiconductor material for the semiconductor component 71. In this case, some or all of the power amplifiers 11-13 can be composed of heterojunction bipolar transistors (HBTs). Alternatively, gallium nitride (GaN) or silicon carbide (SiC) can be used as the semiconductor material for the semiconductor component 71. In this case, some or all of the power amplifiers 11-13 can be composed of HEMTs (High Electron Mobility Transistors) or MESFETs (Metal-Semiconductor Field Effect Transistors). Alternatively, silicon single crystal (Si) can be used as the semiconductor material for the power amplifiers 11-13. In this case, some or all of the power amplifiers 11 to 13 may be made of CMOS (Complementary Metal Oxide Semiconductor) and may be manufactured by an SOI (Silicon on Insulator) process. Note that power amplifier 11 and power amplifiers 12 and 13 may be contained within separate semiconductor components.

[0084] The transformer 15 is formed by wiring on multiple layers of the module substrate 90. For example, a primary coil 151 may be formed by wiring on one or more of the multiple layers, and a secondary coil 152 may be formed by wiring on one or more other of the multiple layers.

[0085] The semiconductor component 72 (PAC) is a semiconductor integrated circuit including a bias circuit 21, and is arranged on the main surface 90a of the module substrate 90. The semiconductor material for the semiconductor component 72 can be, but is not limited to, silicon single crystal (Si), gallium nitride (GaN), or silicon carbide (SiC).

[0086] The semiconductor component 73 (BSSW) is a semiconductor integrated circuit including a switch circuit 31, a coupler 32, a detection circuit 33, an integrating circuit 34, a voltage / current conversion circuit 35, an arithmetic circuit 36, and a temperature sensor 37, and is arranged on the main surface 90a of the module substrate 90. As the semiconductor material for the semiconductor component 73, for example, silicon single crystal (Si), gallium nitride (GaN), or silicon carbide (SiC) can be used, but is not limited to these.

[0087] The elastic wave filters 41-43 (SAW) are surface acoustic wave (SAW) filters and are arranged on the main surface 90a of the module substrate 90. Note that the elastic wave filters 41-43 may also be bulk acoustic wave (BAW) filters. Furthermore, the elastic wave filters 41-43 may be a combination of a SAW filter and / or a BAW filter and an LC filter and / or a dielectric filter.

[0088] The semiconductor component 75 (ANTSW) is a semiconductor integrated circuit including a switch circuit 51, and is arranged on the main surface 90a of the module substrate 90. The semiconductor material for the semiconductor component 75 can be, for example, silicon single crystal (Si), gallium nitride (GaN), or silicon carbide (SiC), but is not limited to these.

[0089] Matching circuit 61 is mounted on the main surface 90a of the module board 90 using two chip capacitors (C). Each of matching circuits 62 to 67 is mounted on the main surface 90a of the module board 90 using a chip inductor (L). Note that the configuration of matching circuits 61 to 67 is not limited to these.

[0090] Chip capacitors and chip inductors refer to discrete SMDs (Surface Mount Devices) that constitute capacitors and inductors. Note that the capacitors and inductors included in matching circuits 61-67 are not limited to chip capacitors and chip inductors. For example, some or all of the capacitors and inductors included in matching circuits 61-67 may be formed by wiring on or within the module board 90, or they may be included in an Integrated Passive Device (IPD).

[0091] In Figure 4, the circuit components of the high-frequency circuit 1 are not arranged on the main surface of the module substrate 90 opposite to the main surface 90a, but this is not limited to this. For example, one or both of the semiconductor components 72 and 73 may be arranged on the main surface of the module substrate 90 opposite to the main surface 90a. Also, the semiconductor component 75 may be arranged on the main surface of the module substrate 90 opposite to the main surface 90a.

[0092] Furthermore, semiconductor components 72 and 73 may be integrated into a single semiconductor component. For example, as shown in Figure 5, semiconductor component 72A (PAC&BSSW) may be a semiconductor integrated circuit including a bias circuit 21, a switch circuit 31, a coupler 32, a detection circuit 33, an integration circuit 34, a voltage / current conversion circuit 35, an arithmetic circuit 36, and a temperature sensor 37.

[0093] [1.5. Relationship between input signals and fracture limits of elastic wave filters 41-43] Next, the relationship between the input signals and fracture limits of the elastic wave filters will be explained with reference to Figures 6A, 6B, and 6C. Figures 6A to 6C are graphs showing the relationship between the input signals and fracture limits of the elastic wave filters.

[0094] An elastic wave filter is destroyed when the integral value of the power of the input signal exceeds the failure limit. For example, in Figure 6A, a transmission signal with greater power is input instantaneously, but the integral signal does not exceed the failure limit, so the elastic wave filter is not destroyed. On the other hand, in Figure 6B, a transmission signal with greater power is input intermittently, and the integral signal increases intermittently, exceeding the failure limit. Therefore, unless the power of the transmission signal is reduced, the elastic wave filter will be destroyed. Also, in Figure 6C, a transmission signal with less power is input continuously, and the integral signal increases continuously, exceeding the failure limit. Therefore, unless the power of the transmission signal is reduced, the elastic wave filter will be destroyed.

[0095] Therefore, when the integrated signal is greater than a threshold lower than the breakdown limit, the breakdown of the elastic wave filter can be effectively suppressed by reducing the bias current and thereby decreasing the power of the transmitted signal. Conversely, when the integrated signal is below the threshold, distortion of the transmitted signal can be suppressed by maintaining a constant bias current and not reducing the power of the transmitted signal.

[0096] [1.6. Summary] As described above, the high-frequency circuit 1 according to this embodiment comprises a power amplifier circuit 10, an elastic wave filter 41 connected to the output terminal of the power amplifier circuit 10, a bias circuit 21 configured to supply bias current to the power amplifier circuit 10, a coupler 32 connected between the power amplifier circuit 10 and the elastic wave filter 41, a detection circuit 33 connected to the coupling port 321 of the coupler 32, an integrating circuit 34 connected to the output terminal of the detection circuit 33, and an arithmetic circuit 36 ​​configured to control the bias current based on the output signal of the integrating circuit 34 and a predetermined threshold, wherein the arithmetic circuit 36 ​​is configured to reduce the bias current when the output signal of the integrating circuit 34 is greater than a predetermined threshold.

[0097] According to this, the bias current is reduced when the output signal of the integrating circuit 34 is greater than a predetermined threshold. Therefore, it is possible to suppress the input integrated power of the transmitted signal to the elastic wave filter 41 from exceeding the breakdown limit, thereby suppressing the breakdown of the elastic wave filter 41. In particular, by using the output signal of the integrating circuit 34, it is possible to suppress the reduction in bias current for temporary input of higher power transmitted signals, and this is also effective in suppressing distortion of the transmitted signal.

[0098] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the calculation circuit 36 ​​may be configured to reduce the bias current according to the difference between the output signal of the integration circuit 34 and the predetermined threshold when the output signal is greater than a predetermined threshold.

[0099] According to this, if the difference between the output signal of the integrating circuit 34 and a predetermined threshold increases, the bias signal can be reduced further, and a balance can be struck between suppressing distortion of the transmitted signal and suppressing damage to the elastic wave filter 41.

[0100] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the arithmetic circuit 36 ​​may be configured to maintain a constant bias current when the output signal of the integrating circuit 34 is below a predetermined threshold.

[0101] According to this, as long as the output signal of the integrating circuit 34 does not exceed a predetermined threshold, the power of the transmitted signal is not limited, and thus distortion of the transmitted signal can be suppressed.

[0102] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the calculation circuit 36 ​​may be configured to change a predetermined threshold according to the power class.

[0103] According to this, a predetermined threshold suitable for the power class can be used, and a balance can be struck between suppressing distortion of the transmitted signal and suppressing damage to the elastic wave filter 41.

[0104] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the predetermined threshold may be smaller for the second power class than for the first power class, the first power class may be defined by the first maximum output power, and the second power class may be defined by a second maximum output power that is lower than the first maximum output power.

[0105] According to this, using a larger predetermined threshold in the high-power class can more effectively suppress distortion of the transmitted signal. Also, using a smaller predetermined threshold in the low-power class can more effectively suppress the breakdown of the elastic wave filter 41. Furthermore, even when the elastic wave filter 41 is compatible with the high-power class, the input of the transmitted signal with unnecessary power to the elastic wave filter 41 can be limited in the low-power class, thereby suppressing the degradation of the elastic wave filter 41.

[0106] For example, the high-frequency circuit 1 according to this embodiment may further include an elastic wave filter 42 and a switch circuit 31 including a common terminal 310 connected to the output terminal of the power amplifier circuit 10, a select terminal 311 connected to the elastic wave filter 41, and a select terminal 312 connected to the elastic wave filter 42, and the predetermined threshold may differ depending on whether the common terminal 310 is connected to the select terminal 311 or to the select terminal 312.

[0107] According to this, a predetermined threshold value corresponding to the characteristics of the elastic wave filters 41 and 42 to which the transmitted signal is input can be used, and the destruction of the elastic wave filters 41 and 42 can be suppressed more effectively.

[0108] For example, in the high-frequency circuit 1 according to this embodiment, the coupler 32 may be connected between the output terminal of the power amplifier circuit 10 and the common terminal 310 of the switch circuit 31.

[0109] According to this, the coupler 32 can detect the transmitted signal regardless of whether the elastic wave filter 41 or 42 is used. In other words, the coupler 32 can be shared between the elastic wave filters 41 and 42, and the number of couplers can be reduced.

[0110] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the coupler 32 may be included in the same semiconductor component 73 as the switch circuit 31.

[0111] According to this design, the coupler 32 can be placed near the elastic wave filters 41 and 42, allowing for more accurate detection of the transmission signals input to the elastic wave filters 41 and 42. Furthermore, there is no need to mount any new components for the coupler 32, which contributes to miniaturization of the high-frequency circuit 1.

[0112] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the detection circuit 33, the integration circuit 34, and the arithmetic circuit 36 ​​may be included in the semiconductor component 73.

[0113] According to this configuration, signal processing for the detection circuit 33, integration circuit 34, and arithmetic circuit 36 ​​is performed within the semiconductor component 73, and the output signal of the arithmetic circuit 36 ​​is output to the bias circuit 21. Since the output signal of the arithmetic circuit 36 ​​is a relatively low-frequency signal, signal quality degradation can be suppressed more effectively than when a high-frequency signal is transmitted to another semiconductor component. Furthermore, there is no need to mount new components for the detection circuit 33, integration circuit 34, and arithmetic circuit 36, which contributes to the miniaturization of the high-frequency circuit 1.

[0114] For example, the high-frequency circuit 1 according to this embodiment may further include a temperature sensor 37 included in the semiconductor component 73, and the calculation circuit 36 ​​may be configured to change a predetermined threshold according to the temperature detected by the temperature sensor 37.

[0115] According to this, a predetermined threshold can be changed according to the temperature of the elastic wave filters 41 and 42, and it is possible to respond to changes in the fracture characteristics of the elastic wave filters 41 and 42 due to temperature changes.

[0116] For example, the high-frequency circuit 1 according to this embodiment may further include a voltage / current conversion circuit 35 configured to convert the output signal of the integrating circuit 34 from a voltage signal to a current signal, and the arithmetic circuit 36 ​​may be configured to control the bias current based on the output signal of the integrating circuit 34 which has been converted to a current signal.

[0117] According to this, a current control circuit can be used in the arithmetic circuit 36, and the responsiveness of the arithmetic circuit 36 ​​can be improved compared to when a voltage control circuit is used in the arithmetic circuit 36.

[0118] From another perspective, the high-frequency circuit 1 according to this embodiment comprises a power amplifier circuit 10, an elastic wave filter 41 connected to the output terminal of the power amplifier circuit 10, a bias circuit 21 configured to supply bias current to the power amplifier circuit 10, a coupler 32 connected between the power amplifier circuit 10 and the elastic wave filter 41, a detection circuit 33 connected to the coupling port 321 of the coupler 32, an integrating circuit 34 connected to the output terminal of the detection circuit 33, a voltage / current conversion circuit 35 connected to the output terminal of the integrating circuit 34, and an arithmetic circuit 36 ​​connected between the voltage / current conversion circuit 35 and the bias circuit 21, wherein the arithmetic circuit 36 ​​is connected to the first terminal connected to the output terminal of the voltage / current conversion circuit 35 and to the power supply terminal. The circuit includes a transistor M61 having a second terminal and a control terminal, a transistor M62 having a first terminal connected to a current source I61, a second terminal connected to a power supply terminal, and a control terminal connected to the control terminal of transistor M61, a first terminal connected to a path between the first terminal of transistor M62 and the current source I61, a second terminal connected to ground, and a control terminal, and a transistor M64 having a first terminal connected to a control terminal, a first terminal connected to a bias circuit 21, a second terminal connected to ground, and a control terminal connected to the control terminal of transistor M63.

[0119] According to this, the input current Iin of the arithmetic circuit 36, converted from the output signal of the integrating circuit 34 by the voltage / current conversion circuit 35, is copied to a mirror current Imr by transistors M61 and M62. When the mirror current Imr is greater than the threshold current Ith supplied from the current source I61, a sink current Isink is supplied to the bias circuit 21. In other words, the arithmetic circuit 36 ​​can reduce the bias current IB and reduce the power of the transmitted signal when the output signal of the integrating circuit 34 is greater than a predetermined threshold. As a result, it is possible to suppress the input integral power of the transmitted signal to the elastic wave filter 41 from exceeding the breakdown limit, thereby suppressing the breakdown of the elastic wave filter 41. In particular, by using the output signal of the integrating circuit 34, it is possible to suppress the reduction of the bias current for temporary inputs of higher power transmitted signals, and it is also effective in suppressing distortion of the transmitted signal. Furthermore, the arithmetic circuit 36 ​​can be configured with two current mirror circuits, which suppresses the complexity of the arithmetic circuit 36 ​​and improves responsiveness.

[0120] For example, in the high-frequency circuit 1 according to this embodiment, transistors M61 and M62 may be p-channel FETs, transistors M63 and M64 may be n-channel FETs, the first terminal of transistors M61 to M64 may be the drain terminal, the second terminal of transistors M61 to M64 may be the source terminal, and the control terminal of transistors M61 to M64 may be the gate terminal.

[0121] According to this, since an FET is used in the arithmetic circuit 36, it becomes easy to include the arithmetic circuit 36 ​​in the same semiconductor component as the switch circuit 31.

[0122] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the current source I61 may be configured to supply a threshold current Ith that changes according to the power class.

[0123] According to this, a threshold current Ith suitable for the power class can be used, and a balance can be struck between suppressing distortion of the transmitted signal and suppressing the breakdown of the elastic wave filter 41.

[0124] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, transistors M61 and M62 may constitute a current mirror circuit with a variable current mirror ratio, and the current mirror circuit may be configured to change the current mirror ratio according to the power class.

[0125] According to this, a current mirror ratio suitable for the power class can be used, achieving an effect similar to that of changing the threshold current Ith.

[0126] (Other Embodiments) The high-frequency circuit according to the present invention has been described above based on embodiments, but the high-frequency circuit according to the present invention is not limited to the above embodiments. Other embodiments realized by combining any of the components in the above embodiments, modified versions obtained by applying various modifications to the above embodiments that a person skilled in the art can conceive of without departing from the spirit of the present invention, and various devices incorporating the above high-frequency circuit are also included in the present invention.

[0127] For example, in the circuit configuration of the high-frequency circuit 1 according to the above embodiment, other circuit elements and wiring may be inserted between the paths connecting each circuit element and signal path disclosed in the drawing. For example, a coupler different from the coupler 32 may be connected between the switch circuit 51 and the antenna connection terminal 100.

[0128] The circuit configuration of the arithmetic circuit 36 ​​according to the above embodiment is not limited to the circuit configuration shown in Figure 2. For example, the arithmetic circuit 36 ​​may be a voltage control circuit or a digital control circuit. In this case, the high-frequency circuit 1 does not have to include a voltage / current conversion circuit 35, and may include an analog / digital conversion circuit and / or a digital / analog conversion circuit as needed. In such a case, the arithmetic circuit 36 ​​may include an inverter that inverts the polarity of the input voltage, and the inverted input voltage may be compared with a threshold voltage. In this case, the arithmetic circuit 36 ​​may reduce the bias current when the inverted input voltage is smaller than the threshold voltage.

[0129] This invention can be widely used in communication devices such as mobile phones as a high-frequency circuit placed in the front end.

[0130] 1. High-frequency circuit 2. Antenna 3. RFIC 4. BBIC 5. Communication device 10. Power amplification circuit 11, 12, 13. Power amplifier 14, 15. Transformer 21. Bias circuit 31, 51. Switch circuit 32. Coupler 33. Detection circuit 34. Integrating circuit 35. Voltage / current conversion circuit 36. Arithmetic circuit 37. Temperature sensor 41, 42, 43. Elastic wave filter 61, 62, 63, 64, 65, 66, 67. Matching circuit 71, 72, 72A, 73, 75. Semiconductor component 90. Module board 90a Main surface 100. Antenna connection terminal 110. High-frequency input terminal 120. Control terminal 141, 151. Primary coil 142, 152. Secondary coil 310, 510. Common terminal 311, 312, 313, 511, 512, 513 Selection terminals 321 Coupling port C31, C41, C42 Capacitors D31 Diode I61 Current source M51, M52, M53, M54, M61, M62, M63, M64 Transistors R41, R51 Resistors U51 Operational amplifier

Claims

1. A high-frequency circuit comprising: a power amplifier circuit; a first elastic wave filter connected to the output terminal of the power amplifier circuit; a bias circuit configured to supply a bias current to the power amplifier circuit; a coupler connected between the power amplifier circuit and the first elastic wave filter; a detection circuit connected to the coupling port of the coupler; an integrator connected to the output terminal of the detection circuit; and a calculation circuit configured to control the bias current based on the output signal of the integrator circuit and a predetermined threshold, wherein the calculation circuit is configured to reduce the bias current when the output signal of the integrator circuit is greater than the predetermined threshold.

2. The high-frequency circuit according to claim 1, wherein the calculation circuit is configured to reduce the bias current in accordance with the difference between the output signal and the predetermined threshold when the output signal of the integration circuit is greater than the predetermined threshold.

3. The high-frequency circuit according to claim 1 or 2, wherein the calculation circuit is configured to maintain the bias current constant when the output signal of the integration circuit is below a predetermined threshold.

4. The high-frequency circuit according to any one of claims 1 to 3, wherein the calculation circuit is configured to change the predetermined threshold according to the power class.

5. The high-frequency circuit according to any one of claims 1 to 3, wherein the predetermined threshold is smaller for the second power class than for the first power class, the first power class is defined by a first maximum output power, and the second power class is defined by a second maximum output power lower than the first maximum output power.

6. The high-frequency circuit further comprises: a second elastic wave filter; a switch circuit including a common terminal connected to the output terminal of the power amplifier circuit, a first select terminal connected to the first elastic wave filter; and a second select terminal connected to the second elastic wave filter, wherein the predetermined threshold value differs depending on whether the common terminal is connected to the first select terminal or the common terminal is connected to the second select terminal, according to any one of claims 1 to 3.

7. The high-frequency circuit according to claim 6, wherein the coupler is connected between the output terminal of the power amplifier circuit and the common terminal of the switch circuit.

8. The high-frequency circuit according to claim 7, wherein the coupler is included in the same semiconductor component as the switch circuit.

9. The high-frequency circuit according to claim 8, wherein the detection circuit, the integration circuit, and the arithmetic circuit are included in the semiconductor component.

10. The high-frequency circuit according to claim 8 or 9, further comprising a temperature sensor included in the semiconductor component, wherein the calculation circuit is configured to change the predetermined threshold according to the temperature detected by the temperature sensor.

11. The high-frequency circuit according to any one of claims 1 to 10, further comprising a voltage / current conversion circuit configured to convert the output signal of the integrating circuit from a voltage signal to a current signal, wherein the arithmetic circuit is configured to control the bias current based on the output signal of the integrating circuit converted to a current signal.

12. A power amplifier circuit, an elastic wave filter connected to the output terminal of the power amplifier circuit, a bias circuit configured to supply a bias current to the power amplifier circuit, a coupler connected between the power amplifier circuit and the elastic wave filter, a detection circuit connected to the coupling port of the coupler, an integrating circuit connected to the output terminal of the detection circuit, a voltage / current conversion circuit connected to the output terminal of the integrating circuit, and an arithmetic circuit connected between the voltage / current conversion circuit and the bias circuit, wherein the arithmetic circuit comprises: a first transistor having a first terminal connected to the output terminal of the voltage / current conversion circuit, a second terminal connected to the power supply terminal, and a control terminal, wherein the first terminal of the first transistor is short-circuited with the control terminal, a second transistor having a first terminal connected to a current source, a second terminal connected to the power supply terminal, and a control terminal connected to the control terminal of the first transistor, a third transistor having a first terminal connected to a path between the first terminal of the second transistor and the current source, a second terminal connected to ground, and a control terminal, wherein the first terminal of the third transistor is short-circuited with the control terminal, A high-frequency circuit including a fourth transistor having a first terminal connected to the bias circuit, a second terminal connected to ground, and a control terminal connected to the control terminal of the third transistor.

13. The high-frequency circuit according to claim 12, wherein the first transistor and the second transistor are p-channel FETs (Field Effect Transistors), the third transistor and the fourth transistor are n-channel FETs, the first terminal of the first transistor, the second transistor, the third transistor and the fourth transistor are drain terminals, the second terminals of the first transistor, the second transistor, the third transistor and the fourth transistor are source terminals, and the control terminals of the first transistor, the second transistor, the third transistor and the fourth transistor are gate terminals.

14. The high-frequency circuit according to claim 12 or 13, wherein the current source is configured to supply a threshold current that varies according to the power class.

15. The high-frequency circuit according to claim 12 or 13, wherein the first transistor and the second transistor constitute a current mirror circuit with a variable current mirror ratio, and the current mirror circuit is configured to change the current mirror ratio according to the power class.

Images