Semiconductor device

Abstract

This semiconductor device according to an embodiment is provided with a gate-all-around transistor, the semiconductor device being provided with a substrate, a channel structure including a plurality of channel layers stacked above the substrate in a stacking direction perpendicular to the substrate, a gate structure including a gate electrode provided so as to cover the periphery of each of the plurality of channel layers via a gate insulating film, and a source-drain structure provided above the substrate so as to extend in the gate length direction beside the plurality of channel layers in the channel structure. On a cross section taken along the stacking direction, the film thickness of each of the plurality of channel layers in the stacking direction is larger than the width of each of the plurality of channel layers in the gate width direction.

Description

Semiconductor device

[0001] The present embodiment relates to a semiconductor device.

[0002] Conventionally, for example, in a semiconductor device having a GAA-FET (Gate All Around Field Effect Transistor) using a nanosheet structure, it is necessary to secure a predetermined gate width in the nanosheet structure. For this purpose, in the gate width direction of the GAA-FET, the thickness of the nanosheets constituting the nanosheet structure is fixed and the width is widened. In this case, in a high-performance cell, the width of the nanosheet becomes large, and the arrangement density of transistors constituting the semiconductor device becomes low.

[0003] An object of one embodiment is to provide a semiconductor device capable of increasing the arrangement density of transistors.

[0004] A semiconductor device according to one embodiment is a semiconductor device including a gate-all-around transistor, comprising: a substrate; a channel structure including a plurality of channel layers stacked above the substrate in a stacking direction perpendicular to the substrate; a gate structure including a gate electrode provided so as to cover the periphery of each of the plurality of channel layers with a gate insulating film interposed therebetween; and a source / drain structure provided above the substrate and extending in the gate length direction beside the plurality of channel layers of the channel structure, wherein a thickness of each of the plurality of channel layers in the stacking direction is larger than a width of each of the plurality of channel layers in the gate width direction.

[0005] Figure 1A is a top view showing an example of the configuration of a semiconductor device according to the first embodiment. Figure 1B is a cross-sectional view showing an example of a part of the configuration of the end face along the gate width direction of the semiconductor device shown in Figure 1A. Figure 1C is a cross-sectional view showing another example of a part of the configuration of the end face along the gate width direction of the semiconductor device shown in Figure 1A. Figure 1D is a cross-sectional view showing an example of a part of the configuration of the end face along the gate length direction of the semiconductor device shown in Figure 1A. Figure 2 is a cross-sectional view showing a modified example of a part of the configuration of the end face along the gate width direction of the semiconductor device shown in Figure 1A. Figure 3A is a cross-sectional view showing an example of the manufacturing process along the gate width direction of the semiconductor device according to the first embodiment. Figure 3B is a cross-sectional view following Figure 3A showing an example of the manufacturing process along the gate width direction of the semiconductor device according to the first embodiment. Figure 3C is a cross-sectional view following Figure 3B showing an example of the manufacturing process along the gate width direction of the semiconductor device according to the first embodiment. Figure 4A is a cross-sectional view showing an example of the manufacturing process along the gate length direction of the semiconductor device according to the first embodiment. Figure 4B is a cross-sectional view following Figure 4A showing an example of the manufacturing process along the gate length direction of the semiconductor device according to the first embodiment. Figure 4C is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the first embodiment, following Figure 4B. Figure 4D is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the first embodiment, following Figure 4C. Figure 4E is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the first embodiment, following Figure 4D. Figure 5A is a cross-sectional view showing an example of a part of the configuration of an end face along the gate width direction of a semiconductor device according to the second embodiment. Figure 5B is a cross-sectional view showing an example of a part of the configuration of an end face along the gate length direction of a semiconductor device according to the second embodiment. Figure 6A is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the second embodiment. Figure 6B is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the second embodiment, following Figure 6A. Figure 6C is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the second embodiment, following Figure 6B. Figure 6D is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the second embodiment, following Figure 6C.Figure 6E is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the second embodiment, following Figure 6D. Figure 6F is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the second embodiment, following Figure 6E. Figure 6G is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the second embodiment, following Figure 6F. Figure 6H is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the second embodiment, following Figure 6G. Figure 7A is a cross-sectional view showing an example of a part of the configuration of an end face along the gate width direction of a semiconductor device according to the third embodiment. Figure 7B is a cross-sectional view showing an example of a part of the configuration of an end face along the gate length direction of a semiconductor device according to the third embodiment. Figure 8A is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the third embodiment. Figure 8B is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the third embodiment, following Figure 8A. Figure 8C is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the third embodiment, following Figure 8B. Figure 8D is a cross-sectional view showing an example of a manufacturing process along the gate length direction of a semiconductor device according to the third embodiment, following Figure 8C. Figure 8E is a cross-sectional view showing an example of the manufacturing process along the gate length direction of the semiconductor device according to the third embodiment, following Figure 8D. Figure 8F is a cross-sectional view showing an example of the manufacturing process along the gate length direction of the semiconductor device according to the third embodiment, following Figure 8E. Figure 8G is a cross-sectional view showing an example of the manufacturing process along the gate length direction of the semiconductor device according to the third embodiment, following Figure 8F. Figure 8H is a cross-sectional view showing an example of the manufacturing process along the gate length direction of the semiconductor device according to the third embodiment, following Figure 8G. Figure 8I is a cross-sectional view showing an example of the manufacturing process along the gate length direction of the semiconductor device according to the third embodiment, following Figure 8H. Figure 8J is a cross-sectional view showing an example of the manufacturing process along the gate length direction of the semiconductor device according to the third embodiment, following Figure 8I. Figure 8K is a cross-sectional view showing an example of the manufacturing process along the gate length direction of the semiconductor device according to the third embodiment, following Figure 8J.

[0006] A semiconductor device according to an embodiment will be described in detail below with reference to the attached drawings. In the following description, components having substantially equivalent functions and configurations will be denoted by the same reference numerals, and redundant descriptions may be omitted. However, the present invention is not limited to these embodiments.

[0007] (First Embodiment) Here, Figure 1A is a top view showing an example of the configuration of a semiconductor device according to the first embodiment. Figure 1B is a cross-sectional view showing an example of a part of the configuration of the end face along the gate width direction of the semiconductor device shown in Figure 1A. Figure 1C is a cross-sectional view showing another example of a part of the configuration of the end face along the gate width direction of the semiconductor device shown in Figure 1A. Figure 1D is a cross-sectional view showing an example of a part of the configuration of the end face along the gate length direction of the semiconductor device shown in Figure 1A. Figure 2 is a cross-sectional view showing a modified example of a part of the configuration of the end face along the gate width direction of the semiconductor device shown in Figure 1A.

[0008] [Semiconductor device] The semiconductor device 100 according to the first embodiment shown in Figures 1A to 1D includes a GAA-FET (Gate All Around Field Effect Transistor) using a nanosheet structure.

[0009] The following describes the various components of this semiconductor device 100.

[0010] For example, as shown in Figure 1A, this semiconductor device 100 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4, all of which are full-circumference gate transistors. Figure 1B shows a portion of the end face configuration of the first transistor T1 shown in Figure 1A along the gate width direction. Figure 1C shows a portion of the end face configuration of the second transistor T2 shown in Figure 1A along the gate width direction X. Figure 1D shows a portion of the end face configuration of the first and second transistors T1 and T2 shown in Figure 1A along the gate length direction Y perpendicular to the gate width direction X.

[0011] Furthermore, a source-drain structure SD is commonly connected between the first transistor T1 and the second transistor T2.

[0012] Furthermore, a source-drain structure SD is commonly connected between the third transistor T3 and the fourth transistor T4.

[0013] Furthermore, the gate structure G of the first transistor T1 and the gate structure G of the third transistor T3 are continuously connected in common.

[0014] Furthermore, the gate structure G of the second transistor T2 and the gate structure G of the fourth transistor T4 are continuously connected in common.

[0015] Furthermore, as shown in Figures 1A, 1B, 1C, and 1D, for example, the first and second transistors T1 and T2 constituting this semiconductor device 100 each comprise a substrate SU, a channel structure C, a gate structure G, and a source-drain structure SD. Note that in Figure 1A, the insulating layer E on the source-drain structure SD is omitted from the illustration. The third and fourth transistors T3 and T4 have a similar configuration.

[0016] [Substrate] The substrate SU is, for example, a silicon substrate. On the surface of this substrate SU, an element isolation structure S (STI: Shallow Trench Isolation) is formed as an element isolation region. The element isolation structure S is composed of an insulating layer embedded in the substrate SU. The element isolation structure S is formed between each transistor T1 to T4. In addition, the element isolation structure S is formed in areas other than the region in which each transistor T1 to T4 is formed.

[0017] [Channel Structure] The channel structure C of the first transistor T1 includes, for example, three channel layers C1, C2, and C3 stacked above the substrate SU in a stacking direction Z perpendicular to the substrate SU (a direction perpendicular to the gate width direction X and the gate length direction Y), as shown in Figures 1B and 1D. The first to third channel layers C1, C2, and C3 are, for example, Si layers (semiconductor layers).

[0018] Furthermore, the channel structure C of the second transistor T2 includes, for example, a plurality (two) of channel layers C1 and C2 stacked above the substrate SU in a stacking direction Z perpendicular to the substrate SU, as shown in Figures 1C and 1D.

[0019] Thus, in the first transistor T1, the multiple channel layers stacked in the stacking direction Z are three channel layers C1, C2, and C3 stacked in the stacking direction Z. However, in the second transistor T2, the multiple channel layers stacked in the stacking direction Z may be, for example, two channel layers C1 and C2 stacked in the stacking direction Z.

[0020] In other words, in this embodiment, considering the thickness of the semiconductor device 100 in the stacking direction Z, the plurality of channel layers include two or three channel layers stacked in the stacking direction Z. However, it is not limited to this, and the semiconductor device 100 may include four or more channel layers in the stacking direction Z.

[0021] For example, as shown in Figure 1B, the widths W of the first to third channel layers C1, C3, and C3 are set in the range of 3 nm to 10 nm in the gate width direction X.

[0022] For example, as shown in Figure 2 described later, the first transistor T1 may include a plurality of channel structures C (a plurality of fin structures F1) arranged in the gate width direction X in order to obtain a predetermined gate width. In this case, the first transistor T1 has a configuration in which a plurality of transistors are connected in parallel in a circuit. With such a configuration, the gate width of the first transistor T1 can be adjusted. The same applies to the other second to fourth transistors T2 to T4.

[0023] [Gate Structure] For example, as shown in Figures 1B and 1D, the gate structure G of the first transistor T1 includes a gate insulating film (e.g., a high dielectric constant material layer) HK, gate electrodes G1, G2, G3, and Gx provided to cover the periphery of each of the channel layers C1, C2, and C3 of the plurality of channel layers via the gate insulating film HK, and an inner spacer IS made of an insulating layer.

[0024] For example, in the cross-sectional view in the gate width direction X shown in Figure 1B, the first transistor T1 has a high dielectric constant material layer HKx formed on the substrate SU and the element isolation structure S. The first transistor T1 also has the previously described channel layers C1, C2, and C3, which are laminated on the high dielectric constant material layer HKx via a metal layer constituting the gate electrode G1. Furthermore, a gate insulating film HK containing the high dielectric constant material layer is formed between the gate electrodes G1, G2, and G3 and the first to third channel layers C1, C2, and C3. Therefore, in the cross-sectional view in the gate width direction X, the channel layers C1, C2, and C3 are each surrounded by the gate insulating film HK.

[0025] Furthermore, as shown in the cross-sectional view in the gate width direction X in Figure 1B, the metal layers constituting the gate structure G are formed continuously with the gate electrodes G1, G2, G3 and Gx shown in Figure 1B. Therefore, in the cross-sectional view in the gate width direction shown in Figure 1B, the channel layers C1, C2, C3 are surrounded by the gate electrodes G1, G2, G3 and Gx.

[0026] Furthermore, for example, in the cross-sectional view in the gate length direction Y shown in Figure 1D, the first transistor T1 has a gate electrode Gx and a gate spacer (sidewall) GS above the uppermost third channel layer C3. The gate electrode Gx is formed on the central part of the channel layer C3, and the gate spacer GS is formed around the gate electrode Gx.

[0027] For example, the gate electrode Gx includes a metal layer. Furthermore, the bottom and side surfaces of the gate electrode Gx, i.e., the contact surfaces with the channel layer C3 and the gate spacer GS, are provided with a gate insulating film HK, for example, which includes a high dielectric constant material layer. The metal layer constituting the gate electrode Gx is filled within the gate insulating film HK.

[0028] Furthermore, as shown in Figure 1D, the inner spacer IS of the first transistor T1 is located on both sides of the gate electrodes G1, G2, and G3 in the gate length direction Y, via the gate insulating film HK. Similarly, the inner spacer IS of the second transistor T2 is located on both sides of the gate electrodes G1, G2, and Gx in the gate length direction Y, via the gate insulating film HK.

[0029] As shown in Figure 1D, in the cross-sectional view along the gate length Y, the gate electrodes G1, G2, and G3 are covered with a gate insulating film HK containing a high dielectric constant material layer at the contact surfaces with the channel layers C1, C2, and C3 and the inner spacer IS. The metal layers constituting the gate electrodes G1, G2, and G3 are filled inside the gate insulating film HK. These metal layers are formed continuously with the gate electrodes G1, G2, G3 and gate electrode Gx.

[0030] [Source-Drain Structure] Also, for example, as shown in Figures 1A and 1D, the first transistor T1 is provided with a source-drain structure SD on both sides of a channel structure C, which is a stack of channel layers C1, C2, and C3 stacked adjacent to gate electrodes G1, G2, and G3 in the stacking direction Z.

[0031] Each channel layer C1, C2, and C3 is connected to the source-drain structure SD on both sides. An inner spacer IS is formed between the gate electrodes G1, G2, and G3 and the source-drain structure SD on both sides.

[0032] In particular, the source-drain structure SD is provided, for example, as shown in Figures 1A and 1D, so as to extend in the gate length direction Y, alongside the multiple channel layers C1, C2, and C3 of the channel structure C.

[0033] For example, as shown in Figure 1D, an insulating layer E is provided on the source-drain structure SD.

[0034] [Dimensions and Effects of Each Components of the Semiconductor Device] Here, the dimensions of each component of the semiconductor device 100 according to this embodiment will be described.

[0035] For example, as shown in Figure 1B, in a cross-section along the gate width direction X and the stacking direction Z, the film thickness Tsi of each of the multiple channel layers C1, C2, and C3 in the stacking direction Z is set to be greater than the width W of each of the multiple channel layers C1, C2, and C3.

[0036] In other words, for example, as shown in Figure 1B, in a cross-section in the gate width direction X, the film thickness Tsi of the first channel layer C1 in the stacking direction Z among the multiple channel layers is set to be greater than the width of the first channel layer C1.

[0037] Furthermore, as shown in Figure 1B, for example, in a cross-section in the gate width direction X, the film thickness of the second channel layer C2, which is stacked adjacent to the first channel layer C1 in the stacking direction Z, is set to be greater than the width of the second channel layer C2.

[0038] Furthermore, as previously described, the multiple channel layers of the channel structure C of the first transistor T1 include a third channel layer C3 provided adjacent to the second channel layer C2 in the stacking direction Z. The film thickness Tsi of the third channel layer C3 is set to be greater than the width W of the third channel layer C3.

[0039] For example, as shown in Figure 1D, the film thickness Tsi of the first channel layer C1 and the film thickness Tsi of the second channel layer C2 are set to be equal in the gate length direction Y.

[0040] Furthermore, in the gate width direction X, the width W of the first channel layer C1 and the width W of the second channel layer C2 are set to be equal, for example.

[0041] Furthermore, for example, in the stacking direction Z, the film thickness Tsi of the first channel layer C1, the film thickness Tsi of the second channel layer C2, and the film thickness Tsi of the third channel layer C3 are set to be equal. However, the film thickness of each channel layer may be set to be different depending on the characteristics required for each transistor T1 to T4.

[0042] In particular, in a cross section in the gate width direction X, for example, the ratio R = Tsi / W of the film thickness Tsi of the first, second, and third channel layers C1, C2, C3 to the width W of the first, second, and third channel layers C1, C2, C3 shown in FIG. 1B is set in a range of 1.0 < R ≤ 6.0. Preferably, in a cross section in the gate width direction X, the ratio R = Tsi / W is set in a range of 2.0 ≤ R ≤ 4.0. More preferably, in a cross section in the gate width direction X, the ratio R = Tsi / W is set in a range of 3.0 ≤ R ≤ 3.5.

[0043] By setting the ratio R within the above range, it is possible to adjust the gate width of the transistor and increase the arrangement density of transistors while keeping the thickness of the semiconductor device 100 within a predetermined range.

[0044] Here, for example, as shown in FIG. 2, the semiconductor device 100 may include a plurality of first fin structures F1 of the first transistor T1, each of which includes a channel structure C and a gate structure G stacked in the stacking direction Z and arranged at a first interval D1 in the gate width direction X.

[0045] For example, as shown in FIG. 2, the first interval D1 in the gate width direction X is set in a range of 10 nm < D1 < 100 nm. Preferably, the first interval D1 in the gate width direction X may be set in a range of 20 nm < D1 < 30 nm.

[0046] As described above, the first transistor T1 may be configured by combining a plurality (two) of transistors connected in parallel by commonly connecting the source-drain structure SD. With this configuration, the gate width of the first transistor T1 can be adjusted.

[0047] Also, for example, as shown in FIG. 2, the semiconductor device 100 may include a plurality of second fin structures F2 of the third transistor T3, each of which includes a channel structure C and a gate structure G stacked in the stacking direction Z and arranged at a second interval D2 different from the first interval D1 in the gate width direction X.

[0048] For example, in the gate width direction X, the second interval D2 is set in the range of 10 nm < D2 < 100 nm.

[0049] With this configuration, for example, by adjusting the spacing between the fin structures, unnecessary contact between the source-drain structure SD between the first and third transistors T1 and T3 can be avoided.

[0050] As described above, the semiconductor device 100 according to this embodiment comprises a substrate SU, a channel structure C including a plurality of channel layers stacked above the substrate SU in a stacking direction Z perpendicular to the substrate SU, a gate structure G including a gate electrode provided so as to cover the periphery of each of the plurality of channel layers via a gate insulating film HK, and a source-drain structure SD provided above the substrate SU so as to extend in the gate length direction Y next to the plurality of channel layers of the channel structure C. In a cross-section along the gate width direction X and the stacking direction Z, the film thickness of each of the plurality of channel layers in the stacking direction Z of the channel layers is set to be greater than the width of each of the plurality of channel layers. More preferably, the plurality of channel layers are two channel layers C1, C2, or three channel layers C1, C2, C3 stacked above the substrate SU in the stacking direction Z.

[0051] This makes it possible to adjust the gate width of the all-around gate transistor to a desired value in the gate width direction X while reducing the width of the channel structure C. In other words, the semiconductor device 100 according to this embodiment can increase the density of transistor arrangement.

[0052] [Method for Manufacturing a Semiconductor Device] Next, an example of a method for manufacturing a semiconductor device according to the first embodiment having the configuration described above will be explained with reference to Figures 3A to 4E. Figures 3A to 3C are cross-sectional views showing an example of each manufacturing process along the gate width direction X of the semiconductor device according to the first embodiment. Figures 4A to 4E are cross-sectional views showing an example of each manufacturing process along the gate length direction Y of the semiconductor device according to the first embodiment.

[0053] For example, as shown in Figure 3A in the gate width direction X, a SiGe layer M1 serving as a sacrificial layer, a nanosheet layer NS1 serving as a channel layer, a SiGe layer M2 serving as a sacrificial layer, a nanosheet layer NS2 serving as a channel layer, a SiGe layer M3 serving as a sacrificial layer, and a nanosheet layer NS3 serving as a channel layer are stacked on a substrate SU.

[0054] For example, the formation of the SiGe layers M1, M2, M3 and the nanosheet layers NS1, NS2, NS3 is carried out using epitaxial growth of Si and SiGe. The SiGe layers M1, M2, M3 are formed to a thickness of approximately 10 nm to 30 nm, for example. The nanosheet layers NS1, NS2, NS3 are formed to a thickness of approximately 10 nm to 60 nm, for example.

[0055] Next, as shown in Figure 3B, in order to form the fin structure of the all-around gate transistor, the laminate of nanosheet layers NS1, NS2, and NS3 is patterned by etching using a method such as reactive ion etching (RIE). At this time, grooves Sa are formed in the substrate SU by etching back the surface of the substrate SU.

[0056] Next, as shown in Figure 3C, the grooves Sa in the substrate SU are filled with an insulating material to form an element isolation structure S.

[0057] On the other hand, as shown in Figure 4A in the gate length direction Y, a dummy gate insulating film DG, a polysilicon (p-Si) dummy gate PC, and a gate spacer GS are formed. In addition, inner spacers IS are formed on both sides of the SiGe layers M1, M2, and M3.

[0058] Then, source-drain structures SD are formed on both sides of the gate length direction Y of the laminate of SiGe layers M1, M2, M3 and first to third channel layers C1, C2, C3 in the stacking direction Z, for example by epitaxial growth. Then, an insulating layer E covering the entire substrate SU is formed by, for example, CVD (Chemical Vapor Deposition), and the insulating layer E is polished and planarized by chemical mechanical polishing (CMP) or the like.

[0059] Next, as shown in Figure 4B, the dummy gate PC surrounded by the dummy gate insulating film DG and gate spacer GS is selectively removed using RIE or the like.

[0060] Next, as shown in Figure 4C, for example, a carbon coating film is deposited on a region containing at least a dummy gate insulating film DG and a gate spacer GS, and then a mask OPL is formed by selective etching, for example, by the RIE method.

[0061] Next, as shown in Figure 4D, the mask OPL is used to etch the dummy gate insulating film DG and the third channel layer C using, for example, the RIE method, until the upper surface of the SiGe layer M3 is exposed. As a result, as shown in Figure 1B, for example, the third channel layer C3 is partially removed, making it possible to construct a transistor with two stacked channel layers and a transistor with three stacked channel layers.

[0062] Next, as shown in Figure 4E, the mask OPL is removed by ashing. Then, the sacrificial layers, SiGe layers M1, M2, and M3, are selectively etched. In this process, the dummy gate insulating film DG is also removed. This exposes the interlayers of the first to third channel layers C1, C2, and C3. Selective etching of the SiGe layers M1, M2, and M3 can be performed using, for example, dry etching with a mixed gas containing hydrogen fluoride and oxygen, or wet etching with a mixed solution of hydrogen fluoride and hydrogen peroxide.

[0063] Then, a high dielectric constant material layer constituting the gate insulating film HK shown in Figure 1D is formed on the substrate SU. This high dielectric constant material layer is, for example, hafnium dioxide (HfO ２ The high dielectric constant material layer is formed from materials such as hafnium oxynitride (HfON). For example, ALD (Atomic Layer Deposition) is used to form the high dielectric constant material layer.

[0064] Then, metal layers constituting gate electrodes G1, G2, G3, and Gx are formed on the high dielectric constant material layer. These metal layers are formed from, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium (Nb), tungsten (W), etc. For example, CVD is used to form the metal layers. Through this process, gate electrodes G1, G2, G3, and Gx (see Figure 1D) made of metal layers are formed between the substrate SU and the first to third channel layers C1, C2, and C3, respectively, via a gate insulating film HK.

[0065] Next, the first and second transistors T1 and T2 shown in Figure 1D are formed by removing unnecessary insulating layers, high dielectric constant material layers, and metal layers using methods such as CMP, and by planarizing the surfaces of each layer. The third and fourth transistors T3 and T4 are formed in the same manner.

[0066] In other words, by the above process, for example, as shown in Figure 1D, a semiconductor device 100 can be manufactured that includes a second transistor T2 having two stacked channel layers C1 and C2, and a first transistor T1 having three stacked channel layers C1, C2, and C3.

[0067] In particular, the semiconductor device 100 comprises a substrate SU, a channel structure C including a plurality of channel layers stacked above the substrate SU in a stacking direction Z perpendicular to the substrate SU, a gate structure G including a gate electrode provided to cover each of the plurality of channel layers via a gate insulating film HK, and a source-drain structure SD provided above the substrate SU, extending in the gate length direction Y alongside the plurality of channel layers of the channel structure C. In a cross-section along the gate width direction X and the stacking direction Z, the film thickness of each of the plurality of channel layers in the stacking direction Z of the channel layers is set to be greater than the width of each of the plurality of channel layers.

[0068] As described above, the semiconductor device according to the first embodiment makes it possible to increase the density of transistor arrangement.

[0069] In the first embodiment described above, an example of a semiconductor device having a GAA-FET using a nanosheet structure was explained. However, the configuration of the semiconductor device is not limited to this. Therefore, in the second and third embodiments below, examples of other configurations of the semiconductor device will be described.

[0070] (Second Embodiment) A semiconductor device according to the second embodiment will be described with reference to Figures 5A and 5B. Figure 5A is a cross-sectional view showing an example of a part of the configuration of the end face along the gate width direction X of the semiconductor device according to the second embodiment. Figure 5B is a cross-sectional view showing an example of a part of the configuration of the end face along the gate length direction Y of the semiconductor device according to the second embodiment. The top view of the semiconductor device according to the second embodiment shown in Figures 5A and 5B is the same as the top view of the semiconductor device according to the first embodiment described above, Figure 1A.

[0071] [Semiconductor Device] The semiconductor device according to the second embodiment shown in Figures 5A to 5B is a GAA-FET full-circumference gate transistor using a nanosheet structure, similar to the first embodiment. The semiconductor device according to this second embodiment differs from the semiconductor device of the first embodiment in that its fin structure includes an element isolation layer SASI (Self-Aligned substrate Isolation). In the example of Figure 5B, the first and second transistors T1 and T2 have stacked three-layer channel layers C1, C2, and C3, but similar to the first embodiment, for example, the second transistor T2 may have stacked two-layer channel layers C1 and C2.

[0072] The following describes the configuration of the semiconductor device according to this second embodiment, focusing on the differences from the first embodiment.

[0073] For example, as shown in Figure 5A for the gate width direction X and Figure 5B for the gate length direction Y, the channel structure C includes a first channel layer C1 among a plurality of channel layers, a second channel layer C2 stacked above the first channel layer C1 adjacent to it in the stacking direction Z, and a third channel layer C3 stacked above the second channel layer C2 adjacent to it in the stacking direction Z.

[0074] For example, the fin structure F1 includes an element isolation layer SASI, which is an insulating film provided between the substrate SU and the first channel layer C1 in the stacking direction Z. The element isolation layer SASI is adjacent to the first channel layer C1 in the stacking direction Z via a high dielectric constant material layer HK, a gate electrode G1, and a gate insulating film HK.

[0075] In other words, an element isolation layer SASI is provided between the substrate SU and the gate electrode G1. This element isolation layer SASI can reduce the influence of parasitic capacitance near the substrate SU.

[0076] Furthermore, the other configurations of the semiconductor device according to this embodiment are the same as those of the semiconductor device according to the first embodiment. That is, the semiconductor device according to this embodiment can increase the density of transistors, similar to the first embodiment.

[0077] [Method for Manufacturing a Semiconductor Device] Next, a method for manufacturing a semiconductor device according to the first embodiment having the configuration described above will be explained with reference to Figures 6A to 6E. Figures 6A to 6H are cross-sectional views showing an example of each manufacturing process along the gate length direction Y of the semiconductor device according to the second embodiment.

[0078] For example, as shown in Figure 6A in the gate length direction Y, a sacrificial SiGe layer Mx, a Si layer Sa, a sacrificial SiGe layer M1, a channel layer C1 composed of a nanosheet layer, a sacrificial SiGe layer M2, a channel layer C2 composed of a nanosheet layer, a sacrificial SiGe layer M3, and a C3 composed of a nanosheet layer are stacked on the substrate SU. Then, a dummy gate insulating film DG, a polysilicon (p-Si) dummy gate PC, and a gate spacer GS are formed. Etching is performed using the RIE method so as to reach the interior of the SiGe layer Mx. This forms a groove V.

[0079] Next, as shown in Figure 6B, a liner film L, composed of, for example, a SiO film Lb and a SiN film La, is formed on the inner surface of the groove V formed by etching. As a result, the sides of the SiGe layers M1, M2, and M3 are covered by the liner film L.

[0080] Next, as shown in Figure 6C, the liner film L, composed of the SiO film Lb and SiN film La on the bottom of the groove V, is selectively removed by anisotropic etching, such as the RIE method, so that the bottom of the groove V is exposed. As a result, the surface of the SiGe layer Mx is exposed at the bottom of the groove V.

[0081] Next, as shown in Figure 6D, the SiGe layer Mx on the substrate SU is selectively removed, for example, by dry selective etching.

[0082] Next, as shown in Figure 6E, the liner film L, which is composed of a SiO film Lb and a SiN film La, is removed, for example, by dry selective etching.

[0083] Next, as shown in Figure 6F, an insulating film that will serve as the element isolation layer SASI is deposited between the substrate SU and the SiGe layer M1, for example, by CVD. Since the fin structure in the gate width direction is thin, pinch-off can be achieved with a thin film.

[0084] Next, as shown in Figure 6G, by anisotropic etching such as the RIE method, for example, unnecessary insulating films on the sides of the laminate of the gate spacer GS, SiGe layers M1, M2, M3, and the first to third channel layers C1, C2, C3, as well as on the substrate SU, can be etched back, thereby forming an element isolation layer SASI with a desired shape between the substrate SU and the SiGe layer M1 through self-alignment.

[0085] Next, as shown in Figure 6H, an inner spacer IS is formed on the laminate of SiGe layers M1, M2, M3 and the first to third channel layers C1, C2, C3.

[0086] Then, source-drain structures SD are formed on both sides of the gate length direction Y of the laminate of SiGe layers M1, M2, M3 and the first to third channel layers C1, C2, C3, for example, by epitaxial growth. Then, an insulating layer E covering the entire substrate SU is formed by, for example, CVD, and the insulating layer E is polished and planarized by CMP or the like.

[0087] Subsequently, similar to the method for manufacturing the semiconductor device according to the first embodiment described above, the dummy gate PC surrounded by the dummy gate insulating film DG and gate spacer GS is removed, and the SiGe layers M1, M2, and M3 are selectively etched. In this step, the dummy gate insulating film DG is also removed. Then, a high dielectric constant material layer constituting the gate insulating film HK shown in Figure 5B is formed on the substrate SU. Then, gate electrodes G1, G2, G3, and Gx (see Figure 5B), made of metal layers, are formed between the substrate SU and the first to third channel layers C1, C2, and C3, respectively, via the gate insulating film HK. This forms the first and second transistors T1 and T2 shown in Figure 5B.

[0088] In other words, by the above process, for example, as shown in Figure 5B, a semiconductor device can be manufactured that includes first and T2 transistors T1 and T2, each comprising three stacked channel layers C1, C2, and C3.

[0089] Furthermore, similar to the first embodiment, the semiconductor device according to the second embodiment comprises a substrate SU, a channel structure C including a plurality of channel layers stacked above the substrate SU in a stacking direction Z perpendicular to the substrate SU, a gate structure G including a gate electrode provided to cover each of the plurality of channel layers via a gate insulating film HK, and a source-drain structure SD provided above the substrate SU, extending in the gate length direction Y next to the plurality of channel layers of the channel structure C.In a cross-section along the gate width direction X and the stacking direction Z, the film thickness of each of the plurality of channel layers in the stacking direction Z of the channel layers is set to be greater than the width of each of the plurality of channel layers.

[0090] As described above, the semiconductor device according to the second embodiment makes it possible to increase the density of transistor arrangement.

[0091] (Third Embodiment) Next, a semiconductor device according to the third embodiment will be described with reference to Figures 7A and 7B. Figure 7A is a cross-sectional view showing an example of a part of the configuration of the end face along the gate width direction of the semiconductor device according to the third embodiment. Figure 7B is a cross-sectional view showing an example of a part of the configuration of the end face along the gate length direction of the semiconductor device according to the third embodiment. Note that the top view of the semiconductor device according to the third embodiment shown in Figures 7A and 7B is the same as the top view of the semiconductor device according to the first embodiment described above (Figure 1A).

[0092] [Semiconductor Device] The semiconductor device according to the third embodiment shown in Figures 7A to 7B is a GAA-FET full-circumference gate transistor using a nanosheet structure, similar to the first embodiment. This semiconductor device according to the third embodiment differs from the semiconductor device of the first embodiment in that it is a CFET (Monolithic Complementary Field Effect Transistor) equipped with an element isolation layer MDI (middle dielectric isolation).

[0093] The following describes the configurations of the semiconductor device according to this third embodiment, focusing on the differences from the first embodiment.

[0094] For example, as shown in Figure 7A in the gate width direction X and Figure 7B in the gate length direction Y, the channel structure includes a first channel layer C1 among a plurality of channel layers, and a second channel layer C2 among a plurality of channel layers, which is stacked above the first channel layer C1 adjacent to it in the stacking direction Z.

[0095] The fin structure F1 includes an element isolation layer MDI provided between the first channel layer C1 and the second channel layer C2, via gate electrodes G2, G3 and a gate insulating film HK. This element isolation layer MDI is made of, for example, an insulating material.

[0096] For example, as shown in Figure 7A, in the gate width direction X, the width of the element isolation layer MDI is equal to, for example, the width W of the first channel layer C1 and the width W of the second channel layer C2.

[0097] Furthermore, as shown in Figure 7A, for example, in the stacking direction Z, the thickness of the element isolation layer MDI is equal to, for example, the thickness Tsi of the first channel layer C1 and the thickness of the second channel layer C2, but it may be different.

[0098] The source-drain structure SD includes, for example, a first source-drain structure SDp and a second source-drain structure SDn, as shown in Figure 7B.

[0099] The first source-drain structure SDp is provided above the substrate SU, extending in the gate length direction Y from both sides of the first channel layer C1.

[0100] The second source-drain structure SDn is provided above the substrate SU, extending in the gate length direction Y from both sides of the second channel layer C2.

[0101] The first channel layer C1, the first source-drain structure SDp, the gate insulating film HK, the inner spacer IS, and the gate electrodes G1 and G2 constitute a first-conductivity type transistor T1p.

[0102] Furthermore, the second channel layer C2, the second source-drain structure SDn, the gate insulating film HK, the inner spacer IS, the gate spacer GS, and the gate electrodes G3 and Gx constitute the second conductivity type transistor T1n.

[0103] For example, the first-conductivity transistor T1p is a p-type transistor, and the second-conductivity transistor T1n is an n-type transistor. However, the first-conductivity transistor T1p may be an n-type transistor, and the second-conductivity transistor T1n may be a p-type transistor.

[0104] Furthermore, the gate electrode G2 of the first-conductivity transistor T1p and the gate electrode G3 of the second-conductivity transistor T1n are insulated from each other by the element isolation layer MDI. In addition, the source-drain structure SDp of the first-conductivity transistor T1p and the source-drain structure SDn of the second-conductivity transistor T1n are insulated from each other by the element isolation layer MDI. In the example shown in Figure 7A, the gate electrodes G1, G2, G3, and Gx of transistors T1p and T1n are connected in a continuous manner.

[0105] Thus, the semiconductor device according to this embodiment constitutes a monolithic CFET using an element isolation layer (MDI).

[0106] Furthermore, the other configurations of the semiconductor device according to this embodiment are the same as those of the semiconductor device according to the first embodiment. That is, the semiconductor device according to this embodiment can increase the density of transistors, similar to the first embodiment.

[0107] [Method for Manufacturing a Semiconductor Device] Next, a method for manufacturing a semiconductor device according to the third embodiment having the configuration described above will be explained with reference to Figures 8A to 8H. Figures 8A to 8H are cross-sectional views showing an example of each manufacturing process along the gate length direction Y of the semiconductor device according to the third embodiment.

[0108] For example, as shown in Figure 8A, a SiGe layer M1 serving as a sacrificial layer, a channel layer C1 composed of nanosheet layers, a SiGe layer M2 serving as a sacrificial layer, a Si layer Sa, a SiGe layer My, a SiGe layer M3 serving as a sacrificial layer, a channel layer C2 composed of nanosheet layers, and a C3 composed of nanosheet layers are stacked on a substrate SU. Subsequently, a dummy gate insulating film DG, a polysilicon (p-Si) dummy gate PC, and a gate spacer GS are formed.

[0109] Next, as shown in Figure 8B, etching is performed using the RIE method to reach the interior of the SiGe layer My. This forms the groove Vy.

[0110] Next, as shown in Figure 8C, a liner film L, composed of, for example, a SiO film Lb and a SiN film La, is formed on the inner surface of the groove Vy formed by etching. As a result, the side surface of the SiGe layer M3 is covered with the liner film L.

[0111] Next, as shown in Figure 8D, the liner film L, composed of the SiO film Lb and SiN film La on the bottom of the groove Vy, is selectively removed by anisotropic etching, such as the RIE method, so that the bottom of the groove Vy is exposed. As a result, the surface of the SiGe layer My is exposed at the bottom of the groove Vy.

[0112] Next, as shown in Figure 8E, the SiGe layer My and the Si layer Sa are selectively removed, for example, by dry selective etching.

[0113] Next, as shown in Figure 8F, the liner film L, which is composed of a SiO film Lb and a SiN film La, is removed, for example, by dry selective etching.

[0114] Next, for example, an insulating film that will become the device isolation layer MDI is deposited between the SiGe layer M2 and the SiGe layer M3 by CVD. Then, as shown in Figure 8G, by anisotropic etching such as RIE, unnecessary insulating films on the sides of the laminate of the gate spacer GS, SiGe layer M3, and channel layer C2, as well as on the SiGe layer M2, can be etched back, thereby forming a device isolation layer MDI with the desired shape between the SiGe layer M2 and the SiGe layer M3 through self-alignment.

[0115] Next, as shown in Figure 8H, the SiGe layer M1, channel layer C1, and SiGe layer M1 are etched along the groove Vy, for example, by anisotropic etching such as the RIE method, so as to reach the interior of the substrate SU.

[0116] Next, as shown in Figure 8I, an inner spacer IS is formed on the laminate of SiGe layers M1, M2, M3, and the element isolation layer MDI and channel layers C1, C2.

[0117] Next, as shown in Figure 8J, for example, a first source-drain structure SDp is formed above the substrate SU by epitaxial growth, extending in the gate length direction Y from both sides of the channel layer C1. Furthermore, for example, a second source-drain structure SDn is formed above the substrate SU by epitaxial growth, extending in the gate length direction Y from both sides of the second channel layer C2.

[0118] Next, as shown in Figure 8K, an insulating layer E covering the entire substrate SU is formed, for example, by the CVD method, and then the insulating layer E is polished and planarized by the CMP method or the like.

[0119] Subsequently, similar to the method for manufacturing the semiconductor device according to the first embodiment described above, the dummy gate PC surrounded by the dummy gate insulating film DG and gate spacer GS is removed, and the SiGe layers M1, M2, and M3 are selectively etched. In this step, the dummy gate insulating film DG is also removed. Then, a high dielectric constant material layer constituting the gate insulating film HK shown in Figure 7B is formed on the substrate SU. Then, gate electrodes G1, G2, G3, and Gx (see Figure 7B), made of metal layers, are formed between the substrate SU and the channel layers C1 and C2, respectively, via the gate insulating film HK. As a result, transistors T1p and T1n, separated by the element isolation layer MDI shown in Figure 7B, are formed.

[0120] Furthermore, similar to the first embodiment, the semiconductor device according to the third embodiment comprises a substrate SU, a channel structure C including a plurality of channel layers stacked above the substrate SU in a stacking direction Z perpendicular to the substrate SU, a gate structure G including a gate electrode provided to cover each of the plurality of channel layers via a gate insulating film HK, and a source-drain structure SD provided above the substrate SU, extending in the gate length direction Y next to the plurality of channel layers of the channel structure C.In a cross-section along the gate width direction X and the stacking direction Z, the film thickness of each of the plurality of channel layers in the stacking direction Z of the channel layers is set to be greater than the width of each of the plurality of channel layers.

[0121] As described above, the semiconductor device according to the third embodiment makes it possible to increase the density of transistor arrangement.

[0122] 100 Semiconductor device SU Substrate C Channel structure G Gate structure SD Source-drain structure

Claims

1. A semiconductor device equipped with a full-circumference gate transistor, comprising: a substrate; a channel structure including a plurality of channel layers stacked on top of the substrate in a stacking direction perpendicular to the substrate; a gate structure including a gate electrode provided so as to cover the periphery of each of the plurality of channel layers via a gate insulating film; and a source-drain structure provided on top of the substrate so as to extend in the gate length direction lateral to the plurality of channel layers of the channel structure, wherein the film thickness of each of the plurality of channel layers in the stacking direction is greater than the width of each of the plurality of channel layers in the gate width direction.

2. The semiconductor device according to claim 1, characterized in that the plurality of channel layers are two or three channel layers stacked on top of the substrate in the stacking direction.

3. The semiconductor device according to claim 1, characterized in that, in the gate width direction, the film thickness of the first channel layer in the stacking direction among the plurality of channel layers is greater than the width of the first channel layer, and the film thickness of the second channel layer stacked adjacent to the first channel layer among the plurality of channel layers is greater than the width of the second channel layer.

4. The semiconductor device according to claim 3, characterized in that, in the stacking direction, the film thickness of the first channel layer and the film thickness of the second channel layer are equal.

5. The semiconductor device according to claim 4, characterized in that, in the gate width direction, the width of the first channel layer and the width of the second channel layer are equal.

6. The semiconductor device according to claim 3, wherein the channel structure includes a third channel layer provided adjacent to the second channel layer in the stacking direction above the second channel layer, and the thickness of the third channel layer is greater than the width of the third channel layer.

7. The semiconductor device according to claim 6, characterized in that the film thickness of the first channel layer, the film thickness of the second channel layer, and the film thickness of the third channel layer C3 are equal.

8. The semiconductor device according to claim 1, comprising a plurality of first fin structures, each including a channel structure and a gate structure stacked in the stacking direction and arranged at a first interval D1 in the gate width direction, wherein the first interval D1 in the gate width direction is set in the range of 10 nm < D1 < 100 nm.

9. The semiconductor device according to claim 8, comprising a plurality of second fin structures F2, each including a channel structure and a gate structure stacked in the stacking direction, and arranged in the gate width direction at a second interval D2 different from the first interval D1, wherein in the gate width direction, the second interval D2 is set in the range of 10 nm < D2 < 100 nm.

10. The semiconductor device according to claim 8, characterized in that, in the gate width direction, the first interval D1 is set in the range of 20 nm < D1 < 30 nm.

11. The semiconductor device according to claim 1, characterized in that the ratio R = Tsi / W of the thickness Tsi of the channel layer to the width W of the channel layer is set in the range of 1.0 < R ≤ 6.

0.

12. The semiconductor device according to claim 11, characterized in that the ratio R = Tsi / W is set in the range of 2.0 ≤ R ≤ 4.

0.

13. The semiconductor device according to claim 1, wherein the channel structure includes a first channel layer among the plurality of channel layers, and a second channel layer stacked adjacent to the first channel layer in the stacking direction, and further includes an element isolation layer provided between the substrate and the first channel layer in the stacking direction, which is adjacent to the first channel layer in the stacking direction via the gate electrode and the gate insulating film.

14. The semiconductor device according to claim 1, wherein the channel structure includes a first channel layer among the plurality of channel layers, and a second channel layer stacked adjacent to the first channel layer in the stacking direction, and further includes an element isolation layer provided between the first channel layer and the second channel layer in the stacking direction, via the gate electrode and the gate insulating film.

15. The semiconductor device according to claim 1, characterized in that the width of the channel layer in the gate width direction is set to a range of 3 nm to 10 nm.

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