Semiconductor device manufacturing method and semiconductor device

Abstract

This semiconductor device comprises: a semiconductor substrate; a plurality of groove-type element isolations that extend in one direction; gate-all-around transistors that are arranged in a matrix formation on the front surface side of the semiconductor substrate in such a manner as to share gate electrodes extending in a direction intersecting the groove-type element isolations; insulating sidewalls that are provided at sidewalls of the respective gate electrodes and extend in a direction intersecting the groove-type element isolations; and back surface-side contacts that are provided at positions sandwiched by the groove-type element isolations and also sandwiched by the gate electrodes so as to pass completely through the semiconductor substrate, and are connected to the sources / drains of the gate-all-around transistors. On both sides of the groove-type element isolations, residues of the sidewalls formed from the same material as the sidewalls are disposed at positions sandwiched by the gate electrodes. The height position of the upper ends of the residues is lower than the height position of the front surface of the semiconductor substrate that is situated below the gate electrodes of the gate-all-around transistors.

Description

Method for manufacturing semiconductor device and semiconductor device

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

[0002] As a technique related to a method for forming a semiconductor device using a nanosheet laminate, there is the technique described in Patent Document 1 below. Patent Document 1 describes a procedure including: forming a dummy gate and sidewall spacers on a nanosheet laminate, then performing a nanosheet recess step, removing a part of the nanosheet laminate (fin) and a part of a semiconductor layer to form a trench, forming an epitaxial placeholder in the trench, and epitaxially growing a source / drain on the epitaxial placeholder. It also describes that in the patterning step of a backside contact, the procedure includes exposing the epitaxial placeholder on the backside of the semiconductor layer, removing the epitaxial placeholder to expose the source / drain, and then forming the backside contact connected to the source / drain.

[0003] US Patent Application Publication No. 2024 / 0429103

[0004] Incidentally, Patent Document 1 discloses a procedure of forming a source / drain in a trench via an epitaxial placeholder, but there are also cases where the source / drain is formed directly in the trench. In this case, the backside contact is connected to the source / drain at the bottom surface of the trench. However, in the nanosheet recess step, the gap between the sidewall spacers is narrow, and the sidewall of the trench is formed into a tapered shape. For this reason, the connection area between the source / drain formed in the trench and the backside contact is small, which is a factor leading to an increase in connection resistance.

[0005] Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can reduce the connection resistance between a backside contact and a source / drain in a configuration having a surrounding-gate transistor.

[0006] The present invention, for solving the above problems, provides a semiconductor device comprising: a semiconductor substrate; a plurality of groove-shaped element isolations extending in one direction on the surface side of the semiconductor substrate; a plurality of all-around gate transistors arranged in a matrix on the surface side of the semiconductor substrate separated by the groove-shaped element isolations, sharing gate electrodes extending in a direction intersecting the groove-shaped element isolations; an insulating sidewall provided on the side wall of each gate electrode and extending in a direction intersecting the groove-shaped element isolations; and a back-side contact provided at a position sandwiched between the groove-shaped element isolations and at a position sandwiched between the gate electrodes, penetrating the semiconductor substrate and connected to the source / drain of the all-around gate transistors, wherein a residue of the sidewall, made of the same material as the sidewall, is arranged on both sides of the groove-shaped element isolations, extending in the same direction as the groove-shaped element isolations at a position sandwiched between the gate electrodes, and the height of the upper end of the residue is lower than the height of the surface of the semiconductor substrate below the gate electrode of the all-around gate transistor, and a method for manufacturing this semiconductor device.

[0007] The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can reduce the connection resistance between the back-side contacts and the source / drain in a configuration having a full-circumference gate transistor.

[0008] This is a diagram showing the configuration of the semiconductor device of the first embodiment. This is the manufacturing process diagram (1) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (2) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (3) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (4) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (5) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (6) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (7) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (8) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (9) of the semiconductor device of the first embodiment. This is a diagram showing the configuration of the semiconductor device of the second embodiment. This is the manufacturing process diagram (1) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (2) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (3) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (4) of the semiconductor device of the second embodiment. This is a diagram showing the configuration of the semiconductor device of the third embodiment. This is the manufacturing process diagram (1) of the semiconductor device of the third embodiment. This is the manufacturing process diagram (2) of the semiconductor device of the third embodiment. This is the manufacturing process diagram (part 3) for the semiconductor device of the third embodiment. This is the manufacturing process diagram (part 4) for the semiconductor device of the third embodiment.

[0009] Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the embodiments described below, the same reference numerals are used for the same components, and some redundant descriptions will be omitted.

[0010] <First Embodiment> <Semiconductor Device of the First Embodiment> Figure 1 is a diagram showing the configuration of the semiconductor device 1 of the first embodiment, and shows a plan view 1a, the X1-X1 cross-section, the X2-X2 cross-section, and the Y-Y cross-section in the plan view 1a. The semiconductor device 1 shown in Figure 1 has a plurality of full-circumference gate transistors 10a. Each full-circumference gate transistor 10a is provided on the surface side of the semiconductor substrate 100, which is one of the main surfaces. In the drawings, the surface facing upward in each cross-section is the surface, and plan view 1a is a view of the semiconductor substrate 100 from the surface side.

[0011] The semiconductor substrate 100 on which the all-around gate transistor 10a is provided has a plurality of groove-shaped element separators 104 extending in one direction on the surface side. Each groove-shaped element separator 104 is constructed by embedding insulating material in the lower part of a groove pattern 100a formed on the surface side of the semiconductor substrate 100. The groove pattern 100a on which the groove-shaped element separators 104 are provided has a forward tapered shape on its side walls, and insulating material is embedded only in the lower part of such a groove pattern 100a to constitute the groove-shaped element separator 104.

[0012] The full-circumference gate transistors 10a are arranged in a matrix on the surface side of the semiconductor substrate 100 separated by groove-type element separators 104. Each full-circumference gate transistor 10a comprises a nanosheet laminate 103, a source / drain 109sd, a gate insulating film 200, and a gate electrode 201g.

[0013] The nanosheet laminate 103 has an island-like patterned shape and is arranged in a matrix on the surface side of the semiconductor substrate 100 separated by the groove-type element separator 104. Each nanosheet laminate 103 is composed of multiple nanosheet layers 102 stacked on top of each other. Each nanosheet layer 102 constitutes a semiconductor channel and is made of, for example, silicon. These nanosheet layers 102 are stacked with spacing between them, and each constitutes a GAA (Gate All Around) structure in which the entire circumference is surrounded by a gate electrode 201g via a gate insulating film 200.

[0014] The source / drain 109sd are located on both sides of the nanosheet laminate 103 in the gate length direction (here, the Y direction). Each source / drain 109sd is formed by epitaxial growth from the semiconductor substrate 100 and the nanosheet layer 102. One of these source / drain 109sd is connected to a surface-side contact of the semiconductor substrate 100 (not shown in this illustration), and through this surface-side contact, it is connected to a surface-side wiring. The other source / drain 109sd is connected to a back-side contact 202 that penetrates the semiconductor substrate 100.

[0015] The gate electrode 201g extends on the surface side of the semiconductor substrate 100 in a direction intersecting the groove-type element separator 104. Such gate electrode 201g is shared by a plurality of full-circumference gate transistors 10a arranged along the groove-type element separator 104. In addition, an insulating sidewall 107s is provided on the side wall of each gate electrode 201g, extending in a direction intersecting the groove-type element separator, electrically isolating the gate electrode 201g from the source / drain 109sd.

[0016] Furthermore, the back-side contact 202 connected to the source / drain 109sd is provided penetrating the semiconductor substrate 100 at a position sandwiched between the groove-type element separator 104 and the gate electrode 201g, and is connected to the source / drain 109sd of the all-around gate transistor 10a. Although not shown in the diagram here, the back-side contact 202 is further connected to the back-side wiring. This back-side wiring constitutes, for example, a Backside Power Delivery Network (BSPDN).

[0017] Here, on both sides of the grooved element separator 104, at a position sandwiched between the gate electrodes 201g, sidewall residue 107fg is positioned, extending in the same direction as the grooved element separator 104 and composed of the same material as the sidewall 107s. This residue 107fg is the portion of the constituent material of the sidewall 107s that was not removed during the sidewall 107s formation process, which will be described later, and is formed along the sidewall of the groove pattern 100a above the grooved element separator 104. This residue 107fg is also positioned on the sidewall of the back-side contact 202, which is connected to the source / drain 109sd at a position sandwiched between the grooved element separators 104. Therefore, the grooved element separator 104 is sandwiched between the residue 107fg.

[0018] In particular, in this semiconductor device 1, the height position [h1] of the upper end of the residue 107fg is lower than the height position [H0] of the surface of the semiconductor substrate 100 below the gate electrode 201g of the all-around gate transistor 10a. Furthermore, the surfaces of the semiconductor substrate 100 and the back-side contact 202 in the position sandwiched by the residue 107fg have a convex shape with the highest height position in the center. Moreover, the height positions of the surfaces of the semiconductor substrate 100 and the back-side contact 202 in the position sandwiched by the residue 107fg are lower than the height position [H0] of the semiconductor substrate 100 below the gate electrode 201g of the all-around gate transistor 10a. Also, the height position [h1] of the upper end of the residue 107fg is less than or equal to the height position of the semiconductor substrate 100 and the back-side contact 202 in the position sandwiched by the residue 107fg.

[0019] Furthermore, the back-side contact 202 is connected to the source / drain 109sd across the entire area between the residue 107fg, and the semiconductor substrate 100 is not sandwiched between the back-side contact 202 and the residue 107fg.

[0020] <Method of Manufacturing a Semiconductor Device of the First Embodiment> Figures 2 to 10 are manufacturing process diagrams (part 1) to (part 9) showing the method of manufacturing the semiconductor device 1 of the first embodiment. Hereinafter, the method of manufacturing the semiconductor device 1 of the first embodiment and the detailed configuration of each part will be explained in accordance with the manufacturing process sequence of the semiconductor device shown in Figures 2 to 10. Figures 2 to 10 correspond to the plan view 1a and each cross-sectional portion of Figure 1. However, the cross-section in the X direction of Figure 2 is common as the X-X cross-section.

[0021] First, as shown in Figure 2, a nanosheet laminate 103 is formed by stacking nanosheet layers 102 made of a semiconductor material via a sacrificial sheet layer 101 on one main surface of a semiconductor substrate 100 made of single crystal silicon. The sacrificial sheet layer 101 is constructed using a material that allows for selective etching of the nanosheet layers 102 made of semiconductor material. For example, when silicon is used as the semiconductor material constituting the nanosheet layers 102, silicon germanium is used as the sacrificial sheet layer 101.

[0022] Next, the nanosheet laminate 103 is patterned in a line extending in one direction (in this case, the Y direction) by etching using a resist pattern (not shown in the illustration) as a mask. Subsequently, using the resist pattern as a mask, one main surface side of the semiconductor substrate 100 is etched back to form a groove pattern 100a. The groove pattern 100a formed here has tapered side walls. After that, an insulating material is embedded to a predetermined depth in the lower part of the groove pattern 100a to form a groove-type element separator 104. The groove-type element separator 104 is formed using, for example, silicon oxide. The direction in which the groove-type element separator 104 extends (Y direction) is the gate length direction of the full-circumference gate transistor that is formed later.

[0023] Next, as shown in Figure 3, a dummy gate structure is formed by stacking a dummy gate 105 and a hard mask layer 106 in this order, extending substantially perpendicular to the nanosheet laminate 103 so as to cross the linearly separated nanosheet laminate 103. The dummy gate 105 is made of, for example, polysilicon, and the hard mask layer 106 is made of, for example, silicon nitride.

[0024] Next, as shown in Figure 4, an insulating liner film 107 is formed to cover the entire surface of the semiconductor substrate 100 on which the nanosheet laminate 103, dummy gate 105, and hard mask layer 106 are formed. This liner film 107 is formed using, for example, SiBCN (boronated silicon carbide nitride). The liner film 107 may also be silicon nitride such as SiN, SiON, or SiOCN.

[0025] Next, as shown in Figure 5, the liner film 107 is etched back to form sidewalls 107s made of the liner film 107 on the sidewalls of the dummy gate 105 and the hard mask layer 106. In this etch-back of the liner film 107, the liner film 107 on the upper surface of the nanosheet laminate 103, the upper surface of the grooved element separator 104, and the upper surface of the hard mask layer 106 is removed. On the other hand, the liner film 107 remains as residue 107fg on the sidewalls of the stepped portion as well as on the sidewalls of the hard mask layer 106. In this case, the residue 107fg is formed on both upper sides of the grooved element separator 104, along the sidewalls of the nanosheet laminate 103 from the sidewalls of the groove pattern 100a, and extends along the extension direction of the grooved element separator 104 at the position sandwiched by the dummy gate 105.

[0026] Next, as shown in Figure 6, the nanosheet laminate 103 is etched using a dummy gate structure consisting of a dummy gate 105 and a hard mask layer 106, and the sidewall 107s as a mask, thereby patterning the nanosheet laminate 103 in an island-like manner. In this etching process, the semiconductor substrate 100 is over-etched. This causes the semiconductor substrate 100 beneath the island-patterned nanosheet laminate 103 to protrude in an island-like manner. Furthermore, this over-etching of the semiconductor substrate 100 forms recesses 100b of a predetermined depth [D1] in the semiconductor substrate 100 at positions sandwiched from the Y direction by the dummy gate 105 and sandwiched from the X direction by the groove-type element separator 104. The depth [D1] of the recesses 100b is typically about the same as or shallower than the surface of the groove-type element separator 104 formed within the groove pattern 100a.

[0027] In the etching of the nanosheet laminate 103 and the semiconductor substrate 100 as described above, the residue 107fg formed along the extension direction of the groove-type element separator 104 remains on the groove-type element separator 104. Then, minute protrusions A1 are formed on the semiconductor substrate 100 along the residue 107fg in the extension portion of the recess 100b. These protrusions A1 are formed because the etched sidewalls become tapered when the semiconductor substrate 100 is over-etched.

[0028] Next, as shown in Figure 7, in the process of forming the sidewall 107s, the residue 107fg of the liner film 107 remaining on both sides of the groove-type element separator 104 is etched back. At this time, the residue 107fg is selectively etched against the semiconductor substrate 100, and the residue 107fg is moved back to a height position [h1] that is at least lower than the surface height [H0] of the semiconductor substrate 100, and further moved back until the residue 107fg is lower than the bottom of the recess 100b (see Figure 6) of the semiconductor substrate 100. In this process, the residue 107fg is selectively etched against the semiconductor substrate 100, but the etchant also acts on minute protrusions A1 (see Figure 6) of the semiconductor substrate 100, so these protrusions A1 are also scraped and moved back. For this reason, preferably, the residue 107fg is etched back to the extent that these minute protrusions A1 are removed.

[0029] In the process described using Figure 6, the semiconductor substrate 100 was over-etched, but the etching of the nanosheet laminate 103 may be stopped when the semiconductor substrate 100 is exposed. In this case, etching is carried out using a fluorine (Br)-based gas that can etch the SiGe constituting the sacrificial sheet layer 101 with high selectivity against the Si constituting the semiconductor substrate 100. In etching using a Br-based gas, the sidewalls of the highly chemically reactive SiGe become tapered during etching. On the other hand, the processing of the flat Si semiconductor substrate 100, which has low chemical reactivity and is resistant to physical impact, hardly progresses. Therefore, etching stops at the surface of the semiconductor substrate 100. Then, the sacrificial sheet layer 101 made of SiGe remains in a tapered shape along the residue 107fg.

[0030] Subsequently, etching of the residue 107fg is carried out under conditions that allow for high selectivity etching of the silicon nitride constituting the residue 107fg against the Si constituting the semiconductor substrate 100. During this etching process, the residue 107fg and the sacrificial sheet layer 101 protrude in a angular shape on the upper part of the semiconductor substrate 100 in the X2-X2 cross section. However, by further etching, etching proceeds intensively at the angular protrusions. As a result, as shown in Figure 7, the residue 107fg recedes to a height roughly the same as the semiconductor substrate 100, and the sacrificial sheet layer 101 on the semiconductor substrate 100 is removed.

[0031] According to the above procedure, the bottommost sacrificial sheet layer 101 in the nanosheet laminate 103 can be reliably removed in the X2-X2 cross-section without over-etching the semiconductor substrate 100. In this case, the surface of the semiconductor substrate 100 between the groove patterns 100a in the X2-X2 cross-section is kept flat at the initial surface height "H0".

[0032] Next, as shown in Figure 8, both ends of the sacrificial sheet layer 101 exposed on the side wall of the nanosheet laminate 103 are replaced with insulating inner spacers 108. In this process, first, both ends of the sacrificial sheet layer 101 are selectively thinned by isotropic etching. Then, an insulating film is deposited by isotropic deposition, and the insulating film is etched back by anisotropic etching. This leaves the insulating film sandwiched only in the positions between the nanosheet layers 102 in the vertical direction and between the bottom nanosheet layer 102 and the semiconductor substrate 100, and the remaining insulating film is formed as the inner spacer 108.

[0033] Next, as shown in Figure 9, source / drain 109sd are formed on both sides of the exposed surface of the nanosheet laminate 103, that is, on both sides in one direction (here, the Y direction) of the nanosheet laminate 103. At this time, each source / drain 109sd containing p-type or n-type impurities is formed by epitaxial growth from the semiconductor substrate 100 exposed in the nanosheet layer 102 and the recess 100b. For example, for a p-type source / drain 109sd, silicon germanium containing p-type impurities is epitaxially grown. For an n-type source / drain 109sd, silicon containing n-type impurities is epitaxially grown. The formation of each conductivity type of source / drain 109sd is carried out with other regions covered by a mask.

[0034] Next, as shown in Figure 10, a gate electrode 201g is formed via a gate insulating film 200 so as to cover the entire circumference of the nanosheet layer 102. In this process, first, the hard mask layer 106 and the dummy gate 105 (see Figure 9) are removed by selective etching, and then the sacrificial sheet layer 101 (see Figure 9) is selectively etched off by etching from the exposed surface of the nanosheet laminate 103. This exposes the central part of the silicon nanosheet layer 102 around its entire circumference.

[0035] Subsequently, a gate insulating film 200 is formed on the exposed surface of the nanosheet layer 102, and then a gate electrode 201g is formed via the gate insulating film 200. The gate electrode 201g then fills the positions sandwiched between the nanosheet layers 102 in the vertical direction, the positions sandwiched between the bottom nanosheet layer 102 and the semiconductor substrate 100, and the positions sandwiched by the sidewalls 107s. At this time, the gate insulating film 200 is formed using a high dielectric constant film, and the gate electrode 201g is formed using, for example, tungsten (W). As a result, a full-circumference gate transistor 10a is obtained in which the entire circumference of the nanosheet layer 102 is surrounded by the gate electrode 201g via the gate insulating film 200.

[0036] Subsequently, although not shown in the diagram here, an interlayer insulating film is formed to cover the full-circumference gate transistor 10a, and a surface-side contact is formed that is connected to one of the source / drain 109sd of the full-circumference gate transistor 10a. Furthermore, surface-side wiring connected to the surface-side contact and gate electrode 201g, and an interlayer insulating film are formed as needed. Next, a carrier substrate is bonded to the surface side of the semiconductor substrate 100 on which the full-circumference gate transistor 10a is formed, and the semiconductor substrate 100 is thinned as needed.

[0037] Following the above steps, as shown in Figure 1, a back-side contact 202 connected to the target source / drain 109sd is formed on the back side of the semiconductor substrate 100. Note that the target source / drain 109sd is one to which the front-side contact is not connected. In this case, first, an opening with the target source / drain 109sd as the bottom surface is patterned on the semiconductor substrate 100. At this time, a mask pattern (not shown here) is formed on the back side of the semiconductor substrate 100, and the semiconductor substrate 100 at the position sandwiched between the residues 107fg is selectively etched from the mask pattern. This forms an opening with the target source / drain 109sd as the bottom surface across the entire surface between the residues 107fg.

[0038] Subsequently, a conductive material film, such as a metal material, is formed on the back side of the semiconductor substrate 100 to fill the opening, and the conductive material film is CMP polished until the semiconductor substrate 100 is exposed. This leaves the conductive material film only inside the opening, and the conductive material film remaining inside the opening is formed as the back side contact 202. This forms the back side contact 202 that penetrates the semiconductor substrate 100 at the position sandwiched between the residues 107fg and is connected to the source / drain 109sd across the entire surface between the residues 107fg.

[0039] The back-side contact 202 formed in this manner has a surface height position lower than the surface height position [H0] of the semiconductor substrate 100 below the gate electrode 201g of the all-around gate transistor 10a. Also, the height position of the upper end of the residue 107fg is lower than or equal to the height position of the back-side contact 202. Furthermore, the surface of the back-side contact 202 has a convex shape with the highest height position in the center.

[0040] Subsequently, although not shown in the diagram here, backside wiring connected to the backside contacts 202 is formed on the back side of the semiconductor substrate 100. This backside wiring constitutes, for example, a backside power delivery network (BSPDN). After that, a cap insulating film is formed to cover the backside wiring, completing the semiconductor device 1.

[0041] <Effects of the First Embodiment> In the semiconductor device 1 of the first embodiment described above, the residue 107fg generated when forming the sidewall 107s of the side wall of the gate electrode 201g recedes to a height position [h1] lower than the height position [H0] of the surface of the semiconductor substrate 100. As a result, the projection A1 (see Figure 6) along the residue 107fg also recedes from the surface portion of the semiconductor substrate 100 at the position sandwiched by the residue 107fg. This makes it possible to suppress the obstruction of the epitaxial growth of the source / drain 109sd on the semiconductor substrate 100 at the position sandwiched by the residue 107fg by the residue 107fg. In other words, as shown in Figure 6, if epitaxial growth of the source / drain 109sd is carried out with the residue 107fg left as is, the lateral epitaxial growth is inhibited by the residue 107fg. However, in the configuration of the first embodiment, the residue 107fg is receded, so the inhibition of epitaxial growth is suppressed.

[0042] Furthermore, in the semiconductor device 1 according to the first embodiment, the protrusion A1 (see FIG. 6) is recessed together with the residue 107fg. Therefore, when the back side contact 202 is formed by penetrating the semiconductor substrate 100 from the back side of the semiconductor substrate 100, it is easy to completely remove the portion of the semiconductor substrate 100 bonded to the source / drain 109sd. For this reason, the back side contact 202 connected to the source / drain 109sd can be formed on the entire surface between the residues 107fg. In contrast, as shown in FIG. 6, when an opening for forming the back side contact 202 is formed in the semiconductor substrate 100 with the residue 107fg left as it is, it is difficult to remove the fine protrusion A1 by etching. For this reason, the protrusion A1 made of the semiconductor substrate 100 remains at a position sandwiched between the source / drain 109sd and the back side contact 202, which becomes a factor that reduces the connection area between the source / drain 109sd and the back side contact. However, in the configuration of the first embodiment, since the residue 107fg is recessed, the connection area between the source / drain 109sd and the back side contact can be secured.

[0043] As a result of the above, according to the first embodiment, in the semiconductor device 1 including the all-around gate transistor 10a, it is possible to reduce the connection resistance between the back side contact 202 and the source / drain 109sd.

[0044] <<Second Embodiment>> <Semiconductor device according to the second embodiment> FIG. 11 is a diagram showing the configuration of a semiconductor device 2 according to the second embodiment, and shows a plan view 1a, a cross-section taken along line X1-X1 in the plan view 1a, a cross-section taken along line X2-X2, and a cross-section taken along line Y-Y. The difference between the semiconductor device 2 according to the second embodiment shown in FIG. 11 and the semiconductor device 1 according to the first embodiment (see FIG. 1) lies in the shapes of the source / drain 109sd and the back side contact 202', and other configurations are the same as those of the first embodiment, so the description thereof is omitted here.

[0045] In other words, the back-side contact 202' is connected to the source / drain 109sd across the entire area between the residue 107fg, and the semiconductor substrate 100 is not sandwiched between the back-side contact 202' and the residue 107fg, as in the first embodiment. On the other hand, the back-side contact 202' has a flat surface. The residue 107fg, which is located on both sides of the back-side contact 202', also has a flat upper surface. Furthermore, the semiconductor substrate 100 at the position sandwiched by the residue 107fg also has a flat surface.

[0046] Furthermore, the height position of the surface of the back-side contact 202' is lower than the height position [H0] of the surface of the semiconductor substrate 100 below the gate electrode 201g of the all-around gate transistor 10a, as in the first embodiment. However, the surface of the semiconductor substrate 100 or the back-side contact 202' at the position sandwiched by the residue 107fg, and the upper surface of the residue 107fg, are flat. Also, the height position [h2] of the upper end of the residue 107fg is lower than the height position [h1] of the first embodiment (see Figure 1), and is about the same as or less than the height position of the surface of the back-side contact 202'. For this reason, the upper end of the residue 107fg is configured to be closer to the surface of the groove-type element separator 104 compared to the first embodiment. Here, the groove pattern 100a on which the groove-type element separator 104 is provided has a forward tapered side wall shape. Therefore, the lower the height position [h2] of the upper end of the residue 107fg, the larger the surface area of ​​the semiconductor substrate 100 and the surface area of ​​the back-side contact 202' exposed in the position sandwiched by the residue 107fg. Consequently, this semiconductor device 2 has a large connection area between the back-side contact 202' and the source / drain 109sd.

[0047] <Method of Manufacturing a Semiconductor Device of the Second Embodiment> Figures 12 to 15 are manufacturing process diagrams (part 1) to (part 4) showing the method of manufacturing the semiconductor device 2 of the second embodiment. Hereinafter, the method of manufacturing the semiconductor device 2 of the second embodiment and the detailed configuration of each part will be explained in accordance with the manufacturing process sequence of the semiconductor device shown in Figures 12 to 15. Figures 12 to 15 correspond to the plan view 1a and each cross-sectional view of Figure 11.

[0048] First, in the first embodiment, the procedure described with reference to FIGS. 1 to 7 is performed, and the steps are carried out until the residual 107fg formed along the extending direction of the groove-type element isolation 104 is selectively etched and retreated.

[0049] Next, as shown in FIG. 12, in the recess 100b of the semiconductor substrate 100 at the position sandwiched between the residues 107fg, the semiconductor substrate 100 is etched to further retreat. Thereby, the depth [D2] of the recess 100b is dug deeper than the initial depth [D1], and the surface of the semiconductor substrate 100 at the position sandwiched between the residues 107fg is planarized. Further, the semiconductor substrate 100 located under the recess 100b is formed in a sidewall tapered shape. Therefore, digging the recess 100b deeper increases the bottom area of the recess 100b. Note that the bottom area of the recess 100b is the exposed area of the semiconductor substrate 100 at the position sandwiched between the residues 107fg.

[0050] Further, before or after etching the recess of the semiconductor substrate 100, etching of the residue 107fg is performed. Thereby, the height position [h2] of the top surface of the residue 107fg is made equal to or lower than the height position of the surface of the semiconductor substrate 100 at the position sandwiched between the residues 107fg, and the top surface of the residue 107fg is planarized. Note that in this step, the etching of the semiconductor substrate 100 and the etching of the residue 107fg made of an insulating material such as a silicon nitride film may be performed in any order according to respective etching conditions.

[0051] Next, as shown in FIG. 13, both ends of the sacrificial sheet layer 101 exposed on the sidewall of the nanosheet laminate 103 are replaced with insulating inner spacers 108. This step is performed in the same manner as the procedure described with reference to FIG. 8 in the first embodiment.

[0052] Next, as shown in FIG. 14, source / drain 109sd are formed on both sides of the exposed surface of the nanosheet laminate 103, that is, on both sides in one direction (here, the Y direction) of the nanosheet laminate 103. This step is performed in the same manner as the procedure described with reference to FIG. 9 in the first embodiment.

[0053] Next, as shown in Figure 15, a gate electrode 201g is formed via the gate insulating film 200 so as to cover the entire circumference of the nanosheet layer 102. This step is carried out in the same manner as the procedure described with reference to Figure 10 in the first embodiment. As a result, a full-circumference gate transistor 10a is obtained in which the entire circumference of the nanosheet layer 102 is surrounded by the gate electrode 201g via the gate insulating film 200.

[0054] Subsequently, in the same procedure as in the first embodiment, interlayer insulating films, surface-side contacts, surface-side wiring, and interlayer insulating films are formed as needed (not shown in the illustration here), the carrier substrate is bonded, and the semiconductor substrate 100 is thinned as needed.

[0055] After the above, as shown in Figure 11, a back-side contact 202' connected to the other of the source / drain 109sd is formed on the back side of the semiconductor substrate 100. Here, the other of the source / drain 109sd is the one to which the front-side contact is not connected, as in the first embodiment. This step is carried out in the same way as the procedure described with reference to Figure 1 in the first embodiment. After that, as in the first embodiment, a back-side wiring connected to the back-side contact 202' is formed on the back side of the semiconductor substrate 100, and a cap insulating film is formed to cover the back-side wiring to complete the semiconductor device 2.

[0056] <Effects of the Second Embodiment> According to the second embodiment described above, by moving the residue 107fg generated when forming the sidewall 107s of the side wall of the gate electrode 201g, and the surface of the semiconductor substrate 100 at the position sandwiched by the residue 107fg, to an even lower height position [h2], it is possible to increase the connection area between the source / drain 109sd and the back side contact 202'. As a result, in the semiconductor device 2 having a full-circumference gate transistor 10a, it is possible to further reduce the connection resistance between the back side contact 202' and the source / drain 109sd.

[0057] <Third Embodiment> <Semiconductor Device of the Third Embodiment> Figure 16 is a diagram showing the configuration of the semiconductor device 3 of the third embodiment, and shows a plan view 1a, the X1-X1 cross-section, the X2-X2 cross-section, and the Y-Y cross-section in the plan view 1a. The difference between the semiconductor device 3 of the third embodiment shown in Figure 16 and the semiconductor device 1 of the first embodiment (see Figure 1) is that it does not have residue 107fg (see Figure 1), and the shape of the groove-type element separator 104" and the back-side contact 202". The other configurations are the same as those of the first embodiment, so their explanation is omitted here.

[0058] In other words, the semiconductor device 3 is one from which the residue 107fg present in the semiconductor device 1 of the first embodiment has been removed, and is free of residue 107fg.

[0059] Furthermore, at the position where the groove-shaped element separator 104" is sandwiched by the gate electrode 201g (see cross section X2-X2), the height of the surface of both side edges along the extension direction is lower than that of the central part. Also, at the position sandwiched by the groove-shaped element separator 104" and sandwiched by the gate electrode 201g, the height of the surface of the semiconductor substrate 100 is approximately equal to the height of the surface of both side edges of the groove-shaped element separator 104", forming a recess that is lower than the height of the surface of the groove-shaped element separator 104".

[0060] The back-side contact 202" has a connection surface with the source / drain 109sd at a height lower than the surface of the groove-type element separator 104", and is connected to the source / drain 109sd across the entire surface between the groove-type element separators 104". Here, the groove pattern 100a in which the groove-type element separator 104" is provided has a forward tapered side wall. Therefore, this semiconductor device 3 has a larger connection area between the back-side contact 202" and the source / drain 109sd than the semiconductor devices of the first and second embodiments.

[0061] <Method of Manufacturing a Semiconductor Device of the Third Embodiment> Figures 17 to 20 are manufacturing process diagrams (part 1) to (part 4) showing the method of manufacturing the semiconductor device 2 of the second embodiment. Hereinafter, the method of manufacturing the semiconductor device 3 of the third embodiment and the detailed configuration of each part will be explained in accordance with the manufacturing process sequence of the semiconductor device shown in Figures 17 to 20. Figures 17 to 20 correspond to the plan view 1a and each cross-sectional view of Figure 16.

[0062] First, the procedure described with reference to Figures 1 to 6 in the first embodiment is carried out to pattern the nanosheet laminate 103 in an island shape, and then to over-etch the semiconductor substrate 100. This causes the semiconductor substrate 100 beneath the nanosheet laminate 103 to protrude in an island shape, and a recess 100b of a predetermined depth [D1] is formed in the semiconductor substrate 100 at a position where it is sandwiched from the Y direction by the dummy gate 105 and sandwiched from the X direction by the groove-type element separator 104.

[0063] Next, as shown in Figure 17, the residue 107fg is selectively etched from the semiconductor substrate 100 to completely remove it. Furthermore, the semiconductor substrate 100 sandwiched between the residue 107fg is etched back, receding to a position lower than the surface of the groove-type element separator 104. In addition, the portion of the groove-type element separator 104 that was below the residue 107fg is etched back, receding to approximately the same level as the surface of the semiconductor substrate 100 sandwiched between the residue 107fg. As a result, the groove-type element separator 104 has a shape in which the height of the surface of both side edges along the extension direction is lower than that of the central part. Also, the semiconductor substrate 100 sandwiched between the residue 107fg and the side edges of the groove-type element separator 104" form a recess 100b" that is lower in height than the surface of the groove-type element separator 104"

[0064] In this process, etching of the semiconductor substrate 100 and etching of the residue 107fg composed of each insulating material and the groove-type element separator 104 can be carried out in any order according to the respective etching conditions.

[0065] Next, as shown in Figure 18, both ends of the sacrificial sheet layer 101 exposed on the side wall of the nanosheet laminate 103 are replaced with insulating inner spacers 108. This step is carried out in the same manner as the procedure described with reference to Figure 8 in the first embodiment.

[0066] Next, as shown in Figure 19, source / drain 109sd are formed on both sides of the exposed surface of the nanosheet laminate 103, that is, on both sides in one direction (here, the Y direction) of the nanosheet laminate 103. This step is carried out in the same manner as the procedure described with reference to Figure 9 in the first embodiment.

[0067] Next, as shown in Figure 20, a gate electrode 201g is formed via the gate insulating film 200 so as to cover the entire circumference of the nanosheet layer 102. This step is carried out in the same manner as the procedure described with reference to Figure 10 in the first embodiment. As a result, a full-circumference gate transistor 10a is obtained in which the entire circumference of the nanosheet layer 102 is surrounded by the gate electrode 201g via the gate insulating film 200.

[0068] Subsequently, in the same procedure as in the first embodiment, interlayer insulating films, surface-side contacts, surface-side wiring, and interlayer insulating films are formed as needed (not shown in the illustration here), the carrier substrate is bonded, and the semiconductor substrate 100 is thinned as needed.

[0069] After the above, as shown in Figure 16, a back-side contact 202" connected to the other of the source / drain 109sd is formed on the back side of the semiconductor substrate 100. Here, the other of the source / drain 109sd is the one to which the front-side contact is not connected, as in the first embodiment. This step is carried out in the same way as the procedure described with reference to Figure 1 in the first embodiment. After that, as in the first embodiment, back-side wiring connected to the back-side contact 202" is formed on the back side of the semiconductor substrate 100, and a cap insulating film is formed to cover the back-side wiring to complete the semiconductor device 3.

[0070] <Effects of the Third Embodiment> According to the third embodiment described above, compared to the configurations of the first and second embodiments, the residue 107fg generated when forming the sidewall 107s of the side wall of the gate electrode 201g is removed, and the surface of the semiconductor substrate 100 at the position sandwiched by the residue 107fg is moved back to a height lower than the surface of the groove-type element separator 104", thereby making it possible to further increase the connection area between the source / drain 109sd and the back-side contact 202",. As a result, compared to the first and second embodiments, it is possible to further reduce the connection resistance between the back-side contact 202", and the source / drain 109sd in the semiconductor device 3 having a full-circumference gate transistor 10a.

[0071] 1, 2, 3… Semiconductor device 10a… Full-circumference gate transistor 100… Semiconductor substrate 100a… Groove 100b, 100b”… Recess 101… Sacrificial sheet layer 102… Nanosheet layer 103… Nanosheet laminate 104, 104”… Groove-type element isolation 105… Dummy gate 106… Hard mask layer 107… Liner film 107fg… Residue 107s… Sidewall 108… Inner spacer 109sd… Source / drain 200… Gate insulating film 201g… Gate electrode 202, 202', 202”… Backside contact A1… Protrusion

Claims

1. A semiconductor device comprising: a semiconductor substrate; a plurality of groove-shaped element isolations extending in one direction on the surface side of the semiconductor substrate; a plurality of full-circumference gate transistors arranged in a matrix on the surface side of the semiconductor substrate separated by the groove-shaped element isolations, sharing gate electrodes extending in a direction intersecting the groove-shaped element isolations; an insulating sidewall provided on the side wall of each gate electrode and extending in a direction intersecting the groove-shaped element isolations; and a back-side contact provided at a position sandwiched between the groove-shaped element isolations and at a position sandwiched between the gate electrodes, penetrating the semiconductor substrate and connected to the source / drain of the full-circumference gate transistors, wherein a residue made of the constituent material of the sidewalls extends on both sides of the groove-shaped element isolations in the same direction as the groove-shaped element isolations at a position sandwiched between the gate electrodes, and the height position of the upper end of the residue is lower than the height position of the surface of the semiconductor substrate below the gate electrode of the full-circumference gate transistor.

2. The semiconductor device according to claim 1, wherein the groove-type element isolation is constructed by embedding an insulating material in the lower part of a groove pattern formed on the surface side of the semiconductor substrate, and the residue is arranged along the inner wall of the groove pattern on the groove-type element isolation.

3. The semiconductor device according to claim 1, wherein the groove pattern in which the groove-shaped element separator is provided has a forward tapered side wall.

4. The semiconductor device according to claim 1, wherein the back-side contact is connected to the source / drain over the entire surface between the residues.

5. The semiconductor device according to claim 1, wherein the height position of the semiconductor substrate and the back-side contact surface at the position sandwiched by the residue is lower than the height position of the semiconductor substrate surface below the gate electrode in the all-around gate transistor, and the height position of the upper end of the residue is less than or equal to the height position of the semiconductor substrate and the back-side contact at the position sandwiched by the residue.

6. The semiconductor device according to claim 1, wherein the surface of the semiconductor substrate and the back-side contact at the position sandwiched by the residue has a convex shape with the highest height position in the central part.

7. The semiconductor device according to claim 1, wherein the surface of the semiconductor substrate and the back-side contact at the position sandwiched by the residue, and the upper surface of the residue, are flat.

8. A semiconductor device comprising: a semiconductor substrate; a plurality of groove-shaped element isolations extending in one direction on the surface side of the semiconductor substrate; a plurality of all-around gate transistors arranged in a matrix on the surface side of the semiconductor substrate separated by the groove-shaped element isolations, sharing gate electrodes extending in a direction intersecting the groove-shaped element isolations; an insulating sidewall provided on the side wall of each gate electrode and extending in a direction intersecting the groove-shaped element isolations; and a back-side contact provided at a position sandwiched between the groove-shaped element isolations and at a position sandwiched between the gate electrodes, penetrating the semiconductor substrate and connected to the source / drain of the all-around gate transistors, wherein the height position of the surface of the semiconductor substrate at the position sandwiched between the groove-shaped element isolations and at a position sandwiched between the gate electrodes forms a recess lower than the height position of the surface of the groove-shaped element isolations; the groove-shaped element isolations have surface height positions at both side edges along the extension direction at the position sandwiched between the gate electrodes lower than the central part; and the source / drain is arranged in contact with both side edges of the groove-shaped element isolations.

9. The semiconductor device according to claim 8, wherein the back-side contact has a connection surface with the source / drain at a height lower than the surface of the groove-type element isolation and is connected to the source / drain across the entire area between the groove-type element isolations.

10. A step of patterning a nanosheet laminate, which is made of multiple nanosheet layers made of semiconductor material, in a linear fashion on the surface of a semiconductor substrate, and further forming a groove pattern by excavating the surface side of the semiconductor substrate; a step of embedding an insulating material in the groove pattern to form a groove-type element isolation; a step of forming a linear dummy gate structure so as to intersect with the linearly patterned nanosheet laminate, and a step of depositing an insulating liner film on the surface of the semiconductor substrate so as to cover the dummy gate structure; a step of etching back the insulating liner film to form a sidewall on the side wall of the dummy gate structure; a step of patterning the linear nanosheet laminate in an island-like fashion by etching from the dummy gate structure and the sidewall; a step of etching back the residue of the insulating liner film left on both sides of the groove-type element isolation in the step of forming the sidewall; a step of forming a source / drain at a position sandwiched between the groove-type element isolation by epitaxial growth from the semiconductor substrate and the nanosheet layer. A method for manufacturing a semiconductor device, comprising the steps of: removing the dummy gate structure, covering the entire circumference of the nanosheet layer with a gate electrode via a gate insulating film; and forming a back-side contact that penetrates the semiconductor substrate and is connected to the source / drain at a position sandwiched between the groove-type element separators and the gate electrode.

11. The method for manufacturing a semiconductor device according to claim 10, wherein in the step of etching back the residue, the height position of the upper end of the residue is lower than the height position of the surface of the semiconductor substrate.

12. The method for manufacturing a semiconductor device according to claim 10, wherein in the step of forming the groove-shaped element isolation, an insulating material is embedded in the lower part of the groove pattern, and in the step of etching back the residue, the residue left along the inner wall of the groove pattern on the groove-shaped element isolation is etched back.

13. The method for manufacturing a semiconductor device according to claim 10, wherein in the step of forming the back-side contact, the back-side contact is formed so as to connect to the source / drain over the entire surface between the residues.

14. The method for manufacturing a semiconductor device according to claim 10, wherein the residue is removed in the step of etching back the residue.

15. The method for manufacturing a semiconductor device according to claim 14, wherein, after removing the residue and before forming the source / drain, the portion of the semiconductor substrate sandwiched between the groove-shaped element separator and the residue is etched back, and the height position of the surface of the semiconductor substrate sandwiched between the groove-shaped element separator and the gate electrode is made into a recess lower than the height position of the surface of the groove-shaped element separator, and the height positions of the surfaces of both side edges along the extension direction of the groove-shaped element separator are lower than the central portion.

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