Liquid crystal display device

Abstract

A liquid crystal display device according to the present disclosure comprises: a plurality of pixels; a horizontal driver that has a plurality of data lines provided so as to correspond to each column of the plurality of pixels and a plurality of first switching elements for switching whether to supply a video signal to each of the plurality of data lines; a pixel inspection circuit that has a plurality of sense amplifiers for, when in a pixel inspection mode, amplifying the potential difference between a prescribed voltage and a plurality of pixel drive voltages which are read out to each of the plurality of data lines from a plurality of pixels provided in a row to be inspected; a first pad that is connected to the horizontal driver and is supplied with a first power supply voltage; a second pad that is connected to the pixel inspection circuit and is supplied with a second power supply voltage; a third pad that is connected at least to the pixel inspection circuit and is supplied with a ground voltage; and a pull-down resistor that is provided between the second pad and the third pad.

Description

Liquid crystal display device

[0001] The present disclosure relates to a liquid crystal display device, and more particularly to a liquid crystal display device suitable for rapidly executing pixel inspection while suppressing an increase in power consumption.

[0002] The liquid crystal display device disclosed in Patent Document 1 includes: a plurality of pixels arranged in a matrix; a plurality of sets of data lines provided corresponding to respective columns of the plurality of pixels; a plurality of gate lines provided corresponding to respective rows of the plurality of pixels; a plurality of switches for sequentially supplying positive and negative video signals in set units to the plurality of sets of data lines; and driving means for driving the plurality of switches and the plurality of gate lines.

[0003] Japanese Unexamined Patent Publication No. 2009-223289

[0004] Incidentally, in order to improve reliability, liquid crystal display devices are required to inspect pixels for defects and characteristic deterioration, for example, before product shipment.

[0005] However, Patent Document 1 does not disclose specific details about a pixel inspection method. Therefore, in the liquid crystal display device disclosed in Patent Document 1, it is considered that, for example, a video signal (pixel driving voltage) written to a pixel to be inspected is read out using a writing path for writing video signals to pixels during normal operation, and pixel inspection is performed based on the read-out video signal. However, in this inspection method, due to the influence of large wiring capacitance added to the video signal propagation path, the video signal written to the pixel to be inspected cannot be read out rapidly, so there is a problem that pixel inspection cannot be performed rapidly.

[0006] Furthermore, in order to solve this problem, if a pixel inspection circuit is provided that reads out a video signal written to a pixel from a path different from the path for writing the video signal to the pixel during pixel inspection, there is a problem that the pixel inspection circuit, which becomes unnecessary after pixel inspection, continues to consume power.

[0007] The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to provide a liquid crystal display device capable of rapidly executing pixel inspection while suppressing an increase in power consumption.

[0008] The liquid crystal display device according to this disclosure comprises a horizontal driver having at least a plurality of pixels arranged in a matrix, a plurality of data lines provided corresponding to each row of the plurality of pixels, and a plurality of first switch elements that switch whether or not to supply a video signal to each of the plurality of data lines, and a pixel inspection circuit having at least a plurality of sense amplifiers that, in pixel inspection mode, amplify the potential difference between a plurality of pixel drive voltages read from each of the plurality of data lines from the plurality of pixels provided in the row to be inspected and a predetermined voltage, and output it as a plurality of detection signals, and each of the pixels comprises a sample-and-hold circuit that samples and holds the video signal supplied to the corresponding data line, and The horizontal driver further comprises a liquid crystal display element composed of a pixel drive electrode, a common electrode, and liquid crystal sealed between them, to which the voltage of the video signal held in the sample-and-hold circuit is supplied; a switch transistor that, in pixel inspection mode, outputs the voltage of the pixel drive electrode as the pixel drive voltage to the corresponding data line; a first pad connected to the horizontal driver and supplied with a first power supply voltage; a second pad connected to the pixel inspection circuit and supplied with a second power supply voltage from a different power supply system than the first power supply voltage; a third pad at least connected to the pixel inspection circuit and supplied with a ground voltage; and a pull-down resistor provided between the second pad and the third pad.

[0009] According to this disclosure, it is possible to provide a liquid crystal display device that can perform pixel inspection quickly while suppressing an increase in power consumption.

[0010] This is a view of the wavelength selective switch according to this disclosure from the x-axis direction. This is a view of the wavelength selective switch according to this disclosure from the y-axis direction. This is a diagram showing an example of a wavelength channel focused on a reflective liquid crystal element applied to the wavelength selective switch according to this disclosure. This is a diagram showing an example configuration of a liquid crystal device in the conceptual stage. This is an enlarged view of the horizontal driver and analog switch section provided in the liquid crystal device shown in Figure 4. This is a diagram showing a specific example configuration of a pixel provided in the liquid crystal device shown in Figure 4. This is a timing chart for explaining the method of driving pixels by the liquid crystal device shown in Figure 4. This is a diagram for explaining the voltage levels from black to white for the positive polarity video signal and negative polarity video signal written to the pixel. This is a timing chart showing the operation of the liquid crystal device shown in Figure 4 in image display mode. This is a view of the configuration of a liquid crystal device in the conceptual stage. This is a diagram showing a part of the pixel inspection circuit provided in the liquid crystal device shown in Figure 10 in more detail. This is a diagram showing a specific example configuration of a sense amplifier provided in the pixel inspection circuit of the liquid crystal device shown in Figure 10. This is a diagram showing a specific example configuration of a shift register circuit provided in the pixel inspection circuit. This is a timing chart showing the operation of the liquid crystal device shown in Figure 10 in pixel inspection mode. This is a diagram showing an example configuration of a liquid crystal device according to Embodiment 1. This figure shows a specific example of the configuration of a sense amplifier provided in the pixel inspection circuit of a liquid crystal device according to Embodiment 1. This is a schematic plan view showing an example of the circuit arrangement of a liquid crystal device chip according to Embodiment 1. This is a schematic perspective view showing the external appearance of a liquid crystal device chip according to Embodiment 1. This is a schematic plan view showing the external appearance of a liquid crystal device according to Embodiment 1.

[0011] <Explanation of Wavelength Selective Switches to which Liquid Crystal Devices According to This Disclosure are Applied> Figure 1 is a diagram showing an example configuration of a Wavelength Selective Switch (WSS) array 100 according to this disclosure. Figure 1 is a view of the WSS array 100 from the x-axis direction.

[0012] In recent years, optical communication networks have been developed to meet the demands for higher speeds and larger capacities in telecommunications and data networks. Generally, optical communication networks employ Wavelength Division Multiplexing (WDM) technology, which utilizes as much of the optical spectrum as possible. In optical WDM, as in wireless WDM, data is modulated on multiple carrier waves of different wavelengths. These multiple carrier waves are called channels (wavelength channels). In optical WDM, optical waves are used instead of radio waves compared to wireless WDM, and different wavelength channels correspond to different frequencies (wavelengths) of light. Generally, in optical communication, channels within or near the wavelength range of 1 to 2 μm are used.

[0013] In many optical communication networks, optical nodes are used that correspond to branching points in the network. Each optical node uses, for example, a reconfigurable optical add-drop multiplexer (ROADM) device with reconfigurable add-drop functionality. Generally speaking, the ROADM functionality allows for the removal or addition of one or more wavelength channels at each optical node.

[0014] The WSS array 100 may be used in a ROADM system for routing arbitrary wavelength channels. In this case, the WSS array 100 may use an optical beam deflection device such as a spatial light modulator, and the optical beam deflection device may select a wavelength for deflection to a desired output port. For example, deflection of a wavelength channel to a drop port results in the channel being removed from the WDM signal. Furthermore, the WSS array 100 may use a spatial light modulator using a reflective liquid crystal element.

[0015] Here, the ROADM function uses a broadcast-and-select (BS) scheme that requires a WSS and an optical splitter at each node. However, future devices may use a route-and-select (RS) scheme with multiple WSS devices instead of an optical splitter.

[0016] The WSS array 100 according to this disclosure comprises at least two WSS devices within a single package. In the WSS array 100, at least two WSS devices share most of the optical components, while at least two WSS devices are configured to operate independently. Therefore, the WSS array 100 not only achieves miniaturization and reduces optical complexity, but can also have independent processing capabilities comparable to larger and more expensive devices. Such a WSS array 100 is suitable for use in optical communication networks, for example, as a reconfigurable optical ROADM, and is also suitable for use as a component in branch nodes using a route-and-select (RS) architecture. Furthermore, the liquid crystal device according to this disclosure is applied as a reflective liquid crystal element in the WSS array 100.

[0017] As shown in Figure 1, the WSS array 100 comprises two independent WSS devices 100a and 100b, each capable of operating as an independent WSS device. In this specification, the term “independent” refers to the function of the other WSS device 100a or 100b to process one or more WDM signals independently of the other WSS device 100a or 100b. In this specification, the term “processing” is used broadly and includes, for example, modulating, attenuating, blocking, redirecting, and switching the individual wavelength channels that constitute each WDM signal.

[0018] The WSS array 100 comprises an input unit 110, an optical system 120, and a reflective liquid crystal element 130.

[0019] The optical system 120 is configured to beam-shape each WDM signal beam. The optical system 120 is also configured to spectrally disperse (multiplex decouple) each WDM signal into wavelength channels or groups thereof that constitute them, and spectrally couple (multiplex) the dispersed wavelength channels or groups thereof into one or more WDM signals. The reflective liquid crystal element 130 optically processes the dispersed wavelength channels or groups thereof, for example, to redirect the individual wavelength channels along a predetermined path within the WSS array 100.

[0020] The WSS array 100 is configured to be line-symmetric with respect to the symmetry axis Z1 extending in the z-axis direction. This allows the WSS array 100 to enable a single optical system 120 and a single reflective liquid crystal element 130 to be shared by multiple WSS devices (WSS devices 100a and 100b in this example). In the WSS array 100, WSS devices 100a and 100b can share most of the optical components, while each WSS device 100a and 100b is configured to operate independently. Therefore, the WSS array 100 not only achieves miniaturization and reduces optical complexity, but can also have independent processing capabilities comparable to larger and more expensive devices.

[0021] The input unit 110 has input ports and output ports for transmitting one or more WDM signals to each WSS device 100a, 100b. Each input port and each output port may be, for example, an optical fiber or a planar waveguide, but in this embodiment, the case of an optical fiber will be described as an example. Therefore, below, each input port will also be referred to as an input fiber, and each output port will also be referred to as an output fiber.

[0022] Specifically, the input unit 110 includes an input fiber FI1 and n (where n is an integer of 1 or more) output fibers FO1_1 to FO1_n for the WSS device 100a, and an input fiber FI2 and n output fibers FO2_1 to FO2_n for the WSS device 100b. Here, in the input unit 110, the optical fibers FI1, FO1_1 to FO1_n that constitute the fiber stack for the WSS device 100a, and the optical fibers FI2, FO2_1 to FO2_n that constitute the fiber stack for the WSS device 100b are arranged along the y-axis.

[0023] The input unit 110 further includes collimating lenses LI1, LO1_1 to LO1_n corresponding to optical fibers FI1, FO1_1 to FO1_n for the WSS device 100a, and collimating lenses LI2, LO2_1 to LO2_n corresponding to optical fibers FI2, FO2_1 to FO2_n for the WSS device 100b. The collimating lenses LI1, LO1_1 to LO1_n and the collimating lenses LI2, LO2_1 to LO2_n constitute a microlens array. In the input unit 110, each collimating lens is positioned on the optical system 120 side of each optical fiber. Each collimating lens is an arbitrary optical element that has the ability to guide or change the direction of light rays and to focus a set of light rays.

[0024] In the input section 110, the optical fibers FI1, FO1_1 to FO1_n and the collimating lenses LI1, LO1_1 to LO1_n constitute the input section of the WSS device 100a, and the optical fibers FI2, FO2_1 to FO2_n and the collimating lenses LI2, LO2_1 to LO2_n constitute the input section of the WSS device 100b.

[0025] In the example shown in Figure 1, the WSS array 100 employs a microlens array, but other types of arrays may be used as long as they do not deviate from the purpose.

[0026] As shown in Figure 1, the optical axes of the collimating lenses LI1, LO1_1 to LO1_n are displaced with respect to the optical axes of the optical fibers FI1, FO1_1 to FO1_n. Due to this relative positional shift between the collimating lenses LI1, LO1_1 to LO1_n and the optical fibers FI1, FO1_1 to FO1_n, the input beam for the WSS device 100a is input to the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100a is output from the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100a are tilted in the negative y-axis direction by an angle θ1 with respect to the axis of symmetry Z1 from the input section 110 to the optical system 120.

[0027] Similarly, the optical axes of the collimating lenses LI2, LO2_1 to LO2_n are displaced with respect to the optical axes of the optical fibers FI2, FO2_1 to FO2_n. Due to this relative positional shift between the collimating lenses LI2, LO2_1 to LO2_n and the optical fibers FI2, FO2_1 to FO2_n, the input beam for the WSS device 100b is input to the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100b is output from the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100b are tilted in the positive y-axis direction by an angle θ2 with respect to the axis of symmetry Z1 from the input section 110 to the optical system 120.

[0028] In the WSS array 100, the first WDM signal incident from the outside is supplied to the input fiber FI1. The input fiber FI1 transmits the first WDM signal parallel to the axis of symmetry Z1. The first WDM signal transmitted from the input fiber FI1 is tilted by an angle θ1 in the negative direction of the y-axis by passing through the collimating lens LI1 and is supplied to the optical system 120. The first WDM signal supplied to the optical system 120 forms a WDM signal beam BI1 that travels along the yz plane in the optical system 120. In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-axis direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, when viewed from the x-axis direction (in other words, when viewed from the yz plane), the lens 121 does not affect the shaping of the WDM signal beam BI1.

[0029] The WDM signal beam BI1 that has passed through lens 121 is incident on lens 122. Lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The function of lens 122 depends on a reflective liquid crystal element 130 positioned at the focal plane of lens 122. Furthermore, the center of lens 122 is located on the axis of symmetry Z1.

[0030] In the WSS array 100, the second WDM signal incident from the outside is supplied to the input fiber FI2. The input fiber FI2 transmits the second WDM signal parallel to the axis of symmetry Z1. The second WDM signal transmitted from the input fiber FI2 passes through the collimating lens LI2, tilting by an angle θ2 in the positive direction of the y-axis, and is supplied to the optical system 120. The second WDM signal supplied to the optical system 120 forms a WDM signal beam BI2 that travels along the yz plane in the optical system 120. In the optical system 120, the WDM signal beam BI2 is incident on a lens 121 that shapes the WDM signal beam BI2 in the x-axis direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, when viewed from the x-axis direction (in other words, when viewed from the yz plane), the lens 121 does not affect the shaping of the WDM signal beam BI2.

[0031] The WDM signal beam BI2 that has passed through lens 121 is incident on lens 122. Lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The function of lens 122 depends on a reflective liquid crystal element 130 positioned at the focal plane of lens 122. Furthermore, the center of lens 122 is located on the axis of symmetry Z1.

[0032] Here, since the reflective liquid crystal element 130 is positioned at the focal plane of the lens 122, any pair of light rays reflected by the reflective liquid crystal element 130 that are reflected from positions at the same distance in the y-axis direction with respect to the axis of symmetry Z1 will be emitted from the lens 122 as a pair of parallel light rays. Conversely, any pair of parallel light rays incident on the lens 122 from the input section 110 will be focused in the reflective liquid crystal element 130 at positions at the same distance in the y-axis direction with respect to the axis of symmetry Z1.

[0033] In the example shown in Figure 1, an arbitrary incident beam (in this example, the WDM signal beam BI1) traveling at an angle θ1 with respect to the axis of symmetry Z1 is directed by the lens 122 toward position LC1 on the reflective liquid crystal element 130. Conversely, rays starting from position LC1 on the reflective liquid crystal element 130 (in this example, the output beams BO1_1 to BO1_n) are directed by the lens 122 as parallel rays traveling at an angle θ1 with respect to the axis of symmetry Z1.

[0034] Similarly, any incident beam (in this example, the WDM signal beam BI2) traveling at an angle θ2 with respect to the axis of symmetry Z1 is directed by the lens 122 toward position LC2 on the reflective liquid crystal element 130. Conversely, rays starting from position LC2 on the reflective liquid crystal element 130 (in this example, the output beams BO2_1 to BO2_n) are directed by the lens 122 as parallel rays traveling at an angle θ2 with respect to the axis of symmetry Z1.

[0035] Figure 2 shows the WSS array 100 as viewed from the y-axis direction. Figure 3 shows an example of a wavelength channel focused on the reflective liquid crystal element 130.

[0036] Referring to Figures 2 and 3, the WDM signal beam BI1 passes through lens 122 and then through a dispersion element 124 located between lenses 122 and 123. The dispersion element 124 is, for example, a transmissive optical component such as a diffraction grating or prism, which angularly disperses the wavelength channel of the WDM signal beam BI1. The wavelength channel dispersed by the dispersion element 124 passes through lens 123. Lens 123 is, for example, a cylindrical lens, which focuses the wavelength channel dispersed by the dispersion element 124 onto position LC1 on the reflective liquid crystal element 130.

[0037] Similarly, the WDM signal beam BI2 passes through lens 122 and then through the dispersion element 124 located between lenses 122 and 123. The dispersion element 124 angularly disperses the wavelength channels of the WDM signal beam BI2. The wavelength channels dispersed by the dispersion element 124 pass through lens 123. Lens 123 focuses the wavelength channels dispersed by the dispersion element 124 onto position LC2 on the reflective liquid crystal element 130.

[0038] The reflective liquid crystal element 130 is a two-dimensional pixelated optical element, such as a pixelated spatial light modulator, which can reflect or redirect one or more of the dispersed wavelength channels so that one or more of the dispersed wavelength channels are routed to any one of the output fibers, as will be described in more detail below.

[0039] In the WSS device 100a, all light rays starting from position LC1 on the reflective liquid crystal element 130 are displaced by the lens 122 by an amount corresponding to the deflection angle from the reflective liquid crystal element 130, and directed as parallel light rays traveling at an angle θ1. Therefore, when the deflection angle is set appropriately, the output light rays reflected by the reflective liquid crystal element 130 (for example, reflected output light rays corresponding to a group of light rays, each of which may contain one or more wavelength channels of the WDM signal beam BI1) can be routed to the output fibers FO1_1 to FO1_n, respectively. Here, since the output light rays reflected by the reflective liquid crystal element 130 are displaced by the same amount by the collimating lenses LO1_1 to LO1_n, they can be recombined to the output fibers FO1_1 to FO1_n with improved efficiency.

[0040] Similarly, in the WSS device 100b, all light rays starting from position LC2 on the reflective liquid crystal element 130 are displaced by the lens 122 by an amount corresponding to the deflection angle from the reflective liquid crystal element 130, and directed as parallel light rays traveling at an angle θ2. Therefore, when the deflection angle is set appropriately, the output light rays reflected by the reflective liquid crystal element 130 (for example, reflected output light rays corresponding to a group of light rays, each of which may contain one or more wavelength channels of the WDM signal beam BI2) can be routed to the output fibers FO2_1 to FO2_n, respectively. Here, since the output light rays reflected by the reflective liquid crystal element 130 are displaced by the same amount by the collimating lenses LO2_1 to LO2_n, they can be recombined to the output fibers FO2_1 to FO2_n with improved efficiency.

[0041] Therefore, the combination of the input unit 110 and the lens 122 results in a WSS array 100 device that, after sending out a predetermined set of beams along a predetermined angle (for example, angle θ1 in the case of WSS device 100a, and angle θ2 in the case of WSS device 100b), directs these beams toward a position on the reflective liquid crystal element 130 that depends only on the input angle (for example, position LC1 in the case of WSS device 100a, and position LC2 in the case of WSS device 100b). Thus, in the WSS array 100, as will be described in more detail below with reference to Figures 2 and 3, the rays from WSS device 100a and WSS device 100b are each processed by a common optical system 120 and reflective liquid crystal element 130, while each wavelength channel is processed separately by the processing capability of the WSS array 100.

[0042] Next, the WSS array 100 will be described using Figures 2 and 3. As already explained, Figure 2 is a view of the WSS array 100 from the y-axis direction. As already explained, Figure 3 is a view of an example of a wavelength channel focused on the reflective liquid crystal element 130. In the following, we will mainly describe the WSS device 100a of the WSS devices 100a and 100b, but the same can be said for the WSS device 100b.

[0043] As shown in Figure 2, in the WSS device 100a, the WDM signal beam BI1 that has passed through the input fiber FI1 is incident on the optical system 120. In the example in Figure 2, the WDM signal beam BI1 travels along a plane perpendicular to the plane of paper (yz plane) at an angle θ1. The WDM signal beam BI1 also includes multiple wavelength channels. The multiple wavelength channels have a wavelength range from the longest wavelength λ1 to the shortest wavelength λn. The WDM signal beam BI1 may also include a large number of wavelength channels, in which case the large number of wavelength channels may be, for example, 96 wavelength channels spaced at 50 or 100 GHz intervals on a fixed grating. In other examples, the WSS device 100a can use a frequency spacing of 12.5 GHz and can be used in an adaptable grating system having, for example, 130 or more wavelength channels (i.e., 97 or more wavelength channels).

[0044] In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-axis direction. For example, the lens 121 expands the WDM signal beam BI1 to have a diameter suitable for the WDM signal beam BI1 to achieve a desired beam size at the dispersive element 124. Note that the collimating lens provided in the input unit 110 and the lens 121 provided in the optical system 120 may function as a beam expanding telescope.

[0045] In the optical system 120, the dispersive element 124 angularly disperses the wavelength channels of the WDM signal beam BI1. The wavelength channels λ1 to λn dispersed by the dispersive element 124 are respectively condensed by the lens 123 onto the reflective liquid crystal element 130. Thereby, the wavelength channels λ1 to λn are spatially dispersed in the chromatic dispersion direction (x-axis direction) on the reflective liquid crystal element 130.

[0046] In the example of Fig. 3, an example of the distribution of wavelength channels in the pixel area of the reflective liquid crystal element 130 is shown. Note that in the example of Fig. 3, only wavelength channels λ1 to λ3 among wavelength channels λ1 to λn are shown. More generally, each wavelength channel may be arranged on the two-dimensional surface of the reflective liquid crystal element 130 as an elongated strip or an elliptical spot. Briefly speaking, each wavelength channel is processed as a discrete wavelength wavelength signal that can be independently acted upon by the reflective liquid crystal element 130. However, the reflective liquid crystal element 130 need not be limited to acting on individual wavelength channels, and may act on a group of wavelength channels. Furthermore, as shown in Fig. 3, the wavelength channel itself or a group of wavelength channels itself does not need to have a fixed bandwidth. This is because the reflective liquid crystal element 130 can be implemented in the WSS array 100 as a dynamically and fully reconfigurable spatial light modulator. Therefore, the WSS array 100 can be used in systems of conventional fixed grating architectures and highly flexible grating architectures that are conventional or may be developed in the future.

[0047] As shown in FIG. 2, thereafter, the reflective liquid crystal element 130 can redirect wavelength channels λ1 to λn selected from a plurality of wavelength channels toward output fibers FO1_1 to FO1_n, respectively. In the example of FIG. 2, the redirection by the reflective liquid crystal element 130 is performed along a plane orthogonal to the paper surface (yz plane). The wavelength channel redirected by being reflected by the reflective liquid crystal element 130 is incident on the lens 123. The lens 123 redirects the incident wavelength channel so that it is recombined at the dispersive element 124. For example, in the dispersive element 124, a plurality of wavelength channels are recombined to form a single beam (output beam). The output beams BO_1 to BO_n formed at the dispersive element 124 are redirected to become parallel rays to each other by the lens 122 and the collimating lens of the input unit 110, and then output to the outside as processed signals via the output fibers FO1_1 to FO1_n.

[0048] For example, consider the case where a WDM signal beam BI1 includes three wavelength channels (hereinafter referred to as wavelength channels λ1 to λ3) respectively having wavelengths λ1, λ2, and λ3 and channel bandwidths δλ1, δλ2, and δλ3. In this case, in the example of FIG. 1, the WDM signal beam BI1 is incident on the optical system 120 at an inclination of angle θ1. Since the ray of the WDM signal beam BI1 traveling inclined at angle θ1 passes through the center of the lens 122, it maintains the inclination of angle θ1. The WDM signal beam BI1 that has passed through the lens 122 is dispersed by the dispersive element 124 along a plane orthogonal to the paper surface of FIG. 1 (zx plane) into a plurality of wavelength channels including the three wavelength channels described above. However, all of the plurality of wavelength channels that have passed through the dispersive element 124 maintain the inclination of angle θ1 in a plane parallel to the paper surface of FIG. 1 (yz plane). The three dispersed wavelength channels described above are then condensed by the lens 123 at different positions on the pixel area of the reflective liquid crystal element 130, as shown in FIG. 3.

[0049] Regarding the routing function of the device, several different routing functions may be combined. For example, considering the case where all three wavelength channels λ1 to λ3 described above are routed to a common output fiber FO_n, the wavelength channels λ1 to λ3 reflected by the reflective liquid crystal element 130 are deflected by the lens 123 and focused before reaching the dispersive element 124. Thereafter, they are recombined (multiplexed) by the dispersive element 124 to form a single output beam BO1_n. The output beam BO1_n that has passed through the dispersive element 124 is redirected by the lens 122 so that it is tilted at an angle θ1.

[0050] The output beam BO1_n, having passed through lens 122, travels along the yz plane at an angle θ1 with respect to the axis of symmetry Z1, passes through lens 121, and is then incident on collimating lens LO1_n. The collimating lens LO1_n redirects the output beam BO1_n so that it is parallel to the axis of symmetry Z1. The output beam BO1_n, having passed through collimating lens LO1_n, is emitted to the outside of the WSS array 100 via output fiber FO1_n.

[0051] Furthermore, the case is not limited to the case where multiple wavelength channels are routed to a common output fiber; multiple wavelength channels may also be routed to multiple different output fibers. For example, considering the case where the three wavelength channels λ1 to λ3 described above are routed to different output fibers FO1_1 to FO1_3, the wavelength channels λ1 to λ3 reflected by the reflective liquid crystal element 130 are deflected by the lens 123 and then their direction is changed by the dispersion element 124, thereby forming output beams BO1_1 to BO1_3 that spread out in a fan shape. The output beams BO1_1 to BO1_3 that have passed through the dispersion element 124 are then directed by the lens 122 so that they are tilted at an angle θ.

[0052] The output beams BO1_1 to BO1_3 of the parallel light rays that have passed through lens 122 all travel along the yz plane at an angle θ1 with respect to the axis of symmetry Z1, and after passing through lens 121, they are incident on collimating lenses LO1_1 to LO1_3, respectively. The collimating lenses LO1_1 to LO1_3 redirect the output beams BO1_1 to BO1_3 so that they are parallel to the axis of symmetry Z1. The output beams BO1_1 to BO1_3 that have passed through collimating lenses LO1_1 to LO1_3 are then emitted to the outside of the WSS array 100 via output fibers FO1_1 to FO1_3, respectively. In other words, in the WSS device 100a, wavelength channels λ1 to λ3 are routed from the input fiber FI1 to the output fibers FO1_1 to FO1_3 via the reflective liquid crystal element 130.

[0053] As described above, any wavelength channel of a WDM signal in WSS device 100a can be routed to one or more output fibers among multiple output fibers as needed. The same applies to any wavelength channel of a WDM signal in WSS device 100b as to WSS device 100a. That is, any wavelength channel of a WDM signal in WSS device 100b can be routed to one or more output fibers among multiple output fibers as needed. This is because, in the WSS array 100, the optical system 120 and the reflective liquid crystal element 130 are configured to be symmetrical with respect to the symmetry axis Z1, and the wavelength channels dispersed in WSS device 100a and the wavelength channels dispersed in WSS device 100b are focused at different positions on the reflective liquid crystal element 130.

[0054] Furthermore, while the examples in Figures 1 to 3 describe a case where each WSS device is provided with one input port (input fiber) and n output ports (output fibers), the explanation is not limited to this, and each WSS device may be provided with any number of input ports and any number of output ports. Also, some or all of the n output ports may be reconfigured as input ports, and one input port may be reconfigured as an output port. In addition, while the examples in Figures 1 to 3 describe a case where the WSS array 100 is composed of two WSS devices 100a and 100b, the explanation is not limited to this, and it may be composed of three or more WSS devices.

[0055] Next, we will explain the details of the reflective liquid crystal element 130 applied to the WSS array 100.

[0056] <Preliminary study on liquid crystal devices> First, the liquid crystal device 50 that the inventors have studied in advance will be described. The liquid crystal device 50 can also be used as a reflective liquid crystal element 130 of the WSS array 100.

[0057] (Configuration of liquid crystal device 50 in the conceptual stage) Figure 4 shows an example configuration of an active matrix type liquid crystal device 50 in the conceptual stage.

[0058] As shown in Figure 4, the liquid crystal device 50 comprises an image display unit 11, a timing generator 13, a polarity switching control circuit 14, a vertical shift register & level shifter 15, a horizontal driver 16, an analog switch unit 17, and AND circuits ADA1 to ADAn and ADB1 to ADBn. The horizontal driver 16, together with the analog switch unit 17, constitutes a data line driving circuit and includes a shift register circuit 161, a one-line latch circuit 162, a comparator unit 163, and a grayscale counter 164. Figure 4 also shows a ramp signal generator 40 that is connected to the liquid crystal device 50 during normal operation.

[0059] Figure 5 is an enlarged view of the horizontal driver 16 and analog switch section 17 provided on the liquid crystal device 50. The comparator section 163 comprises m comparators 163_1 to 163_m corresponding to m rows of pixels 12 (where m is an integer of 2 or more). The analog switch section 17 comprises m sets of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- corresponding to m rows of pixels 12.

[0060] The pixel arrangement area of ​​the image display unit 11 is wired with row scan lines G1 to Gn, readout switch selection lines TG1 to TGn, data lines D1+, D1- to Dm+, Dm-, gate control signal lines S+, S-, and gate control signal line B.

[0061] The row scan lines G1 to Gn are wired in n rows in the vertical direction (J-axis direction) and each extends horizontally. The read switch selection lines TG1 to TGn are wired in n rows in the vertical direction and each extends horizontally. The data lines D1+, D1- to Dm+, Dm- are wired in m columns in the horizontal direction and each extends vertically. Hereinafter, any of the row scan lines G1 to Gn will also be referred to as row scan line Gj. Any of the read switch selection lines TG1 to TGn will also be referred to as read switch selection line TGj. Any of the data lines D1+ to Dm+ will also be referred to as data line Di+. Any of the data lines D1- to Dm- will also be referred to as data line Di-.

[0062] The image display unit 11 has a plurality of regularly arranged pixels 12. Here, the plurality of pixels 12 are arranged in a two-dimensional matrix at a total of n × m intersections where n rows of row scan lines G1 to Gn and m sets of data lines D1+, D1- to Dm+, Dm- intersect.

[0063] The row scan line Gj and the read switch selection line TGj are commonly connected to each of the m pixels 12 located in the jth row. The data lines Di+ and Di- are commonly connected to each of the n pixels 12 located in the i-th column. Furthermore, the gate control signal lines S+, S-, and gate control signal line B are all commonly connected to all pixels 12. However, the gate control signal lines S+, S-, and gate control signal line B may each be provided individually for each row.

[0064] The polarity switching control circuit 14 outputs a positive polarity gate control signal (hereinafter referred to as gate control signal S+) to the gate control signal line S+, a negative polarity gate control signal (hereinafter referred to as gate control signal S-) to the gate control signal line S-, and further outputs a gate control signal (hereinafter referred to as gate control signal B) to the gate control signal line B, based on the timing signal generated by the timing generator 13.

[0065] The vertical shift register & level shifter 15 outputs n-row scan pulses sequentially, one row at a time, from the first row to the nth row, with a period of one horizontal scan period (HST). AND circuits ADA1 to ADAn each control whether to output the n-row scan pulses, output sequentially from the vertical shift register & level shifter 15, to the row scan lines G1 to Gn, based on the externally supplied mode switching signal MD. AND circuits ADB1 to ADBn each control whether to output the n-row scan pulses, output sequentially from the vertical shift register & level shifter 15, to the readout switch selection lines TG1 to TGn, based on the externally supplied mode switching signal MD.

[0066] For example, in the operation of writing a video signal to pixel 12 (image writing operation), an H-level mode switching signal MD is supplied from an external source. In this case, AND circuits ADA1 to ADAn each output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register & level shifter 15, to the row scan lines G1 to Gn. At this time, AND circuits ADB1 to ADBn each do not output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register & level shifter 15, to the read switch selection lines TG1 to TGn. In other words, the read switch selection lines TG1 to TGn are all fixed at the L level.

[0067] In contrast, when the video signal written to the pixel 12 is read out (image readout operation), an L-level mode switching signal MD is supplied from an external source. In this case, AND circuits ADB1 to ADBn each output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the readout switch selection lines TG1 to TGn. At this time, AND circuits ADA1 to ADAn each do not output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the row scan lines G1 to Gn. In other words, the row scan lines G1 to Gn are all fixed at the L level.

[0068] (Specific Configuration Example of Pixel 12) Figure 6 shows a specific configuration example of pixel 12. Here, we will describe a pixel 12 located in the jth row and ith column of an n-row × m-column pixel 12. Note that j is any integer from 1 to n. i is any integer from 1 to m.

[0069] As shown in Figure 6, the pixel 12 includes N-channel MOS transistors (hereinafter simply referred to as transistors) Tr1, Tr2, Tr5, Tr6, Tr9, P-channel MOS transistors (hereinafter simply referred to as transistors) Tr3, Tr4, Tr7, Tr8, holding capacitors Cs1, Cs2, and liquid crystal display elements LC.

[0070] The transistor Tr1 and the holding capacitor Cs1 constitute a sample-and-hold circuit that samples and holds the positive polarity video signal supplied via the data line Di+. Specifically, the source of transistor Tr1 is connected to the data line Di+, the drain is connected to the gate of transistor Tr3, and the gate is connected to the row scan line Gj. The holding capacitor Cs1 is provided between the gate of transistor Tr3 and the ground voltage terminal Vss.

[0071] The transistor Tr2 and the holding capacitor Cs2 constitute a sample-and-hold circuit that samples and holds the negative polarity video signal supplied via the data line Di-. Specifically, the source of transistor Tr2 is connected to the data line Di-, the drain is connected to the gate of transistor Tr4, and the gate is connected to the row scan line Gj. The holding capacitor Cs2 is provided between the gate of transistor Tr4 and the ground voltage terminal Vss. The holding capacitors Cs1 and Cs2 are provided independently of each other and hold the positive and negative polarity video signals in parallel, respectively.

[0072] Transistors Tr3 and Tr7 constitute a source follower buffer (impedance conversion buffer) that outputs the voltage held in the holding capacitance Cs1. Specifically, in the source follower transistor Tr3, the drain is connected to the ground voltage line Vss and the source is connected to node Na. In transistor Tr7, which is used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to node Na, and the gate is connected to the gate control signal line B.

[0073] Transistors Tr4 and Tr8 constitute a source follower buffer that outputs the voltage held in the holding capacitance Cs2. Specifically, in the source follower transistor Tr4, the drain is connected to the ground voltage line Vss and the source is connected to node Nb. In transistor Tr8, which is used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to node Nb, and the gate is connected to the gate control signal line B.

[0074] Transistors Tr5 and Tr6 constitute a polarity switching switch. Specifically, in transistor Tr5, the source is connected to node Na, the drain is connected to the pixel drive electrode PE, and the gate is connected to one of the gate control signal lines S+ of the gate control signal line pair. In transistor Tr6, the source is connected to node Nb, the drain is connected to the pixel drive electrode PE, and the gate is connected to the other gate control signal line S- of the gate control signal line pair.

[0075] The liquid crystal display element (LC) is composed of a pixel driving electrode (reflective electrode) PE having light-reflecting properties, a common electrode CE that is spaced apart from and opposite to the pixel driving electrode and has light-transmitting properties, and liquid crystal LCM filling and encapsulating the space between them. A common voltage Vcom is applied to the common electrode CE. Transistor Tr9 is provided between the pixel driving electrode PE and the data line Di+, and is switched on and off by the readout switch selection line TGj.

[0076] The data line pairs Di+ and Di- are supplied with video signals of opposite polarity, sampled by the analog switch unit 17. When a scan pulse output from the vertical shift register & level shifter 15 is supplied to the row scan line Gj, transistors Tr1 and Tr2 turn on simultaneously. As a result, the voltage of the positive polarity video signal propagating on the data line Di+ is held in the retaining capacitor Cs1 via transistor Tr1. Similarly, the voltage of the negative polarity video signal propagating on the data line Di- is held in the retaining capacitor Cs2 via transistor Tr2.

[0077] Furthermore, the input resistances of the positive and negative source follower buffers are virtually infinite. Therefore, the charge accumulated in the holding capacitors Cs1 and Cs2 is retained without leakage until one vertical scan period has elapsed and a new video signal is written.

[0078] Transistors Tr5 and Tr6, which constitute the polarity switching switch, switch on and off according to the gate control signals S+ and S-, thereby alternately selecting and outputting to the pixel drive electrode PE the output voltage of the positive-side source follower buffer (voltage of the positive polarity video signal) and the output voltage of the negative-side source follower buffer (voltage of the negative polarity video signal). As a result, the pixel drive electrode PE is supplied with a video signal voltage that periodically reverses polarity. In this way, the liquid crystal device 50 has a polarity reversal function in the pixels themselves, and by rapidly switching the polarity of the video signal voltage supplied to the pixel drive electrode PE at each pixel, AC driving at high frequencies becomes possible regardless of the vertical scanning frequency.

[0079] (Explanation of AC driving method for pixel 12) Figure 7 is a timing chart for explaining the AC driving method of pixel 12 by the liquid crystal device 50. Here, we will explain the AC driving method for the pixel 12 located in the jth row and ith column of the n rows x m columns of pixels 12.

[0080] In Figure 7, VST represents the vertical synchronization signal that serves as the reference for vertical scanning of the video signal. B represents the gate control signals supplied to the gates of transistors Tr7 and Tr8, which are used as constant current loads for the two types of source follower buffers. S+ represents the gate control signal supplied to the gate of transistor Tr5 on the positive side of the polarity switching switch. S- represents the gate control signal supplied to the gate of transistor Tr6 on the negative side of the polarity switching switch. VPE represents the voltage applied to the pixel drive electrode PE, and is sometimes written as pixel drive voltage VPE or applied voltage VPE. Vcom represents the voltage applied to the common electrode CE. VLC represents the AC voltage applied to the liquid crystal LCM.

[0081] Figure 8 is a diagram illustrating the voltage levels from black to white for both the positive and negative polarity video signals written to the pixel 12. In the example in Figure 8, the positive polarity video signal represents the black level when the voltage level is minimum and the white level when the voltage level is maximum. Conversely, the negative polarity video signal represents the white level when the voltage level is minimum and the black level when the voltage level is maximum. However, the positive polarity video signal may be configured to represent the white level when the voltage level is minimum and the black level when the voltage level is maximum, and the negative polarity video signal may be configured to represent the black level when the voltage level is minimum and the white level when the voltage level is maximum. The dashed lines in the figure indicate the inversion centers of the positive and negative polarity video signals.

[0082] In pixel 12, transistor Tr9 remains in the off state because the readout switch selection line TGj is fixed at the L level. On the other hand, transistors Tr1 and Tr2 are temporarily turned on when a scan pulse is supplied to the row scan line Gj. When transistors Tr1 and Tr2 are turned on, the positive and negative polarity video signal voltages are stored and held in the holding capacitors Cs1 and Cs2, respectively.

[0083] As shown in Figure 7, the positive-side transistor Tr5 is turned on during the period when the gate control signal S+ is at the H level. At this time, by setting the gate control signal B to the L level, transistor Tr7 is turned on, and the positive-side source follower buffer becomes active. As a result, the pixel drive electrode PE is charged to the voltage level of the positive-polarity video signal. Furthermore, by setting the gate control signal B to the L level, transistor Tr8 is turned on, and the negative-polarity source follower buffer also becomes active. However, since the negative-polarity transistor Tr6 is off, the pixel drive electrode PE is not charged to the voltage level of the negative-polarity video signal. When the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S+ is switched from the H level to the L level. As a result, the pixel drive electrode PE becomes floating, and the positive-polarity drive voltage is maintained in the liquid crystal capacitance.

[0084] On the other hand, during the period when the gate control signal S- is at the H level, the negative-side transistor Tr6 is turned on. At this time, by setting the gate control signal B to the L level, the negative-side transistor Tr8 is turned on, and the negative-side source follower buffer becomes active. As a result, the pixel drive electrode PE is charged to the voltage level of the negative polarity video signal. Furthermore, by setting the gate control signal B to the L level, the transistor Tr7 is turned on, and the positive-side source follower buffer also becomes active. However, since the positive-side transistor Tr5 is off, the pixel drive electrode PE is not charged to the voltage level of the positive polarity video signal. When the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S- is switched from the H level to the L level. As a result, the pixel drive electrode PE becomes floating, and the negative polarity drive voltage is maintained in the liquid crystal capacitance.

[0085] In pixel 12, the operations of the positive and negative electrodes described above are repeated alternately, so that the pixel drive electrode PE is subjected to an AC-converted pixel drive voltage VPE using the voltages of the positive and negative video signals, respectively.

[0086] Furthermore, the charge held in the retention capacitors Cs1 and Cs2 is not directly transferred to the pixel drive electrode PE, but rather transferred via a source follower buffer. Therefore, even when the positive and negative polarity video signal charges are repeatedly charged and discharged at the pixel drive electrode PE, the charge is not neutralized, and pixel driving with suppressed voltage level attenuation can be achieved.

[0087] Furthermore, as shown in Figure 7, the voltage level of the applied voltage Vcom to the common electrode CE is switched to the opposite level to the applied voltage VPE of the pixel drive electrode PE in synchronization with the switching of the applied voltage VPE of the pixel drive electrode PE. Note that the applied voltage Vcom to the common electrode CE is set to an inversion reference voltage that is approximately equal to the inversion reference voltage of the applied voltage VPE to the pixel drive electrode PE.

[0088] Here, the effective AC voltage VLC applied to the liquid crystal LCM is the difference voltage between the voltage VPE applied to the pixel drive electrode PE and the voltage Vcom applied to the common electrode CE. Therefore, an AC voltage VLC without a DC component is applied to the liquid crystal LCM. In this way, the voltage Vcom applied to the common electrode CE switches in opposite phase to the voltage VPE applied to the pixel drive electrode PE, which reduces the amplitude of the voltage required to be applied to the pixel drive electrode PE. As a result, the breakdown voltage and power consumption of the transistors constituting the pixel circuit are reduced.

[0089] Even if the current flowing steadily through the source follower buffer per pixel is a minute current of 1 μA, the total current flowing steadily through all pixels of the liquid crystal device 50 can become a significant amount. For example, a liquid crystal device with 2 million pixels of full HD resolution could consume up to 2 A. Therefore, in pixel 12, transistors Tr7 and Tr8, which are used as constant current loads, are not kept on all the time, but are only turned on for a limited period of time while the positive and negative transistors Tr5 and Tr6 are on, respectively. This allows the operation of one source follower buffer to be stopped when the other source follower buffer is operating, thereby suppressing the increase in current consumption.

[0090] The AC drive frequency of a liquid crystal display element (LC) can be freely adjusted by adjusting the inversion control period of the pixel itself, regardless of the vertical scanning frequency. For example, suppose the vertical scanning frequency is 60 Hz, which is commonly used in television video signals, and the number of vertical periodic scan lines n for full HD is 1125 lines. Also, assume that polarity switching at each pixel is performed at a period of about 15 line periods. In other words, the number of lines r per polarity switching period at each pixel is 30 lines. In this case, the AC drive frequency of the liquid crystal becomes 60 Hz × 1125 / (15 × 2) = 2.25 kHz. In other words, the liquid crystal device 50 can dramatically increase the AC drive frequency of the liquid crystal. As a result, the reliability, stability, and display quality of the image displayed on the liquid crystal screen, which were problems when the AC drive frequency of the liquid crystal was low, can be greatly improved.

[0091] Next, we will explain the operation of the liquid crystal device 50 in each operating mode.

[0092] (Operation of the liquid crystal device 50 in image display mode) First, the operation of the liquid crystal device 50 in image display mode (pixel writing mode) will be explained using Figure 9. Figure 9 is a timing chart showing the operation of the liquid crystal device 50 in image display mode.

[0093] As shown in Figure 9, when the horizontal synchronization signal HST pulse signal is supplied, the shift register circuit 161 sequentially captures m rows of video signals with an N (where N is an integer of 2 or more) bit width in synchronization with the clock signal HCK. The one-line latch circuit 162 simultaneously outputs the m rows of video signals captured by the shift register circuit 161 at the timing when the trigger signal REG_S becomes temporarily active.

[0094] The grayscale counter 164 counts the number of rising edges of the clock signal CNT_CK and outputs a grayscale signal Cout indicating the count value. Here, the grayscale counter 164 outputs a grayscale signal Cout indicating the minimum count value at the start of one horizontal ramp period (the transition period of the ramp signal within one horizontal scanning period) R (when the horizontal synchronization signal HST rises), increases the grayscale level of the grayscale signal Cout as the count value increases, and outputs a grayscale signal Cout indicating the maximum count value at the end of one horizontal ramp period R (the time S before the next rising edge of the horizontal synchronization signal HST). The count value of the grayscale counter 164 is initialized to "0", for example, when the reset signal CNT_R becomes active in response to the rising edge of the horizontal synchronization signal HST. The grayscale counter 164 is not limited to count-up operation, but may also be configured to perform count-down operation. In that case, the count value is initialized to the maximum value when the reset signal CNT_R becomes active.

[0095] The m-row comparators 163_1 to 163_m provided in the comparator unit 163 operate in synchronization with the clock signal CMP_CK. When the grayscale signal Out output from the grayscale counter 164 matches each of the m-row video signals (line data) simultaneously output from the 1-line latch circuit 162, the matching signals P1 to Pm are activated (for example, to an L level).

[0096] Of the m sets of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- provided in the analog switch section 17, the positive polarity switch elements SW1_1+ to SW1_m+ are provided between the data lines D1+ to Dm+ and the common wiring Dcom+, respectively. The negative polarity switch elements SW1_1- to SW1_m- are provided between the data lines D1- to Dm- and the common wiring Dcom-, respectively. The m sets of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are switched on and off by the matching signals P1 to Pm from the comparators 163_1 to 163_m, respectively.

[0097] The common wiring Dcom+ is supplied with the reference lamp voltage Ref_R+, which is the positive polarity lamp signal output from the lamp signal generator 40. The common wiring Dcom- is supplied with the reference lamp voltage Ref_R-, which is the negative polarity lamp signal output from the lamp signal generator 40.

[0098] The reference lamp voltage Ref_R+ is a sweep signal in which the image level changes from a black level to a white level from the start to the end of each horizontal scan period. The reference lamp voltage Ref_R- is a sweep signal in which the image level changes from a black level to a white level from the start to the end of each horizontal scan period. Therefore, the reference lamp voltage Ref_R+ with respect to the common voltage Vcom and the reference lamp voltage Ref_R- with respect to the common voltage Vcom are inverse relationships with each other.

[0099] For example, the reference lamp voltage Ref_R+ linearly increases the voltage level from 0V (black level) to 4V (white level) from the start to the end of the horizontal lamp period R. The reference lamp voltage Ref_R- linearly decreases the voltage level from 4V (black level) to 0V (white level) from the start to the end of the horizontal lamp period R. Then, between the end of one horizontal lamp period R and the start of the next, the reference lamp voltage Ref_R+ returns to 0V (black level), and the reference lamp voltage Ref_R- returns to 4V (black level).

[0100] The switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are all turned on simultaneously when the start signal SW_Start becomes active (e.g., at level H) at the start of the horizontal ramp period R. Subsequently, the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are each switched from on to off when the matching signals P1 to Pm output from comparators 163_1 to 163_m become active (e.g., at level L) before the horizontal ramp period R has elapsed. After the end of the horizontal ramp period R and before the start of the next horizontal ramp period R, the start signal SW_Start becomes inactive (e.g., at level L).

[0101] In the example in Figure 9, the waveform SPk represents the timing of switching the on and off of the switch elements SWq+ and SWq- (where q is an integer from 1 to m), which are provided in correspondence with the pixel row on which the video signal of gradation level k is written. Referring to Figure 9, the switch elements SWq+ and SWq- are turned on at the rising edge of the start signal SW_Start, and then switch from on to off when the matching signal Pq becomes active before the horizontal ramp period R has elapsed. Here, the switch elements SWq+ and SWq- sample the reference ramp voltages Ref_R+ and Ref_R- (voltages P and Q in Figure 9) at the timing of switching from on to off. The voltages P and Q sampled by the switch elements SWq+ and SWq- are supplied to the data lines Dq+ and Dq-, respectively. In other words, the analog voltages P and Q, which are the DA conversion results of the video signal at grayscale level k, are supplied to the data lines Dq+ and Dq-, respectively.

[0102] In image display mode, an H-level mode switching signal MD is supplied from an external source. Therefore, the n-row scan pulses output sequentially from the vertical shift register & level shifter 15 are supplied to the row scan lines G1 to Gn, respectively. As a result, for example, transistors Tr1 and Tr2 provided at each pixel 12 in the j-th row are temporarily turned on. Consequently, the corresponding positive and negative polarity video signal voltages are stored and held in the retention capacitors Cs1 and Cs2 provided at each pixel 12 in the j-th row. On the other hand, transistor Tr9 provided at each pixel 12 is fixed to the off position. The subsequent AC driving method for each pixel 12 is as previously described. This pixel writing operation is performed sequentially, row by row, from the m pixels 12 in the first row to the m pixels 12 in the n-th row.

[0103] As described above, the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are all turned on simultaneously at the start of each horizontal scanning period, but each is turned off at an arbitrary timing corresponding to the grayscale level of the image to be displayed on the corresponding pixel 12. In other words, the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- may all be turned off at the same time, or they may be turned off at different timings. Furthermore, the order in which they are turned off is not fixed.

[0104] In this way, the liquid crystal device 50 can improve the linearity of the image by performing a D / A conversion of the video signal using a ramp signal and then writing it to the pixels 12.

[0105] (Operation of the liquid crystal device 50 in pixel inspection mode) Next, the operation of the liquid crystal device 50 in pixel inspection mode (pixel readout mode) will be described. In pixel inspection mode, an inspection device (not shown) is provided instead of the lamp signal generator 40. Alternatively, in pixel inspection mode, the lamp signal generator 40 may be configured to function as the inspection device.

[0106] In pixel inspection mode, first, inspection video signals are written to the m pixels 12 in the j-th row that are to be inspected. The operation of writing the inspection video signals is basically the same as the operation of writing video signals in image display mode. After that, the video signals (pixel drive voltage VPE) written to the m pixels 12 in the j-th row that are to be inspected are read out.

[0107] During the pixel readout operation, the mode switching signal MD switches from the high level to the low level, so the scan pulse for the j-th row output from the vertical shift register & level shifter 15 is supplied to the readout switch selection line TGj. As a result, the transistor Tr9 provided at each pixel 12 in the j-th row to be inspected is temporarily turned on. On the other hand, the transistors Tr1 and Tr2 provided at each pixel 12 are fixed to the off position.

[0108] For example, in the pixel 12 located in the j-th row and i-th column, the pixel drive electrode PE and the data line Di+ become conductive when transistor Tr9 is turned on. At this time, by activating transistors Tr7 and Tr8 and turning on either transistor Tr5 or Tr6, the pixel drive electrode PE becomes driven by a source follower buffer consisting of transistors Tr3 and Tr7 or transistors Tr4 and Tr8. As a result, the drive voltage VPE applied to the pixel drive electrode PE is read out to the data line Di+.

[0109] The m pixel drive voltages VPE, read from each of the m pixels 12 in the j-th row to the data lines D1+ to Dm+, are sequentially supplied to the common wiring Dcom+ by sequentially turning on m sets of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- provided in the analog switch unit 17. An inspection device (not shown), provided in place of the lamp signal generator 40, detects the presence or absence of failures (pixel defects and characteristic degradation) in the m pixels 12 in the j-th row based on the m pixel drive voltages VPE supplied sequentially via the common wiring Dcom+.

[0110] This type of inspection is performed row by row, starting from the m pixels 12 in the first row to the m pixels 12 in the nth row.

[0111] In this case, the pixel drive voltage VPE of the pixel drive electrode PE, which is driven by a low-output impedance source follower buffer, is read directly from the pixel 12 being inspected. Therefore, defects and characteristic degradation of the pixel 12 being inspected can be detected accurately and easily.

[0112] (Challenges of the liquid crystal device 50) However, the pixel drive voltage VPE read from the pixel 12 to be inspected is output to an external inspection device via the data line Di+, the switch element SWi+, and the common wiring Dcom+. Therefore, the source follower buffer of the pixel 12 to be inspected needs to drive wiring with a large load capacitance and large resistance.

[0113] Specifically, the data line Di+ has the wiring capacitance for n rows of pixels 12 added to it. For example, in the case of FHD (Full High Definition), such as Full HD, the data line Di+ has the wiring capacitance for 1080 pixels (e.g., 1 pF) added to it. In addition, the common wiring Dcom+ has the wiring capacitance for 5 pF added to it. Therefore, the source follower buffer of the pixel 12 to be inspected needs to be charged with a high load capacitance totaling about 6 pF over a long period of time in order to stabilize the pixel drive voltage VPE to the same level as the holding voltage of either the holding capacitance Cs1 or Cs2. Furthermore, in pixel inspection mode, the pixel drive voltage VPE of each pixel 12 is read serially, which makes the inspection time by the inspection device very long. In other words, the liquid crystal device 50 had the problem that the inspection of pixels 12 could not be performed quickly by the inspection device. The long inspection time leads to an increase in inspection costs.

[0114] Furthermore, if the inspection of the target pixel 12 is performed without waiting for the pixel drive voltage VPE to stabilize in order to shorten the inspection time, the inspection device will not be able to accurately detect defects or characteristic degradation in the target pixel 12. In this case, for example, the pixel defect cannot be identified without displaying the entire image on the image display unit 11, which increases the man-hours required for liquid crystal assembly and projection evaluation, and as a result, increases costs.

[0115] Therefore, the next step was to consider a liquid crystal device 60 that could perform rapid inspection of the pixels 12.

[0116] (Description of the liquid crystal device 60 in the conceptual stage) Figure 10 shows an example configuration of the liquid crystal device 60 in the conceptual stage. Compared to the liquid crystal device 50, the liquid crystal device 60 further includes a pixel inspection circuit 18. The pixel inspection circuit 18 has a path for reading video signals from pixels 12, separate from the path for writing video signals to pixels 12. Specifically, the pixel inspection circuit 18 includes a switch unit 181, a sense amplifier unit 182, a latch unit 183, and a shift register circuit 184.

[0117] The switch unit 181 switches whether or not to output m positive or negative pixel drive voltages VPE, read from each of the m data lines D1+ to Dm+ from the m pixels 12 of the row to be inspected, to nodes Nd1_1 to Nd1_m. Furthermore, the switch unit 181 also switches whether or not to output a predetermined voltage (predetermined voltage mid) of the voltage supply line mid to the m sets of data lines D1+ to Dm+.

[0118] The sense amplifier unit 182 amplifies the potential difference between the voltages output from m data lines D1+ to Dm+ to each of nodes Nd1_1 to Nd1_m via the switch unit 181 and a predetermined voltage mid, and outputs amplified signals e_1 to e_m. The latch unit 183 latches the amplified signals e_1 to e_m output from the sense amplifier unit 182 and outputs them all at once.

[0119] Figure 11 is a diagram showing in more detail the switch section 181, sense amplifier section 182, and latch section 183 provided in the pixel inspection circuit 18.

[0120] As shown in Figure 11, the switch section 181 comprises m switch elements SW2_1 to SW2_m and m switch elements SW3_1 to SW3_m. The sense amplifier section 182 comprises m sense amplifiers SA_1 to SA_m. The latch section 183 comprises m switch elements SW4_1 to SW4_m.

[0121] In the switch section 181, the switch elements SW2_1 to SW2_m are each provided between the data lines D1+ to Dm+ and the nodes Nd1_1 to Nd1_m, and are switched on and off by the switching signal KSW. The switch elements SW3_1 to SW3_m are each provided between the nodes Nd1_1 to Nd1_m and the voltage supply line mid, and are switched on and off by the switching signal nut.

[0122] In the sense amplifier section 182, the sense amplifiers SA_1 to SA_m amplify the potential difference between the voltages of nodes Nd1_1 to Nd1_m and a predetermined voltage mid, and output amplified signals e_1 to e_m.

[0123] (Specific Configuration Example of Sense Amplifier SA_i) Figure 12 is a circuit diagram showing a specific configuration example of sense amplifier SA_i. The voltage source circuit 30 is also shown in Figure 12. Note that sense amplifier SA_i is any one of sense amplifiers SA_1 to SA_m.

[0124] As shown in Figure 12, the sense amplifier SA_i comprises transistors Tr11 to Tr17. Transistors Tr13 to Tr16 are all P-channel MOS transistors, and transistors Tr11, Tr12, and Tr17 are all N-channel MOS transistors. The voltage source circuit 30 comprises transistors Tr21 to Tr25. Transistors Tr21 and Tr24 are all P-channel MOS transistors, and transistors Tr22, Tr23, and Tr25 are all N-channel MOS transistors.

[0125] Transistors Tr15 and Tr16 are connected in parallel between the power supply voltage terminal Vdd2 and the ground voltage terminal Vss, and the voltage of node N2 is applied to their respective gates. Transistors Tr13 and Tr14 are connected in series with transistors Tr15 and Tr16, and the output voltage Va of the voltage source circuit 30 is applied to their respective gates. Transistors Tr11 and Tr12 are connected in series with transistors Tr13 and Tr14, and their respective gates are connected to a non-inverting input terminal to which the voltage of node Nd1_i (the node corresponding to the sense amplifier SA_i among nodes Nd1_1 to Nd1_m) is supplied, and an inverting input terminal to which a predetermined voltage mid is supplied. Transistor Tr17 is connected between transistors Tr11 and Tr12 and the ground voltage terminal Vss, and the output voltage Vb of the voltage source circuit 30 is applied to its gate. The voltage at node N1 between transistors Tr11 and Tr13 is inverted by inverter INV3 and then output as an amplified signal e_i (the amplified signal corresponding to sense amplifier SA_i among the amplified signals e_1 to e_m).

[0126] In the voltage source circuit 30, transistors Tr21 to Tr23 are all diode-connected and are provided in series between the power supply voltage terminal Vdd2 and the ground voltage terminal Vss. The gate voltages of transistors Tr21 and Tr22 are output as the voltage Va of the voltage source circuit 30. Transistors Tr24 and Tr25 are all diode-connected and are provided in series between the power supply voltage terminal Vdd2 and the ground voltage terminal Vss. The gate voltage of transistor Tr25 is output as the voltage Vb of the voltage source circuit 30.

[0127] In the latch section 183, the switch elements SW4_1 to SW4_m are each placed on the signal lines through which the amplified signals e_1 to e_m output from the sense amplifiers SA_1 to SA_m propagate, and are switched on or off by the trigger signal Tlat.

[0128] For example, by turning on switch elements SW2_1 to SW2_m and then turning on switch elements SW3_1 to SW3_m, m data lines D1+ to Dm+ and the voltage supply line mid are short-circuited. As a result, the voltages of the m data lines D1+ to Dm+ are refreshed to a predetermined voltage mid.

[0129] Furthermore, for example, by turning on switch elements SW2_1 to SW2_m and turning off switch elements SW3_1 to SW3_m, m pixel drive voltages read from each of the m data lines D1+ to Dm+ from the m pixels 12 of the j row under inspection are output to nodes Nd1_1 to Nd1_m. At this time, sense amplifiers SA_1 to SA_m amplify the potential difference between each voltage of nodes Nd1_1 to Nd1_m and a predetermined voltage mid, and output amplified signals e_1 to e_m expressed as H or L level. Then, in the latch unit 183, switch elements SW4_1 to SW4_m latch the amplified signals e_1 to e_m from sense amplifiers SA_1 to SA_m and output them simultaneously.

[0130] The shift register circuit 184 has the configuration of a dynamic shift register, and takes in the amplified signals e_1 to e_m that are simultaneously output from the latch unit 183, and outputs them one by one as a test signal (detection signal) TOUT while shifting them.

[0131] The power supply voltage terminal Vdd2 is supplied with a power supply voltage of, for example, 5V (hereinafter also referred to as power supply voltage Vdd2) from an external source. The power supply voltage terminal Vdd is supplied with a power supply voltage of, for example, 1.8V (hereinafter also referred to as power supply voltage Vdd) from an external source. The ground voltage terminal Vss is supplied with a ground voltage of, for example, 0V (hereinafter also referred to as ground voltage Vss) from an external source. The power supply voltage Vdd2 is used as the voltage to be written to the pixel after a 1.8V amplitude control signal for operating the circuit is shifted to a desired voltage level, or as the power supply voltage used in the circuit for generating a predetermined voltage mid or a test voltage to be written to the pixel during pixel inspection.

[0132] (Specific Configuration Example of Shift Register Circuit 184) Figure 13 shows a specific configuration example of the shift register circuit 184. The shift register circuit 184 comprises inverters INV1_1 to INV1_m, inverters INV2_1 to INV2_m, switch elements SW5_1 to SW5_m, switch elements SW6_1 to SW6_m, and buffer BF1.

[0133] Switch elements SW5_1 to SW5_m are provided in series between the ground voltage terminal Vss and the output terminal OUT. Inverters INV1_1 to INV1_m are provided downstream of switch elements SW5_1 to SW5_m. Switch elements SW6_1 to SW6_m are provided downstream of inverters INV1_1 to INV1_m. Inverters INV2_1 to INV2_m are provided downstream of switch elements SW6_1 to SW6_m. Buffer BF1 is provided downstream of inverter INV2_m. The amplified signals e_1 to e_m, output simultaneously from the latch unit 183, are supplied to the input terminals of inverters INV1_1 to INV1_m. Switch elements SW5_1 to SW5_m are switched on and off by the clock signal TCK. Switch elements SW6_1 to SW6_m are switched on and off in a complementary manner with switch elements SW5_1 to SW5_m by the clock signal TCKb. The configuration of the shift register circuit 184 is not limited to the configuration shown in Figure 13 and can be appropriately changed to other configurations that can achieve equivalent functionality.

[0134] (Operation of the liquid crystal device 60 in pixel inspection mode) Next, the operation of the liquid crystal device 60 in pixel inspection mode will be explained using Figure 14 in addition to Figures 10 and 11. Figure 14 is a timing chart showing the operation of the liquid crystal device 60 in pixel inspection mode.

[0135] First, a test video signal is written to multiple pixels 12 in row j, which are the target of inspection. During the video signal writing operation, an externally supplied H-level mode switching signal MD is provided. The operation of writing the test video signal is basically the same as the operation of writing the video signal in image display mode.

[0136] Specifically, the vertical shift register & level shifter 15 outputs a scan pulse for the j-th row (time t1). At this point, the mode switching signal MD indicates a high level, so the scan pulse for the j-th row output from the vertical shift register & level shifter 15 is supplied to the j-th row scan line Gj (time t1). As a result, transistors Tr1 and Tr2 provided in each pixel 12 of the j-th row are temporarily turned on, and the corresponding positive and negative polarity video signal voltages are stored and held in the retention capacitors Cs1 and Cs2 provided in each pixel 12 of the j-th row, respectively. On the other hand, transistor Tr9a provided in each pixel 12 of the j-th row is fixed to the off position.

[0137] Subsequently, the video signals written to multiple pixels 12 in the j-th row, which are the subject of inspection, are read out. During the video signal readout operation, the mode switching signal MD switches from the H level to the L level.

[0138] Specifically, first, the switch elements SW1+, SW1- to SWm+, SWm- provided in the analog switch section 17 are all controlled to be off. In other words, the control signals P1 to Pm (A_SW in Figure 14) that control the on / off state of the switch elements SW1+, SW1- to SWm+, SWm- provided in the analog switch section 17 are controlled to be inactive (L level).

[0139] Then, the switching signal KSW is controlled to be active (e.g., high level) (time t2). As a result, the switching elements SW2_1 to SW2_m switch from off to on, and the non-inverting input terminals of the sense amplifiers SA_1 to SA_m and the data lines D1+ to Dm+ become conductive. Subsequently, the switching signal nut is temporarily controlled to be active (e.g., high level) (time t3). As a result, the switching elements SW3_1 to SW3_m are temporarily turned on, causing a short circuit between the data lines D1+ to Dm+ and the voltage supply line mid, and as a result, the voltage of the data lines D1+ to Dm+ is refreshed to the predetermined voltage mid.

[0140] Subsequently, the positive video signals written to the storage capacity Cs1 of each of the m pixels 12 in the j-th row that are being inspected are read out to the data lines D1+ to Dm+.

[0141] Specifically, first, gate control signal S+ is activated (high level) and gate control signal B is activated (low level) (time t4). As a result, transistor Tr5 of each pixel 12 in the j-th row is turned on, and the positive polarity source follower buffer consisting of transistors Tr3 and Tr7 of each pixel 12 in the j-th row becomes active, so the pixel drive electrode PE of each pixel 12 in the j-th row is charged with the voltage of the positive polarity video signal held in the holding capacitor Cs1.

[0142] Subsequently, the vertical shift register & level shifter 15 outputs a scan pulse for the j-th row (time t5). At this point, the mode switching signal MD is at the L level, so the scan pulse for the j-th row output from the vertical shift register & level shifter 15 is supplied to the readout switch selection line TGj for the j-th row (time t5). As a result, the transistor Tr9 provided in each pixel 12 of the j-th row is temporarily turned on, and the pixel drive electrodes PE of the m pixels 12 of the j-th row and the data lines D1+ to Dm+ are temporarily conductive. Consequently, the positive polarity video signal voltage VPE charged in the pixel drive electrodes PE of the m pixels 12 of the j-th row is read out as positive polarity pixel drive voltage and held on the data lines D1+ to Dm+, respectively.

[0143] Here, since all the switching elements of the analog switch section 17 are controlled to be off, the data line Di+ does not have the wiring capacitance of approximately 5pF of the common wiring Dcom+ added to it, and only the wiring capacitance of the n rows of pixels 12 is added. For example, in the case of FHD, only the wiring capacitance of approximately 1pF for 1080 pixels is added to the data line Di+. Therefore, in the liquid crystal device 60, the source follower buffer consisting of transistors Tr3 and Tr7 provided at the j-th row and i-th column pixel 12 to be inspected can charge the data line Di+ in a short time without being affected by the wiring capacitance or wiring resistance of the common wiring Dcom+.

[0144] The voltages of the positive polarity video signals (positive polarity pixel drive voltages) of the m pixels 12 in the jth row, read out on each of the data lines D1+ to Dm+, are supplied to the non-inverting input terminals of the sense amplifiers SA_1 to SA_m, respectively.

[0145] The sense amplifiers SA_1 to SA_m amplify the potential difference between the voltages of m positive video signals read from each of the m pixels 12 in the j-th row onto the data lines D1+ to Dm+, and a predetermined voltage mid, and output amplified signals e_1 to e_m, which are represented as H or L levels.

[0146] Then, the switch elements SW4_1 to SW4_m provided in the latch unit 183 simultaneously output the amplified signals e_1 to e_m when the trigger signal Tlat becomes temporarily active (time t6). Subsequently, the shift register circuit 184 takes in the amplified signals e_1 to e_m that were simultaneously output from the latch unit 183 and outputs them one by one as the test signal TOUT while shifting them (time t7).

[0147] An inspection device (not shown) located outside the liquid crystal device 60 detects failures (defects, characteristic degradation, etc.) in the m pixels 12 of the j-th row, which are the subject of inspection, by comparing the value of the inspection signal TOUT with the expected value.

[0148] This type of inspection is performed row by row, starting from the m pixels 12 in the first row to the m pixels 12 in the nth row.

[0149] Once the inspection of the signals written to the retention capacitor Cs1 of all pixels 12 is complete, the inspection of the signals written to the retention capacitor Cs2 of all pixels 12 is then performed. The specific processing is the same as the inspection of the signals written to the retention capacitor Cs1 of all pixels 12, except that at time t4, the gate control signal S- is activated (H level) instead of the gate control signal S+, thereby turning on the transistor Tr6 of each pixel 12 in the j-th row instead of the transistor Tr5 of each pixel 12 in the j-th row. Therefore, the explanation is omitted.

[0150] Thus, in the liquid crystal device 60, the pixel inspection circuit 18 has a read path for video signals from the pixels 12, separate from the write path for video signals to the pixels 12. When reading video signals written to the pixels 12 under inspection, a portion of the write path for video signals to the pixels 12 is electrically isolated from the data lines. As a result, when reading video signals written to the pixels 12 under inspection, the liquid crystal device 60 does not need to excessively charge the wiring capacitance of, for example, the common wiring Dcom+. This shortens the time it takes for the source follower buffer of each pixel 12 to stabilize the pixel drive voltage VPE, and consequently, the inspection of the pixels 12 by the inspection device can be performed quickly.

[0151] Furthermore, the liquid crystal device 60 can also be used to inspect for charge leakage accumulated in the retaining capacitors Cs1 and Cs2 provided in each pixel 12.

[0152] In each pixel 12, the N-type diffusion layer forming the drain of transistor Tr1 and the P-well are connected by a PN junction. Therefore, if a defect occurs in the PN junction during the manufacturing process, the charge accumulated in the retaining capacitor Cs1 may leak into the P-well through the PN junction. As a result, the voltage of the retaining capacitor Cs1 may gradually decrease toward the ground voltage level. Similarly, the N-type diffusion layer forming the drain of transistor Tr2 and the P-well are connected by a PN junction. Therefore, if a defect occurs in the PN junction during the manufacturing process, the charge accumulated in the retaining capacitor Cs2 may leak into the P-well through the PN junction. As a result, the voltage of the retaining capacitor Cs2 may gradually decrease toward the ground voltage level. In this case, a pixel defect will occur in the display image of the liquid crystal display panel (display screen of the image display unit 11).

[0153] Therefore, in the liquid crystal device 60, when inspecting for charge leakage stored in the retention capacitors Cs1 and Cs2 provided in each pixel 12, the time from when the video signal is written to the retention capacitor Cs1 of the pixel 12 under inspection until the video signal written to the retention capacitor Cs1 is read out is made longer than during normal inspection.

[0154] Consequently, if the charge in the retaining capacitor Cs1 leaks, the voltage held in the retaining capacitor Cs1 decreases over time. This decreased voltage is then output directly as the pixel drive voltage by the source follower buffer consisting of transistors Tr3 and Tr7.

[0155] When inspecting for charge leakage in a retaining capacitor Cs1 provided in a pixel 12 under inspection, for example, the expected value of the pixel drive voltage read from the retaining capacitor Cs1 is set to 2.6V, and a predetermined voltage mid is set to, for example, 2.5V. As a result, for example, if there is no charge leakage in the retaining capacitor Cs1 provided in the pixel 12 under inspection, the pixel drive voltage read from the pixel 12 will be 2.6V, and the output of the sense amplifier will show an H level indicating that the pixel 12 under inspection is normal. On the other hand, if there is charge leakage in the retaining capacitor Cs1 of the pixel 12 under inspection, the pixel drive voltage read from the pixel 12 will be lower than the expected value (for example, 2.4V), and the output of the sense amplifier will show an L level indicating that there is charge leakage in the retaining capacitor Cs1 provided in the pixel 12 under inspection. Furthermore, by repeatedly fine-tuning the expected value of the pixel drive voltage and performing the inspection, it is also possible to determine the amount of leakage in the retaining capacitor Cs1.

[0156] When inspecting for charge leakage in a retaining capacitor Cs2 provided in a pixel 12 under inspection, for example, the expected value of the pixel drive voltage read from the retaining capacitor Cs2 is set to 2.6V, and a predetermined voltage mid is set to, for example, 2.5V. As a result, for example, if there is no charge leakage in the retaining capacitor Cs2 provided in the pixel 12 under inspection, the pixel drive voltage read from the pixel 12 will be 2.6V, and the output of the sense amplifier will show an H level indicating that the pixel 12 under inspection is normal. On the other hand, if there is charge leakage in the retaining capacitor Cs2 of the pixel 12 under inspection, the pixel drive voltage read from the pixel 12 will be lower than the expected value (for example, 2.4V), and the output of the sense amplifier will show an L level indicating that there is charge leakage in the retaining capacitor Cs2 provided in the pixel 12 under inspection. Furthermore, by repeatedly fine-tuning the expected value of the pixel drive voltage and performing the inspection, it is also possible to determine the amount of leakage in the retaining capacitor Cs2.

[0157] In this way, the liquid crystal device 60 can be used to inspect for leakage of the retaining capacitances Cs1 and Cs2 provided in each pixel 12.

[0158] Furthermore, if the amount of leakage in the retained capacities Cs1 and Cs2 and the location of the leakage can be identified, it is possible to correct the amount of leakage during normal operation. This makes it possible to correct and reuse chips that would otherwise have been discarded, thereby improving yield.

[0159] Furthermore, the PAD added for probe testing (for example, the PAD through which external signals TCK, TCKb, Tlat, nut, mid, KSW, and TOUT are exchanged) is not used after the inspection and is therefore fixed to a predetermined value by, for example, pulling down or pulling up. As a result, even if the PAD added for probe testing is floating without an external signal voltage input, the pixel inspection circuit 18 can prevent unintended operation and unintended leakage current.

[0160] As described above, the liquid crystal device 60 can not only quickly inspect whether each of the transistors Tr1 to Tr9 and the retaining capacitors Cs1 and Cs2 that constitute the pixel 12 to be inspected are operating normally, but it can also identify the amount of leakage of the retaining capacitors Cs1 and Cs2.

[0161] Furthermore, in pixel inspection mode, the liquid crystal device 60 performs both the operation of writing a video signal to the pixel 12 and the operation of reading a video signal from the pixel 12. Therefore, it is possible to inspect not only the pixel 12 but also whether its peripheral circuits are functioning correctly. Needless to say, the pixel inspection method of the liquid crystal device 60 may be used in combination with other inspection methods.

[0162] (Challenges of the liquid crystal device 60) The pixel inspection circuit 18 is located within the panel of the liquid crystal device 60, but it becomes unnecessary after being used for acceptance testing (probe testing), such as checking the number and location of pixel defects and checking for driver malfunctions. However, while the liquid crystal device 60 is in use as a product, the pixel inspection circuit 18 is supplied with a power supply voltage Vdd2, which causes leakage current to occur. For example, since the pixel inspection circuit 18 is supplied with a power supply voltage of 5V, a significant leakage current that cannot be ignored occurs. As a result, the liquid crystal device 60 has the problem of increased power consumption.

[0163] Therefore, a liquid crystal device 1 capable of reducing power consumption was discovered.

[0164] <Embodiment 1> Figure 15 shows a liquid crystal device (liquid crystal display device) 1 according to Embodiment 1. In the liquid crystal device 1, the pixel inspection circuit 18 is supplied with a power supply voltage separate from the power supply voltage supplied to circuits other than the pixel inspection circuit 18. The other configurations of the liquid crystal device 1 are the same as those of the liquid crystal device 60, so their explanation is omitted.

[0165] Specifically, the vertical driver 19 and the horizontal driver 16, which are circuits other than the pixel inspection circuit 18, are supplied with power supply voltage Vdd and power supply voltage Vdd2, respectively. In addition, the vertical driver 19 and the horizontal driver 16 are each supplied with ground voltage Vss. The vertical driver 19 includes a vertical shift register & level shifter 15 and a polarity switching control circuit 14. The power supply voltage Vdd is, for example, 1.8V, and the power supply voltage Vdd2 is, for example, 5V. The ground voltage Vss is 0V. Hereinafter, the pad to which the power supply voltage Vdd is supplied will also be referred to as pad Vdd. The pad to which the power supply voltage Vdd2 is supplied will also be referred to as pad Vdd2. The pad to which the ground voltage Vss is supplied will also be referred to as pad Vss. In other words, pads Vdd, Vdd2, and Vss are connected to the vertical driver 19 and the horizontal driver 16, respectively.

[0166] In contrast, the pixel inspection circuit 18 is supplied with a separate power supply voltage TVdd2, which is distinct from the power supply voltages Vdd and Vdd2. The pixel inspection circuit 18 is also supplied with a ground voltage Vss, just like the other circuits. The power supply voltage TVdd is, for example, 5V. Hereafter, the pad to which the power supply voltage TVdd is supplied will also be referred to as pad TVdd. In other words, pads TVdd and Vss are connected to the pixel inspection circuit 18.

[0167] Figure 16 is a circuit diagram showing a specific configuration example of the sense amplifier SA_i provided in the pixel inspection circuit 18. The voltage source circuit 30 is also shown in Figure 16. Note that the sense amplifier SA_i is any one of the sense amplifiers SA_1 to SA_m.

[0168] The sense amplifier SA_i shown in Figure 16 is connected to a power supply voltage terminal (hereinafter referred to as power supply voltage terminal TVdd) to which the power supply voltage TVdd is supplied, instead of the power supply voltage terminal Vdd2, compared to the sense amplifier SA_i shown in Figure 12. The other configurations of the sense amplifier SA_i shown in Figure 16 are the same as those of the sense amplifier SA_i shown in Figure 12, so their explanation is omitted.

[0169] Figure 17 is a schematic plan view showing an example of the circuit layout of the chip 10 of the liquid crystal device 1. As shown in Figure 17, an image display unit 11 consisting of multiple pixels 12 is arranged on the silicon substrate 20 of the chip 10, and a vertical driver 19, a horizontal driver 16, and a pixel inspection circuit 18 are arranged around the image display unit 11. In addition, multiple pads are arranged around the outer periphery of the silicon substrate 20. Here, pads Vdd, Vdd2, and Vss are connected to the vertical driver 19 and the horizontal driver 16, respectively. In contrast, pads TVdd and Vss are connected to the pixel inspection circuit 18. In other words, the pixel inspection circuit 18 and the circuits other than the pixel inspection circuit 18 are supplied with power supply voltages from different power supply systems. Furthermore, a resistor element R1 that acts as a pull-down resistor is provided between pad TVdd and pad Vss. The resistance value of the resistor element R1 is, for example, 1 kΩ.

[0170] For example, in pixel inspection mode, probe inspection is performed on the wafer before the chip 10 of the liquid crystal device 1 is cut out by dicing. At this time, the pad TVdd is supplied with a power supply voltage TVdd that is the same value (5V in this example) as the power supply voltage Vdd2 supplied to the pad Vdd2. Therefore, the pixel inspection circuit 18 is driven by the power supply voltage TVdd. After the probe inspection is completed and the pixel inspection mode ends, the pixel inspection circuit 18 is no longer needed, and the power supply voltage TVdd is no longer supplied to the pad TVdd. Therefore, the voltage of the pad TVdd is pulled down to the ground voltage Vss by the resistor R1. As a result, no leakage current is generated in the pixel inspection circuit 18 while the liquid crystal device 1 is used as a product, and thus the increase in power consumption is suppressed. In addition, the pixel inspection circuit 18 does not cause malfunctions in other circuits of the liquid crystal device 1 after pixel inspection, starting from foreign matter or other contaminants, so the decrease in reliability is suppressed.

[0171] Figure 18 is a schematic perspective view showing the external appearance of the chip 10 of the liquid crystal device 1. As shown in Figure 18, the chip 10 of the liquid crystal device 1 has a chip body 10a cut out by dicing from a wafer after probe testing is completed, and a glass substrate 10b provided on the chip body 10a. The glass substrate 10b is a transparent substrate and is used as the common electrode CE of the liquid crystal LC.

[0172] The glass substrate 10b is placed on a pixel area PA1 formed on a silicon substrate 20, which is the base for the chip body 10a. The pixel area PA1 is the area where the image display unit 11, consisting of multiple pixels 12, is located. The glass substrate 10b and the silicon substrate 20 are bonded together by an insulating sealant (not shown) in a seal area SA1 formed on the silicon substrate 20, outside the pixel area PA1. The seal area SA1 is the area where the vertical driver 19, the horizontal driver 16, and the pixel inspection circuit 18 are located. Here, the insulating sealant covers the pixel inspection circuit 18, thereby preventing short circuits between the pixel inspection circuit 18 and other circuits.

[0173] Figure 19 is a schematic plan view showing the external appearance of the liquid crystal device 1. In the example shown in Figure 19, the liquid crystal device 1 comprises a reflective liquid crystal element including a chip 10 shown in Figure 18 and a flexible printed circuit board 25 attached to the chip 10. The liquid crystal device 1 according to this disclosure can quickly perform pixel inspection by including a pixel inspection circuit 18. Furthermore, the liquid crystal device 1 according to this disclosure can suppress an increase in power consumption by cutting off the power supply voltage to the pixel inspection circuit 18 after pixel inspection, and can also improve reliability by preventing malfunctions caused by the pixel inspection circuit 18. In other words, the liquid crystal device 1 according to this disclosure can quickly perform pixel inspection while suppressing an increase in power consumption.

[0174] This disclosure is not limited to the embodiments described above, and may be modified as appropriate without departing from its spirit.

[0175] This application claims priority based on Japanese Patent Application No. 2025-048783, filed on 24 March 2025, and incorporates all of its disclosures herein.

[0176] This disclosure can be suitably applied to liquid crystal display devices mounted on projectors and the like, and to optical switching elements mounted on wavelength selective switching devices.

[0177] 1 Liquid Crystal Device 10 Chip 10a Chip Body 10b Glass Substrate 11 Image Display Unit 12 Pixel 13 Timing Generator 14 Polarity Switching Control Circuit 15 Vertical Shift Register & Level Shifter 16 Horizontal Driver 17 Analog Switch Unit 18 Pixel Inspection Circuit 19 Vertical Driver 20 Silicon Substrate 25 Flexible Printed Circuit Board 30 Voltage Source Circuit 40 Lamp Signal Generator 50 Liquid Crystal Device 60 Liquid Crystal Device 100 WSS Array 100a, 100b WSS Device 110 Input Unit 120 Optical System 121-123 Lens 124 Dispersive Element 130 Reflective Liquid Crystal Element 161 Shift Register Circuit 162 1-Line Latch Circuit 163 Comparator Unit 163_1-163_m Comparator 164 Grayscale Counter 181 Switch Unit 182 Sense amplifier section 183 Latch section 184 Shift register circuit ADA1 to ADAn AND circuit ADB1 to ADBn AND circuit B Gate control signal line BF1 Buffer CE Common electrode Cs1, Cs2 Holding capacitance D1+, D1- to Dm+, Dm- Data line Dcom+, Dcom- Common wiring FI1 Input fiber (input port) FI2 Input fiber (input port) FO1_1 to FO1_n Output fiber (output port) FO2_1 to FO2_n Output fiber (output port) G1 to Gn Row scan line LC Liquid crystal display element LCM Liquid crystal LI1, LI2 Collimating lens LO1_1 to LO1_n Collimating lens LO2_1 to LO2_n Collimating lens Na, Nb Node PE Pixel driving electrode (reflector electrode) R1 Resistor element S+, S- Gate control signal line SA_1 to SA_m Sense amplifier SW1_1+, SW1_1- to SW1_m+,SW1_m - Switch element SW2_1 to SW2_m Switch element SW3_1 to SW3_m Switch element SW4_1 to SW4_m Switch element SW5_1 to SW5_m Switch element SW6_1 to SW6_m Switch element TG1 to TGn Readout switch selection line Tr1 to Tr9 Transistor Tr11 to Tr17 Transistor Tr21 to Tr25 Transistor,

Claims

1. A horizontal driver having at least a plurality of pixels arranged in a matrix, a plurality of data lines provided corresponding to each row of the plurality of pixels, and a plurality of first switch elements for switching whether or not to supply a video signal to each of the plurality of data lines, and a pixel inspection circuit having at least a plurality of sense amplifiers that, in pixel inspection mode, amplify the potential difference between a plurality of pixel drive voltages read from each of the plurality of data lines provided from the plurality of pixels to be inspected and a predetermined voltage, and output it as a plurality of detection signals, wherein each of the pixels has a sample-and-hold circuit that samples and holds the video signal supplied to the corresponding data line, a liquid crystal display element composed of a pixel drive electrode, a common electrode, and liquid crystal sealed between them to which the voltage of the video signal held in the sample-and-hold circuit is supplied, and a switch transistor that, in pixel inspection mode, outputs the voltage of the pixel drive electrode as the pixel drive voltage to the corresponding data line, and a first pad connected to the horizontal driver to which a first power supply voltage is supplied, A liquid crystal display device further comprising: a second pad connected to the pixel inspection circuit and supplied with a second power supply voltage from a different power supply system than the first power supply voltage; a third pad at least connected to the pixel inspection circuit and supplied with a ground voltage; and a pull-down resistor provided between the second pad and the third pad.

2. The liquid crystal display device according to claim 1, wherein the pixel inspection circuit is provided on a silicon substrate and is covered with an insulating sealing material that adheres the silicon substrate and a plate-shaped glass substrate used as the common electrode.

3. After the pixel inspection mode, the supply of the second power supply voltage to the second pad is stopped, as described in claim 1.

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