Drive circuit

Abstract

This gate drive circuit 10 generates a gate voltage of an N-channel type semiconductor switch Q1 for turning on and off a main power supply line connected to a first DC power supply. A charge pump circuit 20 generates a high-side reference potential of the gate drive circuit 10 in which a low-side reference potential is connected to the main power supply line. A clock generation circuit 30 generates a clock voltage for driving the charge pump circuit 20 by using a voltage of a second DC power supply whose voltage is lower than that of the first DC power supply. The clock generation circuit 30 generates a clock voltage shaped to have a waveform of an opposite phase to the phase of the ripple generated in the high-side reference potential.

Description

Drive Circuit

[0001] The present disclosure relates to a drive circuit that drives a semiconductor switch.

[0002] In a power line of a power supply system using a battery as a supply source, a charge / discharge switch is often employed on the high side. Control of the charge / discharge switch requires a semiconductor switch, a drive circuit, and a high-side power supply on the high side. As an inexpensive and simple method for configuring the high-side power supply, a method using a charge pump circuit is widely employed (see, for example, Patent Documents 1 to 4).

[0003] As shown in FIG. 1, the high-side voltage HV boosted by the charge pump circuit 20 is maintained by the output holding capacitor Co and the output holding diode D1, but gradually decreases due to the current consumption and leakage current of the gate drive circuit 10. To maintain the on-state of the semiconductor switch Q1, it is necessary to set the charge clock sufficiently fast to repeat charging, and control the high-side voltage HV so that it does not fall below the threshold voltage of the semiconductor switch Q1. As shown in FIG. 2, repeated charging causes transient ripples in the high-side voltage HV. This ripple generates radiated noise via the semiconductor switch Q1.

[0004] Japanese Patent Application Laid-Open No. 11-178224, Japanese Patent Application Laid-Open No. 2007-124768, Japanese Patent Application Laid-Open No. 2017-529046, Japanese Patent Application Laid-Open No. 2023-183371

[0005] The present disclosure has been made in view of such circumstances, and an object of the present disclosure is to provide a technique for reducing ripple noise generated when generating the gate voltage of a semiconductor switch using a charge pump circuit at low cost.

[0006] To solve the above problems, a drive circuit in one aspect of the present disclosure includes: a gate drive circuit that generates a gate voltage for an N-channel semiconductor switch to turn on / off a main power line connected to a first DC power supply; a charge pump circuit that generates a high-side reference potential for the gate drive circuit, the low-side reference potential of which is connected to the main power line; and a clock generation circuit that generates a clock voltage for driving the charge pump circuit using the voltage of a second DC power supply having a lower voltage than the first DC power supply. The clock generation circuit generates a clock voltage that is shaped to have a waveform with the opposite phase to the phase of the ripple generated at the high-side reference potential.

[0007] According to this disclosure, ripple noise generated when generating the gate voltage of a semiconductor switch can be reduced at low cost using a charge pump circuit.

[0008] This figure shows an example configuration of a semiconductor switch drive circuit according to a comparative example. This figure schematically shows the transient waveform of the high-side voltage. This figure shows an example configuration of a semiconductor switch drive circuit according to an embodiment. This figure schematically shows the transient waveform of the high-side voltage, the output voltage of the first inverter, and the output voltage of the second inverter.

[0009] Figure 1 shows an example configuration of the drive circuit 1 for a semiconductor switch Q1 according to a comparative example. In Figure 1, an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used for the semiconductor switch Q1. To drive an N-channel MOSFET, it is necessary to generate a gate voltage higher than the source voltage (generally, about source voltage + 10V).

[0010] Furthermore, an N-channel IGBT (Insulated Gate Bipolar Transistor) may be used as the semiconductor switch Q1. To drive an N-channel IGBT, it is necessary to generate a gate voltage higher than the emitter voltage.

[0011] The semiconductor switch Q1 is used to turn on / off the main power line connected to the battery pack 2 (first DC power supply). When the battery pack 2 is used in an automotive application, for example, it is used as a 48V power supply and provides power to 48V loads in the vehicle (e.g., turbocharger, power steering, infotainment system). The battery pack 2 is also charged with energy recovered from regenerative braking when the vehicle is decelerating.

[0012] Furthermore, when battery pack 2 is used as the drive battery for an electric vehicle, battery pack 2 is used as a 200V to 800V power source and supplies power to the drive motor via an inverter. Battery pack 2 is also charged with power supplied from an external charger.

[0013] The semiconductor switch Q1 shown in Figure 1 is used as a charging switch for the battery pack 2. The source terminal of the semiconductor switch Q1 is connected to the battery pack 2 side of the main power line, and the drain terminal is connected to the load side. The gate terminal of the semiconductor switch Q1 is connected to the gate drive circuit 10. In an N-channel MOSFET, a parasitic diode is formed from the source to the drain. Therefore, the semiconductor switch Q1 for charging cannot interrupt the discharge current.

[0014] Although not shown in Figure 1, typically, a discharge semiconductor switch is connected in series with the charging semiconductor switch Q1, in the opposite direction to the charging semiconductor switch Q1. The source terminal of the discharge semiconductor switch is connected to the load side of the main power line, and the drain terminal of the discharge semiconductor switch is connected to the drain terminal of the charging semiconductor switch Q1.

[0015] The comparative example drive circuit 1 comprises a gate drive circuit 10, a charge pump circuit 20, an inverter IN1, and a control circuit 40. The control circuit 40 is composed of, for example, a microcontroller.

[0016] The gate drive circuit 10 generates the gate voltage of the semiconductor switch Q1. The high-side reference potential of the gate drive circuit 10 is connected to a high-voltage control power line connected to the charge pump circuit 20, and the low-side reference potential of the gate drive circuit 10 is connected to the main power line. The gate drive circuit 10 includes a push-pull circuit in which a P-channel transistor and an N-channel transistor are connected in series.

[0017] The push-pull circuit is connected between the high-side reference potential and the low-side reference potential of the gate drive circuit 10, and outputs the high-side voltage HV of the high-voltage control power line connected to the high-side reference potential, or the first power supply voltage VBAT of the main power line connected to the low-side reference potential, in response to a control signal from the control circuit 40.

[0018] When the gate drive circuit 10 receives an ON signal for semiconductor switch Q1 from the control circuit 40, it inputs a high-side voltage HV to the gate terminal of semiconductor switch Q1 to control semiconductor switch Q1 to the ON state. When the gate drive circuit 10 receives an OFF signal for semiconductor switch Q1 from the control circuit 40, it inputs a first power supply voltage VBAT to the gate terminal of semiconductor switch Q1 to control semiconductor switch Q1 to the OFF state.

[0019] The charge pump circuit 20 generates a high-side voltage HV, which is used as the high-side reference potential for the gate drive circuit 10. The charge pump circuit 20 includes an output holding capacitor Co, an output holding diode D1, a flying capacitor Cf1, and a Zener diode ZD1.

[0020] The output holding capacitor Co is connected between the high-voltage control power line and the main power line. The flying capacitor Cf1 is connected between the anode terminal of the output holding diode D1 and the output terminal of the inverter IN1. The output holding diode D1 is connected between the high-side terminal of the flying capacitor Cf1 and the high-side terminal of the output holding capacitor Co. The anode terminal of the output holding diode D1 is connected to the high-side terminal of the flying capacitor Cf1, and the cathode terminal of the output holding diode D1 is connected to the high-side terminal of the output holding capacitor Co.

[0021] The Zener diode ZD1 is connected between the anode terminal of the output holding diode D1 and the main power line. The Zener diode ZD1 is used as a constant voltage source, and a voltage obtained by subtracting the forward voltage Vf of the Zener diode ZD1 from the first power supply voltage VBAT is applied to the high-side terminal of the flying capacitor Cf1. Since the forward voltage Vf of the Zener diode ZD1 is small with respect to the first power supply voltage VBAT, the forward voltage Vf of the Zener diode ZD1 is considered negligible here.

[0022] Inverter IN1 generates a clock voltage for driving the charge pump circuit 20 using the voltage VDD of the second DC power supply (hereinafter referred to as the second power supply voltage VDD). The second power supply voltage VDD is a voltage lower than the first power supply voltage VBAT supplied from the battery pack 2. For automotive applications, a 12V output lead-acid battery can be used as the second DC power supply. The second power supply voltage VDD may also be generated by stepping down the first power supply voltage VBAT using a switching regulator or linear regulator.

[0023] The high-side reference potential of inverter IN1 is connected to a low-voltage control power line connected to the high-side potential of the second DC power supply, and the low-side reference potential of inverter IN1 is connected to a ground line connected to the low-side potential of the second DC power supply. Inverter IN1 includes a push-pull circuit in which a P-channel transistor and an N-channel transistor are connected in series. The push-pull circuit is connected between the high-side reference potential and the low-side reference potential of inverter IN1.

[0024] Inverter IN1 supplies the charge pump circuit 20 with a square wave signal (charge clock) supplied from the control circuit 40, but with the phase inverted. Specifically, when the square wave signal supplied from the control circuit 40 is low level, inverter IN1 applies the second power supply voltage VDD to the low-side terminal of the flying capacitor Cf1, and when the square wave signal supplied from the control circuit 40 is high level, inverter IN1 applies the ground voltage to the low-side terminal of the flying capacitor Cf1. Note that the square wave signal input to inverter IN1 may be generated by an oscillator other than the control circuit 40.

[0025] The flying capacitor Cf1 is charged during periods when the clock signal output from inverter IN1 is low level. During this charging period, the voltage of the flying capacitor Cf1 becomes the first power supply voltage VBAT. During periods when the clock signal output from inverter IN1 is high level, the flying capacitor Cf1 transfers the stored charge to the output holding capacitor Co and the gate drive circuit 10. When the transition from the charging period to the transfer period occurs, the voltage of the flying capacitor Cf1 rises to a voltage obtained by adding the second power supply voltage VDD to the first power supply voltage VBAT (hereinafter referred to as the boosted voltage (VBAT + VDD)). In this way, the flying capacitor Cf1 repeatedly charges and transfers charge in synchronization with the clock signal supplied from inverter IN1.

[0026] During the transfer period of the flying capacitor Cf1, the output holding capacitor Co is charged to the boosted voltage (VBAT + VDD). The forward voltage Vf of the output holding diode D1 is negligible relative to the boosted voltage (VBAT + VDD), so it is ignored here.

[0027] After the voltage across the flying capacitor Cf1 rises to the boosted voltage (VBAT + VDD), ideally, the high-side voltage HV should be maintained at the boosted voltage (VBAT + VDD) by the output holding capacitor Co and the output holding diode D1. However, in reality, the high-side voltage HV gradually decreases due to the current consumption and leakage current of the gate drive circuit 10.

[0028] Figure 2 schematically shows the transient waveform of the high-side voltage HV. Ideally, the high-side voltage HV should be a constant voltage waveform as shown by the dotted line. However, in reality, due to the current consumption and leakage current of the gate drive circuit 10, the voltage across the flying capacitor Cf1 rises to the boosted voltage (VBAT + VDD), and then the high-side voltage HV gradually decreases. Therefore, ripple occurs in the high-side voltage HV according to the frequency of the charge clock signal. Since the lower limit of the high-side voltage HV is the first power supply voltage VBAT, ripple occurs in the range between the boosted voltage (VBAT + VDD) and the first power supply voltage VBAT.

[0029] When ripple occurs in the high-side voltage HV, the ripple propagates to the gate voltage of semiconductor switch Q1, causing the on-resistance of semiconductor switch Q1 to fluctuate. When the on-resistance of semiconductor switch Q1 fluctuates, noise is superimposed on the voltage and current of the main power line. In automotive systems, strict safety standards are required, so it is necessary to minimize radiated noise from the main power line.

[0030] To mitigate ripple in the high-side voltage (HV), it is conceivable to increase the speed of the charge clock. However, increasing the speed of the charge clock will increase current consumption. Alternatively, to mitigate ripple, it is conceivable to connect an RC low-pass filter to the high-voltage control power supply line. However, connecting an RC low-pass filter will increase the charge time of the output holding capacitor Co, increase losses due to resistance, and increase component costs. Furthermore, to mitigate ripple, it is conceivable to increase the capacitance of the output holding capacitor Co. However, this will increase the initial charge time of the output holding capacitor Co and increase component costs.

[0031] Figure 3 shows an example of the configuration of the drive circuit 1 of the semiconductor switch Q1 according to the embodiment. The differences from the drive circuit 1 of the semiconductor switch Q1 according to the comparative example shown in Figure 1 will be explained below. The drive circuit 1 according to the embodiment includes a gate drive circuit 10, a charge pump circuit 20, a clock generation circuit 30, and a control circuit 40.

[0032] The charge pump circuit 20 includes an output holding capacitor Co, a first output holding diode D1, a first flying capacitor Cf1, a first Zener diode ZD1, a second output holding diode D2, a second flying capacitor Cf2, and a second Zener diode ZD2. The charge pump circuit 20 according to this embodiment has the addition of a second output holding diode D2, a second flying capacitor Cf2, and a second Zener diode ZD2 compared to the charge pump circuit 20 according to the comparative example shown in Figure 1. In this embodiment, the low-side terminal of the first flying capacitor Cf1 is connected to the output terminal of the first inverter IN1 of the clock generation circuit 30.

[0033] The second flying capacitor Cf2 is connected between the high-voltage control power line and the output terminal of the second inverter IN2 of the clock generation circuit 30. The second output holding diode D2 is connected in parallel with the first output holding diode D1 between the high-side terminal of the second flying capacitor Cf2 and the high-side terminal of the output holding capacitor Co. The anode terminal of the second output holding diode D2 is connected to the high-side terminal of the second flying capacitor Cf2, and the cathode terminal of the second output holding diode D2 is connected to the high-side terminal of the output holding capacitor Co.

[0034] The second Zener diode ZD2 is connected between the anode terminal of the second output holding diode D2 and the main power line. The second Zener diode ZD2 is used as a second constant voltage source, and a voltage obtained by subtracting the forward voltage Vf of the second Zener diode ZD2 from the first power supply voltage VBAT is applied to the high-side terminal of the second flying capacitor Cf2. Since the forward voltage Vf of the second Zener diode ZD2 is small with respect to the first power supply voltage VBAT, the forward voltage Vf of the second Zener diode ZD2 is considered negligible here.

[0035] The clock generation circuit 30 uses the second power supply voltage VDD to generate a clock voltage for driving the charge pump circuit 20. At that time, the clock generation circuit 30 generates a clock voltage that is shaped to have a waveform with the opposite phase to the ripple generated at the high-side reference potential of the gate drive circuit 10. The circuit configuration of the clock generation circuit 30 will be described in detail below.

[0036] The clock generation circuit 30 includes a first clock generation unit 31 and a second clock generation unit 32. The first clock generation unit 31 generates a first shaped clock voltage to be applied to the low-side terminal of the first flying capacitor Cf1. The second clock generation unit 32 generates a second shaped clock voltage to be applied to the low-side terminal of the second flying capacitor Cf2, which has a phase shift of 180 degrees relative to the first shaped clock voltage.

[0037] The first clock generation unit 31 includes a first inverter IN1, a first series resistor Rs1, a first bypass capacitor Cb1, a first voltage divider resistor Rd1, and a first voltage divider switch SW1. The second clock generation unit 32 includes a second inverter IN2, a second series resistor Rs2, a second bypass capacitor Cb2, a second voltage divider resistor Rd2, and a second voltage divider switch SW2.

[0038] The first series resistor Rs1 is connected to a low-voltage control power line that connects the high-side potential of the second DC power supply to the high-side reference potential of the first inverter IN1. The first bypass capacitor Cb1 is connected between the first connection point N1 between the first series resistor Rs1 and the high-side reference potential of the first inverter IN1, and the ground line. The first series resistor Rs1 and the first bypass capacitor Cb1 constitute a low-pass filter.

[0039] A first voltage divider resistor Rd1 and a first voltage divider switch SW1 are connected in series between the first connection point N1 and the ground line. An N-channel semiconductor switch is used for the first voltage divider switch SW1. In the example shown in Figure 3, an N-channel MOSFET is used. The source terminal of the first voltage divider switch SW1 is connected to the ground line, the drain terminal is connected to the first voltage divider resistor Rd1, and the gate terminal is connected to the input terminal of the first inverter IN1.

[0040] A first square wave signal (charge clock) is input to the input terminal of the first inverter IN1 from the control circuit 40. The first voltage divider switch SW1 conducts when the first square wave signal is at a high level, and the first voltage divider resistor Rd1 becomes active. The first voltage divider switch SW1 is blocked when the first square wave signal is at a low level, and the first voltage divider resistor Rd1 becomes inactive. During the period when the first voltage divider resistor Rd1 is active, the first series resistor Rs1 and the first voltage divider resistor Rd1 constitute a resistive voltage divider circuit, and the voltage at the first connection point N1 is the voltage obtained by dividing the second power supply voltage VDD by the voltage division ratio of the first series resistor Rs1 and the first voltage divider resistor Rd1.

[0041] The high-side reference potential of the second inverter IN2 is connected to the low-voltage control power line, and the low-side reference potential of the second inverter IN2 is connected to the ground line. The input terminal of the second inverter IN2 is connected to the output signal line of the first inverter IN1. The second inverter IN2 applies an inverted-phase square wave signal, obtained by inverting the phase of the square wave signal supplied from the first inverter IN1, as the clock voltage to the low-side terminal of the second flying capacitor Cf2.

[0042] The second series resistor Rs2 is connected to a low-voltage control power line that connects the high-side potential of the second DC power supply to the high-side reference potential of the second inverter IN2. The second bypass capacitor Cb2 is connected between the second connection point N2 between the second series resistor Rs2 and the high-side reference potential of the second inverter IN2, and the ground line. The second series resistor Rs2 and the second bypass capacitor Cb2 constitute a low-pass filter.

[0043] A second voltage dividing resistor Rd2 and a second voltage dividing switch SW2 are connected in series between the second connection point N2 and the ground line. An N-channel type semiconductor switch is used for the second voltage dividing switch SW2. In the example shown in Fig. 3, an N-channel MOSFET is used. The source terminal of the second voltage dividing switch SW2 is connected to the ground line, the drain terminal is connected to the second voltage dividing resistor Rd2, and the gate terminal is connected to the input terminal of the second inverter IN2.

[0044] A second square wave signal output from the first inverter IN1 and having a phase opposite to that of the first square wave signal is input to the input terminal of the second inverter IN2. Note that the second square wave signal input to the input terminal of the second inverter IN2 may be generated by inverting the first square wave signal generated by the control circuit 40 or an oscillator by another inverter other than the first inverter IN1.

[0045] The second voltage dividing switch SW2 is conductive during a period when the second square wave signal is at a high level, and the second voltage dividing resistor Rd2 becomes enabled. The second voltage dividing switch SW2 is cut off during a period when the second square wave signal is at a low level, and the second voltage dividing resistor Rd2 becomes disabled. During a period when the second voltage dividing resistor Rd2 is enabled, the second series resistor Rs2 and the second voltage dividing resistor Rd2 constitute a resistance voltage dividing circuit, and the voltage at the second connection point N2 is a voltage obtained by dividing the second power supply voltage VDD by the voltage dividing ratio of the second series resistor Rs2 and the second voltage dividing resistor Rd2.

[0046] Fig. 4 is a diagram schematically showing a transient waveform of the high-side voltage HV, the output voltage V1 of the first inverter IN1, and the output voltage V2 of the second inverter IN2. As described above, in the comparative example, ripples occur in the high-side voltage HV due to the consumption current and leakage current of the gate drive circuit 10. If the high-side voltage HV drops due to the consumption current and leakage current of the gate drive circuit 10, the output voltage V1 of the first inverter IN1 during the transfer period of the first flying capacitor Cf1 and the output voltage V2 of the second inverter IN2 during the transfer period of the second flying capacitor Cf2 may be transiently increased so as to offset the voltage drop. This can suppress fluctuations due to ripples in the high-side voltage HV.

[0047] In this embodiment, at the start of the transfer period of the first flying capacitor Cf1, the output voltage V1 of the first inverter IN1 is lowered below the second power supply voltage VDD by resistance division of the first series resistor Rs1 and the first voltage dividing resistor Rd1. After the start of the transfer period, the first voltage dividing switch SW1 is controlled to gradually increase the output voltage V1 of the first inverter IN1 up to the second power supply voltage VDD. The first inverter IN1 generates a first shaped clock voltage V1 based on a first rectangular wave signal, and applies the generated voltage to the low-side terminal of the first flying capacitor Cf1.

[0048] Similarly, at the start of the transfer period of the second flying capacitor Cf2, the output voltage V2 of the second inverter IN2 is lowered below the second power supply voltage VDD by resistance division of the second series resistor Rs2 and the second voltage dividing resistor Rd2. After the start of the transfer period, the second voltage dividing switch SW2 is controlled to gradually increase the output voltage V2 of the second inverter IN2 up to the second power supply voltage VDD. The second inverter IN2 generates a second shaped clock voltage V2 based on a second rectangular wave signal that is opposite in phase to the first rectangular wave signal, and applies the generated voltage to the low-side terminal of the second flying capacitor Cf2.

[0049] A more specific description will be given below. In the charging period of the first flying capacitor Cf1, the first rectangular wave signal becomes high level, so the first voltage dividing switch SW1 is turned on, and the first voltage dividing resistor Rd1 is enabled. Therefore, the high-side reference potential of the first inverter IN1 is the voltage at a first connection point N1 obtained by dividing the second power supply voltage VDD according to the voltage division ratio of the first series resistor Rs1 and the first voltage dividing resistor Rd1. The clock voltage V1 output from the first inverter IN1 is at a low level and becomes the ground voltage.

[0050] When the first flying capacitor Cf1 switches from the charging phase to the transfer phase, the first square wave signal transitions to a low level, causing the first voltage divider switch SW1 to turn off and the first voltage divider resistor Rd1 to become inactive. Consequently, the high-side reference potential of the first inverter IN1 rises to the second power supply voltage VDD, depending on the time constants of the first series resistor Rs1 and the first bypass capacitor Cb1. The clock voltage V1 output from the first inverter IN1 is linked to the rise in the high-side reference potential of the first inverter IN1.

[0051] The time constants of the first series resistor Rs1 and the first bypass capacitor Cb1 are set so that they match the time constants of the resistance component corresponding to the current consumption and leakage current of the gate drive circuit 10 and the output holding capacitor Co. The values ​​of the resistance component corresponding to the current consumption and leakage current of the gate drive circuit 10 can be determined by experiment or simulation.

[0052] The initial value of the high-side reference potential of the first inverter IN1 at the start of the transfer period of the first flying capacitor Cf1 can be determined from the second power supply voltage VDD, the unit transfer period time, and the time constant curves of the first series resistor Rs1 and the first bypass capacitor Cb1. Based on the determined initial value of the high-side reference potential of the first inverter IN1, the voltage division ratio of the first series resistor Rs1 and the first voltage divider resistor Rd1 is determined, and the constant of the first voltage divider resistor Rd1 is determined based on the voltage division ratio and the constant of the first series resistor Rs1.

[0053] During the charging period of the second flying capacitor Cf2, the second square wave signal becomes high level, causing the second voltage divider switch SW2 to turn on and the second voltage divider resistor Rd2 to become active. Therefore, the high-side reference potential of the second inverter IN2 is the voltage at the second connection point N2, which is obtained by dividing the second power supply voltage VDD by the voltage division ratio of the second series resistor Rs2 and the second voltage divider resistor Rd2. The clock voltage V2 output from the second inverter IN2 is low level and becomes the ground voltage.

[0054] When the second flying capacitor Cf2 switches from the charging phase to the transfer phase, the second square wave signal transitions to a low level, causing the second voltage divider switch SW2 to turn off and the second voltage divider resistor Rd2 to become inactive. Consequently, the high-side reference potential of the second inverter IN2 rises to the second power supply voltage VDD, depending on the time constants of the second series resistor Rs2 and the second bypass capacitor Cb2. The clock voltage V2 output from the second inverter IN2 is linked to the rise in the high-side reference potential of the second inverter IN2.

[0055] The constants of the second series resistor Rs2, the second bypass capacitor Cb2, and the second voltage divider resistor Rd2 should basically be set to the same values ​​as the constants of the first series resistor Rs1, the first bypass capacitor Cb1, and the first voltage divider resistor Rd1.

[0056] The first flying capacitor Cf1 and the second flying capacitor Cf2 alternately supply charge to the high-voltage control power line, thereby eliminating ripple in the high-side voltage HV.

[0057] As described above, according to this embodiment, by boosting the voltages of the first flying capacitor Cf1 and the second flying capacitor Cf2 with transient inverted phase voltages, the current consumption of the gate drive circuit 10 and the ripple noise caused by the leakage current can be canceled out. This makes it possible to keep the gate voltage of the semiconductor switch Q1 constant and suppress noise superimposed on the main power line.

[0058] In this embodiment, there is no need to increase the capacitance of the expensive high-voltage flying capacitor Cf1 and output holding capacitor Co; it is sufficient to simply add an inexpensive low-voltage RC low-pass filter, voltage divider resistor, and N-channel MOSFET. Furthermore, since there is no need to make the charge clock excessively fast, the increase in current consumption is also suppressed. As a result, the ripple noise generated when generating the gate voltage of the semiconductor switch Q1 using the charge pump circuit 20 can be suppressed at low cost and with low current consumption.

[0059] The present disclosure has been described above based on embodiments. The embodiments are illustrative, and it will be understood by those skilled in the art that various modifications are possible in combinations of their components and processing processes, and that such modifications are also within the scope of the present disclosure.

[0060] In the embodiment described above, the drive circuit 1 for the semiconductor switch Q1 for charging the battery pack 2 was explained, but the drive circuit for the semiconductor switch for discharging the battery pack 2 can be configured in the same way as the drive circuit 1 for the semiconductor switch Q1 for charging. In that case, the position of the main power line to which the gate drive circuit 10 and the charge pump circuit 20 are connected is set to be on the load side of the semiconductor switch for discharging.

[0061] In the embodiments described above, the battery pack 2 is assumed to be used for automotive applications, but this disclosure is also applicable when the battery pack 2 is used for other applications. For example, it is also applicable when it is used as a backup power supply for a data center.

[0062] The embodiments may be specified by the following items.

[0063] [Item 1] A drive circuit (1) comprising: a gate drive circuit (10) that generates the gate voltage of an N-channel semiconductor switch (Q1) for turning on / off a main power line connected to a first DC power supply (2); a charge pump circuit (20) that generates a high-side reference potential of the gate drive circuit (10) whose low-side reference potential is connected to the main power line; and a clock generation circuit (30) that generates a clock voltage for driving the charge pump circuit (20) using the voltage of a second DC power supply, the voltage of which is greater than that of the first DC power supply (2), wherein the clock generation circuit (30) generates a clock voltage that is shaped to have a waveform with the opposite phase to the phase of the ripple generated at the high-side reference potential. According to this, ripple noise generated when generating the gate voltage of the semiconductor switch (Q1) can be reduced at low cost.[Item 2] The charge pump circuit (20) includes: an output holding capacitor (Co) connected between a high-voltage control power supply line and the main power supply line for supplying the high-side reference potential to the gate drive circuit (10); a first diode (D1) whose cathode terminal is connected to the high-side terminal of the output holding capacitor (Co); a first constant voltage source (ZD1) connected between the anode terminal of the first diode (D1) and the main power supply line; a first flying capacitor (Cf1) whose high-side terminal is connected to the anode terminal of the first diode (D1); a second diode (D2) whose cathode terminal is connected to the high-side terminal of the output holding capacitor (Co); a second constant voltage source (ZD2) connected between the anode terminal of the second diode (D2) and the main power supply line; and a second flying capacitor (Cf2) whose high-side terminal is connected to the anode terminal of the second diode (D2). The clock generation circuit (30) includes: The drive circuit (1) according to item 1 comprises: a first clock generation unit (31) that generates a first shaped clock voltage applied to the low-side terminal of the first flying capacitor (Cf1); and a second clock generation unit (32) that generates a second shaped clock voltage applied to the low-side terminal of the second flying capacitor (Cf2) that is phase-shifted with respect to the first shaped clock voltage. With this, when one of the first flying capacitor (Cf1) and the second flying capacitor (Cf2) is in the charging period, ripple noise can be removed by the shaped boosted voltage of the other, and ripple noise can be removed over the entire period.[Item 3] The first clock generation unit (31) includes: a first inverter (IN1); a first series resistor (Rs1) connected to a low-voltage control power line connecting the high-side potential of the second DC power supply and the high-side reference potential of the first inverter (IN1); a first bypass capacitor (Cb1) connected between a first connection point between the first series resistor (Rs1) and the high-side reference potential of the first inverter (IN1) and the low-side potential of the second DC power supply; a first voltage divider resistor (Rd1) connected between the first connection point and the low-side potential of the second DC power supply; and a first voltage divider switch (SW1) connected in series with the first voltage divider resistor (Rd1). The second clock generation unit (32) includes: a second inverter (IN2); a second series resistor (Rs2) connected to a low-voltage control power line connecting the high-side potential of the second DC power supply and the high-side reference potential of the second inverter (IN2). The drive circuit (1) described in item 2 comprises: a second connection point between the second series resistor (Rs2) and the high-side reference potential of the second inverter (IN2) and a second bypass capacitor (Cb2) connected between the second connection point and the low-side potential of the second DC power supply; a second voltage divider resistor (Rd2) connected between the second connection point and the low-side potential of the second DC power supply; and a second voltage divider switch (SW2) connected in series with the second voltage divider resistor (Rd2), wherein the first inverter (IN1) generates the first shaped clock voltage based on the input first square wave signal and applies it to the low-side terminal of the first flying capacitor (Cf1); and the second inverter (IN2) generates the second shaped clock voltage based on the second square wave signal which is out of phase with the first square wave signal and applies it to the low-side terminal of the second flying capacitor (Cf2). According to this, a shaped clock voltage for canceling out ripple noise can be generated using a simple circuit.[Item 4] The drive circuit (1) described in Item 3, wherein the first voltage divider switch (SW1) is an N-channel semiconductor switch to which the first rectangular wave signal is input to the gate terminal, and the second voltage divider switch (SW2) is an N-channel semiconductor switch to which the second rectangular wave signal is input to the gate terminal. With this, the timing at which the high-side reference potential of the first inverter (IN1) starts to rise and the timing at which the high-side reference potential of the second inverter (IN2) starts to rise can be defined with high precision.

[0064] This disclosure can be used in a drive circuit for driving a semiconductor switch.

[0065] 2 Battery pack, 1 Drive circuit, 10 Gate drive circuit, 20 Charge pump circuit, 30 Clock generation circuit, 31 First clock generation unit, 32 Second clock generation unit, 40 Control circuit, Q1 Semiconductor switch, Co Output holding capacitor, D1 First output holding diode, D2 Second output holding diode, ZD1 First Zener diode, ZD2 Second Zener diode, Cf1 First flying capacitor, Cf2 Second flying capacitor, IN1 First inverter, IN2 Second inverter, Rs1 First series resistor, Rs2 Second series resistor, Rd1 First voltage divider resistor, Rd2 Second voltage divider resistor, Cb1 First bypass capacitor, Cb2 Second bypass capacitor, SW1 First voltage divider switch, SW2 Second voltage divider switch.

Claims

1. A drive circuit comprising: a gate drive circuit that generates the gate voltage of an N-channel semiconductor switch for turning on / off a main power line connected to a first DC power supply; a charge pump circuit that generates the high-side reference potential of the gate drive circuit, the low-side reference potential of which is connected to the main power line; and a clock generation circuit that generates a clock voltage for driving the charge pump circuit using the voltage of a second DC power supply having a lower voltage than the first DC power supply, wherein the clock generation circuit generates a clock voltage shaped to have a waveform with the opposite phase to the ripple occurring at the high-side reference potential.

2. The charge pump circuit includes: an output holding capacitor connected between a high-voltage control power supply line and the main power supply line for supplying the high-side reference potential to the gate drive circuit; a first diode with its cathode terminal connected to the high-side terminal of the output holding capacitor; a first constant voltage source connected between the anode terminal of the first diode and the main power supply line; a first flying capacitor with its high-side terminal connected to the anode terminal of the first diode; a second diode with its cathode terminal connected to the high-side terminal of the output holding capacitor; a second constant voltage source connected between the anode terminal of the second diode and the main power supply line; and a second flying capacitor with its high-side terminal connected to the anode terminal of the second diode. The clock generation circuit includes: a first clock generation unit that generates a first shaped clock voltage to be applied to the low-side terminal of the first flying capacitor; The drive circuit according to claim 1, further comprising: a second clock generation unit that generates a second shaped clock voltage which is phase-shifted with respect to the first shaped clock voltage and is applied to the low-side terminal of the second flying capacitor.

3. The first clock generation unit includes a first inverter, a first series resistor connected to a low-voltage control power line connecting the high-side potential of the second DC power supply and the high-side reference potential of the first inverter, a first bypass capacitor connected between a first connection point between the first series resistor and the high-side reference potential of the first inverter and the low-side potential of the second DC power supply, a first voltage divider resistor connected between the first connection point and the low-side potential of the second DC power supply, and a first voltage divider switch connected in series with the first voltage divider resistor. The second clock generation unit includes a second inverter, a second series resistor connected to a low-voltage control power line connecting the high-side potential of the second DC power supply and the high-side reference potential of the second inverter, a second bypass capacitor connected between a second connection point between the second series resistor and the high-side reference potential of the second inverter and the low-side potential of the second DC power supply, The drive circuit according to claim 2, comprising: a second voltage divider resistor connected between the second connection point and the low-side potential of the second DC power supply; and a second voltage divider switch connected in series with the second voltage divider resistor, wherein the first inverter generates a first shaped clock voltage based on a first square wave signal input and applies it to the low-side terminal of the first flying capacitor; and the second inverter generates a second shaped clock voltage based on a second square wave signal that is out of phase with the first square wave signal and applies it to the low-side terminal of the second flying capacitor.

4. The drive circuit according to claim 3, wherein the first voltage divider switch is an N-channel semiconductor switch to which the first rectangular wave signal is input at its gate terminal, and the second voltage divider switch is an N-channel semiconductor switch to which the second rectangular wave signal is input at its gate terminal.

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