Silicon wafer bonding method and element

Abstract

In this method for bonding a silicon wafer 40, the silicon wafer 40 and a quartz wafer 50 are cooled in a cooling step (step S6) so that the silicon wafer 40 can be divided along a cross section along a virtual plane P on which a modified part 12 is formed, without damaging the quartz wafer 50.

Description

Silicon wafer bonding method and element

[0001] The present invention relates to a silicon wafer bonding method for bonding a silicon wafer and a wafer to be bonded, and an element.

[0002] Conventionally, a silicon wafer bonding method for bonding a silicon wafer and a wafer to be bonded is known (see, for example, Patent Document 1).

[0003] The above Patent Document 1 discloses a method for manufacturing an angular velocity sensor including a step of bonding a silicon wafer and glass (a wafer to be bonded). The silicon wafer and the glass are bonded by anodic bonding.

[0004] Japanese Patent Laying-Open No. 2010-143792

[0005] However, although not explicitly stated in the above Patent Document 1, the coefficient of thermal expansion of a silicon wafer and the coefficient of thermal expansion of glass may differ from each other. In this case, thermal stress is generated in the silicon wafer and the glass due to a difference in the degree of shrinkage during cooling after bonding in a heated state. Then, cracks are generated due to the thermal stress, and the silicon wafer and the glass (wafer to be bonded) may be broken at unintended positions. Therefore, even when the coefficient of thermal expansion of the silicon wafer and the coefficient of thermal expansion of the wafer to be bonded are different, there is a demand for a silicon wafer bonding method capable of suppressing damage caused by cracks generated at unintended positions in the silicon wafer and the wafer to be bonded when the silicon wafer and the wafer to be bonded are bonded in a heated state.

[0006] The present invention has been made to solve the above problems, and one object of the present invention is to provide a silicon wafer bonding method and an element capable of suppressing damage caused by cracks generated at unintended positions in a silicon wafer and a wafer to be bonded when the silicon wafer and the wafer to be bonded are bonded in a heated state, even when the coefficient of thermal expansion of the silicon wafer and the coefficient of thermal expansion of the wafer to be bonded are different from each other.

[0007] To achieve the above objective, the silicon wafer joining method according to the first aspect of this invention comprises: a modified portion forming step of irradiating a silicon wafer having at least one first main surface with a laser to form a modified portion along a virtual plane perpendicular to the first main surface; a silicon wafer heating step of heating the silicon wafer; a wafer to be joined heating step of heating a wafer to be joined having a thermal expansion coefficient different from that of the silicon wafer and having at least one second main surface; a wafer joining step of joining the heated silicon wafer and the wafer to be joined in parallel with the first main surface and the second main surface facing each other; and a cooling step of cooling the silicon wafer and the wafer to be joined, wherein by cooling the silicon wafer and the wafer to be joined in the cooling step, the silicon wafer is divided along a cross section along the virtual plane on which the modified portion was formed without damaging the wafer to be joined.

[0008] In the silicon wafer joining method according to the first aspect of this invention, as described above, by cooling the silicon wafer and the wafer to be joined during the cooling process, the silicon wafer is divided along a cross section that follows the virtual plane on which the modified portion is formed, without damaging the wafer to be joined. As a result, the silicon wafer is divided at the intended position along the cross section that follows the virtual plane on which the modified portion is formed, so that cracks do not occur and damage occurs in the silicon wafer and the wafer to be joined at positions other than the cross section that follows the virtual plane on which the modified portion is formed (unintended positions). As a result, even if the thermal expansion coefficients of the silicon wafer and the wafer to be joined are different, when joining the silicon wafer and the wafer to be joined while heated, it is possible to join the silicon wafer and the wafer to be joined while suppressing damage caused by cracks occurring in unintended positions.

[0009] In the silicon wafer bonding method according to the first surface described above, preferably, the modified portion is formed along a plurality of virtual planes, and the plurality of cross-sections along the plurality of virtual planes on the silicon wafer are orthogonal to each other. With this configuration, it is possible to suppress the occurrence of unintended cracks caused by shrinkage in multiple directions that are along the first main surface and the second main surface and are orthogonal to each other. Furthermore, because the plurality of cross-sections on the silicon wafer are orthogonal to each other, it is possible to easily divide the silicon wafer into a plurality of rectangular pieces. As a result, the step of dividing the silicon wafer into a plurality of rectangular pieces in a subsequent process can be reduced.

[0010] In this case, preferably, the multiple cross-sections of the silicon wafer include cross-sections that are orthogonal to each other and cross-sections that are parallel to each other, and the multiple parallel cross-sections are arranged at equidistant intervals. With this configuration, multiple square-shaped pieces can be easily divided from the silicon wafer. As a result, compared to the case where the pieces are rectangular in shape, the shrinkage and thermal stress after fragmentation are equal in the directions that are orthogonal to each other, so the occurrence of cracks can be suppressed more effectively.

[0011] In the silicon wafer bonding method according to the first aspect described above, preferably, the modified portion is formed along a virtual plane extending along the cleavage surface of the silicon wafer, and in the cooling step, by cooling the silicon wafer and the wafer to be bonded, the silicon wafer is cleaved along the cross section along the virtual plane on which the modified portion is formed, thereby dividing it. With this configuration, the silicon wafer can be easily divided along the cross section along the virtual plane on which the modified portion is formed by cleaving it. Furthermore, since the divided surface of the silicon wafer can be easily smoothed by cleaving, the step of smoothing the divided surface of the silicon wafer in a subsequent process can be reduced.

[0012] In this case, preferably, the modified portion is formed along a virtual plane extending along the (110) plane in the silicon wafer crystal. Here, the (110) plane in the silicon wafer crystal is along the cleavage plane of the silicon wafer. Therefore, if the modified portion is formed along a virtual plane extending along the (110) plane in the silicon wafer crystal, it can be easily divided by cleaving the silicon wafer.

[0013] In the silicon wafer joining method according to the first aspect described above, preferably, the wafer to be joined has a thermal expansion coefficient smaller than that of the silicon wafer, and the fracture stress, which is the stress at the moment of fracture of the wafer to be joined, is smaller than the fracture stress of the silicon wafer. With this configuration, it is possible to easily join a silicon wafer and a wafer to be joined without damaging the wafer to be joined, as the wafer to be joined has a thermal expansion coefficient smaller than that of the silicon wafer and a fracture stress smaller than that of the silicon wafer.

[0014] In this case, preferably, the wafer to be bonded is a quartz wafer. With this configuration, a silicon wafer and a quartz wafer can be easily bonded without damaging the quartz wafer.

[0015] In the silicon wafer bonding method according to the first aspect described above, preferably, after the cooling step, a fragmentation step is further provided in which the bonded wafer, in the bonded state with the silicon wafer, is divided along the dividing lines of the silicon wafer to be fragmented into individual elements. With this configuration, the dividing lines of the silicon wafer used to suppress damage to the bonded wafer can be used as dividing lines for fragmentation.

[0016] In the silicon wafer joining method according to the first surface described above, preferably, in the modified portion formation step, the modified portion is formed along a virtual plane such that there is one modified portion aligned in a direction perpendicular to the first main surface of the silicon wafer. In general stealth dicing, the modified portion is formed along a virtual plane such that there are multiple modified portions aligned in a direction perpendicular to the first main surface of the silicon wafer. Therefore, by forming the modified portion along a virtual plane such that there is one modified portion aligned in a direction perpendicular to the first main surface of the silicon wafer, the fracture load, which is the load at the moment of fracture of the cross section along the virtual plane on which the modified portion is formed in the silicon wafer, can be increased compared to general stealth dicing. As a result, it is possible to suppress the unintentional division of the silicon wafer when transporting the silicon wafer with the modified portion formed.

[0017] In the silicon wafer joining method according to the first aspect described above, preferably, the fracture stress, which is the stress at the moment of fracture in the modified portion of the silicon wafer, is smaller than the fracture stress in other parts of the silicon wafer. With this configuration, when the silicon wafer is divided, it is divided along the cross-section including the modified portion. As a result, the silicon wafer can be easily divided along a cross-section that aligns with the virtual plane in which the modified portion is formed.

[0018] In this case, preferably, the fracture load, which is the load at the moment of fracture of the cross-section along the virtual plane in which the modified portion is formed on the silicon wafer, is smaller than the fracture load of the cross-section along the virtual plane on the bonded wafer joined to the silicon wafer. With this configuration, when thermal stress is generated in the silicon wafer and the bonded wafer due to the difference in the degree of shrinkage during cooling between the silicon wafer and the bonded wafer, the silicon wafer is separated first, so the silicon wafer can be easily separated along the cross-section along the virtual plane in which the modified portion is formed. As a result, the silicon wafer and the bonded wafer can be joined without damaging the bonded wafer, which has a smaller fracture load than the silicon wafer.

[0019] The element according to the second aspect of this invention comprises a rectangular silicon substrate and a rectangular quartz substrate joined to the silicon substrate in parallel with their respective main surfaces facing each other. The four sides of the silicon substrate include modified portions having a fracture stress smaller than the fracture stress, which is the stress at the moment of fracture of the other parts of the silicon substrate. The fracture load, which is the load at the moment of fracture of the sides of the quartz substrate, is smaller than the fracture load of the parts of the silicon substrate other than the four sides including the modified portions. The fracture load of the four sides of the silicon substrate including the modified portions is smaller than the fracture load of the corresponding sides of the quartz substrate. The four sides of the quartz substrate do not include modified portions and have a homogeneous surface.

[0020] In the device according to the second aspect of this invention, as described above, the four sides of the silicon substrate include modified portions having a fracture stress smaller than the fracture stress, which is the stress at the moment of fracture of other parts of the silicon substrate; the fracture load, which is the load at the moment of fracture of the sides of the quartz substrate, is smaller than the fracture load of parts of the silicon substrate other than the four sides including the modified portions; the fracture load of the four sides of the silicon substrate including the modified portions is smaller than the fracture load of the corresponding sides of the quartz substrate; and the four sides of the quartz substrate do not include modified portions and have a homogeneous surface. As a result, when the silicon wafer and the quartz wafer are joined and cooled while heated during the manufacturing of the device, the silicon wafer is divided at the intended position along the cross section (side of the silicon substrate) along the modified portion, thereby suppressing the occurrence of cracks and damage to the silicon wafer and quartz wafer at positions other than the sides of the silicon substrate (unintended positions).

[0021] According to the present invention, as described above, even when the thermal expansion coefficient of the silicon wafer and the wafer to be bonded are different, it is possible to suppress damage to the silicon wafer and the wafer to be bonded due to the occurrence of cracks at unintended locations when bonding the silicon wafer and the wafer to be bonded while they are heated.

[0022] This is a perspective view of a semiconductor chip according to one embodiment of the present invention. This is an exploded perspective view of a semiconductor chip according to one embodiment of the present invention. This is an enlarged side view of a semiconductor chip according to one embodiment of the present invention. This is a flowchart showing a silicon wafer bonding method according to one embodiment of the present invention. This is a perspective view of a silicon wafer according to one embodiment of the present invention. This is a plan view of a silicon wafer for explaining a virtual plane according to one embodiment of the present invention. This is a cross-sectional view of a silicon wafer along a virtual plane P for explaining a modified part according to one embodiment of the present invention. This is a plan view of a silicon wafer on which an element function part has been formed according to one embodiment of the present invention. This is a perspective view of a quartz wafer according to one embodiment of the present invention. This is a plan view of a quartz wafer according to one embodiment of the present invention. This is a cross-sectional view along the line XI-XI in Figure 8 showing the silicon wafer bonding process corresponding to the flowchart in Figure 4 ((a), (b): corresponding to step S5, (c): corresponding to step S6, (d): corresponding to step S7). This is a diagram for explaining a modified part according to a modified example of one embodiment of the present invention.

[0023] Hereinafter, an embodiment of the present invention will be described based on the drawings.

[0024] (Configuration of the semiconductor chip) The configuration of the semiconductor chip 1 according to this embodiment will be described with reference to Figures 1 to 3. Note that the semiconductor chip 1 is an example of the "element" in the claims.

[0025] As shown in Figure 1, the semiconductor chip 1 comprises a silicon substrate 10, a quartz substrate 20, and a bonding material 30. In the drawing, the thickness direction of the semiconductor chip 1 is defined as the Z direction. Within the Z direction, the upward direction is defined as the Z1 direction, and the downward direction is defined as the Z2 direction.

[0026] The silicon substrate 10 is made of single-crystal silicon. As shown in Figure 2, the silicon substrate 10 has a rectangular shape. Specifically, the silicon substrate 10 has a square shape. As shown in Figure 2, the silicon substrate 10 has two parallel main surfaces 10a and 10b. The main surfaces 10a and 10b extend in a direction perpendicular to the thickness direction (Z direction) of the silicon substrate 10. As shown in Figure 2, the main surface 10a is located on the upper surface (Z1 side) of the silicon substrate 10, and the main surface 10b is located on the lower surface (Z2 side) of the silicon substrate 10. Also, as shown in Figure 2, the element function section 11 is located on the upper surface (main surface 10a) of the silicon substrate 10. The element function section 11 includes, for example, an integrated circuit (IC).

[0027] The quartz substrate 20 is made of quartz. As shown in Figure 2, the quartz substrate 20 has a rectangular shape. Specifically, the quartz substrate 20 has a square shape. As shown in Figure 2, the quartz substrate 20 has two parallel main surfaces 20a and 20b. The main surfaces 20a and 20b extend in a direction perpendicular to the thickness direction (Z direction) of the quartz substrate 20. As shown in Figure 2, the main surface 20a is located on the upper surface (Z1 side) of the quartz substrate 20, and the main surface 20b is located on the lower surface (Z2 side) of the quartz substrate 20.

[0028] Furthermore, the quartz substrate 20 has a smaller coefficient of thermal expansion than the silicon substrate 10. Specifically, the coefficient of thermal expansion of the silicon substrate 10 is approximately 2.6 ppm / °C, while the coefficient of thermal expansion of the quartz substrate 20 is approximately 0.5 ppm / °C.

[0029] As shown in Figures 1 and 2, the bonding material 30 is located between the silicon substrate 10 and the quartz substrate 20, surrounding the functional element 11 from all sides. The silicon substrate 10, bonding material 30, and quartz substrate 20 are stacked in this order. As a result, the functional element 11 is located in the space surrounded by the silicon substrate 10, the quartz substrate 20, and the bonding material 30. In the semiconductor chip 1, the main surface 10a of the silicon substrate 10 and the main surface 20b of the quartz substrate 20 face each other in a parallel state. The bonding material 30 is for bonding the silicon substrate 10 and the quartz substrate 20. The bonding material 30 includes, for example, an AuSn (gold-tin) alloy.

[0030] As shown in Figure 3, multiple modified portions 12 exist on the side surface of the silicon substrate 10. These multiple modified portions 12 are arranged in a line along the direction in which the main surface 10a and main surface 10b extend on the side surface of the silicon substrate 10. Although only a portion of the side surface of the silicon substrate 10 is shown in Figure 3, the multiple modified portions 12 exist continuously from one end to the other along the direction in which the main surface 10a and main surface 10b extend on the side surface of the silicon substrate 10. Furthermore, although only one side surface of the silicon substrate 10 is shown in Figure 3, the multiple modified portions 12 exist similarly on all (four) sides of the silicon substrate 10.

[0031] The modified portion 12 has a fracture stress smaller than the fracture stress, which is the stress at the moment of fracture of the other parts of the silicon substrate 10 (parts other than the modified portion 12). Also, the fracture load, which is the load at the moment of fracture of the side surface of the quartz substrate 20, is smaller than the fracture load of the parts of the silicon substrate 10 other than the four side surfaces including the modified portion 12. Furthermore, the fracture load of the four side surfaces of the silicon substrate 10 including the modified portion 12 is smaller than the fracture load of the corresponding side surfaces of the quartz substrate 20. As shown in Figure 3, the side surface of the quartz substrate 20 does not include the modified portion 12 and has a homogeneous surface. Note that although only a part of the side surface of the quartz substrate 20 is shown in Figure 3, the modified portion 12 does not exist on the entire side surface of the quartz substrate 20. Also, although only one side surface of the quartz substrate 20 is shown in Figure 3, the modified portion 12 does not exist on all (four) side surfaces of the quartz substrate.

[0032] (Method for joining silicon wafers) Next, the method for joining silicon wafers 40 (see Figure 5) according to this embodiment will be described with reference to Figures 4 to 11. Note that the method for joining silicon wafers 40 described below is performed by a control unit of a device not shown. This control unit of the device not shown may differ for each step of the method for joining silicon wafers 40, but in the following, the main component of the method for joining silicon wafers 40 will be described as the "control unit".

[0033] As shown in Figures 4 to 7, in step S1, the control unit forms a modified portion 12 on the silicon wafer 40. Details of step S1 are shown below. As shown in Figure 5, the silicon wafer 40 has a substantially disc shape. In the drawings, the thickness direction of the silicon wafer 40 is the Z direction, the upward direction is the Z1 direction, and the downward direction is the Z2 direction. The silicon wafer 40 is made of single-crystal silicon. As shown in Figure 5, the silicon wafer 40 has two parallel main surfaces 40a and 40b. The main surfaces 40a and 40b extend in directions perpendicular to the thickness direction (Z direction) of the silicon wafer 40. The main surface 40a is located on the upper surface (Z1 side) of the silicon wafer 40, and the main surface 40b is located on the lower surface (Z2 side) of the silicon wafer 40. The main surface 40a is an example of the "first main surface" of the claims.

[0034] Furthermore, as shown in Figure 5, the side surface of the silicon wafer 40 has a planar portion 40c that extends in a direction perpendicular to the main surface 40a and the main surface 40b. This planar portion 40c is a so-called orientation flat. The planar portion 40c, and the plane that extends in the thickness direction (Z direction) of the silicon wafer 40 among the planes perpendicular to the planar portion 40c, extend along the (110) plane in the crystal of the silicon wafer 40. Step S1 is an example of the "modified portion formation process" of the claims.

[0035] Furthermore, in step S1, as shown in Figures 6 and 7, the control unit forms a plurality of modified portions 12 along the virtual plane P. In the drawings, the direction in which the planar portion 40c extends, among the directions perpendicular to the Z direction of the silicon wafer 40, is defined as the X direction. The directions perpendicular to both the X and Z directions of the silicon wafer 40 are defined as the Y direction. One of the X directions is defined as the X1 direction, and the other as the X2 direction. Similarly, one of the Y directions is defined as the Y1 direction, and the other as the Y2 direction.

[0036] Note that the virtual plane P is a virtual plane used to explain the modified portion 12 and does not exist as a physical object. In Figure 6, the virtual plane P is shown as a dashed line and extends along the thickness direction (Z direction) of the silicon wafer 40. In other words, the virtual plane P is a plane that extends in a direction perpendicular to the main surfaces 40a and 40b of the silicon wafer 40 (see Figure 5). As shown in Figure 6, the virtual plane P includes virtual planes P1, P2, P3, P4, P5 and P6 which are parallel to the planar portion 40c, and virtual planes P7, P8, P9, P10, P11 and P12 which are perpendicular to the planar portion 40c. The virtual planes P1 to P12 extend along the (110) plane in the crystal of the silicon wafer 40. Here, the (110) plane in the crystal of the silicon wafer 40 is the cleavage plane of the silicon wafer 40. As described above, the virtual planes P1 to P12 extend along the cleavage plane of the silicon wafer 40.

[0037] As shown in Figure 7, the control unit pulses a laser L along a virtual plane P using a laser irradiation device (not shown) to form multiple modified areas 12 on the silicon wafer 40 along the virtual plane P. In this process, the control unit forms the modified areas 12 while scanning the laser L along the arrows shown in Figure 7. Although Figure 7 only shows a portion of the cross-section of the silicon wafer 40 along the virtual plane P, in reality, the control unit forms multiple modified areas 12 over the entire cross-section of the silicon wafer 40 along the virtual plane P. In this embodiment, as shown in Figure 7, the control unit forms the modified areas 12 such that there is one modified area along the direction (Z direction) perpendicular to the main surfaces 40a and 40b of the silicon wafer 40. Also, as shown in Figure 6, the control unit forms modified areas 12 along multiple virtual planes P (virtual planes P1 to P12). The modified areas 12 are regions that have been thermally processed and modified by the focusing of the laser L. The fracture stress of the modified portion 12, which is the stress at the moment of fracture, is smaller than the fracture stress of other parts of the silicon wafer 40 (other than the modified portion 12).

[0038] In this embodiment, as shown in Figure 6, when viewed from the thickness direction (Z direction) of the silicon wafer 40, the multiple cross-sections along the multiple virtual planes P in the silicon wafer 40 include cross-sections that are orthogonal to each other and cross-sections that are parallel to each other. Furthermore, the multiple parallel cross-sections along the multiple virtual planes P are arranged at equidistant intervals. Here, the parallel cross-sections along the multiple virtual planes P in the silicon wafer 40 are, for example, the cross-sections of the silicon wafer 40 along virtual planes P1 to P6 and the cross-sections of the silicon wafer 40 along virtual planes P7 to P12.

[0039] Next, as shown in Figures 4 and 8, in step S2, the control unit forms the element function portion 11 on the silicon wafer 40. Specifically, the control unit forms the element function portion 11 on the main surface 40a (see Figure 5) of the silicon wafer 40, in a portion surrounded by a plurality of virtual planes P. The element function portion 11 does not overlap with the virtual planes P. In Figure 8, for ease of explanation, the number of element function portions 11 and portions on the main surface 40a of the silicon wafer 40, surrounded by a plurality of virtual planes P, is shown as an example of 21. However, in reality, the number of element function portions 11 and portions on the main surface 40a of the silicon wafer 40, surrounded by a plurality of virtual planes P, is, for example, several thousand.

[0040] Furthermore, in step S2, as shown in Figure 8, the control unit forms a bonding material 30 on the main surface 40a (see Figure 5) of the silicon wafer 40, in a portion surrounded by a plurality of virtual planes P, so as to surround the element functional portion 11. In addition, as shown in Figure 8, the control unit also forms a bonding material 30 on the outer periphery of the main surface 40a of the silicon wafer 40.

[0041] Next, as shown in Figure 4, in step S3, the control unit heats the silicon wafer 40. Specifically, the control unit heats the silicon wafer 40 to, for example, 320°C or higher. At this time, the silicon wafer 40 expands thermally according to its coefficient of thermal expansion. Note that step S3 is an example of the "silicon wafer heating step" within the claims.

[0042] Next, as shown in Figure 4, in step S4, the control unit heats the quartz wafer 50 (see Figure 9), which will be described later. Specifically, the control unit heats the quartz wafer 50 to, for example, 320°C or higher. At this time, the quartz wafer 50 expands thermally according to its coefficient of thermal expansion. As shown in Figure 9, the quartz wafer 50 has approximately the same shape and thickness as the silicon wafer 40 (see Figure 5). In the drawings, the thickness direction of the quartz wafer 50 is the Z direction, the upward direction is the Z1 direction, and the downward direction is the Z2 direction. The quartz wafer 50 is made of quartz. As shown in Figure 9, the quartz wafer 50 has two parallel main surfaces 50a and 50b. The main surfaces 50a and 50b extend in directions perpendicular to the thickness direction (Z direction) of the quartz wafer 50. The main surface 50a is located on the upper surface (Z1 side) of the quartz wafer 50, and the main surface 50b is located on the lower surface (Z2 side) of the quartz wafer 50. Note that the main surface 50b is an example of the "second main surface" in the claims.

[0043] The quartz wafer 50 has a smaller coefficient of thermal expansion than the silicon wafer 40. Specifically, the coefficient of thermal expansion of the silicon wafer 40 is approximately 2.6 ppm / °C, while the coefficient of thermal expansion of the quartz wafer 50 is approximately 0.5 ppm / °C. Furthermore, the fracture stress, which is the stress at the moment of fracture of the quartz wafer 50, is smaller than the fracture stress of the silicon wafer 40. As shown in Figure 10, on the main surface 50b of the quartz wafer 50, there is a bonding material 30 (see Figure 8) formed on the main surface 40a of the silicon wafer 40. Note that the quartz wafer 50 is an example of the "wafer to be bonded" in the claims. Also, step S4 is an example of the "wafer to be bonded heating step" in the claims.

[0044] Next, as shown in FIG. 4, in step S5, the control unit bonds the silicon wafer 40 and the quartz wafer 50. Specifically, first, as shown in FIG. 11(a), the control unit holds the silicon wafer 40 and the quartz wafer 50 with the main surface 40a and the main surface 50b facing each other. At this time, based on an alignment mark (not shown) or the like, the control unit aligns the bonding material 30 of the silicon wafer 40 and the bonding material 30 of the quartz wafer 50 in the thickness direction of the silicon wafer 40 and the quartz wafer 50 After aligning the silicon wafer 40 and the quartz wafer 50 so as to face each other along (Z direction), the wafers are held.

[0045] Then, as shown in FIG. 11(b), the control unit brings the silicon wafer 40 and the quartz wafer 50 relatively close to each other, thereby pressure-bonding the silicon wafer 40 and the quartz wafer 50 via the bonding material 30. At this time, the control unit bonds the silicon wafer 40 and the quartz wafer 50 in parallel with the main surface 40a and the main surface 50b facing each other. In step S5, the control unit bonds the silicon wafer 40 and the quartz wafer 50 while maintaining the heated state in step S3 and step S4. Note that step S5 is an example of the "wafer bonding step" in the claims.

[0046] Next, as shown in FIG. 4, in step S6, the control unit cools the silicon wafer 40 and the quartz wafer 50 bonded in step S5. Specifically, the control unit holds the silicon wafer 40 and the quartz wafer 50 bonded in a heated state in a normal temperature environment to allow natural cooling. At this time, the silicon wafer 40 and the quartz wafer 50 tend to contract by the amount thermally expanded according to their respective thermal expansion coefficients in step S3 and step S4. Note that step S6 is an example of the "cooling step" in the claims.

[0047] In step S6, as the silicon wafer 40 and the quartz wafer 50 are cooled and shrink, thermal stress is generated in the silicon wafer 40 and the quartz wafer 50 due to the difference in the degree of shrinkage between them. As a result of this thermal stress, as shown in Figure 11(c), the silicon wafer 40 is divided along the cross-sections that follow the virtual planes P (virtual planes P8 to P11 in the drawing) where the modified portion 12 is formed. At this time, the quartz wafer 50 is not damaged and is not divided. Note that although Figure 11(c) illustrates the division of the silicon wafer 40 along the cross-sections that follow the virtual planes P8 to P11, in reality, it is divided along the cross-sections that follow all of the virtual planes P (virtual planes P1 to P12).

[0048] Furthermore, in the present embodiment, as described above, the virtual plane P extends along the cleavage plane of the silicon wafer 40. Therefore, in step S6, the silicon wafer 40 is divided by cleaving along a cross-section along the virtual plane P. Then, as shown in FIG. 11(c), among the portions formed by dividing the silicon wafer 40, the portion having the element functional portion 11 on the upper surface (the surface on the Z1 side) is the portion that becomes the aforementioned silicon substrate 10 (see FIG. 1). Further, as shown in FIG. 11(c), the modified portions 12 exist on both of the cross-sections formed by dividing the silicon wafer 40. As a result, the side surface of the silicon substrate 10 includes the modified portion 12. Here, in the present embodiment, as shown in FIG. 11(c), the fracture load, which is the load at the moment of fracture of a cross-section along the virtual plane P (virtual planes P8 to P11 in the drawings) where the modified portion 12 is formed in the silicon wafer 40, is smaller than the fracture load of a cross-section along the virtual plane P (virtual planes P8 to P11 in the drawings) in the quartz wafer 50 bonded to the silicon wafer 40. Therefore, the quartz wafer 50 is not fractured along the virtual plane P, and the silicon wafer 40 is divided at the cross-section along the virtual plane P in the silicon wafer 40. Note that between the silicon wafer 40 and the quartz wafer 50, the silicon wafer 40 has a larger coefficient of thermal expansion. Therefore, during shrinkage, a load in the tensile direction is applied from the quartz wafer 50 to the cross-section along the thickness direction (Z direction) of the silicon wafer 40. Then, among the cross-sections along the thickness direction (Z direction) of the silicon wafer 40, the cross-section along the virtual plane P including the modified portion 12, which has a smaller fracture stress than other portions, fractures before other portions.

[0049] Next, as shown in Figure 4, in step S7, the control unit breaks the bonded silicon wafer 40 and quartz wafer 50 into smaller pieces. Specifically, as shown in Figure 11(d), after step S6, the control unit breaks the quartz wafer 50, which is bonded to the silicon wafer 40, into smaller pieces for each semiconductor chip 1 (element) by dividing it along the dividing line (virtual plane P) of the silicon wafer 40. At this time, the control unit divides the quartz wafer 50 with a blade or the like. Note that step S7 is an example of the "piece breaking process" in the claims. After the completion of step S7, the method for bonding the silicon wafer 40 is completed.

[0050] (Effects of the Embodiment) Next, the effects of this embodiment will be described.

[0051] In this embodiment, as described above, by cooling the silicon wafer 40 and the quartz wafer 50 in the cooling process (step S6), the silicon wafer 40 is divided along the cross-section parallel to the virtual plane P on which the modified portion 12 is formed, without damaging the quartz wafer 50. As a result, the silicon wafer 40 is divided at the intended position along the cross-section parallel to the virtual plane P on which the modified portion 12 is formed, thus preventing cracks from occurring and damaging the silicon wafer 40 and the quartz wafer 50 at positions other than the cross-section parallel to the virtual plane P on which the modified portion 12 is formed (unintended positions). Consequently, even if the thermal expansion coefficient of the silicon wafer 40 and the thermal expansion coefficient of the wafer to be bonded are different, the silicon wafer 40 and the wafer to be bonded can be bonded while preventing cracks from occurring and damaging the silicon wafer 40 and the wafer to be bonded at unintended positions.

[0052] Furthermore, in this embodiment, as described above, the modified portion 12 is formed along a plurality of virtual planes P, and the plurality of cross-sections along the plurality of virtual planes P in the silicon wafer 40 are orthogonal to each other. This makes it possible to suppress the occurrence of unintended cracks caused by shrinkage in multiple directions that are orthogonal to each other, along the main surfaces 40a, 40b, 50a, and 50b. In addition, because the plurality of cross-sections in the silicon wafer 40 are orthogonal to each other, the silicon wafer 40 can be easily divided into a plurality of rectangular pieces. As a result, the step of dividing the silicon wafer 40 into a plurality of rectangular pieces in a subsequent process can be reduced.

[0053] Furthermore, in this embodiment, as described above, the multiple cross-sections of the silicon wafer 40 include cross-sections that are orthogonal to each other and cross-sections that are parallel to each other, and the multiple parallel cross-sections are arranged at equidistant intervals. This makes it easy to divide the silicon wafer 40 into multiple square-shaped small pieces (silicon substrates 10). As a result, compared to the case where the small pieces are rectangular in shape, the shrinkage and thermal stress after fragmentation are equal in the directions that are orthogonal to each other, so the occurrence of cracks can be suppressed more effectively.

[0054] Furthermore, in this embodiment, as described above, the modified portion 12 is formed along a virtual plane P extending along the cleavage surface of the silicon wafer 40, and in the cooling process (step S6), by cooling the silicon wafer 40 and the quartz wafer 50, the silicon wafer 40 is cleaved and divided along the cross-section along the virtual plane P on which the modified portion 12 is formed. As a result, by cleaving the silicon wafer 40, it is possible to easily divide it along the cross-section along the virtual plane P on which the modified portion 12 is formed. In addition, since the divided surface of the silicon wafer 40 can be easily smoothed by cleaving, the step of smoothing the divided surface of the silicon wafer 40 in a subsequent process can be reduced.

[0055] Furthermore, in this embodiment, as described above, the modified portion 12 is formed along a virtual plane P that extends along the (110) plane in the crystal of the silicon wafer 40. This allows the silicon wafer 40 to be easily cleaved and divided.

[0056] Furthermore, in this embodiment, as described above, the quartz wafer 50 has a thermal expansion coefficient smaller than that of the silicon wafer 40, and the fracture stress, which is the stress at the moment of fracture of the quartz wafer 50, is smaller than the fracture stress of the silicon wafer 40. As a result, the silicon wafer 40 and the quartz wafer 50 can be easily joined without damaging the quartz wafer 50, which has a thermal expansion coefficient smaller than that of the silicon wafer 40 and a fracture stress smaller than that of the silicon wafer 40.

[0057] Furthermore, in this embodiment, as described above, after the cooling step (step S6), a fragmentation step (step S7) is included in which the quartz wafer 50, which is bonded to the silicon wafer 40, is divided along the dividing lines of the silicon wafer 40 to form small pieces for each element. This makes it possible to use the dividing lines of the silicon wafer 40, which are used to suppress damage to the quartz wafer 50, as dividing lines for fragmentation.

[0058] Furthermore, in this embodiment, as described above, in the modified portion formation step (step S1), the control unit forms the modified portion 12 along a virtual plane P such that there is one modified portion aligned in a direction perpendicular to the main surface 40a and main surface 40b of the silicon wafer 40. This makes it possible to increase the fracture load, which is the load at the moment of fracture of the cross section of the silicon wafer 40 along the virtual plane P on which the modified portion 12 is formed, compared to general stealth dicing. As a result, it is possible to suppress the unintentional division of the silicon wafer 40 when transporting the silicon wafer 40 with the modified portion 12 formed on it.

[0059] Furthermore, in this embodiment, as described above, the fracture stress, which is the stress at the moment of fracture in the modified portion 12 of the silicon wafer 40, is smaller than the fracture stress in other parts of the silicon wafer 40. As a result, when the silicon wafer 40 is divided, it is divided along the cross-section including the modified portion 12. Consequently, the silicon wafer 40 can be easily divided along a cross-section that aligns with the virtual plane P on which the modified portion 12 is formed.

[0060] Furthermore, in this embodiment, as described above, the fracture load, which is the load at the moment of fracture of the cross-section of the silicon wafer 40 along the virtual plane P on which the modified portion 12 is formed, is smaller than the fracture load of the cross-section of the quartz wafer 50 joined to the silicon wafer 40 along the virtual plane P. As a result, when thermal stress is generated in the silicon wafer 40 and the quartz wafer 50 due to the difference in the degree of shrinkage during cooling between the silicon wafer 40 and the quartz wafer 50, the silicon wafer 40 is separated first, so the silicon wafer 40 can be easily separated along the cross-section of the virtual plane P on which the modified portion 12 is formed. As a result, the silicon wafer 40 and the quartz wafer 50 can be joined without damaging the quartz wafer 50, which has a smaller fracture load than the silicon wafer 40.

[0061] Furthermore, in this embodiment, as described above, the four sides of the silicon substrate 10 include modified portions 12 having a fracture stress smaller than the fracture stress, which is the stress at the moment of fracture of other parts of the silicon substrate 10. The fracture load, which is the load at the moment of fracture of the sides of the quartz substrate 20, is smaller than the fracture load of other parts of the silicon substrate 10 other than the four sides including the modified portions 12. The fracture load of the four sides of the silicon substrate 10 including the modified portions 12 is smaller than the fracture load of the corresponding sides of the quartz substrate 20. The four sides of the quartz substrate 20 do not include the modified portions 12 and have a homogeneous surface. As a result, when the silicon wafer 40 and the quartz wafer 50 are joined and cooled while heated during the manufacturing of the semiconductor chip 1, the silicon wafer 40 is divided at the intended position along the cross section (side of the silicon substrate 10) along the modified portions 12. This suppresses the occurrence of cracks and damage to the silicon wafer 40 and the quartz wafer 50 at positions other than the sides of the silicon substrate 10 (unintended positions).

[0062] [Modifications] It should be noted that the embodiments disclosed herein are illustrative and not restrictive in all respects. The scope of the present invention is indicated by the claims rather than the description of the embodiments above, and further includes all modifications (modifications) within the meaning and scope equivalent to the claims.

[0063] In the above embodiment, an example was shown in which a quartz wafer 50 is used as the "wafer to be bonded," but the present invention is not limited thereto. For example, as the "wafer to be bonded," a wafer made of a material other than quartz may be used, as long as it has a lower coefficient of thermal expansion and a lower fracture load than the silicon wafer 40.

[0064] Furthermore, although the above embodiment shows an example in which the quartz wafer 50 has approximately the same thickness as the silicon wafer 40, the present invention is not limited to this. For example, if the fracture load between corresponding cross-sections is smaller for the quartz wafer 50 than for the silicon wafer 40 (excluding the portion including the modified portion 12), the thicknesses of the silicon wafer 40 and the quartz wafer 50 may be different.

[0065] Furthermore, in the above embodiment, in the modified portion formation step (step S1), the control unit formed the modified portion 12 along a virtual plane P such that there is one modified portion aligned in a direction perpendicular to the main surface 40a and main surface 40b of the silicon wafer 40. However, the present invention is not limited to this. For example, if the silicon wafer 40 is not unintentionally divided when transporting the silicon wafer 40 with the modified portion 12 formed, the control unit may form the modified portion 12 along a virtual plane P such that there are multiple modified portions aligned in a direction perpendicular to the main surface 40a and main surface 40b of the silicon wafer 40 in the modified portion formation step (step S1).

[0066] Furthermore, in the above embodiment, the control unit formed the modified portion 12 on the silicon wafer 40 in step S1, and then formed the element function portion 11 on the silicon wafer 40 in step S2. However, the present invention is not limited to this. For example, the control unit may form the element function portion 11 on the silicon wafer 40 and then form the modified portion 12 on the silicon wafer 40.

[0067] Furthermore, although the above embodiment shows an example in which the control unit forms the element function section 11 on top of the silicon wafer 40, the present invention is not limited to this. For example, the control unit may process the silicon wafer 40 itself, or / or the quartz wafer 50 itself, to form the element function section 11 inside the silicon wafer 40, or / or the quartz wafer 50.

[0068] Furthermore, in the above embodiment, the control unit is shown to heat the silicon wafer 40 in step S3 and then heat the quartz wafer 50 in step S4, but the present invention is not limited thereto. For example, the control unit may heat the quartz wafer 50 first and then heat the silicon wafer 40, or it may heat the silicon wafer 40 and the quartz wafer 50 simultaneously.

[0069] Furthermore, in the above embodiment, as shown in Figure 7, the control unit is shown to form a plurality of modified sections 12 in a line along the direction in which the main surfaces 40a and 40b extend, but the present invention is not limited to this. For example, the control unit may form a plurality of modified sections 12 in a zigzag pattern, as long as it is along the virtual plane P.

[0070] Furthermore, although the above embodiment shows an example in which the control unit forms a plurality of modified portions 12 over the entire cross-section along the virtual plane P of the silicon wafer 40, the present invention is not limited to this. For example, the control unit may form a plurality of modified portions 12 in only a part of the cross-section along the virtual plane P of the silicon wafer 40.

[0071] Furthermore, in the above embodiment, the control unit is shown to pulse a laser L along a virtual plane P using a laser irradiation device (not shown) to form a plurality of modified portions 12 on the silicon wafer 40 along the virtual plane P, but the present invention is not limited to this. For example, as shown in the modified example of Figure 12, the control unit may continuously irradiate a laser L along the virtual plane P using a laser irradiation device (not shown) to form a single layer-shaped (strip-shaped) modified portion 12a on the silicon wafer 60 along the virtual plane P.

[0072] Furthermore, in the above embodiment, the control unit is shown to cool the bonded silicon wafer 40 and quartz wafer 50 by natural cooling in step S6, but the present invention is not limited to this. For example, the control unit may actively cool the bonded silicon wafer 40 and quartz wafer 50 by a cooling method including direct cooling and indirect cooling.

[0073] 1 Semiconductor chip (device) 10 Silicon substrate 10a, 10b Main surface 12, 12a Modified part 20 Quartz substrate 20a, 20b Main surface 30 Bonding material 40, 60 Silicon wafer 40a Main surface (first main surface) 40b Main surface 50 Quartz wafer (wafer to be bonded) 50a Main surface 50b Main surface (second main surface) L Laser P Virtual plane

Claims

1. A method for joining a silicon wafer, comprising: a modification portion forming step of irradiating a silicon wafer having at least one first main surface with a laser to form a modified portion along a virtual plane perpendicular to the first main surface; a silicon wafer heating step of heating the silicon wafer; a wafer to be joined heating step of heating a wafer to be joined having a thermal expansion coefficient different from that of the silicon wafer and having at least one second main surface; a wafer joining step of joining the heated silicon wafer and the wafer to be joined in parallel with the first main surface and the second main surface facing each other; and a cooling step of cooling the silicon wafer and the wafer to be joined after being joined in a heated state, wherein in the cooling step, the silicon wafer and the wafer to be joined are cooled so that the wafer to be joined is not damaged and the silicon wafer is divided along a cross section along the virtual plane on which the modified portion was formed.

2. The silicon wafer bonding method according to claim 1, wherein the modified portion is formed along a plurality of virtual planes, and the plurality of cross-sections along the plurality of virtual planes in the silicon wafer are orthogonal to each other.

3. The silicon wafer joining method according to claim 2, wherein the plurality of cross-sections in the silicon wafer include cross-sections that are orthogonal to each other and cross-sections that are parallel to each other, and the plurality of parallel cross-sections are arranged at equidistant intervals.

4. The silicon wafer bonding method according to claim 1, wherein the modified portion is formed along a virtual plane extending along the cleavage surface of the silicon wafer, and in the cooling step, the silicon wafer and the wafer to be bonded are cooled, causing the silicon wafer to cleave and be divided along the cross section along the virtual plane on which the modified portion is formed.

5. The silicon wafer bonding method according to claim 4, wherein the modified portion is formed along the virtual plane extending along the (110) plane in the crystal of the silicon wafer.

6. The method for joining a silicon wafer according to claim 1, wherein the wafer to be joined has a coefficient of thermal expansion smaller than that of the silicon wafer, and the fracture stress, which is the stress at the moment of fracture of the wafer to be joined, is smaller than the fracture stress of the silicon wafer.

7. The method for joining silicon wafers according to claim 6, wherein the wafer to be joined is a quartz wafer.

8. The silicon wafer bonding method according to claim 1, further comprising a fragmentation step after the cooling step, in which the bonded wafer, which is bonded to the silicon wafer, is divided along the dividing lines of the silicon wafer to form individual elements.

9. The silicon wafer bonding method according to claim 1, wherein in the modified portion formation step, the modified portion is formed along the virtual plane such that there is one modified portion aligned in a direction perpendicular to the first main surface of the silicon wafer.

10. The method for joining a silicon wafer according to claim 1, wherein the fracture stress, which is the stress at the moment of fracture of the modified portion of the silicon wafer, is smaller than the fracture stress of other parts of the silicon wafer.

11. The silicon wafer bonding method according to claim 10, wherein the fracture load, which is the load at the moment of fracture of the cross section along the virtual plane on which the modified portion is formed in the silicon wafer, is smaller than the fracture load of the cross section along the virtual plane in the wafer to be bonded to the silicon wafer.

12. An element comprising a rectangular silicon substrate and a rectangular quartz substrate joined to the silicon substrate in parallel with their respective main surfaces facing each other, wherein the four sides of the silicon substrate include modified portions having a fracture stress smaller than the fracture stress, which is the stress at the moment of fracture of other parts of the silicon substrate; the fracture load, which is the load at the moment of fracture of the sides of the quartz substrate, is smaller than the fracture load of parts of the silicon substrate other than the four sides including the modified portions; the fracture load of the four sides of the silicon substrate including the modified portions is smaller than the fracture load of the corresponding sides of the quartz substrate; and the four sides of the quartz substrate do not include the modified portions and have a homogeneous surface.

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