High-frequency power amplifier circuit

Abstract

According to the present invention, a power amplifier amplifies a high-frequency signal. At least one filter filters the high-frequency signal output from the power amplifier. A bias circuit supplies a bias to the power amplifier. A power detection circuit outputs a detected physical quantity depending on the power of a traveling wave of a transmission line on the input side of the power amplifier or the power of at least one of a traveling wave and a reflected wave of a transmission line on the output side of the power amplifier. A bias power supply circuit supplies a bias power supply current to the bias circuit. The bias circuit generates a bias to be supplied to the power amplifier, on the basis of the bias power supply current. The bias power supply circuit is configured to reduce the bias power supply current in accordance with the increase in the detected physical quantity when the detected physical quantity exceeds a limit start threshold.

Description

High-frequency power amplification circuit

[0001] This invention relates to a high-frequency power amplification circuit.

[0002] An amplification circuit is known that inputs a high-frequency signal to a power amplifier via a programmable variable gain amplifier to perform power amplification (Patent Document 1). In this amplification circuit, the output power of the power amplifier is detected, the detection result is converted from digital to digital, and a controller controls the gain of the programmable variable gain amplifier based on this digital signal. By setting the gain of the programmable variable gain amplifier according to the output power, a decrease in the adjacent channel leakage power ratio (ACLR) is suppressed.

[0003] Patent No. 5131540

[0004] Typically, a filter is inserted between the output of a power amplifier and the antenna. If the output of the power amplifier exceeds the filter's allowable upper limit, the filter may be damaged. In configurations where the gain of a programmable variable gain amplifier is set according to the output power, the control delay becomes large, making it difficult to protect the filter. The object of the present invention is to provide a high-frequency power amplifier circuit that can protect a filter connected to the output side of a power amplifier.

[0005] According to one aspect of the present invention, a high-frequency power amplification circuit is provided, comprising: a power amplifier for amplifying a high-frequency signal; at least one filter for filtering the high-frequency signal output from the power amplifier; a bias circuit for supplying a bias to the power amplifier; a power detection circuit for outputting a detectable physical quantity that depends on the power of the traveling wave in the input transmission line of the power amplifier, or the power of at least one of the traveling wave and the reflected wave in the output transmission line of the power amplifier; and a bias power supply circuit for supplying a bias power supply current to the bias circuit, wherein the bias circuit generates a bias to be supplied to the power amplifier based on the bias power supply current, and the bias power supply circuit is configured to decrease the bias power supply current in proportion to the increase in the detectable physical quantity when the detectable physical quantity exceeds a limiting start threshold.

[0006] When the detected physical quantity exceeds the limiting threshold, the bias power supply current is reduced, lowering the bias supplied to the power amplifier, and consequently lowering the power amplifier's output. Compared to configurations that set the gain of a programmable variable gain amplifier, there is less delay before the power amplifier's output is reduced. This makes it possible to protect filters connected to the output side of the power amplifier.

[0007] Figure 1 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the first embodiment. Figure 2A is an equivalent circuit diagram of the voltage amplitude detection circuit 42, and Figure 2B shows the gate voltage V of the NMOS transistor 42D. ＩＮ and current I ＲＥＣ This is a graph showing the relationship. Figure 3 is the equivalent circuit diagram of the voltage-current conversion circuit 43. Figure 4A shows the detected current I output from the power detection circuit 40. ＯＵＴ And the output current I of the second current mirror circuit 52 １ This graph shows the relationship with the detected current I, and Figure 4B shows the relationship with the detected current I. ＯＵＴ This is a graph showing the relationship between the current and the bias power supply current IEC. Figure 5 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to a comparative example. Figure 6 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a modified example of the first embodiment. Figure 7 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the second embodiment. Figure 8A is an equivalent circuit diagram showing one configuration example of the integrating circuit 48, and Figure 8B is an equivalent circuit diagram showing another configuration example of the integrating circuit 48. Figure 9 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the third embodiment. Figure 10 is an equivalent circuit diagram of the first current source 55. Figure 11 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the fourth embodiment. Figure 12 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the fifth embodiment. Figure 13 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the sixth embodiment. Figure 14 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the seventh embodiment. Figure 15 shows the power of the high-frequency signal input to the filter 30 (filter input power) and the output current I Ｔ , I Ｒ , I １1 is a graph showing an example of a relationship with. FIG. 16 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to an eighth embodiment. FIG. 17 is a schematic equivalent circuit diagram of high-frequency power amplification according to a modification of the eighth embodiment. FIG. 18 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a ninth embodiment. FIGS. 19A, 19B, and 19C are equivalent circuit diagrams each of the first current mirror circuit 51. FIG. 20 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to a tenth embodiment.

[0008] [First Embodiment] A high-frequency power amplifier circuit according to a first embodiment will be described with reference to the drawings from FIG. 1 to FIG. 4.

[0009] FIG. 1 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the first embodiment. The high-frequency power amplifier circuit according to the first embodiment includes a power amplifier 20, a bias circuit 25, a filter 30, a power detection circuit 40, and a bias power supply circuit 50. A high-frequency signal RF from the input node 90 ＩＮ is input, and is input to the power amplifier 20 via the impedance matching circuit 80 and the input capacitor 21. The power amplifier 20 amplifies the input high-frequency signal. For example, a heterojunction bipolar transistor (HBT) is used as an amplifying element of the power amplifier 20.

[0010] The high-frequency signal amplified by the power amplifier 20 is output from the output node 91 via the impedance matching circuit 81 and the filter 30. The filter 30 filters the high-frequency signal. For example, the filter 30 is a band-pass filter that passes only a high-frequency signal in a specific frequency band. As the filter 30, a filter using a piezoelectric material, for example, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, or the like can be used. For example, an antenna or the like is connected to the output node 91.

[0011] The bias power supply circuit 50 supplies a bias power supply current IEC to the bias circuit 25. The bias circuit 25 is controlled by the bias control current IB from the bias control circuit 26, thereby outputting a bias current based on the bias power supply current IEC. The bias current is supplied to the power amplifier 20 via the ballast resistance element 22.

[0012] The bias circuit 25 includes an emitter follower transistor 25Q, a diode circuit 25D, and a resistor 25R. The bias power supply current IEC is supplied to the collector of the emitter follower transistor 25Q. The bias control current IB, input from the bias control circuit 26, is supplied to the base of the emitter follower transistor 25Q via the resistor 25R. The base of the emitter follower transistor 25Q is grounded via the diode circuit 25D. The diode circuit 25D includes two diodes connected in two stages such that the forward direction is from the base of the emitter follower transistor 25Q toward the ground potential.

[0013] In this configuration, the bias circuit 25 receives control from the bias control current IB and generates a bias current to supply to the power amplifier 20 based on the bias power supply current IEC. For example, when the bias control current IB flows and the emitter follower transistor 25Q turns on, the bias power supply current IEC is supplied to the power amplifier 20, and the power amplifier 20 operates. When the supply of the bias control current IB is stopped and the emitter follower transistor 25Q turns off, the power amplifier 20 is no longer supplied with bias, and the amplification operation of the power amplifier 20 stops.

[0014] The power detection circuit 40 detects the detected current I as a physical quantity that depends on the power of the traveling wave in the transmission line on the output side of the power amplifier 20. ＯＵＴ It outputs the following: As the power of the traveling wave increases, the detected current I ＯＵＴ It also increases. Detected current I ＯＵＴ This is input to the bias power supply circuit 50. The bias power supply circuit 50 receives the detected current I ＯＵＴ Based on this, the bias power supply current IEC is generated. The bias power supply circuit 50 receives the detection current I from the power detection circuit 40. ＯＵＴ When the detected current I reaches a predetermined threshold, the bias power supply current IEC is limited. This threshold is referred to as the limiting threshold. Specifically, the bias power supply circuit 50 controls the detected current I ＯＵＴ When the detection current I exceeds the limit start threshold, ＯＵＴAs the value increases, decrease the bias power supply current IEC.

[0015] Next, the power detection circuit 40 will be described. The power detection circuit 40 includes a directional coupler 41, a voltage amplitude detection circuit 42, and a voltage-to-current conversion circuit 43. The directional coupler 41 is coupled to the transmission line between the power amplifier 20 and the filter 30, extracts a portion of the traveling wave, and supplies it to the voltage amplitude detection circuit 42. The portion of the traveling wave extracted by the directional coupler 41 is converted into a high-frequency signal RF Ｔ This is the case. The voltage amplitude detection circuit 42 receives the input high-frequency signal RF Ｔ Voltage V depends on the voltage amplitude. ＲＥＣ The voltage-current conversion circuit 43 outputs the voltage V ＲＥＣ The detection current I is proportional to ＯＵＴ Outputs.

[0016] Next, an example of a voltage amplitude detection circuit 42 will be described with reference to Figures 2A and 2B. Figure 2A is an equivalent circuit diagram of the voltage amplitude detection circuit 42. The high-frequency signal RF is part of the traveling wave. Ｔ This is input to the gate of the NMOS transistor 42D via the DC-blocking capacitor 42A. The bias circuit 42C applies a bias voltage to the gate of the NMOS transistor 42D via the resistor element 42B.

[0017] The power supply voltage is applied to the drain of the NMOS transistor 42D, and its source is grounded via the resistor element 42E. A high-frequency signal RF is being transmitted. Ｔ Current I is supplied to the resistor element 42E in accordance with the voltage. ＲＥＣ A current flows. A voltage equivalent to the voltage drop across the resistor 42E is generated at the source of the NMOS transistor 42D. This voltage is filtered by the fundamental wave rejection filter 42F to produce a voltage V ＲＥＣ It will be output as follows.

[0018] Figure 2B shows the gate voltage V of the NMOS transistor 42D. ＩＮ and current I ＲＥＣ This graph shows the relationship between the gate voltage V. The horizontal axis represents the gate voltage V. ＩＮ This represents the current I on the vertical axis. ＲＥＣ This represents the gate voltage V. ＩＮAs the current I increases, ＲＥＣ Although it also increases, the relationship between the two is nonlinear. (High frequency signal RF) Ｔ When this is input, the gate voltage V ＩＮ This is the bias voltage V ＩＮ０ It changes periodically around this point.

[0019] Low amplitude high-frequency signal RF ＴＳ When this is input, the effects of nonlinearity are almost nonexistent. Therefore, high-frequency signal RF ＴＳ The current I that flows when the input is received ＴＳ The average value I ＡＶＥＳ is a high-frequency signal RF ＴＳ The average value of the voltage (i.e., bias voltage V) ＩＮ０ ) Corresponding current I ＲＥＣ It becomes equal to.

[0020] High-frequency signals with large amplitude (RF) ＴＬ When this is input, the effects of nonlinearity appear, resulting in a high-frequency signal RF ＴＬ Current I when the voltage is in the positive direction ＴＬ The current I when the amplitude is in the negative direction ＴＬ It becomes larger than the amplitude. Therefore, current I ＴＬ The average value I ＡＶＥＬ However, low amplitude high-frequency signals (RF) ＴＳ Current I when input ＴＳ The average value I ＡＶＥＳ It will get bigger.

[0021] Voltage V output through the fundamental wave removal filter 42F ＲＥＣ is current I ＴＳ , I ＴＬ Average value I ＡＶＥＳ , I ＡＶＥＬ It depends on the high-frequency signal RF. Ｔ When the voltage amplitude increases, the voltage V ＲＥＣ It will rise.

[0022] Next, an example of the voltage-current conversion circuit 43 will be described with reference to Figure 3. Figure 3 is an equivalent circuit diagram of the voltage-current conversion circuit 43. The voltage-current conversion circuit 43 includes an operational amplifier 43A, a PMOS current mirror circuit 43C, and a resistor element 43B. The voltage V output from the voltage amplitude detection circuit 42 ＲＥＣ This is input to the inverting input node of the operational amplifier 43A. The output node of the operational amplifier 43A is connected to the gates of the reference and output transistors of the PMOS current mirror circuit 43C. The sources of the reference and output transistors of the PMOS current mirror circuit 43C are connected to the power supply voltage.

[0023] The drain of the reference transistor is grounded via the resistor element 43B and connected to the non-inverting input node of the operational amplifier 43A. A voltage V is applied across the resistor element 43B. ＲＥＣ A current flows according to the ratio. Based on the current flowing through the resistor element 43B, a detection current I corresponding to the Miller ratio is supplied to the output transistor. ＯＵＴ A current flows. That is, the detected current I ＯＵＴ Voltage V ＲＥＣ It is proportional to the detected current I. ＯＵＴ This depends on the power of the traveling wave detected by the directional coupler 41, and as the power of the traveling wave increases, the detected current I ＯＵＴ It increases.

[0024] Next, the bias power supply circuit 50 will be described with reference to Figure 1. The bias power supply circuit 50 includes a first current mirror circuit 51 composed of NMOS transistors, a second current mirror circuit 52 composed of PMOS transistors, a third current mirror circuit 53 composed of PMOS transistors, a first current source 55, and a second current source 56. The reference current of the first current mirror circuit 51 is the detection current I input from the power detection circuit 40. ＯＵＴ It is constructed to be equal to [the given expression].

[0025] The first current mirror circuit 51, the second current mirror circuit 52, and the first current source 55 are configured such that the current obtained by subtracting the current generated by the first current source 55 from the output current of the first current mirror circuit 51 becomes the reference current of the second current mirror circuit 52. That is, the sum of the current generated by the first current source 55 and the reference current of the second current mirror circuit 52 is equal to the output current of the first current mirror circuit 51. The first current source 55 generates a current of a magnitude corresponding to the limiting threshold current (hereinafter referred to as the limiting threshold current I) that initiates the limitation of the bias power supply current IEC. ＴＨ This generates (that is said).

[0026] The Miller ratio of the first current mirror circuit 51 is 1. At this time, the detected current I ＯＵＴ The limiting threshold current I ＴＨ When the following conditions are met, no reference current flows through the second current mirror circuit 52: Detected current I ＯＵＴ The limiting threshold current I ＴＨ When it exceeds this value, a reference current flows through the second current mirror circuit 52, and as a result, the output current I １ The following will be output.

[0027] The third current mirror circuit 53 has a reference current I ＲＥＦ However, the output current I of the second current source 56 ２ The output current I of the second current mirror circuit 52 １ It is configured to be equal to the current obtained by subtracting from it. That is, the reference current I of the third current mirror circuit 53 ＲＥＦ and the output current I of the second current mirror circuit 52 １ The sum of these is the output current I of the second current source 56. ２ This becomes equal to the output current of the third current mirror circuit 53, which is supplied to the bias circuit 25 as the bias power supply current IEC.

[0028] Figure 4A shows the detected current I output from the power detection circuit 40. ＯＵＴ And the output current I of the second current mirror circuit 52 １ This graph shows the relationship between the two. The horizontal axis represents the detected current I. ＯＵＴ This represents the output current I on the vertical axis. １ This represents the detected current I. ＯＵＴreflects the power of the traveling wave detected by the directional coupler 41. Detection current I ＯＵＴ is within the range below the limiting start threshold current I ＴＨ , no output current I １ flows. When detection current I ＯＵＴ exceeds the limiting start threshold current I ＴＨ , output current I １ starts to flow. The slope of output current I ＯＵＴ with respect to detection current I １ is determined by the mirror ratio A of the second current mirror circuit 52. For example, when the mirror ratio A increases, the slope of output current I ＯＵＴ with respect to detection current I １ increases.

[0029] FIG. 4B is a graph showing the relationship between detection current I ＯＵＴ and bias power supply current IEC. The horizontal axis represents detection current I ＯＵＴ , and the vertical axis represents bias power supply current IEC. When detection current I ＯＵＴ is within the range below the limiting start threshold current I ＴＨ , no output current I １ flows, so the reference current I ＲＥＦ of the third current mirror circuit 53 is equal to the output current I ２ of the second current source 56. When the mirror ratio of the third current mirror circuit 53 is denoted as B, the bias power supply current IEC is equal to B times the output current I ２ of the second current source 56.

[0030] When detection current I ＯＵＴ exceeds the limiting start threshold current I ＴＨ , the increase in output current I １ causes the reference current I ＲＥＦ of the third current mirror circuit 53 to decrease. As a result, the bias power supply current IEC decreases.

[0031] Next, the excellent effects of the first embodiment will be described. In the high-frequency power amplifier circuit according to the first embodiment, the power of the traveling wave traveling from the power amplifier 20 toward the filter 30 is the limiting start threshold current I generated by the first current source 55 (FIG. 1) ＴＨWhen it exceeds a certain value, the bias power supply current IEC decreases. When the bias power supply current IEC decreases, the bias current supplied to the power amplifier 20 also decreases, so the output of the power amplifier 20 is suppressed and damage to the filter 30 is suppressed. Also, as shown in Figure 4B, instead of stopping the supply of the bias power supply current IEC, the bias power supply current IEC is gradually reduced, making it possible to maintain communication.

[0032] In the first embodiment, the high-frequency signal RF is input to the input node 90. ＩＮ Since the size of the input node does not change, there is no need to provide a control circuit before the input node 90. Control is completed within the so-called front-end module. Furthermore, AD conversion processing and digital processing are not required. As a result, the circuit configuration is simple and control delay can be suppressed.

[0033] Furthermore, in the first embodiment, the slope of the bias power supply current IEC can be adjusted by the Miller ratio A of the second current mirror circuit 52. For example, the bias power supply current IEC can also be generated by drawing a portion of a constant current. However, in this configuration, if the bias power supply current IEC is large, the size of the transistor for current extraction must be increased. In contrast, in the first embodiment, a large bias power supply current IEC can be generated by increasing the Miller ratio B of the third current mirror circuit 53, eliminating the need for a large transistor for current extraction. This is advantageous in terms of miniaturization.

[0034] Next, the superior effects of the first embodiment will be explained in comparison with the comparative example shown in Figure 5. Figure 5 is a schematic equivalent circuit diagram of the high-frequency amplifier circuit according to the comparative example. In the comparative example, the collector of the emitter follower transistor 25Q of the bias circuit 25 is connected to a constant voltage source, and a constant voltage V is applied to the collector. ＢＡＴＴ A high-frequency signal RF, which is part of the traveling wave transmitted from the power amplifier 20 to the filter 30, is applied. Ｔ The bias control circuit 26 receives the high-frequency signal RF. ＴThe bias control current IB is controlled based on the power. By controlling the bias control current IB, the gain of the power amplifier 20 is adjusted. This protects the filter 30.

[0035] High-frequency signal RF input to power amplifier 20 ＩＮ As the amplitude of the voltage waveform increases, the emitter voltage of the emitter follower transistor 25Q decreases due to the negative voltage of the voltage waveform. Therefore, even if the bias control current IB is not supplied from the bias control circuit 26, the base-emitter voltage of the emitter follower transistor 25Q increases, and base current flows through the emitter follower transistor 25Q. As a result, bias is supplied to the power amplifier 20, and the power amplifier 20 starts operating. This effect is called the self-bias effect.

[0036] In the comparative example (Figure 5), it may not be possible to properly adjust the gain of the power amplifier 20 due to the self-bias effect. In contrast, in the first embodiment, since the bias power supply current IEC is controlled, it is possible to limit the output power of the power amplifier 20 without being affected by the self-bias effect.

[0037] Next, a modified high-frequency power amplifier circuit according to the first embodiment will be described with reference to Figure 6. Figure 6 is a schematic equivalent circuit diagram of the modified high-frequency power amplifier circuit according to the first embodiment. Comparing the modified example shown in Figure 6 with the first embodiment (Figure 1), the configuration of the power detection circuit 40 is different. Furthermore, in the modified example shown in Figure 6, the first current source 55 (Figure 1) of the high-frequency power amplifier circuit according to the first embodiment is not connected.

[0038] In the comparative example, the power detection circuit 40 includes a directional coupler 41, a voltage amplitude detection circuit 42, and a voltage-to-current conversion circuit 43, as well as a threshold voltage source 44, a comparator 45, a subtraction circuit 46, and a multiplexer 47. The threshold voltage source 44 is a limit start threshold voltage V corresponding to the limit start threshold that initiates the limiting of the bias power supply current IEC. ＴＨ The subtraction circuit 46 outputs the voltage V output from the voltage amplitude detection circuit 42. ＲＥＣ and the limit start threshold voltage V ＴＨA voltage equivalent to the difference between the two values ​​is applied to one input node of the multiplexer 47. 0V is applied to the other input node of the multiplexer 47.

[0039] Comparator 45 measures voltage V ＲＥＣ and the limit start threshold voltage V ＴＨ The voltage V is compared with the voltage V, and the comparison result is given to the multiplexer 47. ＲＥＣ The limiting threshold voltage V ＴＨ The multiplexer 47 inputs 0V to the voltage-to-current conversion circuit 43 in the following case: At this time, the detected current I ＯＵＴ No output is produced. Voltage V ＲＥＣ The limiting threshold voltage V ＴＨ When it is greater than V, the multiplexer 47 controls the voltage V. ＲＥＣ and the limit start threshold voltage V ＴＨ The voltage difference is input to the voltage-to-current conversion circuit 43. At this time, the detected current I, which is proportional to the voltage difference, is input. ＯＵＴ The following will be output.

[0040] Detection current I ＯＵＴ When this is output, the second current mirror circuit 52 detects the current I ＯＵＴ A times the output current I １ This outputs the following. As a result, the bias power supply current IEC is limited. In the modified example shown in Figure 6, the same control as in the first embodiment is achieved. In the modified example, the limiting start threshold voltage V ＴＨ The voltage V is the point of comparison. ＲＥＣ This can be considered a detected physical quantity.

[0041] In the first embodiment (Figure 1), the first current source 55 connected to the output side of the first current mirror circuit 51 provides the same functionality as the threshold voltage source 44, comparator 45, and subtraction circuit 46 in the modified example (Figure 6). Therefore, from the viewpoint of miniaturization, the first embodiment is more advantageous than the modified example.

[0042] [Second Embodiment] Next, a high-frequency power amplifier circuit according to the second embodiment will be described with reference to Figures 7, 8A, and 8B. Hereinafter, the common components with the high-frequency power amplifier circuit according to the first embodiment, which was described with reference to Figures 1 to 4B, will not be explained.

[0043] Figure 7 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the second embodiment. The power detection circuit 40 of the high-frequency power amplifier circuit according to the second embodiment includes an integrating circuit 48 in addition to the multiple components of the power detection circuit 40 of the high-frequency power amplifier circuit according to the first embodiment (Figure 1). The integrating circuit 48 receives the voltage V output from the voltage amplitude detection circuit 42. ＲＥＣ Integrating this gives the average voltage V ＲＥＣＡＶＥ The voltage-current conversion circuit 43 outputs the average voltage V. ＲＥＣＡＶＥ Detection current I ＯＵＴ Convert to.

[0044] The fundamental wave rejection filter 42F (Figure 2A) of the high-frequency power amplifier circuit according to the first embodiment can also be considered a type of integrating circuit. The fundamental wave rejection filter 42F filters the high-frequency signal RF ＩＮ It has a time constant of approximately the period. In contrast, the time constant of the integrating circuit 48 is greater than the time constant of the fundamental wave rejection filter 42F. For example, the integrating circuit 48 processes a high-frequency signal RF ＩＮ Voltage V over a certain period spanning multiple cycles ＲＥＣ Average voltage V ＲＥＣＡＶＥ This outputs the following. Therefore, the bias power supply circuit 50 controls the bias power supply current IEC based on the average value of the power of the traveling wave over a certain period.

[0045] Figure 8A is an equivalent circuit diagram showing one example configuration of the integrating circuit 48. An L-type CR low-pass filter composed of a capacitor 48A and a resistor 48B can be used as the integrating circuit 48. Alternatively, a T-type or π-type CR low-pass filter may be used instead of the L-type CR low-pass filter.

[0046] Figure 8B is an equivalent circuit diagram showing another configuration example of the integrating circuit 48. The integrating circuit 48 is a circuit including the operational amplifier 48C. Voltage V ＲＥＣ The voltage V is input to the inverting input node of the operational amplifier 48C via the resistor element 48D. The non-inverting input node of the operational amplifier 48C is grounded via the pull-down resistor element 48G. A feedback resistor element 48E and a feedback capacitor 48F are connected between the inverting input node and the output node of the operational amplifier 48C. The average voltage V is output from the output node of the operational amplifier 48C. ＲＥＣＡＶＥ The following will be output.

[0047] In the high-frequency power amplifier circuit according to the second embodiment, the bias power supply current IEC is limited based on the average power of the traveling wave of the high-frequency signal output from the power amplifier 20. The limiting start threshold current I from the first current source 55 ＴＨ However, this is used as a threshold to limit the average power output of the power amplifier 20. Also, the output current I from the second current source 56 ２ As shown in Figure 4B, this determines the maximum value of the bias power supply current IEC. Therefore, the output current I ２ This limits the peak power output of the power amplifier 20.

[0048] Next, the superior effects of the second embodiment will be described. The larger the average power per unit time of the output of the power amplifier 20, the greater the amount of heat generated by the filter 30, making it more susceptible to damage. In the second embodiment, since the bias power supply current IEC is limited based on the average power of the output of the power amplifier 20, damage caused by heat generation in the filter 30 can be suppressed. Furthermore, the output current I of the second current source 56 ２ This allows the peak power of the output of the power amplifier 20 to be limited. Thus, in the second embodiment, both the average power and the peak power of the output of the power amplifier 20 can be limited.

[0049] [Third Embodiment] Next, a high-frequency power amplifier circuit according to the third embodiment will be described with reference to Figures 9 and 10. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the first embodiment, which was described with reference to Figures 1 to 4B, will be omitted from the explanation.

[0050] Figure 9 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the third embodiment. The first current source 55 of the high-frequency power amplifier circuit according to the third embodiment has a temperature compensation function. For example, when the ambient temperature rises, the first current source 55 sets a limiting threshold current I ＴＨ It has temperature characteristics that reduce [the power of the device]. Therefore, as the ambient temperature rises, the bias power supply current IEC limitation begins when the power of the traveling wave is lower.

[0051] Figure 10 is an equivalent circuit diagram of the first current source 55. The first current source 55 includes two PMOS current mirror circuits 55A and 55B. The drain of the PMOS transistor on the reference current side of one of the PMOS current mirror circuits 55A is grounded via a series circuit of a resistor 55C and a diode 55D. The diode 55D is connected in a direction such that the direction toward ground potential from the PMOS transistor is the forward direction. The difference voltage between the drain voltage of the PMOS transistor through which the reference current flows and the silicon bandgap voltage VBG is applied to the gates of the two PMOS transistors of the PMOS current mirror circuit 55A.

[0052] The temperature of diode 55D changes depending on the ambient temperature, and its forward voltage also changes depending on the temperature of diode 55D. The output current Iitat of the PMOS current mirror circuit 55A also changes depending on the temperature of diode 55D. More specifically, as the temperature of diode 55D rises, the output current Iitat decreases.

[0053] The drain of the PMOS transistor on the reference current side of the other PMOS current mirror circuit 55B is grounded via a resistor 55E. The difference voltage between the drain voltage of the PMOS transistor through which the reference current flows and the silicon bandgap voltage VBG is applied to the gates of the two PMOS transistors of the PMOS current mirror circuit 55B. The output current Iztat of the PMOS current mirror circuit 55B is a constant value that does not depend on temperature and depends on the resistance value of the resistor 55E.

[0054] Limiting start threshold current I from the first current source 55 ＴＨ This is equal to the sum of the output currents Iitat and Iztat. Therefore, the limiting threshold current I ＴＨ It decreases as the ambient temperature rises.

[0055] Next, the superior effects of the third embodiment will be described. Generally, the filter 30 becomes more susceptible to damage as the temperature rises. In the third embodiment, the limiting threshold current I that starts limiting the bias power supply current IEC increases as the ambient temperature rises. ＴＨThis reduces the filter's performance. As a result, sufficient protection for the filter 30 is obtained even at high temperatures.

[0056] Next, a high-frequency power amplifier circuit according to a modification of the third embodiment will be described. In the third embodiment, the temperature of the diode 55D is configured to change in accordance with the ambient temperature. Alternatively, the thermal coupling between the diode 55D and the filter 30 may be made tighter so that the temperature change of the filter 30 is reflected in the temperature change of the diode 55D. With such a configuration, it becomes possible to limit the output of the power amplifier 20 more quickly when the temperature of the filter 30 rises.

[0057] [Fourth Embodiment] Next, a high-frequency power amplifier circuit according to the fourth embodiment will be described with reference to Figure 11. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the first embodiment, which was described with reference to Figures 1 to 4B, will be omitted from the explanation.

[0058] Figure 11 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the fourth embodiment. The high-frequency power amplifier circuit according to the first embodiment (Figure 1) includes one filter 30, but the high-frequency power amplifier circuit according to the fourth embodiment includes two filters 30. The two filters 30 have different passbands. For example, a filter 30 is provided for each band of the high-frequency signal to be amplified.

[0059] A filter selection switch 31 is inserted between the power amplifier 20 and the two filters 30. The filter selection switch 31 transmits the high-frequency signal output from the power amplifier 20 to one of the two filters 30 that has been selected. The filter selection switch 31 is also called a band selection switch. The directional coupler 41 of the power detection circuit 40 is coupled to the transmission line between the power amplifier 20 and the filter selection switch 31.

[0060] The antenna switch 32 is connected to the output side of the two filters. The antenna switch 32 connects one of the two filters 30 to the antenna terminal 33. An antenna is connected to the antenna terminal 33. By switching the filter selection switch 31 and the antenna switch 32, it is possible to transmit a high-frequency signal on one of the multiple bands.

[0061] The filter selection switch 31, power detection circuit 40, bias power supply circuit 50, first current mirror circuit 51, first current source 55, and second current mirror circuit 52 are formed on the first chip 61, while the third current mirror circuit 53, second current source 56, and bias control circuit 26 are formed on the other second chip 62. For example, silicon substrates, SOI substrates, etc., are used for the first chip 61 and the second chip 62. In contrast, the power amplifier 20, bias circuit 25, and impedance matching circuits 80 and 81 are formed on a power amplifier core chip made of compound semiconductor. The first chip 61, the second chip 62, and the power amplifier core chip are mounted on a module substrate.

[0062] Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, the directional coupler 41 is coupled to the transmission line between the power amplifier 20 and the filter selection switch 31, rather than to each filter 30. Since the power detection circuit 40 is shared by multiple filters 30, it is possible to miniaturize the high-frequency power amplification circuit.

[0063] The first chip 61 and the second chip 62 are mounted on a common module board and connected by wiring provided on the module board. For example, the output current I of the second current mirror circuit 52 １ The wiring within the module board is used as the wiring through which the current flows. In the fourth embodiment, the fundamental frequency component is removed by the fundamental frequency filter 42F (Figure 2A) of the voltage amplitude detection circuit 42. That is, the output current I １ It does not contain high-frequency components. Therefore, the output current I flowing through the wiring of the module board １ This makes it less susceptible to noise from other components mounted on the module board, and the output current I １This also reduces the impact on other parts.

[0064] Next, a high-frequency power amplifier circuit according to a modification of the fourth embodiment will be described. The high-frequency power amplifier circuit according to the fourth embodiment has two filters 30, but it may have three or more filters 30.

[0065] In the fourth embodiment, the chip is isolated between the second current mirror circuit 52 and the third current mirror circuit 53, but the chip may be isolated at other points where the signal from which the fundamental wave component has been removed is transmitted. For example, the chip may be isolated between the voltage amplitude detection circuit 42 and the voltage-current conversion circuit 43, or between the voltage-current conversion circuit 43 and the first current mirror circuit 51, etc.

[0066] [Fifth Embodiment] Next, a high-frequency power amplifier circuit according to the fifth embodiment will be described with reference to Figure 12. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the fourth embodiment, described with reference to Figure 11, will be omitted from the explanation.

[0067] Figure 12 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the fifth embodiment. High-frequency signal RF ＩＮ The impedance matching circuits 80, 81, power amplifier 20, filter selection switch 31, multiple filters 30, bias circuit 25, and bias control circuit 26 of the power amplifier 20, from the input node 90 to the output terminals of the multiple filters 30, are considered to be one amplification system. The high-frequency power amplifier circuit according to the fourth embodiment (Figure 11) has one amplification system. In contrast, the high-frequency power amplifier circuit according to the fifth embodiment has a first amplification system 28a and a second amplification system 28b.

[0068] The first amplification system 28a and the second amplification system 28b have different operating frequency bands. The connection configuration of each component is the same in the first amplification system 28a and the second amplification system 28b, but the circuit constants of each component are optimized according to the operating frequency band.

[0069] The antenna switch 32 connects one of the output nodes of the first amplification system 28a and the second amplification system 28b to the antenna terminal 33. The directional coupler 41 of the power detection circuit 40 is coupled to the transmission line between the antenna switch 32 and the antenna terminal 33. That is, the power detection circuit 40 detects a detection current I, which is a physical quantity that depends on the power of the traveling wave between the antenna switch 32 and the antenna terminal 33. ＯＵＴ Outputs.

[0070] The output node of the bias power supply circuit 50, which outputs the bias power supply current IEC, is connected to both the bias circuit 25 of the first amplification system 28a and the bias circuit 25 of the second amplification system 28b.

[0071] When the antenna switch 32 selects the first amplification system 28a, the bias control circuit 26 of the first amplification system 28a supplies the bias control current IB, while the bias control circuit 26 of the second amplification system 28b does not supply the bias control current IB. As a result, the emitter follower transistor 25Q of the bias circuit 25 of the first amplification system 28a is turned on, and the emitter follower transistor 25Q of the bias circuit 25 of the second amplification system 28b is turned off. Therefore, the bias power supply current IEC flows only into the bias circuit 25 of the first amplification system 28a, and only the first amplification system 28a operates.

[0072] When the antenna switch 32 selects the second amplification system 28b, the bias control circuit 26 of the second amplification system 28b supplies the bias control current IB, while the bias control circuit 26 of the first amplification system 28a does not supply the bias control current IB. In this case, the bias power supply current IEC flows only into the bias circuit 25 of the second amplification system 28b, and only the second amplification system 28b operates.

[0073] Next, the excellent effects of the fifth embodiment will be described. In the fifth embodiment, since the power detection circuit 40 and the bias power supply circuit 50 are shared between the first amplification system 28a and the second amplification system 28b, it is possible to miniaturize the high-frequency power amplification circuit.

[0074] [Sixth Embodiment] Next, a high-frequency power amplifier circuit according to the sixth embodiment will be described with reference to Figure 13. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the first embodiment, described with reference to Figures 1 to 4B, will be omitted from the explanation.

[0075] Figure 13 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the sixth embodiment. In the high-frequency power amplifier circuit according to the first embodiment (Figure 1), the directional coupler 41 extracts a portion of the forward wave from the transmission line between the power amplifier 20 and the filter 30 and supplies it to the voltage amplitude detection circuit 42. In contrast, the directional coupler 41 according to the sixth embodiment extracts a portion of the reflected wave from the transmission line between the power amplifier 20 and the filter 30 and supplies it to the voltage amplitude detection circuit 42. A portion of the reflected wave is used to generate a high-frequency signal RF Ｒ Let's assume that's the case.

[0076] The power detection circuit 40 detects the high-frequency signal RF caused by the reflected wave. Ｒ Detection current I corresponding to the power ＯＵＴ The output is generated. For example, a portion of the high-frequency signal that passes through filter 30 and is supplied to the antenna connected to output node 91 is reflected by the antenna, the reflected wave passes through filter 30, and a portion of the reflected wave that has passed through filter 30 is extracted by directional coupler 41.

[0077] The power detection circuit 40 detects the high-frequency signal RF caused by the reflected wave. Ｒ Detection current I corresponding to the power ＯＵＴ It outputs the high-frequency signal RF caused by the reflected wave. Ｒ The bias power supply current IEC is limited according to the power.

[0078] Next, the excellent effects of the sixth embodiment will be described. Under the condition that the reflection coefficient of the antenna connected to the output node 91 is constant, when the power of the traveling wave from the power amplifier 20 to the filter 30 increases, the power of the reflected wave also increases. For this reason, detecting the power of the reflected wave can be said to be indirectly detecting the power of the traveling wave. Therefore, in the sixth embodiment as well, it is possible to limit the bias power supply current IEC based on the power of the traveling wave.

[0079] Furthermore, fluctuations in the antenna's input impedance cause fluctuations in the reflected wave power. Filter 30 is more susceptible to damage when the voltage standing wave ratio (VSWR) of the transmission line on the output node 91 side increases. A higher VSWR corresponds to a higher reflected wave power.

[0080] In the sixth embodiment, a high-frequency signal RF is generated due to the power of the reflected wave. Ｒ To limit the bias power supply current IEC based on the power, the filter 30 can be protected by comprehensively determining both the forward wave and the VSWR.

[0081] [Seventh Embodiment] Next, a high-frequency power amplifier circuit according to the seventh embodiment will be described with reference to Figures 14 and 15. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the first embodiment, which was described with reference to Figures 1 to 4B, will be omitted from the explanation.

[0082] Figure 14 is a schematic equivalent circuit diagram of the high-frequency power amplifier circuit according to the seventh embodiment. In the high-frequency power amplifier circuit according to the first embodiment (Figure 1), the directional coupler 41 detects the traveling wave, but the directional coupler 41 of the high-frequency power amplifier circuit according to the seventh embodiment detects both the traveling wave and the reflected wave. The high-frequency signal RF caused by the traveling wave Ｔ This is input to the voltage amplitude detection circuit 42T for the traveling wave, and the high-frequency signal RF caused by the reflected wave is input. Ｒ This is input to the voltage amplitude detection circuit 42R for the reflected wave.

[0083] The voltage-to-current conversion circuit 43T for traveling waves converts the high-frequency signal RF caused by the traveling wave. Ｔ Based on the power, the detection current I for the traveling wave ＯＵＴＴ It outputs the high-frequency signal RF caused by the reflected wave. Similarly, the voltage-to-current conversion circuit 43R for reflected waves outputs the high-frequency signal RF. Ｒ Based on the power, the detection current I for the reflected wave ＯＵＴＲ Outputs.

[0084] The bias power supply circuit 50 includes a first current mirror circuit 51T, a first current source 55T, and a second current mirror circuit 52T for forward waves, and a first current mirror circuit 51R, a first current source 55R, and a second current mirror circuit 52R for reflected waves. The first current source 55T provides a limiting starting threshold current I for forward waves. ＴＨＴ The first current source 55R generates a limiting threshold current I for the reflected wave. ＴＨＲ Generates.

[0085] The mirror ratio of the second current mirror circuit 52T for traveling waves is set to A. Ｔ This is expressed as follows, and the mirror ratio of the second current mirror circuit 52R for reflected waves is A Ｒ This is how it is written. Output current I of the second current mirror circuit 52T for traveling waves. Ｔ And the output current I of the second current mirror circuit 52R for reflected waves Ｒ The output current I is the sum of the two. １ However, it flows into the third current mirror circuit 53. The reference current I of the third current mirror circuit 53 ＲＥＦ The output current I of the second current source 56 ２ Output current I １ It will be the size after subtracting [a certain factor].

[0086] Figure 15 shows the power of the high-frequency signal input to the filter 30 (filter input power) and the output current I. Ｔ , I Ｒ , I １ This graph shows an example of the relationship between the filter input power and the current. The horizontal axis represents the filter input power, and the vertical axis represents the magnitude of the current. The filter input power is the limiting threshold current I for the traveling wave. ＴＨＴ When the corresponding threshold power is exceeded, the output current I Ｔ The current begins to flow. Output current I Ｔ The slope is the mirror ratio A of the second current mirror circuit 52T for the traveling wave. Ｔ This is determined by the filter input power, which is the limiting threshold current I for the reflected wave. ＴＨＲ When the corresponding threshold power is exceeded, the output current I Ｒ The current begins to flow. Output current I Ｒ The slope is the mirror ratio A of the second current mirror circuit 52R for reflected waves. Ｒ It is determined by the output current I. １ The output current IＴ and output current I Ｒ It is equal to the sum of the two.

[0087] Figure 15 shows the limiting threshold current I for the traveling wave. ＴＨＴ The threshold power corresponding to the limiting start threshold current I for reflected waves is ＴＨＲ The example shown is smaller than the corresponding threshold power, but the relationship between the two can be reversed. Also, in Figure 15, the Miller ratio A for traveling waves is shown. Ｔ Mirror ratio A for reflected waves Ｒ While a smaller example is shown, the relative sizes could be reversed.

[0088] The bias power supply circuit 50 controls one of the detected physical quantities (detected current I ＯＵＴＴ ) is the limiting threshold current I ＴＨＴ When it exceeds this value, the output current I increases in proportion to the increase in filter input power. １ As this increases, the bias power supply current IEC decreases. Furthermore, the other detected physical quantity (detection current I) decreases. ＯＵＴＲ ) also the limiting threshold current I ＴＨＲ When it exceeds this value, the output current I increases in proportion to the increase in filter input power. １ As the increase becomes steeper, the bias power supply current IEC decreases more steeply.

[0089] Next, the excellent effects of the seventh embodiment will be described. In the seventh embodiment, the bias power supply current IEC is limited when either the power of the traveling wave or the power of the reflected wave exceeds the threshold power for starting the limit. Therefore, it is possible to suppress the destruction of the filter 30 due to an increase in the power of the traveling wave and the destruction of the filter 30 due to an increase in the power of the reflected wave. Furthermore, even if the power of the traveling wave or the reflected wave alone does not lead to the destruction of the filter 30, the combined power of the traveling wave and the reflected wave may lead to the destruction of the filter 30. In the seventh embodiment, by appropriately setting the threshold power for starting the limit for the traveling wave and the reflected wave, it is possible to suppress the destruction of the filter 30 due to the combined power of the traveling wave and the reflected wave.

[0090] [Eighth Embodiment] Next, a high-frequency power amplifier circuit according to the eighth embodiment will be described with reference to Figure 16. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the first embodiment, which was described with reference to Figures 1 to 4B, will be omitted from the explanation.

[0091] Figure 16 is a schematic equivalent circuit diagram of the high-frequency power amplifier circuit according to the eighth embodiment. In the high-frequency power amplifier circuit according to the first embodiment (Figure 1), the directional coupler 41 is coupled to the transmission line on the output side of the power amplifier 20. In contrast, in the high-frequency power amplifier circuit according to the eighth embodiment, the directional coupler 41 is coupled to the transmission line on the input side of the power amplifier 20. The high-frequency signal RF caused by the traveling wave in the transmission line Ｔ This is input to the voltage amplitude detection circuit 42. Therefore, the power detection circuit 40 detects the power of the traveling wave input to the power amplifier 20 and sets a detection current I corresponding to the power of the traveling wave. ＯＵＴ Outputs.

[0092] When the power of the forward wave input to the power amplifier 20 exceeds the limiting threshold power, the bias power supply circuit 50 limits the bias power supply current IEC.

[0093] Next, the excellent effects of the eighth embodiment will be described. When the power of the traveling wave input to the power amplifier 20 exceeds the threshold power at which the limiting starts, the bias power supply current IEC is limited, causing the output of the power amplifier 20 to decrease. As a result, the power of the high-frequency signal input to the filter 30 is limited, thus protecting the filter 30.

[0094] Next, a high-frequency power amplifier circuit according to a modification of the eighth embodiment will be described with reference to Figure 17. Figure 17 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a modification of the eighth embodiment. In the high-frequency power amplifier circuit according to the eighth embodiment (Figure 16), the power of the traveling wave is detected by a directional coupler 41 coupled to the transmission line. In contrast, in the modification shown in Figure 17, the voltage of the transmission line on the input side of the power amplifier 20 is directly input to the voltage amplitude detection circuit 42.

[0095] The impedance seen from the output node of the power amplifier 20 to the load side is affected by fluctuations in the input impedance of the antenna. In contrast, the impedance seen from the transmission line on the input side of the power amplifier 20 to the load side does not fluctuate. Therefore, the voltage appearing in the transmission line is proportional to the power of the traveling wave in the transmission line. Consequently, by limiting the bias power supply current IEC based on the voltage of the transmission line on the input side of the power amplifier 20, it is possible to protect the filter 30 in the same way as when limiting based on the power of the traveling wave.

[0096] [Ninth Embodiment] Next, a high-frequency power amplifier circuit according to the ninth embodiment will be described with reference to the drawings from Figure 18 to Figure 19C. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the fourth embodiment, which was described with reference to Figure 11, will be omitted from the explanation.

[0097] Figure 18 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the ninth embodiment. In the high-frequency power amplifier circuit according to the fourth embodiment (Figure 11), the Miller ratio of the first current mirror circuit 51 of the bias power supply circuit 50 is fixed. In contrast, in the high-frequency power amplifier circuit according to the ninth embodiment, the Miller ratio of the first current mirror circuit 51 is variable. The control circuit 35 controls the filter selection switch 31 and adjusts the Miller ratio of the first current mirror circuit 51 according to the selected filter 30. The adjustment of the Miller ratio of the first current mirror circuit 51 is performed, for example, by changing the substantial dimensions of the reference current side transistor. The diagonal arrow attached to the reference side transistor of the first current mirror circuit 51 indicates that its substantial dimensions are variable.

[0098] When the mirror ratio of the first current mirror circuit 51 is changed, the output current I shown in Figure 4A １ The threshold at which the system starts to rise changes. As a result, the threshold at which the bias power supply current IEC limiting begins changes.

[0099] Next, a specific example of the configuration of the first current mirror circuit 51 will be described with reference to Figures 19A, 19B, and 19C. Figures 19A, 19B, and 19C are equivalent circuit diagrams of the first current mirror circuit 51, respectively.

[0100] In the configuration example shown in Figure 19A, a cascode current mirror circuit is used as the first current mirror circuit 51. The first current mirror circuit 51 includes a reference-side cascode connection circuit 51CR and an output-side cascode connection circuit 51CM. Each transistor in the reference-side cascode connection circuit 51CR has a configuration that allows its substantial dimensions to be changed. By changing the substantial dimensions of the transistors in the reference-side cascode connection circuit 51CR, the Miller ratio can be changed. By using a cascode current mirror circuit in the first current mirror circuit 51, current accuracy can be improved.

[0101] Figure 19B is an equivalent circuit diagram of the first current mirror circuit 51 in which the actual dimensions of the transistors in the reference cascode connection circuit 51CR are varied. The reference cascode connection circuit 51CR includes three sets of cascode connection circuits 51CR1, 51CR2, and 51CR3 connected in parallel with each other.

[0102] In the two transistors of the cascode connection circuit 51CR1, the gates are always connected to the drains. In the transistors of the cascode connection circuits 51CR2 and 51CR3, a switch S is connected between the gate and drain. ＧＤ It is inserted, and the gate is switch S ＧＲ It is connected to the ground potential via this.

[0103] Switch S of the cascode connection circuits 51CR2 and 51CR3 ＧＲ Turn on switch S ＧＤ When this is turned off, the cascode connection circuits 51CR2 and 51CR3 become non-conductive. Conversely, the switches S of the cascode connection circuits 51CR2 and 51CR3 ＧＲ Turn it off, switch S ＧＤ When this is turned on, the cascode connection circuits 51CR2 and 51CR3 become conductive. Cascode connection circuit 51CR1 is always conductive.

[0104] By controlling the conduction and non-conductivity of the cascode connection circuits 51CR2 and 51CR3, the effective dimensions of the transistor in the cascode connection circuit 51CR on the reference current side can be changed.

[0105] Figure 19C is an equivalent circuit diagram of the first current mirror circuit 51 in another configuration example. Two branch paths 51B1 and 51B2 are connected in parallel to the reference cascode connection circuit 51CR. Each of the branch paths 51B1 and 51B2 consists of two cascode-connected transistors. A switch S is connected between the gate-drain of the ground-side transistors of each of the branch paths 51B1 and 51B2. ＧＤ It is inserted, and the gate is switch S ＧＲ It is connected to ground potential via [a certain connection]. The gates of the power supply side transistors in each of the branch paths 51B1 and 51B2 are always connected to the drains.

[0106] Switch S of branch routes 51B1 and 51B2 ＧＲ Turn on switch S ＧＤ When this is turned off, branch paths 51B1 and 51B2 become non-conductive. Conversely, the respective switches S of branch paths 51B1 and 51B2 ＧＲ Turn it off, switch S ＧＤ When this is turned on, branch paths 51B1 and 51B2 become conductive. The cascode connection circuit 51CR is always conductive.

[0107] When at least one of the branch paths 51B1 and 51B2 is made conductive, the detected current I ＯＵＴ Because a portion of the current flows through branch paths 51B1 and 51B2, the current flowing through the reference-side cascode connection circuit 51CR decreases. Consequently, the output current flowing through the output-side cascode connection circuit 51CM also decreases. In other words, the same effect as if the Miller ratio of the first current mirror circuit 51 had changed is obtained.

[0108] The first current mirror circuit 51 shown in Figure 19C has fewer switches than the first current mirror circuit 51 shown in Figure 19B. Therefore, the circuit configuration shown in Figure 19C is more advantageous in terms of the area occupied by the first current mirror circuit 51 on the circuit board.

[0109] Next, the excellent effects of the ninth embodiment will be described. In the ninth embodiment, the limiting start threshold for limiting the bias power supply current IEC can be changed by changing the Miller ratio of the first current mirror circuit 51. Therefore, an appropriate limiting start threshold can be set for each filter 30 selected by the filter selection switch 31.

[0110] Next, we will explain the excellent effects of making the actual dimensions of the reference transistor in the first current mirror circuit 51 variable.

[0111] As an example, the Miller ratio can also be changed in a configuration where the dimensions of the reference transistor are fixed and the dimensions of the output transistor are variable. If the reference transistor becomes saturated, the Miller operation cannot be performed correctly. For this reason, it is preferable to determine the dimensions of the reference transistor to match the maximum value of the variable range of the input reference current. If the dimensions of the reference transistor are determined to match the maximum value of the reference current, the accuracy of the output current will decrease in the region where the reference current decreases.

[0112] In the ninth embodiment, the dimensions of the reference transistor are to be designed based on the threshold current at which the bias power supply current IEC is limited. The dimensions of the reference transistor are to be designed so that the accuracy of the output current is sufficiently high near the threshold current. When the reference current exceeds the threshold current, the output of the power amplifier 20 is limited, so a reference current that significantly exceeds the threshold current is not input to the first current mirror circuit 51. For this reason, if the dimensions of the reference transistor are designed based on the threshold current, saturation of the reference transistor can be avoided. For example, the dimensions of the reference transistor are to be determined so that the reference transistor does not saturate even when the maximum output expected when the output of the power amplifier 20 is limited occurs.

[0113] Next, a high-frequency power amplifier circuit according to the tenth embodiment will be described with reference to Figure 20. The following description will omit details of components common to the high-frequency power amplifier circuit according to the second embodiment, which was described with reference to Figures 7, 8A, and 8B.

[0114] Figure 20 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the tenth embodiment. The power detection circuit 40 of the high-frequency power amplifier circuit according to the tenth embodiment includes a delay suppression circuit 49 in addition to the components of the power detection circuit 40 according to the second embodiment (Figure 7). The delay suppression circuit 49 is connected in parallel to the integrating circuit 48 between the input node and the output node of the integrating circuit 48. The integrating circuit 48 is composed of a capacitor 48A and a resistor 48B, similar to the integrating circuit shown in Figure 8A. The delay suppression circuit 49 controls the voltage V input to the integrating circuit 48. ＲＥＣ When the rise is steep, the average voltage V input to the voltage-to-current conversion circuit 43 ＲＥＣＡＶＥ It has a function to suppress startup delays.

[0115] Next, the configuration and operation of the delay suppression circuit 49 will be described. The delay suppression circuit 49 includes a resistive voltage divider circuit 49A, a comparator 49B, and a switching element 49C. For example, an NMOSFET is used as the switching element 49C.

[0116] A resistive voltage divider circuit 49A is connected between the input node of the integrating circuit 48 and the ground potential. The voltage divided by the resistive voltage divider circuit 49A is input to the non-inverting input node of the comparator 49B. The voltage at the output node of the integrating circuit 48 is input to the inverting input node of the comparator 49B. The output node of the comparator 49B is connected to the gate of a switching element 49C, which is made of an NMOSFET. The switching element 49C is connected between the input node and the output node of the integrating circuit.

[0117] When the voltage divided by the resistive voltage divider circuit 49A is higher than the voltage at the output node of the integrating circuit 48, the output node of the comparator 49B goes high. For example, when the voltage at the input node of the integrating circuit 48 is higher than the voltage at the output node of the integrating circuit 48, and the difference between the two is greater than or equal to a first threshold, the output node of the comparator 49B goes high. When the output node of the comparator 49B goes high, the switching element 49C turns on, and the input node and output node of the integrating circuit 48 are short-circuited.

[0118] When the power of the high-frequency signal input to the filter 30 rises sharply, the voltage at the input node of the integrating circuit 48 rises sharply. If the rise of the voltage at the output node of the integrating circuit 48 is delayed compared to the rise of the voltage at the input node, the voltage at the input node becomes significantly higher than the voltage at the output node. As a result, the switching element 49C turns on, and the voltage at the output node rises in sync with the rise of the voltage at the input node. Therefore, the detection current I in response to the sharp rise in the power of the high-frequency signal ＯＵＴ The startup delay is suppressed.

[0119] Furthermore, when the switching element 49C is turned on, the output node of the voltage amplitude detection circuit 42 is short-circuited to the capacitor 48A of the integrating circuit 48, so that the capacitor 48A is charged with a short time constant. When the capacitor 48A is charged, the voltage at the output node rises rapidly in response to the voltage rise at the input node of the integrating circuit 48. Therefore, the detection current I in response to the rise in power of the high-frequency signal ＯＵＴ The startup delay is suppressed.

[0120] Next, the excellent effects of the tenth embodiment will be described. In the tenth embodiment, when the power of the high-frequency signal input to the filter 30 rises rapidly, the detected current I ＯＵＴ The signal rises with low latency. As a result, the bias current supplied to the power amplifier 20 decreases, and the output of the power amplifier 20 is suppressed. Therefore, the protection function of the filter 30 during the rapid rise of high-frequency signals can be enhanced.

[0121] Next, a modified example of the tenth embodiment will be described. In the tenth embodiment, when the switching element 49C is turned on, the input node and output node of the integrating circuit 48 are substantially short-circuited. However, the input node and output node of the integrating circuit 48 may be connected with a low resistance. For example, the delay suppression circuit 49 may be configured to connect the input node and output node of the integrating circuit 48 with a resistance value lower than the electrical resistance of the integrating circuit 48 itself between the input node and output node of the integrating circuit 48 (for example, the resistance value of the resistive element 48B).

[0122] In this configuration, the effective time constant of the integrating circuit 48, including the delay suppression circuit 49, becomes shorter than the time constant of the integrating circuit 48 itself. Therefore, the delay between the rise of the voltage at the output node and the rise of the voltage at the input node of the integrating circuit 48 can be suppressed.

[0123] The embodiments described above are illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects and benefits from similar configurations in multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the embodiments described above. For example, it will be obvious to those skilled in the art that various modifications, improvements, and combinations are possible.

[0124] 20 Power amplifier 21 Input capacitor 22 Ballast resistor 25 Bias circuit 25D Diode circuit 25Q Emitter follower transistor 25R Resistor 26 Bias control circuit 28a First amplification system 28b Second amplification system 30 Filter 31 Filter selection switch 32 Antenna switch 33 Antenna terminal 35 Control circuit 40 Power detection circuit 41 Directional coupler 42, 42R, 42T Voltage amplitude detection circuit 42A DC cut capacitor 42B Resistor 42C Bias circuit 42D NMOS transistor 42E Resistor 42F Fundamental wave rejection filter 43, 43R, 43T Voltage-current conversion circuit 43A Op-amp 43B Resistor 43C PMOS current mirror circuit 44 Threshold voltage source 45 Comparator 46 Subtraction circuit 47 Multiplexer 48 Integrating circuit 48A Capacitor 48B Resistor 48C Op-amp 48D Resistor 48E Feedback resistor 48F Feedback capacitor 48G Pull-down resistor 49 Delay suppression circuit 49A Resistor voltage divider circuit 49B Comparator 49C Switching element 50 Bias power supply circuit 51, 51R, 51T First current mirror circuit 51B1, 51B2 Branch path 51CM Output side cascode connection circuit 51CR, 51CR1, 51CR2, 51CR3 Reference side cascode connection circuit 52, 52R, 52T Second current mirror circuit 53 Third current mirror circuit 55, 55R, 55T First current source 55A, 55B PMOS current mirror circuit 55C Resistor 55D Diode 55E Resistor element 56 Second current source 61 First chip 62 Second chip 80, 81 Impedance matching circuit 90 Input node 91 Output node

Claims

1. A high-frequency power amplifier comprising: a power amplifier for amplifying a high-frequency signal; at least one filter for filtering the high-frequency signal output from the power amplifier; a bias circuit for supplying a bias to the power amplifier; a power detection circuit for outputting a detectable physical quantity that depends on the power of the traveling wave in the input transmission line of the power amplifier, or the power of at least one of the traveling wave and the reflected wave in the output transmission line of the power amplifier; and a bias power supply circuit for supplying a bias power supply current to the bias circuit, wherein the bias circuit generates a bias to be supplied to the power amplifier based on the bias power supply current, and the bias power supply circuit is configured to decrease the bias power supply current in proportion to the increase in the detectable physical quantity when the detectable physical quantity exceeds a limit start threshold.

2. The detection physical quantity is current, and the bias power supply circuit includes: a first current mirror circuit that uses the detection physical quantity as a reference current; a first current source that outputs a current that determines the limit start threshold; a second current mirror circuit that uses as a reference current the current obtained by subtracting the current generated by the first current source from the output current of the first current mirror circuit; a second current source; and a third current mirror circuit that uses as a reference current the current obtained by subtracting the output current of the second current mirror circuit from the current generated by the second current source, and outputs the bias power supply current as the output current.

3. The high-frequency power amplifier circuit according to claim 2, wherein the first current source has a temperature characteristic that reduces the output current as the temperature rises.

4. The high-frequency power amplifier circuit according to any one of claims 1 to 3, wherein the at least one filter includes a plurality of filters with different passbands, and comprises a filter selection switch that transmits a high-frequency signal output from the power amplifier to one of the plurality of filters selected from the plurality of filters, and the power detection circuit outputs the detected physical quantity which depends on the power of at least one of the forward wave and the reflected wave transmitted in the transmission line between the power amplifier and the filter selection switch.

5. A high-frequency power amplifier according to any one of claims 1 to 4, wherein the power amplifier, the bias circuit, and the at least one filter constitute a first amplification system, further comprising a second amplification system including another power amplifier for amplifying a high-frequency signal, another bias circuit for supplying bias to the other power amplifier based on the bias power supply current, and at least one other filter for filtering the high-frequency signal output from the other power amplifier, an antenna terminal to which an antenna is connected, and an antenna switch for connecting one of the output nodes of the first amplification system and the second amplification system to the antenna terminal, wherein the power detection circuit outputs the detected physical quantity which depends on the power of at least one of the forward wave and reflected wave in the transmission line between the antenna switch and the antenna terminal, and the bias power supply circuit supplies the bias power supply current to the bias circuit of the first amplification system and the bias circuit of the second amplification system.

6. The high-frequency power amplifier circuit according to any one of claims 1 to 5, wherein the power detection circuit outputs the detected physical quantity based on the power of the forward wave and the reflected wave, and the bias power supply circuit holds the limit start threshold for each of the detected physical quantities, and when one of the detected physical quantities exceeds the limit start threshold, the bias power supply current is reduced in proportion to the increase in the detected physical quantity, and when the other detected physical quantity also exceeds the limit start threshold, the bias power supply current is reduced more sharply in proportion to the increase in the detected physical quantity.

7. The high-frequency power amplifier circuit according to any one of claims 1 to 3, wherein the power detection circuit outputs the detected physical quantity which depends on the power of the traveling wave in the transmission line on the input side of the power amplifier.

8. The high-frequency power amplifier circuit according to claim 2, wherein the at least one filter includes a plurality of filters with different passbands, and further includes a filter selection switch that transmits a high-frequency signal output from the power amplifier to one of the plurality of filters selected from the plurality of filters, the power detection circuit outputs the detected physical quantity which depends on the power of at least one of the forward wave and the reflected wave in the transmission line between the power amplifier and the filter selection switch, and the first current mirror circuit is configured such that the mirror ratio changes according to the filter selected by the filter selection switch.

9. The high-frequency power amplifier circuit according to claim 2, wherein the at least one filter includes a plurality of filters with different passbands, and further includes a filter selection switch that transmits a high-frequency signal output from the power amplifier to one of the plurality of filters selected from the plurality of filters, the power detection circuit outputs the detected physical quantity which depends on the power of at least one of the forward wave and the reflected wave in the transmission line between the power amplifier and the filter selection switch, and the bias power supply circuit includes at least one branch path connected in parallel with the reference current path of the first current mirror circuit, the branch path being configured such that conduction and non-conductivity change depending on the filter selected by the filter selection switch.

10. The high-frequency power amplifier circuit according to any one of claims 1 to 9, wherein the power detection circuit comprises: a directional coupler coupled to the input transmission line of the power amplifier or the output transmission line of the power amplifier; a voltage amplitude detection circuit that outputs a voltage corresponding to the amplitude of the voltage of the high-frequency signal output from the directional coupler; and a voltage-current conversion circuit that converts the voltage output from the voltage amplitude detection circuit into a current and outputs the converted current as the detected physical quantity.

11. The high-frequency power amplifier circuit according to any one of claims 1 to 10, wherein the power detection circuit includes an integration circuit that calculates the average value over a certain period of the power of the traveling wave in the transmission line on the input side of the power amplifier, or the power of at least one of the traveling wave and reflected wave in the transmission line on the output side of the power amplifier, and outputs the detected physical quantity based on the average value after integration.

12. The high-frequency power amplifier circuit according to claim 11, wherein the power detection circuit includes a delay suppression circuit connected in parallel with the integrating circuit, and the delay suppression circuit connects the input node of the integrating circuit and the output node of the integrating circuit with a resistance value lower than the electrical resistance of the integrating circuit itself between the input node and the output node of the integrating circuit when the voltage at the input node of the integrating circuit is higher than the voltage at the output node of the integrating circuit and the difference between the voltage at the input node of the integrating circuit and the voltage at the output node of the integrating circuit is greater than or equal to a first threshold.

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