Semiconductor device

Abstract

Provided is a semiconductor device enabling execution of high-precision AD conversion.　This semiconductor device comprises: a first chopper circuit to which a differential analog signal is inputted; a programmable gain amplifier connected to an output side of the first chopper circuit and having a pair of second chopper circuits for chopping a differential input signal and a differential output signal; a ΔΣ analog-to-digital converter that includes an integrator connected to an output side of the programmable gain amplifier and having a pair of third chopper circuits for chopping a differential input signal and differential output signal of the integrator, and a quantizer connected to an output side of the integrator; and a fourth chopper circuit for chopping and outputting the output of the quantizer. The first chopper circuit and fourth chopper circuit, the pair of second chopper circuits, and the pair of third chopper circuits are driven by patterns generated according to different rules depending on operating frequency.

Description

Semiconductor equipment

[0001] This disclosure relates to semiconductor devices.

[0002] Conventionally, there is an integrated circuit that includes an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to the output side of the amplifier, a buffer circuit coupled to the output side of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to the output of the buffer circuit, and a plurality of nested chopping circuits, the first pair of chopping circuits having at least the amplifier positioned between them and configured to remove the offset of the analog input signal, and the second pair of chopping circuits having at least the first pair of chopping circuits positioned between them, wherein the amplifier, the AAF, the sigma-delta modulator and the chopping circuits are formed on the same integrated circuit board (see, for example, Patent Document 1).

[0003] Japanese Patent Publication No. 2022-008258

[0004] Incidentally, conventional integrated circuits do not specify the relationship between the frequency at which the amplifier chops and the frequency at which the sigma-delta modulator chops. Therefore, when the amplifier output is integrated by the sigma-delta modulator, the offset of the operational amplifier's output accumulates, which may reduce the accuracy of the analog-to-digital (AD) conversion.

[0005] Therefore, the objective is to provide a semiconductor device capable of performing high-precision AD conversion.

[0006] A semiconductor device according to an embodiment of the present disclosure includes a first chopping circuit to which a differential analog signal is input; a programmable gain amplifier connected to the output side of the first chopping circuit, having a pair of second chopping circuits for chopping the differential input signal and differential output signal of the programmable gain amplifier; a ΔΣ type analog-to-digital converter having an integrator connected to the output side of the programmable gain amplifier, having a pair of third chopping circuits for chopping the differential input signal and differential output signal of the integrator; and a quantizer connected to the output side of the integrator; and a fourth chopping circuit that chops and outputs the output of the quantizer, wherein the first chopping circuit, the fourth chopping circuit, the pair of second chopping circuits, and the pair of third chopping circuits are driven by patterns generated according to different rules depending on the operating frequency.

[0007] We can provide a semiconductor device capable of performing high-precision AD conversion.

[0008] This figure shows an example of the configuration of the semiconductor device 100 of the embodiment. This figure illustrates an example of a fractal sequence. This is a timing chart showing an example of the operation of the semiconductor device 100 of the embodiment. This figure illustrates an example of the effect of a fractal sequence.

[0009] The following describes embodiments applying the semiconductor device of this disclosure.

[0010] <Embodiment> Figure 1 shows an example of the configuration of the semiconductor device 100 according to the embodiment. The semiconductor device 100 includes a chopping circuit 110, a PGA (Programmable Gain Amplifier) ​​120, an n-th order ΔΣ type ADC (Analog to Digital Converter) 130, a chopping circuit 140, a digital filter 150, and a chopping control unit 160.

[0011] As an example, the semiconductor device 100 is configured as one IC (Integrated Circuit) package. As an example, the PGA 120 and the nth-order ΔΣ-type ADC 130 are an AFE (Analog Front End) that digitally converts (AD converts) an analog signal input from an unillustrated analog circuit and outputs the converted signal.

[0012] The chopping circuit 110 is an example of a first chopping circuit. The PGA 120 is an example of a programmable gain amplifier. The nth-order ΔΣ-type ADC 130 is an example of a ΔΣ-type analog-to-digital converter. The chopping circuit 140 is an example of a fourth chopping circuit. The digital filter 150 is an example of an averaging processing unit.

[0013] <Chopping Circuit 110> The chopping circuit 110 has two input terminals connected to input terminals 101 and 102 to which differential input signals (+) and (-) are input from an unillustrated analog circuit, and two output terminals respectively connected to two input terminals of the PGA 120. In accordance with a chopping signal Chop3 input from a chopping control unit 160, the chopping circuit 110 performs either a first operation of not inverting the signs of the differential input signals (+) and (-), or a second operation of inverting the signs of the differential input signals (+) and (-). The chopping circuit 110 performs the first operation when the chopping signal Chop3 is at H (High) level, and performs the second operation when the chopping signal Chop3 is at L (Low) level. Since the chopping signal Chop3 is also input to the chopping circuit 140, the chopping circuit 110 performs either the first operation or the second operation together with the chopping circuit 140.

[0014] The first operation is an operation that does not invert the output value with respect to the input value over a plurality of consecutive cycles of the sampling frequency fs of the semiconductor device 100. The second operation is an operation that inverts the output value with respect to the input value over a plurality of consecutive cycles of the sampling frequency fs of the semiconductor device 100. The first operation and the second operation are operations for oversampling. The sampling frequency fs is an example of an operating frequency. Note that the semiconductor device 100 continuously repeats the first operation and the second operation by performing the first operation after the second operation. Details of this will be described later with reference to FIG. 4.

[0015] <PGA120> The PGA 120 is connected to the output side of the chopping circuit 110, and includes two differential input differential output operational amplifiers 121, two chopping circuits 122A, and two chopping circuits 122B.

[0016] One chopping circuit 122A is connected to the input side of each operational amplifier 121. More specifically, two output terminals of the upper chopping circuit 122A are connected to the non-inverting input terminal (+) and the inverting input terminal (-) of the upper operational amplifier 121. Two output terminals of the lower chopping circuit 122A are connected to the non-inverting input terminal (+) and the inverting input terminal (-) of the lower operational amplifier 121.

[0017] One chopping circuit 122B is connected to the output side of each operational amplifier 121. More specifically, two input terminals of the upper chopping circuit 122B are connected to the non-inverting output terminal (+) and the inverting output terminal (-) of the upper operational amplifier 121. Two input terminals of the lower chopping circuit 122A are connected to the non-inverting output terminal (+) and the inverting output terminal (-) of the lower operational amplifier 121.

[0018] The operational amplifier 121 is an example of a first operational amplifier of the differential input differential output type. The pair of chopping circuits 122A and 122B connected to the input and output sides of each operational amplifier 121 are an example of a pair of second chopping circuits. The PGA 120 may have a circuit configuration in which multiple amplification circuits are connected in series, each consisting of a pair of chopping circuits 122A and 122B and an operational amplifier 121 connected between the pair of chopping circuits 122A and 122B. Each operational amplifier 121 has an offset. Therefore, in order to accurately adjust the offset of each operational amplifier 121, it is preferable that a pair of chopping circuits 122A and 122B be connected to each operational amplifier 121.

[0019] Furthermore, three resistors are connected between the output terminals of the two chopping circuits 122B. The output terminals of the two chopping circuits 122B are connected to the two input terminals of the first stage integrator 130AA1 of the integrating circuit 130A, respectively.

[0020] In Figure 1, the upper input terminal of the upper chopping circuit 122A is connected to the upper output terminal of the chopping circuit 110, and the lower input terminal of the lower chopping circuit 122A is connected to the lower output terminal of the chopping circuit 110. The lower input terminal of the upper chopping circuit 122A is connected between the first and second resistors from the top of the three resistors, and the upper input terminal of the lower chopping circuit 122A is connected between the second and third resistors from the top of the three resistors.

[0021] A chopping control unit 160 is connected to the chopping circuits 122A and 122B, and a chopping signal Chop2 is input to it. When the chopping signal Chop2 is at a high level, the chopping circuits 122A and 122B output the input signal without inverting it, and when the chopping signal Chop2 is at a low level, they output the input signal after inverting it.

[0022] Both chopping circuits 122A and 122B perform operations that invert the input signal before outputting it, as well as operations that output the input signal without inverting it. This reduces the offset included in the output of the operational amplifier 121. The details of this will be described later.

[0023] <n-th order ΔΣ type ADC 130> The n-th order ΔΣ type ADC 130 has an integrating circuit 130A and a quantizer 130B. The n-th order integrating circuit 130A has n-stage integrators 130AA1 to 130AAn. The configuration of the n-stage integrators 130AA1 to 130AAn is the same as an example. Hereafter, unless otherwise specified, the n-stage integrators 130AA1 to 130AAn will simply be referred to as integrator 130AA. Note that n can be any integer greater than or equal to 1, but Figure 1 shows a configuration where n is 2 or greater as an example.

[0024] The integrator 130AA includes a differential input / differential output operational amplifier 131, two chopping circuits 132A and 132B, and two switched capacitors 133. The operational amplifier 131 is an example of a differential input / differential output second operational amplifier. The chopping circuits 132A and 132B are connected to the input and output sides of the operational amplifier 131, respectively. The pair of chopping circuits 132A and 132B connected to the input and output sides of the operational amplifier 131 is an example of a pair of third chopping circuits.

[0025] More specifically, in the first stage integrator 130AA1, the upper input terminal of the chopping circuit 132A is connected to the upper output terminal of the PGA 120, and the lower input terminal of the chopping circuit 132A is connected to the lower output terminal of the PGA 120. The upper output terminal of the chopping circuit 132A is connected to the non-inverting input terminal (+) of the operational amplifier 131, and the lower output terminal of the chopping circuit 132A is connected to the inverting input terminal (-) of the operational amplifier 131.

[0026] The inverting output terminal (-) of the operational amplifier 131 is connected to the upper input terminal of the chopping circuit 132B, and the non-inverting output terminal (+) of the operational amplifier 131 is connected to the lower input terminal of the chopping circuit 132B. The upper output terminal of the chopping circuit 132B is connected to the upper input terminal of the next stage integrator 130AA, and the lower output terminal of the chopping circuit 132B is connected to the lower input terminal of the next stage integrator 130AA.

[0027] An upper switched capacitor 133 is connected between the upper input terminal and the upper output terminal of the integrator 130AA, and a lower switched capacitor 133 is connected between the lower input terminal and the lower output terminal of the integrator 130AA.

[0028] The n-stage integrators 130AA1 to 130AAn are connected in series with each other. In other words, the n-stage integrators 130AA1 to 130AAn are cascaded. Furthermore, the two output terminals of the nth (final) stage integrator 130AAn are connected to the two input terminals of the quantizer 130B.

[0029] A chopping control unit 160 is connected to the chopping circuits 132A and 132B, and a chopping signal Chop1 is input to it. When the chopping signal Chop1 is at a high level, the chopping circuits 132A and 132B output the input signal without inverting it, and when the chopping signal Chop1 is at a low level, they output the input signal after inverting it.

[0030] Both chopping circuits 132A and 132B perform operations that invert the input signal before outputting it, as well as operations that output the input signal without inverting it. This reduces the offset included in the output of the operational amplifier 131. The details of this will be described later.

[0031] The output terminal of the quantizer 130B is connected to the input terminal of the chopping circuit 140. The quantizer 130B digitally converts the output of the nth stage (final stage) integrator 130AAn and outputs it to the chopping circuit 140.

[0032] <Chopping Circuit 140> The chopping circuit 140 includes a MUX 141 and an inverting unit 142. The upper of the two input terminals of the MUX 141 is connected to the output terminal of the quantizer 130B, and the lower input terminal is connected to the output terminal of the quantizer 130B via the inverting unit 142.

[0033] A chopping control unit 160 is connected to the selection signal input terminal of MUX141, and a chopping signal Chop3 is input to it. MUX141 outputs one of the signals input to the two input terminals according to the chopping signal Chop3.

[0034] MUX141 performs either a first operation, which is receiving the output of the quantizer 130B without inverting its sign, or a second operation, which is receiving the output of the quantizer 130B after inverting its sign using the inverting unit 142, based on the chopping signal Chop3 input from the chopping control unit 160. MUX141 performs the first operation when the chopping signal Chop3 is at a high level, and performs the second operation when the chopping signal Chop3 is at a low level.

[0035] By having both the chopping circuit 110 and the MUX 141 perform a first operation and a second operation together according to the chopping signal Chop3, the offset of outputs other than the operational amplifiers 121, 131, etc., included in the PGA 120 and the nth-order ΔΣ type ADC 130 can be reduced.

[0036] <Digital Filter 150> The digital filter 150 performs averaging on the output of the chopping circuit 140. The digital filter 150 calculates the average value of the first output value obtained from the chopping circuit 140 while the chopping circuits 110 and 140 are performing the first operation, and the second output value obtained from the chopping circuit 140 while the chopping circuits 110 and 140 are performing the second operation.

[0037] <Chopping Control Unit 160> The chopping control unit 160 is, for example, an electronic circuit such as an MCU (Micro Controller Unit), FPGA (Field Programmable Gate Array), or ASIC (Application Specific Integrated Circuit). The chopping control unit 160 controls the chopping operation of the semiconductor device 100 as a whole by executing instruction codes stored in memory and outputting chopping signals Chop1, Chop2, and Chop3.

[0038] The chopping signal Chop1 is input to the chopping circuits 132A and 132B of the integrators 130AA1 to 130AAn. The chopping signal Chop2 is input to the chopping circuits 122A and 122B of the PGA 120. The chopping signal Chop3 is input to the chopping circuits 110 and 140.

[0039] The chopping signal Chop1 is a signal whose H level and L level are set by a fractal sequence based on the sampling frequency fs. When it is at the H level, the chopping circuits 132A and 132B do not invert the input signal. When it is at the L level, the chopping circuits 132A and 132B invert the input signal. The chopping signal Chop1 transitions between the H level and the L level by a fractal sequence having the rules shown in Figure 2, which will be described later.

[0040] The chopping signal Chop2 is a signal that transitions between high and low levels at half the sampling frequency fs (fs / 2). The meaning of the high and low levels of the chopping signal Chop2 is the same as that of the chopping signal Chop1. When it is at the high level, the chopping circuits 122A and 122B do not invert the sign of the input signal. When it is at the low level, the chopping circuits 122A and 122B invert the sign of the input signal.

[0041] The chopping signal Chop3 is a signal for oversampling, and is a signal for performing either a first operation of not inverting the sign of differential input signals (+) and (-) or a second operation of inverting the sign of differential input signals (+) and (-) over a plurality of cycles of the sampling frequency fs.

[0042] The meanings of the H level and L level of the chopping signal Chop3 are the same as those of the chopping signals Chop1 and Chop2. When the signal is at H level, the chopping circuits 110 and 140 perform the first operation and do not invert the sign of the input signal. When the signal is at L level, the chopping circuits 110 and 140 perform the second operation and invert the sign of the input signal.

[0043] <Reason for using a fractal sequence in integration circuit 130A> The semiconductor device 100 is driven by chopping signals Chop1, Chop2, and Chop3, and the output of the MUX 141 when the chopping circuits 110 and 140 are performing the first operation is AD １ , and the output of the MUX 141 when the chopping circuits 110 and 140 are performing the second operation is AD ２ .

[0044] Output AD １ and AD ２ can be expressed as follows. Vdiff is the voltage difference between the differential input signals (+) and (-), and Voffset is the offset voltage included in output AD １ and AD ２ . AD １ = Vdiff + Voffset AD ２ = Vdiff - Voffset

[0045] If the digital filter 150 calculates the average output AD of output AD １ and AD ２ , the average output AD is obtained as follows. AD = (AD １ + AD ２ ) ÷ 2 = {(Vdiff + Voffset) + (Vdiff - Voffset)} ÷ 2 = Vdiff

[0046] The average output AD calculated in this way does not include the offset voltage Voffset, and thus the offset voltage Voffset can be reduced.

[0047] For the PGA120, the offset voltage and low-frequency error can be reduced by chopping the chopping circuits 122A and 122B, which are provided on the input and output sides of the operational amplifier 121, with a chopping signal Chop2 at a frequency of fs / 2. This is a common technique.

[0048] However, the integrating circuit 130A performs integration in each integrator 130AA. Therefore, even if the chopping circuits 132A and 132B provided on the input and output sides of the operational amplifier 131 are chopped with a chopping signal of frequency fs / 2, for example, the integrating circuit 130A, in which the integrators 130AA are cascaded, cannot completely reduce the effect of the offset.

[0049] For these reasons, in the semiconductor device 100, the integrator 130AA of the integration circuit 130A is chopped using a fractal sequence to enhance the reduction of the offset.

[0050] Figure 2 illustrates an example of a fractal sequence. In Figure 2, the high level in the fractal sequence is represented by +, and the low level is represented by -. In other words, a fractal sequence is a signal that has both a + (which does not invert the input signal) and a - (which inverts the input signal).

[0051] When the order n of the integrating circuit 130A is 1, the fractal sequence is S １ It is represented by = (+ -). The sign of + and - is switched with each sampling period. S １ The (+ / -) sign represents the signal for one period of the fractal sequence. １ The length of the period of = (+-) is the length of two sampling periods. Also, for this reason, S １ The frequency of the (+ / -) sign is half the sampling frequency fs.

[0052] If the order n of the integrating circuit 130A is 2 or greater, then, if the order n is k, the fractal sequence is Sｋ = [S ｋ－１ , -S ｋ－１ It is represented by ]. S ｋ = [S ｋ－１ , -S ｋ－１ ] is the signal for one period of a fractal sequence when the order n is k (k≧2), S ｋ = [S ｋ－１ , -S ｋ－１ The length of the period of ] is S １ = (+-) period 2 (ｋ－１) It is twice as long. Therefore, S ｋ＋１ = [S ｋ , -S ｋ The frequency of ] is S １ = (+ / -) is 1 / k of the frequency.

[0053] Specifically, when the order n of the integrating circuit 130A is 2, the fractal sequence is S ２ = [S １ , -S １ ] = (+--+). S ２ = [S １ , -S １ ] = (+--+) is the signal for one period of the fractal sequence when the order n is 2. The signs + and - are switched with each sampling period, so the fractal sequence S ２ = [S １ , -S １ The length of the period of ] = (+--+) is four times the length of the sampling period. Therefore, S ２ The length of the period of = (+--+) is S １ = (+-) is twice the length of the period, S ２ The frequency of = (+--+) is S １ = (+ -) is half the frequency.

[0054] The same applies when the order n of the integrating circuit 130A is 3 or greater, and the length of the period of the fractal sequence is S １ = The length of the period of (+-) is k (k≧3), and the frequency of the fractal sequence is S １ The frequency becomes 1 / k (k≧3) of the (+-) frequency. In other words, as the order n of the integrating circuit 130A increases, the frequency of the fractal sequence decreases.

[0055] Furthermore, the fractal sequences input to the chopping circuits 132A and 132B of all integrators 130AA1 to 130AAn in the integration circuit 130A are identical.

[0056] Also, Figure 2 shows S ｋ = [S ｋ－１ , -S ｋ－１ The fractal sequence represented by ] is shown. Note that S ｋ = [S ｋ－１ , -S ｋ－１ The pattern is not limited to the one represented by [], but may also be a pattern in which the signs of + and - change.

[0057] <Chopping signals Chop1, Chop2, Chop3> Figure 3 is a timing chart showing an example of the operation of the semiconductor device 100 of the embodiment.

[0058] Figure 3 shows a clock with sampling frequency fs and chopping signals Chop1, Chop2, and Chop3. One period of the clock with sampling frequency fs is the sampling period.

[0059] <Chopping signal Chop1> The chopping signal Chop1 is a signal whose H level (+) and L level (-) are set by a fractal sequence based on the sampling frequency fs, and the rising edge of the first H level in the fractal sequence is synchronized with the rising edge of the sampling frequency clock.

[0060] Figure 3 shows a fractal sequence S as an example. ２ The chopping signal Chop1 is shown, which is composed of the fractal sequence S. ２ = [S １ , -S １ The sign of ] = (+--+) switches between +, -, -, + for each of the four sampling periods.

[0061] <Chopping signal Chop2> The chopping signal Chop2 is a signal that transitions between high and low levels at half the sampling frequency fs (fs / 2), and the rising edge of the first high level of the chopping signal Chop2 is synchronized with the rising edge of the sampling frequency clock.

[0062] <Chopping signal Chop3> Chopping signal Chop3 is a signal for oversampling, and the first rising high level of chopping signal Chop3 is synchronized with the rising edge of the sampling frequency clock. Since chopping signal Chop3 is a signal for oversampling, it has a longer period than the sampling period, the period of chopping signal Chop1, and the period of chopping signal Chop2.

[0063] The semiconductor device 100 performs AD conversion according to the chopping signal Chop3. Figure 3 shows four AD conversions (1) to (4). The period during AD conversions (1) and (3) when the chopping signal Chop3 is at a high level is the period during which the chopping circuits 110 and 140 perform their first operation. The period during AD conversions (2) and (4) when the chopping signal Chop3 is at a low level is the period during which the chopping circuits 110 and 140 perform their second operation.

[0064] <Calculation of average value by digital filter 150> The digital filter 150 calculates the average value of the output obtained from the chopping circuit 140 during the period when the chopping signal Chop3 is at a high level and the output obtained from the chopping circuit 140 during the period when the chopping signal Chop3 is at a low level. In this way, the digital filter 150 performs an averaging process on the output of the chopping circuit 140.

[0065] For the AD conversions (1) to (4) shown in Figure 3, the digital filter 150 calculates the average value of the output obtained from the chopping circuit 140 during the AD conversion (1) period and the output obtained from the chopping circuit 140 during the AD conversion (2) period. The digital filter 150 also calculates the average value of the output obtained from the chopping circuit 140 during the AD conversion (2) period and the output obtained from the chopping circuit 140 during the AD conversion (3) period. The digital filter 150 also calculates the average value of the output obtained from the chopping circuit 140 during the AD conversion (3) period and the output obtained from the chopping circuit 140 during the AD conversion (4) period. In this way, by performing the averaging process while shifting the AD conversion periods one by one, high-precision AD conversion can be efficiently performed.

[0066] Note that the chopping signals Chop1 to 3 shown in Figure 3 are just examples. Chopping signals Chop1 to 3 are patterns generated according to different rules depending on the sampling frequency.

[0067] <Effects of Fractal Sequences> Figure 4 illustrates an example of the effects of fractal sequences. Figure 4 shows the results of comparing the offset voltages of output (1), output (2), and output (3) under three conditions. Output (1) is the output of chopping circuit 132B when op-amp 131 and chopping circuits 132A and 132B are considered as a single circuit. Output (2) is the output of the first stage integrator 130AA1. Output (3) is the output of the second stage integrator 130AA2. Figure 4 shows the offset voltages included in output (1), output (2), and output (3).

[0068] The three conditions concern chopping. Condition (1) is that no chopping is performed in the chopping circuits 132A and 132B (no chopping). Condition (2) is that chopping is performed by setting the frequency of the chopping signal input to the chopping circuits 132A and 132B to fs / 2. Condition (3) is that the chopping signal input to the chopping circuits 132A and 132B is a fractal sequence S ２ The condition for performing chopping is set to (+--+).

[0069] In condition (1), since no chopping occurs, the offset voltage of output (1) takes a positive value, the offset voltage of the output of integrator 130AA1 (output (2)) gradually increases, and the offset voltage of the output of integrator 130AA2 (output (3)) increases significantly.

[0070] In the case of condition (2), chopping is performed at frequency fs / 2, so the offset voltage of output (1) takes positive and negative values ​​around zero, and the offset voltage of the output of integrator 130AA1 (output (2)) takes the integral value of output (1) and is almost completely removed. However, the offset voltage of the output of integrator 130AA2 (output (3)) will increase due to the accumulation of the small offset voltage included in the output of integrator 130AA1.

[0071] In the case of condition (3), chopping is performed according to the fractal sequence, so the offset voltage of output (1) takes positive and negative values ​​around zero, the offset voltage of the output of integrator 130AA1 (output (2)) takes the integral value of output (1), and the offset voltage of the output of integrator 130AA2 (output (3)) takes the integral value of output (2), and neither increases.

[0072] Thus, by using a fractal sequence, the reduction of the output offset voltage can be enhanced in an integrating circuit 130A in which multiple integrators 130AA are cascaded. This is an effect of using a fractal sequence.

[0073] Therefore, the semiconductor device 100 can reduce the offset voltage included in the output of the integrating circuit 130A, enabling high-precision AD conversion.

[0074] <Effects> The semiconductor device 100 of this disclosure includes a chopping circuit 110 to which a differential analog signal is input, a PGA 120 connected to the output side of the chopping circuit 110, the PGA 120 having a pair of chopping circuits 122A and 122B that chop the differential input signal and differential output signal of the PGA 120, and an integrator 130AA connected to the output side of the PGA 120, the integrator 130AA having a pair of chopping circuits that chop the differential input signal and differential output signal of the integrator 130AA The ΔΣ type ADC 130 includes an integrator 130AA having 132A and 132B, and a quantizer 130B connected to the output side of the integrator 130AA, and a chopping circuit 140 that chops the output of the quantizer 130B and outputs the result. The chopping circuits 110 and 140, the pair of chopping circuits 122A and 122B, and the pair of chopping circuits 132A and 132B are driven by patterns generated according to different rules depending on the operating frequency. As a result, the chopping circuit 110, PGA 120, integrator 130A, and chopping circuit 140 can reduce the offset voltage of the entire system.

[0075] Therefore, it is possible to provide a semiconductor device 100 capable of performing high-precision AD conversion.

[0076] Furthermore, the PGA 120 may further include a differential input, differential output operational amplifier 121 connected between a pair of chopping circuits 122A and 122B. This allows the offset voltage of the operational amplifier 121 to be reduced by the pair of chopping circuits 122A and 122B, enabling high-precision AD conversion.

[0077] Furthermore, the PGA 120 may have a circuit configuration in which multiple amplification circuits are connected in series, each consisting of a pair of chopping circuits 122A and 122B and a differential input / differential output operational amplifier 121 connected between the pair of chopping circuits 122A and 122B. Therefore, the offset voltage of each operational amplifier 121 can be reduced by the pair of chopping circuits 122A and 122B, enabling high-precision AD conversion. Also, since each operational amplifier 121 has an offset, by providing one operational amplifier 121 between each pair of chopping circuits 122A and 122B, the offset voltages of multiple operational amplifiers 121 can be adjusted with high precision.

[0078] Furthermore, the ΔΣ type ADC 130 has n stages (where n is an integer of 1 or more) of integrators 130AA, and each of the n stages of integrators 130AA1 to 130AAn may further have a differential input differential output type operational amplifier 131 connected between a pair of chopping circuits 132A and 132B. Therefore, the offset voltage of the operational amplifier 131 can be reduced by the pair of chopping circuits 132A and 132B, enabling high-precision AD conversion.

[0079] Furthermore, the system includes a chopping control unit 160 that controls the driving of a pair of chopping circuits 122A and 122B and a pair of chopping circuits 132A and 132B. The chopping control unit 160 may perform chopping of the chopping circuits 122A and 122B at a frequency of fs / 2, which is half the operating frequency fs, and may also perform chopping of the chopping circuits 132A and 132B according to a fractal sequence based on the operating frequency fs. This effectively reduces the offset included in the output of the PGA 120 and the output of the integrating circuit 130A, enabling more accurate AD conversion.

[0080] Furthermore, the ΔΣ type ADC 130 includes a chopping control unit 160 that controls the driving of the chopping circuits 132A and 132B, and the ΔΣ type ADC 130 has n (where n is an integer of 1 or more) stages of integrators 130AA, and the chopping control unit 160 controls the driving of n pairs of chopping circuits 132A and 132B of n stages of integrators 130AA1 to 130AAn, and if non-inversion of the sign in chopping is + and inversion is -, then when n is 1, 2, ..., k, S １ = (+-), S ２ = [S １ , -S １ ] = (+--+), ..., S ｋ＋１ = [S ｋ , -S ｋ The n pairs of chopping circuits 132A and 132B may be chopped by switching + and - according to the operating frequency according to the fractal sequence represented by [ ]. By using a fractal sequence, the offset included in the output of the n-stage integrators 130AA1 to 130AAn can be effectively reduced, enabling more accurate AD conversion.

[0081] The system further includes a chopping control unit 160 that controls the driving of chopping circuits 110 and 140, and a digital filter 150 that performs averaging processing on the output of chopping circuit 140. The chopping control unit 160 causes chopping circuits 110 and 140 to continuously perform a first operation over multiple consecutive periods of the operating frequency, in which the output value does not invert with respect to the input value, and a second operation over multiple consecutive periods of the operating frequency, in which the output value inverts with respect to the input value. The digital filter 150 may calculate the average value of a first output value obtained from chopping circuit 140 over multiple consecutive periods of the operating frequency when chopping circuits 110 and 140 perform the first operation, and a second output value obtained from chopping circuit 140 over multiple consecutive periods of the operating frequency when chopping circuits 110 and 140 perform the second operation. By calculating the average value of the first output value and the second output value, the offset voltage of the entire system can be reduced, and more accurate AD conversion can be performed.

[0082] The chopping control unit 160 causes the chopping circuits 110 and 140 to perform the first operation immediately after the second operation, thereby repeatedly performing the first and second operations. The digital filter 150 may then, after calculating the average value of the first and second output values ​​obtained by the chopping circuits 110 and 140 performing the first and second operations in that order, calculate the average value of the second and first output values ​​obtained by the chopping circuits 110 and 140 performing the second and first operations in that order. This allows for efficient and highly accurate AD conversion.

[0083] Although exemplary embodiments of the semiconductor devices described herein have been described above, this disclosure is not limited to the specifically disclosed embodiments, and various modifications and changes are possible without departing from the scope of the claims.

[0084] This international application claims priority based on Japanese Patent Application No. 2025-048708, filed on 24 March 2025, the entire contents of which are incorporated herein by reference.

[0085] 100 Semiconductor device, 110 Chopping circuit (example of a first chopping circuit), 120 PGA (example of a programmable gain amplifier), 121 Operational amplifier (example of a first operational amplifier with differential input and differential output), 122A, 122B Chopping circuit (example of a pair of second chopping circuits), 130 n-th order ΔΣ ADC (example of a ΔΣ analog-to-digital converter), 131 Operational amplifier (example of a second operational amplifier with differential input and differential output), 132A, 132B Chopping circuit (example of a pair of third chopping circuits), 140 Chopping circuit (example of a fourth chopping circuit), 141 MUX, 142 Inverting unit, 150 Digital filter (example of an averaging unit), 160 Chopping control unit

Claims

1. A semiconductor device comprising: a first chopping circuit to which a differential analog signal is input; a programmable gain amplifier connected to the output side of the first chopping circuit, having a pair of second chopping circuits for chopping the differential input signal and differential output signal of the programmable gain amplifier; a ΔΣ type analog-to-digital converter having an integrator connected to the output side of the programmable gain amplifier, having a pair of third chopping circuits for chopping the differential input signal and differential output signal of the integrator; and a quantizer connected to the output side of the integrator; and a fourth chopping circuit that chops and outputs the output of the quantizer, wherein the first chopping circuit, the fourth chopping circuit, the pair of second chopping circuits, and the pair of third chopping circuits are driven by patterns generated according to different rules depending on the operating frequency.

2. The semiconductor device according to claim 1, wherein the programmable gain amplifier further comprises a differential input differential output type first operational amplifier connected between the pair of second chopping circuits.

3. The semiconductor device according to claim 1, wherein the programmable gain amplifier has a circuit configuration in which a plurality of amplification circuits are connected in series, each of which consists of a pair of second chopping circuits and a differential input differential output type first operational amplifier connected between the pair of second chopping circuits.

4. The semiconductor device according to claim 1, wherein the ΔΣ type analog-to-digital converter has n (where n is an integer of 1 or more) stages of the integrator, and each of the n stages of the integrator further has a second operational amplifier of differential input differential output type connected between the pair of third chopping circuits.

5. The semiconductor device according to any one of claims 1 to 4, further comprising a chopping control unit that controls the driving of the pair of second chopping circuits and the pair of third chopping circuits, wherein the chopping control unit performs chopping of the second chopping circuits at a frequency fs / 2, which is half the operating frequency fs, and performs chopping of the third chopping circuits according to a fractal sequence based on the operating frequency fs.

6. The ΔΣ type analog-to-digital converter further includes a chopping control unit that controls the driving of the third chopping circuit, the ΔΣ type analog-to-digital converter has n stages of the integrator (where n is an integer of 1 or more), the chopping control unit controls the driving of n pairs of the n stages of the integrator, and if non-inversion of the sign in chopping is + and inversion is -, then when n is 1, ..., k (k≧2), S １ =(+-),...,S ｋ = [S ｋ－１ , -S ｋ－１ The semiconductor device according to claim 1, wherein the n pairs of third chopping circuits are chopped by switching + and - according to the operating frequency in accordance with the fractal sequence represented by ].

7. The semiconductor device according to claim 1, further comprising: a chopping control unit for controlling the driving of the first chopping circuit and the fourth chopping circuit; and an averaging processing unit for performing an averaging process on the output of the fourth chopping circuit, wherein the chopping control unit causes the first chopping circuit and the fourth chopping circuit to continuously perform a first operation over a plurality of consecutive periods of the operating frequency, which does not invert the output value relative to the input value, and a second operation over the plurality of consecutive periods of the operating frequency, which inverts the output value relative to the input value, and the averaging processing unit calculates the average value of a first output value obtained from the fourth chopping circuit over the plurality of consecutive periods of the operating frequency by the first chopping circuit and the fourth chopping circuit performing the first operation, and a second output value obtained from the fourth chopping circuit over the plurality of consecutive periods of the operating frequency by the first chopping circuit and the fourth chopping circuit performing the second operation.

8. The semiconductor device according to claim 7, wherein the chopping control unit causes the first chopping circuit and the fourth chopping circuit to perform the first operation consecutively after the second operation, thereby repeatedly performing the first operation and the second operation, and the averaging processing unit performs a process to calculate the average value of the first output value and the second output value obtained by the first chopping circuit and the fourth chopping circuit performing the first operation and the second operation in that order, followed by a process to calculate the average value of the second output value and the first output value obtained by the first chopping circuit and the fourth chopping circuit performing the second operation and the first operation in that order.

Images