High frequency power amplification circuit and control circuit therefor

Abstract

This control circuit controls a gate voltage of a shunt transistor comprising an NMOSFET connected between a reference potential and a transmission line on the output side of a power amplifier or between the reference potential and a transmission line on the input side of the power amplifier. A power detection circuit of the control circuit detects a power waveform of one of a traveling wave and a reflected wave transmitted through the transmission lines connected to the power amplifier. A first transistor comprising an NMOSFET and a second transistor comprising a PMOSFET, which are connected in series, are connected between a power supply voltage and the reference potential. A threshold control circuit applies a threshold control voltage to the gate of the second transistor. A third transistor comprising a PMOSFET has a source connected to the power supply voltage, a drain connected to a gate of the shunt transistor, and a gate connected to a drain of the first transistor. A pull-down resistance element is connected between the drain of the third transistor and a fixed potential lower than or equal to the reference potential. The source of the first transistor is connected to the reference potential, the source of the second transistor is connected to the power supply voltage, and the power waveform detected by the power detection circuit is configured to be inputted to the gate of the first transistor.

Description

High-frequency power amplification circuit and its control circuit

[0001] This invention relates to a high-frequency power amplification circuit and its control circuit.

[0002] A high-frequency power amplifier circuit is known that is configured to suppress damage when reflected power is generated due to load fluctuations (Patent Document 1). In this high-frequency power amplifier circuit, a variable impedance circuit is connected between the power amplifier and the output terminal. The variable impedance circuit includes an FET connected between the output node of the power amplifier and a reference potential (ground). When the load impedance changes significantly, the impedance of the variable impedance circuit is changed by switching this FET on and off, thereby reducing reflected power.

[0003] Japanese Patent Publication No. 2006-333023

[0004] A high-frequency power amplification circuit includes a power amplifier and a filter that filters the high-frequency signal amplified by the power amplifier. If the output power from the power amplifier becomes excessively large, the filter may be destroyed. In the configuration of the high-frequency power amplification circuit described in Patent Document 1, it is difficult to suppress filter destruction. The object of the present invention is to provide a high-frequency power amplification circuit and its control circuit that can suppress filter destruction caused by an increase in output power from the power amplifier.

[0005] According to one aspect of the present invention, a control circuit is provided for controlling the gate voltage of a shunt transistor made of an NMOSFET connected between a transmission line on the output side of a power amplifier and a reference potential, or between a transmission line on the input side of a power amplifier and a reference potential, the control circuit comprising: a power detection circuit for detecting one of the power waveforms of a forward wave and a reflected wave transmitted through a transmission line connected to the power amplifier; a first transistor made of an NMOSFET and a second transistor made of a PMOSFET connected in series between a power supply voltage and a reference potential; a threshold control circuit for applying a threshold control voltage to the gate of the second transistor; a third transistor made of a PMOSFET whose source is connected to the power supply voltage, whose drain is connected to the gate of the shunt transistor and whose gate is connected to the drain of the first transistor; and a pull-down resistor element connected between the drain of the third transistor and a fixed potential below the reference potential, wherein the source of the first transistor is connected to the reference potential, the source of the second transistor is connected to the power supply voltage, and the power waveform detected by the power detection circuit is input to the gate of the first transistor.

[0006] According to another aspect of the present invention, a power detection circuit is provided which includes: a control circuit; a power amplifier; a shunt transistor consisting of an NMOSFET connected between the output transmission line of the power amplifier and a reference potential, or between the input transmission line of the power amplifier and a reference potential; a plurality of filters for filtering a high-frequency signal output from the power amplifier; a filter selection switch inserted between the output node of the power amplifier and each of the plurality of filters, and connecting one filter selected from the plurality of filters to the output node of the power amplifier; an antenna terminal connected to an antenna; and an antenna switch connecting the output terminal of one filter selected from the plurality of filters to the antenna terminal, wherein the power detection circuit provides a high-frequency power amplification circuit that detects a power waveform of either a traveling wave or a reflected wave transmitted through any of the transmission lines: the transmission line between the output node of the power amplifier and the filter selection switch; the transmission line between the filter selection switch and each of the plurality of filters; the transmission line between each of the plurality of filters and the antenna switch; or the transmission line between the antenna switch and the antenna terminal.

[0007] As the output power of the power amplifier increases and the peak voltage of the power waveform detected by the power detection circuit rises, the drain voltage of the first transistor increases, and the gate voltage of the third transistor also increases. As a result, the third transistor turns on, and the gate voltage of the shunt transistor increases. The increase in the gate voltage of the shunt transistor turns on the shunt transistor, limiting the output power of the power amplifier. As a result, the damage to the filter connected to the output side of the power amplifier is suppressed.

[0008] Figure 1 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the first embodiment. Figure 2 shows the gate voltage V Ｇ１ and drain voltage V ＤＳ１ An example of the relationship is the drain current I Ｄ１ Saturation value I Ｄ１ｓａｔ and drain current I Ｄ２ Saturation value I Ｄ２ｓａｔwhich is shown in association with . FIG. 3 is a graph showing current-voltage characteristics of a first transistor 21 and a second transistor 22. FIG. 4 is a graph showing the relationship between the gate voltage V of the first transistor 21 Ｇ１ and the gate voltage V of the shunt transistor 55 Ｇ０ . FIG. 5 is a graph showing the relationship between the output power P of the power amplifier 50 ＯＵＴ and the input power to the filter 52. FIG. 6 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a second embodiment. FIG. 7 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a third embodiment. FIG. 8 is a graph showing an example of the relationship between the gate voltage V of the first transistor 21 in the high-frequency power amplifier circuit according to the third embodiment Ｇ１ and the gate voltage V of the shunt transistor 55 Ｇ０ . FIG. 9 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a fourth embodiment. FIG. 10 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a fifth embodiment. FIG. 11 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a sixth embodiment. FIG. 12 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a seventh embodiment. FIG. 13 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to an eighth embodiment. FIG. 14 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a ninth embodiment. FIG. 15 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to a tenth embodiment.

[0009] [First Embodiment] A high-frequency power amplifier circuit according to a first embodiment will be described with reference to the drawings from FIG. 1 to FIG. 5.

[0010] FIG. 1 is a schematic equivalent circuit diagram of a high-frequency amplifier circuit according to the first embodiment. The high-frequency amplifier circuit according to the first embodiment includes a power amplifier 50, a filter selection switch 51 (also referred to as a band selection switch), a plurality of filters 52, an antenna switch 53, an antenna terminal 54, a shunt transistor 55, and a control circuit 10. The power amplifier 50 receives an input high-frequency signal RF ＩＮ amplifies and outputs it. The power of the high-frequency signal output from the power amplifier 50 is denoted as P ＯＵＴ .

[0011] A shunt transistor 55, made of an NMOSFET, is connected between the transmission line on the output side of the power amplifier 50 and the reference potential (ground). More specifically, the drain of the shunt transistor 55 is connected to the output node of the power amplifier 50, and the source is connected to the reference potential. The gate of the shunt transistor 55 is connected to the control circuit 10. The control circuit 10 controls the gate voltage V of the shunt transistor 55. Ｇ０ Control.

[0012] Each of the multiple filters 52 filters the high-frequency signal output from the power amplifier 50. The multiple filters 52 have different passbands. As filters 52, for example, filters made of elastic materials, such as surface acoustic wave (SAW) filters and bulk acoustic wave (BAW) filters, are used. A filter selection switch 51 is inserted between the output node of the power amplifier 50 and each of the multiple filters 52. The filter selection switch 51 connects the output node of the power amplifier 50 to the input terminal of one of the filters 52 selected from the multiple filters 52.

[0013] The antenna is connected to the antenna terminal 54. The antenna switch 53 connects the output terminal of one filter 52 selected from the multiple filters 52 to the antenna terminal 54.

[0014] Next, the configuration of the control circuit 10 will be described. The power detection circuit 20 detects the power waveform of the traveling wave transmitted through the transmission line between the output node of the power amplifier 50 and the filter selection switch 51. A directional coupler is used as the power detection circuit 20.

[0015] Power supply voltage V ＤＤ A series circuit consisting of a first transistor 21 made of an NMOSFET and a second transistor 22 made of a PMOSFET is connected between the power supply voltage V. Specifically, the source of the second transistor 22 is the power supply voltage V. ＤＤ The drains of the first transistor 21 and the second transistor 22 are connected to each other, and the source of the first transistor 21 is connected to a reference potential.

[0016] The gate of the second transistor 22 is connected to the threshold control circuit 35. The threshold control circuit 35 applies a constant threshold control voltage V to the gate of the second transistor 22. ＴＨＣ The threshold control circuit 35 includes a constant voltage source that generates a constant voltage. The drain current of the second transistor 22 is the threshold control voltage V ＴＨＣ The matching value is limited to the following: That is, the second transistor 22 is biased such that the maximum value of the drain current is limited.

[0017] The power waveform detected by the power detection circuit 20 is input to the gate of the first transistor 21 via the DC cut capacitor 31. The gate voltage of the first transistor 21 is set to V Ｇ１ This is indicated as follows. The gate of the first transistor 21 is connected to the bias circuit 38 via a resistor 32. A bias voltage is applied from the bias circuit 38 to the gate of the first transistor 21 via the resistor 32.

[0018] The drains of the first transistor 21 and the second transistor 22 are connected to the gate of the third transistor 23, which is a PMOSFET. The gate voltage of the third transistor 23 is V Ｇ３ This is indicated as follows. The source of the third transistor 23 is the power supply voltage V. ＤＤ The third transistor 23 is connected to the gate of the shunt transistor 55, and the drain of the third transistor 23 is connected to the gate of the shunt transistor 55. Furthermore, the drain of the third transistor 23 is connected to a fixed potential via a pull-down resistor element 33. In the first embodiment, this fixed potential is equal to the reference potential.

[0019] Next, referring to Figure 2, the gate voltage V of the first transistor 21 Ｇ１ When the drain voltage V of the first transistor 21 changes, ＤＳ１ and drain current I Ｄ１ The saturation value and the drain current I of the second transistor 22. Ｄ２ The following explains the change in the gate voltage V. Figure 2 shows the gate voltage V. Ｇ１ and drain voltage V ＤＳ１ An example of the relationship is the drain current I Ｄ１ Saturation value and drain current I Ｄ２This figure shows the relationship with the saturation value.

[0020] Gate voltage V of the first transistor 21 Ｇ１ As the value increases, the drain current I Ｄ１ Saturation value I Ｄ１ｓａｔ The drain current I Ｄ２ Saturation value I Ｄ２ｓａｔ Starting from the smallest point, drain current I Ｄ１ Saturation value I Ｄ１ｓａｔ The drain current I Ｄ２ Saturation value I Ｄ２ｓａｔ Approaching a certain gate voltage V Ｇ１ In this case, both values ​​become the same. Drain current I Ｄ１ Saturation value I Ｄ１ｓａｔ The drain current I Ｄ２ Saturation value I Ｄ２ｓａｔ As it gets larger, the drain voltage V ＤＳ１ It decreases.

[0021] Next, referring to Figure 3, the drain voltage of the first transistor 21 and the gate voltage V of the third transistor 23 are shown. Ｇ３ The changes will be explained in detail. Figure 3 is a graph showing the current-voltage characteristics of the first transistor 21 and the second transistor 22. The horizontal axis represents the drain voltage V of the first transistor 21. ＤＳ１ The vertical axis represents the drain current. The drain voltage V of the first transistor 21. Ｄ１ This is the gate voltage V of the third transistor 23. Ｇ３ It is equal to.

[0022] The left end of the horizontal axis is V. ＤＳ１ This corresponds to 0V, and the rightmost point is V. ＤＳ１ = V ＤＤ This corresponds to the drain voltage V of the second transistor 22. ＤＳ２ is negative, V ＤＳ１ -V ＤＳ２ = V ＤＤ Therefore, at the left end of the horizontal axis in Figure 3, V ＤＳ２ = -V ＤＤ And at the right end, V ＤＳ２ = 0V. The solid line in Figure 3 represents the gate voltage V Ｇ１ The drain current I of the first transistor 21 when it is constant Ｄ１The dashed line indicates the gate voltage V of the second transistor 22. Ｇ２ The threshold control voltage V ＴＨＣ The drain current I of the second transistor 22 when it is fixed in place. Ｄ２ This indicates.

[0023] The gate voltage V of the first transistor 21 is adjusted according to the voltage fluctuation detected by the power detection circuit 20. Ｇ１ The gate voltage V fluctuates. Ｇ１ When it rises, the drain current I Ｄ１ The saturation value increases. Drain current I of the first transistor 21 Ｄ１ The saturation value is the drain current I of the second transistor 22. Ｄ２ The gate voltage V when it matches the saturation value. Ｇ１ The limiting threshold voltage V ＴＨＣ１ Let's assume that's the case.

[0024] Drain current I of the first transistor 21 Ｄ１ Since this is equal to the drain current of the second transistor 22, the gate voltage V Ｇ１ When it fluctuates, the drain current I of the first transistor 21 Ｄ１ A graph showing the change and the drain current I of the second transistor 22. Ｄ２ The drain current flows at the intersection with the graph showing the change in the gate voltage V. Ｇ１ White circles are placed at the intersections where the parameters change.

[0025] Drain voltage V of the first transistor 21 ＤＳ１ This corresponds to the voltage at the intersection point of the graph. Gate voltage V Ｇ１ When the gate voltage is near 0V, the second transistor 22 operates in the linear region and the first transistor 21 operates in the saturation region. Ｇ１ When the voltage rises, the second transistor 22 saturates. After the second transistor 22 saturates, the gate voltage V Ｇ１ As the drain voltage V increases ＤＳ１ It will decline sharply.

[0026] Next, referring to Figure 4, the gate voltage V of the first transistor 21 Ｇ１ and the gate voltage V of shunt transistor 55Ｇ０ The relationship with . Fig. 4 is a graph showing the gate voltage V of the first transistor 21 Ｇ１ and the gate voltage V of the shunt transistor 55 Ｇ０ The horizontal axis represents the gate voltage V Ｇ１ and the vertical axis represents the gate voltage V Ｇ０ .

[0027] In the range where the gate voltage V Ｇ１ is equal to or lower than the limit start threshold voltage V ＴＨＣ１ , as shown in FIG. 3, the gate voltage V of the third transistor 23 Ｇ３ is close to the power supply voltage V ＤＤ , so the third transistor 23 is off. For this reason, the gate voltage V of the shunt transistor 55 Ｇ０ is approximately 0 V, and the shunt transistor 55 is off.

[0028] When the gate voltage V of the first transistor 21 Ｇ１ exceeds the limit start threshold voltage V ＴＨＣ１ , as shown in FIG. 3, the gate voltage V of the third transistor 23 Ｇ３ drops sharply, turning the third transistor 23 on. As a result, the gate voltage V of the shunt transistor 55 Ｇ０ rises.

[0029] When a high-frequency power waveform RF is detected by the power detection circuit 20 １ , the power waveform RF is superimposed on the gate voltage V Ｇ１ １ . During the period when the peak voltage of the power waveform RF １ exceeds the limit start threshold voltage V ＴＨＣ１ , the gate voltage V of the shunt transistor 55 Ｇ０ is generated. When the gate voltage V Ｇ０ exceeds the gate threshold voltage of the shunt transistor 55, the shunt transistor 55 is turned on. During the period when the shunt transistor 55 is on, part of the high-frequency signal output from the power amplifier 50 flows to the reference potential. Therefore, the peak voltage of the high-frequency signal output from the power amplifier 50 is limited.

[0030] FIG. 5 shows the output power P of the power amplifier 50​ＯＵＴ This graph shows the relationship between the output power P and the input power to filter 52. ＯＵＴ When it is small, that is, the high-frequency power waveform RF detected by the power detection circuit 20 １ When the amplitude is small, the power waveform RF １ The peak voltage of the limiting start threshold voltage V ＴＨＣ１ (Figure 4) is not reached. Therefore, the shunt transistor 55 does not turn on, and the output power P ＯＵＴ As the value increases, the input power to filter 52 also increases.

[0031] Output power P ＯＵＴ As it increases, the power waveform RF of the traveling wave detected by the power detection circuit 20 １ The amplitude increases. Power waveform RF １ The amplitude increases, and the peak voltage is limited to the threshold voltage V. ＴＨＣ１ When it exceeds (Figure 4), the gate voltage V of the shunt transistor 55 becomes as shown in Figure 4. Ｇ０ This occurs, and the shunt transistor 55 turns on. As a result, the increase in the amplitude of the high-frequency signal input to the filter 52 is suppressed. That is, the output power P ＯＵＴ The limiting threshold voltage V ＴＨＣ１ When the power exceeds a certain level, the increase in input power to filter 52 is suppressed.

[0032] Next, the excellent effects of the first embodiment will be described. In the first embodiment, the output power P of the power amplifier 50 ＯＵＴ When this value exceeds a certain threshold, the increase in input power to the filter 52 is suppressed. As a result, the failure of the filter 52 caused by an increase in output power from the power amplifier 50 can be suppressed.

[0033] The limiting threshold voltage V is the voltage at which the suppression of input power to filter 52 begins. ＴＨＣ１ (Figure 5) shows the threshold control voltage V generated by the threshold control circuit 35, as shown in Figure 3. ＴＨＣ It depends on the threshold control voltage V. ＴＨＣ By setting this appropriately, the input power to the filter 52 can be suppressed according to the upper limit of the filter 52's power tolerance.

[0034] Next, a high-frequency amplification circuit according to a modification of the first embodiment will be described. In the first embodiment, the on / off state of the shunt transistor 55 is controlled based on the power waveform of the traveling wave from the power amplifier 50 to the filter 52, but the configuration may also be such that the on / off state of the shunt transistor 55 is controlled based on the power waveform of the reflected wave. For example, if the load impedance (antenna impedance) fluctuates and deviates significantly from the impedance matching condition, the power of the reflected wave will increase.

[0035] When the power of the reflected wave increases, the voltage standing wave ratio (VSWR) increases, which can lead to the failure of the filter 52. By controlling the on / off state of the shunt transistor 55 based on the power waveform of the reflected wave, the failure of the filter 52 caused by the increase in the reflected wave can be suppressed.

[0036] A configuration may be adopted in which the power waveform generated in the transmission line between the power amplifier 50 and the filter selection switch 51 is directly applied to the gate of the first transistor 21. The power waveform of the transmission line reflects power information from both the forward wave and the reflected wave. Therefore, in a configuration in which the power waveform of the transmission line is applied to the gate of the first transistor 21, the on / off state of the shunt transistor 55 is controlled based on both the forward wave and the reflected wave, thereby suppressing the breakdown of the filter 52.

[0037] [Second Embodiment] Next, a high-frequency power amplifier circuit according to the second embodiment will be described with reference to Figure 6. Hereinafter, the common components with the high-frequency power amplifier circuit according to the first embodiment, which was described with reference to Figures 1 to 5, will not be explained.

[0038] Figure 6 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the second embodiment. In the first embodiment (Figure 1), the threshold control circuit 35 is configured with a constant voltage source. In contrast, in the control circuit 10 according to the second embodiment, the threshold control circuit 35 is configured with a reference-side fourth transistor that forms a current mirror together with the second transistor 22, and a threshold control current I is supplied to the fourth transistor 24. ＴＨＣ It includes a threshold-controlled current source 36 that supplies current.

[0039] Threshold control current IＴＨＣ Accordingly, a constant voltage is generated at the gate of the fourth transistor 24, and this voltage is applied to the gate of the second transistor 22. The drain current I of the second transistor 22 Ｄ２ The maximum value is the threshold control current I ＴＨＣ This is limited to the gate voltage V of the first transistor 21. Therefore, in the second embodiment as well, the gate voltage V of the first transistor 21 is limited to the gate voltage V of the first transistor 21, as in the first embodiment shown in Figure 3. Ｇ１ In response to the change, the drain voltage V of the first transistor 21 ＤＳ１ and the gate voltage V of the third transistor 23 Ｇ３ The limiting threshold voltage V shown in Figure 4 changes. ＴＨＣ１ The threshold control current I ＴＨＣ It is determined by [something].

[0040] Next, the excellent effects of the second embodiment will be described. In the second embodiment, as in the first embodiment, the output power P of the power amplifier 50 is also described. ＯＵＴ When this value exceeds a certain threshold, the increase in input power to the filter 52 is suppressed, thereby preventing the filter 52 from being damaged due to an increase in output power from the power amplifier 50.

[0041] [Third Embodiment] Next, a high-frequency power amplifier circuit according to the third embodiment will be described with reference to Figures 7 and 8. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the second embodiment, described with reference to Figure 6, will be omitted from the explanation.

[0042] Figure 7 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the third embodiment. In the high-frequency power amplifier circuit according to the second embodiment (Figure 6), the fixed potential to which the gate of the shunt transistor 55 is connected via the pull-down resistor element 33 is set as the reference potential. That is, the gate of the shunt transistor 55 is connected to the same potential as the source potential.

[0043] In contrast, in the third embodiment, the fixed potential to which the gate of the shunt transistor 55 is connected via the pull-down resistor element 33 is set to a potential lower than the reference potential. A negative potential is generated by the negative potential generation circuit 37. For example, a charge pump is used as the negative potential generation circuit 37. The negative potential generated by the negative potential generation circuit 37 is -V Ｃ This is how it is written.

[0044] The negative potential generation circuit 37 is at a negative potential -V Ｃ The output node that outputs the signal is connected to a reference potential via capacitor 34. Capacitor 34 suppresses the input of high-frequency signals to the negative potential generation circuit 37.

[0045] Figure 8 shows the gate voltage V of the first transistor 21 in the high-frequency power amplifier circuit according to the third embodiment. Ｇ１ and the gate voltage V of shunt transistor 55 Ｇ０ This graph shows an example of the relationship. In the first embodiment (Figure 4), the gate voltage V of the first transistor 21 Ｇ１ The limiting threshold voltage V ＴＨＣ１ Within the following range, the gate voltage V of the shunt transistor 55 Ｇ０ The voltage is fixed at the reference potential (0V). In contrast, in the third embodiment, the gate voltage V of the first transistor 21 Ｇ１ The range until the voltage starts to rise (V ＴＨＣ２ Within the following range, the gate voltage V of the shunt transistor 55 Ｇ０ Negative potential -V Ｃ It will be fixed in place.

[0046] The output power of the power amplifier 50 increases, and the gate voltage V of the first transistor 21 increases. Ｇ１ The gate voltage V rises. Ｇ１ Voltage V ＴＨＣ３ When it reaches this point, the gate voltage V of the shunt transistor 55 Ｇ０ This becomes the reference potential (0V). Gate voltage V Ｇ１ If it rises further, the gate voltage V Ｇ０ The gate voltage V of the first transistor 21 rises above the reference potential. Ｇ１ Voltage V ＴＨＣ３When the value exceeds a certain limit, the shunt transistor 55 turns on, and the input power to the filter 52 is limited.

[0047] Next, the excellent effects of the third embodiment will be described. When the voltage of the high-frequency signal output from the power amplifier 50 swings significantly in the negative direction, a large negative voltage is applied to the drain of the shunt transistor 55. If a reference potential is applied to the gate of the shunt transistor 55, when the drain voltage swings significantly in the negative direction, the shunt transistor 55 may turn on, and current may flow in reverse from the source to the drain.

[0048] In the third embodiment, a negative potential -V is applied to the gate of the shunt transistor 55 by the negative potential generation circuit 37. Ｃ Because a voltage is applied, even if a negative voltage is generated at the drain, the shunt transistor 55 is less likely to turn on, which is an excellent effect. In addition, the threshold control current I generated by the threshold control current source 36 ＴＨＣ By adjusting this, the gate voltage V when the shunt transistor 55 turns on can be adjusted. Ｇ１ (Voltage V) ＴＨＣ３ ) is the limiting start threshold voltage V in the case of the first embodiment (Figure 4). ＴＨＣ１ It is possible to adjust it so that it is equal to [the specified value]. Therefore, as in the first embodiment, it is possible to limit the input power to the filter 52.

[0049] [Fourth Embodiment] Next, a high-frequency power amplifier circuit according to the fourth embodiment will be described with reference to Figure 9. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the third embodiment, described with reference to Figures 7 and 8, will be omitted from the explanation.

[0050] Figure 9 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the fourth embodiment. In the third embodiment (Figure 7), the drain of the third transistor 23 is directly connected to the pull-down resistor element 33. In contrast, in the fourth embodiment, a fifth transistor 25 made of a PMOSFET is inserted between the drain of the third transistor 23 and the pull-down resistor element 33. For example, the source of the fifth transistor 25 is connected to the drain of the third transistor 23, and the drain is connected to the pull-down resistor element 33. A reference potential (0V) is applied to the gate of the fifth transistor 25.

[0051] Next, the excellent effects of the fourth embodiment will be described. In the third embodiment (Figure 7), the power supply voltage V is applied between the source and drain of the third transistor 23. ＤＤ and negative potential -V Ｃ A differential voltage is applied. This differential voltage does not exceed the breakdown voltage between the source and drain of the third transistor 23, so that it does not exceed a negative potential -V Ｃ You need to configure this.

[0052] In contrast, in the fourth embodiment, the lower limit of the source voltage of the fifth transistor 25 is set to the gate voltage (reference potential) of the fifth transistor 25, and the gate threshold voltage V ＴＨ５ The voltage is limited to the applied voltage. Therefore, the source-drain voltage of the third transistor 23 is a negative potential -V. Ｃ V ＤＤ -V ＴＨ５ It does not become greater than this. Therefore, the negative potential -V Ｃ The degree of freedom in selection increases. At this time, the negative potential -V Ｃ It is preferable to select such a transistor so that the voltage between the source and drain of the fifth transistor 25 does not exceed its breakdown voltage.

[0053] [Fifth Embodiment] Next, a high-frequency power amplifier circuit according to the fifth embodiment will be described with reference to Figure 10. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the fourth embodiment, described with reference to Figure 9, will be omitted from the explanation.

[0054] Figure 10 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the fifth embodiment. In the fourth embodiment (Figure 9), the drain of the fifth transistor 25 is directly connected to the pull-down resistor element 33 and the gate of the shunt transistor 55. In contrast, in the fifth embodiment, a sixth transistor made of a PMOSFET is inserted between the drain of the fifth transistor 25 and the pull-down resistor element 33. For example, the source of the sixth transistor 26 is connected to the drain of the fifth transistor 25, and its drain is connected to the gate of the pull-down resistor element 33 and the shunt transistor 55. The gate of the sixth transistor 26 is connected to a fixed potential (negative potential -V) generated by the negative potential generation circuit 37. Ｃ ) is given.

[0055] Next, the excellent effects of the fifth embodiment will be described. The transmission line connected to the output node of the power amplifier 50 is coupled to the gate of the shunt transistor 55 through the parasitic capacitance between the drain and gate of the shunt transistor 55. Therefore, the power waveform of the high-frequency signal output from the power amplifier 50 appears at the gate of the shunt transistor 55. This power waveform is then coupled to the negative potential -V generated by the negative potential generation circuit 37. Ｃ It is superimposed on it.

[0056] In the fourth embodiment (Figure 9), the negative potential is -V. Ｃ A high-frequency voltage with a power waveform superimposed is applied to the drain of the fifth transistor 25. Therefore, even when the power waveform shows a negative peak, a negative potential -V is maintained so that the voltage between the source and drain of the fifth transistor 25 does not exceed the breakdown voltage. Ｃ It is preferable to set this.

[0057] In contrast, in the fifth embodiment, a negative potential -V is applied to the gate of the sixth transistor 26. Ｃ Because a voltage is applied, the source voltage of the sixth transistor 26 is a negative potential -V Ｃ The gate threshold voltage V ＴＨ６ The voltage will not drop below the applied voltage. In other words, the lower limit of the drain voltage of the fifth transistor 25 is -V Ｃ +V ＴＨ６This is limited to the lower limit of the drain voltage of the fifth transistor 25, and is not affected by the amplitude of the power waveform of the high-frequency signal.

[0058] Furthermore, when the voltage amplitude of the high-frequency signal output from the power amplifier 50 shows a negative peak, the source voltage of the sixth transistor 26 is -V Ｃ +V ＴＨ６ Therefore, compared to the case where the negative peak of the power waveform is directly applied to the drain of the fifth transistor 25, the source-drain voltage of the sixth transistor is less likely to exceed the breakdown voltage. For this reason, in the fifth embodiment, compared to the fourth embodiment, the negative potential -V Ｃ The degree of freedom of choice increases.

[0059] [Sixth Embodiment] Next, a high-frequency power amplifier circuit according to the sixth embodiment will be described with reference to Figure 11. Hereinafter, the configuration common to the high-frequency power amplifier circuit according to the third embodiment, described with reference to Figures 7 and 8, will be omitted from the explanation.

[0060] Figure 11 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the sixth embodiment. In the third embodiment (Figure 7), the negative potential generation circuit 37 is directly connected to the pull-down resistor element 33. In contrast, in the sixth embodiment, a current limiting circuit 40 is inserted between the pull-down resistor element 33 and the negative potential generation circuit 37. The current limiting circuit 40 may also be inserted between the drain of the third transistor 23 and the pull-down resistor element 33. In other words, the current limiting circuit 40 can be inserted at any point between the drain of the third transistor 23 and the negative potential generation circuit 37.

[0061] The current limiting circuit 40 includes an NMOS current mirror circuit. The sources of the reference transistor 42 and the output transistor 41 of this NMOS current mirror circuit are connected to the negative potential generation circuit 37. The drain of the reference transistor 42 is connected to the reference potential via a current limiting resistor element 43. The drain of the output transistor 41 is connected to a pull-down resistor element 33.

[0062] The reference transistor 42 has a reference potential (0V) and a negative potential -V generated by the negative potential generation circuit 37. ＣA reference current flows through the circuit, corresponding to the resistance value of the current-limiting resistor element 43. The upper limit of the current flowing through the output transistor 41 is limited by this reference current. As a result, the current flowing into the negative potential generation circuit 37 is limited.

[0063] Next, the excellent effects of the sixth embodiment will be described. When the current flowing into the negative potential generation circuit 37 becomes larger than the driving capacity of the negative potential generation circuit 37, the negative potential -V generated by the negative potential generation circuit 37 increases. Ｃ The voltage rises. The negative potential generating circuit 37 also generates a negative potential -V in the other switch circuits 60. Ｃ When supplying, negative potential -V Ｃ If it rises, it will affect the operation of other switch circuits 60. In the sixth embodiment, the current flowing into the negative potential generation circuit 37 is limited, so the generated negative potential -V Ｃ This can suppress the rise.

[0064] [Seventh Embodiment] Next, a high-frequency power amplifier circuit according to the seventh embodiment will be described with reference to Figure 12. Hereinafter, the common components of the high-frequency power amplifier circuit and control circuit according to the second embodiment, as described with reference to Figure 6, will be omitted from the explanation.

[0065] Figure 12 is a schematic equivalent circuit diagram of the high-frequency power amplifier circuit according to the seventh embodiment. In the second embodiment (Figure 6), the threshold control current I generated by the threshold control current source 36 ＴＨＣ In contrast, in the seventh embodiment, the threshold control current source 36 controls the threshold control current I according to the filter 52 selected by the filter selection switch 51. ＴＨＣ The filter selection control circuit 56 controls the filter selection switch 51 to select one filter 52 from a plurality of filters 52. The threshold control current source 36 controls the threshold control current I based on the command from the filter selection control circuit 56. ＴＨＣ Change it.

[0066] Threshold control current I ＴＨＣ When this changes, the threshold control voltage V output by the threshold control circuit 35 ＴＨＣ This changes. As a result, the limit start threshold voltage V shown in Figure 4 changes. ＴＨＣ１As the output power P of the power amplifier 50 changes and the filter input power limiting begins, as shown in Figure 5, ＯＵＴ The limit start threshold changes.

[0067] Next, the excellent effects of the seventh embodiment will be described. In the seventh embodiment, the output power P of the power amplifier 50 is adjusted to match the allowable upper limit of the input power of the multiple filters 52. ＯＵＴ A limiting threshold can be set. This allows for appropriate protection according to the characteristics of the filter 52.

[0068] Next, a high-frequency power amplifier circuit according to a modification of the seventh embodiment will be described. In the seventh embodiment, the threshold control current I is controlled according to the selected filter 52. ＴＨＣ This changes the threshold control voltage V. In the high-frequency power amplifier circuit according to the first embodiment (Figure 1), the threshold control voltage source constituting the threshold control circuit 35 changes the threshold control voltage V. ＴＨＣ It may also be configured to change the value.

[0069] [Eighth Embodiment] Next, a high-frequency power amplifier circuit according to the eighth embodiment will be described with reference to Figure 13. Hereinafter, the common components of the high-frequency power amplifier circuit and control circuit according to the second embodiment, as described with reference to Figure 6, will be omitted from the explanation.

[0070] Figure 13 is a schematic equivalent circuit diagram of the high-frequency power amplifier circuit according to the eighth embodiment. In the second embodiment (Figure 6), the drain of the shunt transistor 55 is connected to the transmission line on the output side of the power amplifier 50. In contrast, in the eighth embodiment, the drain of the shunt transistor 55 is connected to the transmission line on the input side of the power amplifier 50. When the shunt transistor 55 is turned on, the power of the high-frequency signal input to the power amplifier 50 is limited. As a result, the output power of the power amplifier 50 is limited, and the input power to the filter 52 is also limited.

[0071] Next, the excellent effects of the eighth embodiment will be described. In the eighth embodiment, as in the second embodiment, the output power P of the power amplifier 50 is also described. ＯＵＴAs this value increases, the increase in input power to the filter 52 is suppressed, thereby preventing the filter 52 from being damaged due to an increase in output power from the power amplifier 50.

[0072] [Ninth Embodiment] Next, a high-frequency power amplifier circuit according to the ninth embodiment will be described with reference to Figure 14. Hereinafter, the common components of the high-frequency power amplifier circuit and control circuit according to the second embodiment, as described with reference to Figure 6, will be omitted from the explanation.

[0073] Figure 14 is a schematic equivalent circuit diagram of a high-frequency power amplifier circuit according to the ninth embodiment. In the second embodiment (Figure 6), the shunt transistor 55 is composed of one NMOSFET. In contrast, in the ninth embodiment, the shunt transistor 55 includes three NMOSFETs 55A, 55B, and 55C connected in series. Note that three or more NMOSFETs may be connected in series. That is, the shunt transistor 55 has a stack structure consisting of multiple NMOSFETs. The drain of the third transistor 23 is connected to the gates of each of the multiple NMOSFETs 55A, 55B, and 55C of the shunt transistor 55.

[0074] Next, the excellent effects of the ninth embodiment will be described. In the ninth embodiment, a stack structure is used for the shunt transistor 55, so the voltage applied to each of the multiple NMOSFETs is reduced. Therefore, NMOSFETs with low breakdown voltage can be used.

[0075] Furthermore, even when the negative peak in the power waveform of the high-frequency signal from the power amplifier 50 becomes large, each NMOSFET 55A, 55B, and 55C is less likely to turn on, resulting in the excellent effect of preventing backflow from source to drain.

[0076] [Tenth Embodiment] Next, a high-frequency power amplifier circuit according to the tenth embodiment will be described with reference to Figure 15. Hereinafter, the common components of the high-frequency power amplifier circuit and control circuit according to the ninth embodiment, which were described with reference to Figure 14, will be omitted from the explanation.

[0077] Figure 15 is a schematic equivalent circuit diagram of the high-frequency power amplifier circuit according to the 10th embodiment. The high-frequency power amplifier circuit according to the 10th embodiment includes, in addition to the components of the high-frequency amplifier circuit according to the 9th embodiment (Figure 14), the negative potential generation circuit 37 of the high-frequency power amplifier circuit according to the 3rd embodiment (Figure 7), the 5th transistor 25 and 6th transistor 26 of the high-frequency power amplifier circuit according to the 5th embodiment (Figure 10), and the current limiting circuit 40 of the high-frequency power amplifier circuit according to the 6th embodiment (Figure 11). In the 6th embodiment (Figure 11), the current limiting circuit 40 is inserted between the pull-down resistor element 33 and the negative potential generation circuit 37, but in the 10th embodiment, the current limiting circuit 40 is inserted between the drain of the 6th transistor 26 and the pull-down resistor element 33.

[0078] Furthermore, in the tenth embodiment, the gates of the multiple NMOSFETs 55A, 55B, and 55C of the shunt transistor 55 are connected to the drains of the sixth transistor 26 via resistors 57A, 57B, and 57C, respectively.

[0079] Next, the excellent effects of the tenth embodiment will be described. In the tenth embodiment, a stack structure similar to that of the ninth embodiment (Figure 14) is adopted as the shunt transistor 55. As a result, as in the ninth embodiment, a low-voltage NMOSFET can be used. Furthermore, the excellent effect is obtained that each NMOSFET 55A, 55B, and 55C is less likely to turn on, and backflow from source to drain is less likely to occur.

[0080] In the tenth embodiment, resistor elements 57A, 57B, and 57C are connected to the gates of NMOSFETs 55A, 55B, and 55C, respectively. As a result, when the power waveform of the high-frequency signal swings significantly in the negative direction, the voltage generated at the gate will not be the same among the multiple NMOSFETs 55A, 55B, and 55C due to parasitic capacitance between the drain and gate. Specifically, when the power waveform of the high-frequency signal swings significantly in the negative direction, the high-frequency component superimposed on the gate voltage increases in the order of NMOSFETs 55A, 55B, and 55C. Therefore, the effect of making it difficult for NMOSFETs 55A, 55B, and 55C to turn on is enhanced.

[0081] The high-frequency power amplifier circuit according to the 10th embodiment has a negative potential generation circuit 37, similar to the third embodiment (Figure 7). Therefore, the same effect as the third embodiment is obtained, namely, the excellent effect that the shunt transistor 55 is less likely to turn on even when a negative voltage is generated at the drain of the shunt transistor 55.

[0082] The high-frequency power amplifier circuit according to the 10th embodiment has a fifth transistor 25, a sixth transistor 26, and a negative potential generation circuit 37, similar to the fifth embodiment (Figure 10). Therefore, it has the same effect as the fifth embodiment, namely the negative potential -V generated by the negative potential generation circuit 37. Ｃ This has the excellent effect of increasing the degree of freedom in making choices.

[0083] The high-frequency power amplifier circuit according to the 10th embodiment has a current limiting circuit 40, similar to the 6th embodiment (Figure 11). Therefore, it has the same effect as the 6th embodiment, namely, by limiting the current flowing into the negative potential generation circuit 37, the generated negative potential -V Ｃ This method offers the excellent benefit of suppressing the rise in [the substance].

[0084] The embodiments described above are illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects and benefits from similar configurations in multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the embodiments described above. For example, it will be obvious to those skilled in the art that various modifications, improvements, and combinations are possible.

[0085] 10 Control circuit 20 Power detection circuit 21 First transistor 22 Second transistor 23 Third transistor 24 Fourth transistor 25 Fifth transistor 26 Sixth transistor 31 DC cut capacitor 32 Resistor element 33 Pull-down resistor element 34 Capacitor 35 Threshold control circuit 36 ​​Threshold control current source 37 Negative potential generation circuit 38 Bias circuit 40 Current limiting circuit 41 Output transistor 42 Reference transistor 43 Current limiting resistor element 50 Power amplifier 51 Filter selection switch 52 Filter 53 Antenna switch 54 Antenna terminal 55 Shunt transistor 55A, 55B, 55C NMOSFET 56 Filter selection control circuit 57A, 57B, 57C Resistor element 60 Switch circuit

Claims

1. A control circuit for controlling the gate voltage of a shunt transistor made of an NMOSFET connected between the output transmission line of a power amplifier and a reference potential, or between the input transmission line of the power amplifier and a reference potential, comprising: a power detection circuit for detecting the power waveform of either a forward wave or a reflected wave transmitted through the transmission line connected to the power amplifier; a first transistor made of an NMOSFET and a second transistor made of a PMOSFET connected in series between the power supply voltage and a reference potential; a threshold control circuit for applying a threshold control voltage to the gate of the second transistor; a third transistor made of a PMOSFET whose source is connected to the power supply voltage, whose drain is connected to the gate of the shunt transistor, and whose gate is connected to the drain of the first transistor; and a pull-down resistor element connected between the drain of the third transistor and a fixed potential below the reference potential, wherein the source of the first transistor is connected to the reference potential, the source of the second transistor is connected to the power supply voltage, and the power waveform detected by the power detection circuit is input to the gate of the first transistor.

2. The control circuit according to claim 1, wherein the threshold control circuit comprises a threshold control voltage source that generates the threshold control voltage.

3. The control circuit according to claim 1, wherein the threshold control circuit includes a reference-side fourth transistor that constitutes a current mirror together with the second transistor, and a threshold control current source that supplies a threshold control current to the fourth transistor.

4. The control circuit according to claim 1 or 2, further comprising a negative potential generating circuit that generates a potential lower than the reference potential as the fixed potential.

5. The control circuit according to claim 4, further comprising a fifth transistor, which is inserted between the drain of the third transistor and the pull-down resistor element, the source of which is connected to the drain of the third transistor, the drain of which is connected to the pull-down resistor element, and the gate of which is a PMOSFET with a reference potential.

6. The control circuit according to claim 5, further comprising a sixth transistor, which is inserted between the drain of the fifth transistor and the pull-down resistor element, the source of which is connected to the drain of the fifth transistor, the drain of which is connected to the pull-down resistor element, and the gate of which is a PMOSFET with the fixed potential applied.

7. The control circuit according to any one of claims 4 to 6, further comprising a current limiting circuit inserted between the drain of the third transistor and the negative potential generating circuit, the current limiting circuit including an NMOS current mirror circuit, wherein the sources of the reference transistor and output transistor of the NMOS current mirror circuit of the current limiting circuit are connected to the negative potential generating circuit, the drain of the reference transistor is connected to a reference potential via a current limiting resistor element, and the drain of the output transistor is connected to the drain of the third transistor.

8. The control circuit according to any one of claims 1 to 7, wherein the shunt transistor includes a plurality of NMOSFETs connected in series, and the drain of the third transistor is connected to the gate of each of the plurality of NMOSFETs of the shunt transistor.

9. A high-frequency power amplification circuit comprising: a control circuit according to any one of claims 1 to 7; a power amplifier; a shunt transistor consisting of an NMOSFET connected between the output transmission line of the power amplifier and a reference potential, or between the input transmission line of the power amplifier and a reference potential; a plurality of filters for filtering a high-frequency signal output from the power amplifier; a filter selection switch inserted between the output node of the power amplifier and each of the plurality of filters, and connecting one filter selected from the plurality of filters to the output node of the power amplifier; an antenna terminal connected to an antenna; and an antenna switch connecting the output terminal of one filter selected from the plurality of filters to the antenna terminal, wherein the power detection circuit detects a power waveform of either a traveling wave or a reflected wave transmitted through any of the transmission lines: the transmission line between the output node of the power amplifier and the filter selection switch; the transmission line between the filter selection switch and each of the plurality of filters; the transmission line between each of the plurality of filters and the antenna switch; or the transmission line between the antenna switch and the antenna terminal.

10. The high-frequency power amplifier circuit according to claim 9, wherein the threshold control circuit is configured to change the threshold control voltage according to the filter selected by the filter selection switch.

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