Semiconductor device and storage element

Abstract

The present invention reduces the circuit area in a semiconductor device that uses an electric fuse and an anti-fuse.　One end of the anti-fuse is connected to a first input node. The electric fuse is inserted between the other end of the anti-fuse and a second input node. A control circuit performs at least one from among: first write control for changing the resistive state of the anti-fuse by applying a prescribed first stress voltage between the first input node and the second input node; and second write control for changing the resistive state of the electric fuse by applying a second stress voltage, which is higher than the first stress voltage, between the first input node and the second input node.

Description

Semiconductor device and memory element

[0001] The present technology relates to a semiconductor device. More specifically, it relates to a semiconductor device provided with a fuse whose resistance state changes, and a memory element.

[0002] Semiconductor integrated circuits may be integrated with OTP (One Time Programmable) memory that allows data writing only once, or MTP (Multi-Time Programmable) memory that allows data writing multiple times. In these memories, electrical fuses or antifuses are used. For example, there has been proposed a semiconductor device in which a voltage is applied to a memory element formed by connecting a polysilicon-type electrical fuse and an oxide breakdown-type antifuse in series to change the resistance state of each fuse (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2014-143284

[0004] In the above-described conventional technology, three-value data writing to a memory element is achieved by changing the resistance states of the electrical fuse and the antifuse, respectively. However, with the above-described conventional technology, it is difficult to further reduce the circuit area.

[0005] The present technology has been developed in view of such circumstances, and an object thereof is to reduce the circuit area in a semiconductor device using an electrical fuse and an antifuse.

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is a semiconductor device comprising: an antifuse with one end connected to a first input node; a via-type electric fuse inserted between the other end of the antifuse and a second input node; and a control circuit that performs at least one of a first write control that changes the resistance state of the antifuse by applying a predetermined first stress voltage between the first input node and the second input node; and a second write control that changes the resistance state of the electric fuse by applying a second stress voltage higher than the first stress voltage between the first input node and the second input node. This results in data being written to a semiconductor device with a reduced circuit area.

[0007] Furthermore, in this first aspect, the control circuit may perform the second write control after the first write control if it is changing the resistance state of the electrical fuse. This results in the data being written to the electrical fuse after the antifuse.

[0008] Furthermore, in this first aspect, the system may further include a read circuit that generates a read voltage corresponding to the resistance value of the memory element including the antifuse and the electrical fuse, a reference voltage generation circuit that generates a predetermined reference voltage, and a comparator that compares the read voltage with the reference voltage and outputs the comparison result. This brings about the function of reading out the data.

[0009] Furthermore, in this first aspect, the reference voltage includes first and second reference voltages, the resistance value of the memory element includes a first resistance value before the first write control, a second resistance value after the first write control and before the second write control, and a third resistance value after the second write control, the first reference voltage may be a voltage corresponding to the resistance value between the distribution of the first resistance value and the distribution of the second resistance value, and the second reference voltage may be a voltage corresponding to the resistance value between the distribution of the first resistance value and the distribution of the third resistance value. This results in the reading of three-value data.

[0010] Furthermore, in this first aspect, the antifuse and the electrical fuse may be placed in each of the multiple memory elements. This results in data being stored in each of the multiple memory elements.

[0011] Furthermore, in this first aspect, the antifuse may be an oxide film destruction type antifuse. This results in the oxide film being destroyed by data writing.

[0012] Furthermore, a second aspect of this technology is a memory element comprising an antifuse with one end connected to the first input node, and a via-type electrical fuse inserted between the other end of the antifuse and the second input node. This results in a reduction in circuit area.

[0013] This is a circuit diagram showing an example configuration of a semiconductor device in the first embodiment of this technology. This is an example of a cross-sectional view and a plan view of a semiconductor device in the first embodiment of this technology. This is a diagram for explaining the first write operation in the first embodiment of this technology. This is a diagram for explaining the second write operation in the first embodiment of this technology. This is a timing chart showing an example of write control of a semiconductor device in the first embodiment of this technology. This is a diagram for explaining the first read operation in the first embodiment of this technology. This is a diagram for explaining the second read operation in the first embodiment of this technology. This is a diagram showing an example of the resistance state of a memory element in the first embodiment of this technology. This is a graph showing an example of the variation in the resistance value of a memory element in the first embodiment of this technology. This is a timing chart showing another example of write control of a semiconductor device in the first embodiment of this technology. This is a circuit diagram showing an example configuration of a semiconductor device in the second embodiment of this technology. This is a circuit diagram showing an example configuration of a semiconductor device in the second embodiment of this technology in which a reference voltage generation circuit is shared in multiple rows.

[0014] The following describes the embodiments for implementing this technology. The description will proceed in the following order: 1. First embodiment (an example in which an antifuse and a via-type electric fuse are connected in series) 2. Second embodiment (an example in which an antifuse and a via-type electric fuse are connected in series for each of the multiple memory elements)

[0015] <1. First Embodiment> [Example of Semiconductor Device Configuration] Figure 1 is a circuit diagram showing an example configuration of a semiconductor device 100 in the first embodiment of this technology. The semiconductor device 100 is a device capable of writing data up to two times and comprises a control circuit 110, a writing circuit 120, a memory element 130, a reading circuit 140, a reference voltage generation circuit 150, and a comparator 160. As the semiconductor device 100, for example, an OTP memory or an MTP memory is envisioned. These memories can be mounted on an image sensor or the like and stored in them to store data used for correction.

[0016] The control circuit 110 controls the writing of data to the memory element 130 and the reading of data from the memory element 130 according to external write and read commands. The control circuit 110 generates a voltage Vfuse and control signals Sw and Vblow and supplies them to the write circuit 120. The control circuit 110 also generates control signals Sr1 and Sr2 and supplies them to the read circuit 140, and generates control signals Sr3, Sr4, Sr5 and Sr6 and supplies them to the reference voltage generation circuit 150.

[0017] The writing circuit 120 writes data to the memory element 130. This writing circuit 120 includes a blow transistor 121 and a writing transistor 122. For example, an nMOS (n-channel Metal Oxide Semiconductor) transistor is used as the blow transistor 121. For example, a pMOS (p-channel MOS) transistor is used as the writing transistor 122.

[0018] The blow transistor 121 opens and closes the path between the input node N1 of the memory element 130 and the ground node according to the control signal Vblow. The write transistor 122 opens and closes the path between the voltage Vfuse and the input node N2 of the memory element 130 according to the control signal Sw.

[0019] The memory element 130 includes an oxide film destruction type antifuse 131 and a via-type electric fuse 132. One end of the antifuse 131 is connected to input node N1, and the electric fuse 132 is inserted between the other end of the antifuse 131 and input node N2. That is, the antifuse 131 and the electric fuse 132 are connected in series. Input nodes N1 and N2 are examples of the first and second input nodes described in the claims.

[0020] Furthermore, the resistance state of the antifuse 131 is either a high-resistance state where the resistance value is higher than a predetermined value, or a low-resistance state where the resistance value is lower than that predetermined value. In the initial state, the antifuse 131 is in the high-resistance state, and after the first write operation, it changes from the high-resistance state to the low-resistance state.

[0021] Furthermore, the resistance state of the electrical fuse 132 is either a high-resistance state where the resistance value is higher than a predetermined value, or a low-resistance state where the resistance value is lower than that predetermined value. In the initial state, the electrical fuse 132 is in the low-resistance state, and after the second write operation, it changes from the low-resistance state to the high-resistance state.

[0022] The read circuit 140 generates a read voltage Vm corresponding to the resistance value of the memory element 130. This read circuit 140 includes a pMOS transistor 141 and an nMOS transistor 142.

[0023] The pMOS transistor 141 opens and closes the path between the power supply voltage VDD and the non-inverting input terminal (+) of the comparator 160 according to the control signal Sr1. The nMOS transistor 142 opens and closes the path between the input node N2 and the non-inverting input terminal (+) of the comparator 160 according to the control signal Sr2.

[0024] The reference voltage generation circuit 150 generates a reference voltage Vref and supplies it to the inverting input terminal (-) of the comparator 160. This reference voltage generation circuit 150 comprises a pMOS transistor 151, nMOS transistors 152, 153 and 154, and resistors 155 and 156.

[0025] One end of each resistor element 155 and 156 is commonly connected to the source of the nMOS transistor 152. The other end of resistor element 155 is connected to the drain of the nMOS transistor 153, and the other end of resistor element 156 is connected to the drain of the nMOS transistor 154. The resistance values ​​of these resistor elements 155 and 156 are different. Let the resistance value of resistor element 155 be Rth1, and the resistance value of resistor element 156 be Rth2.

[0026] The pMOS transistor 151 opens and closes the path between the power supply voltage VDD and the inverting input terminal (-) of the comparator 160 according to the control signal Sr3.

[0027] The nMOS transistor 152 opens and closes the path between the connection nodes of the resistors 155 and 156 and the inverting input terminal (-) of the comparator 160, according to the control signal Sr4.

[0028] The nMOS transistor 153 opens and closes the path between the resistor 155 and the ground node according to the control signal Sr5. The nMOS transistor 154 opens and closes the path between the resistor 156 and the ground node according to the control signal Sr6.

[0029] The comparator 160 compares the read voltage Vm with the reference voltage Vref and outputs data showing the comparison result as Sout. For example, a sense amplifier can be used as the comparator 160.

[0030] Figure 2 shows an example of a cross-sectional view and a plan view of the semiconductor device 100 in the first embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor device 100, and b shows a plan view of the semiconductor device 100.

[0031] As illustrated in Figure a, the semiconductor device 100 is provided with a silicon substrate Sub. The axis perpendicular to the substrate plane of the silicon substrate Sub is defined as the "Z axis," and a predetermined axis parallel to the substrate plane is defined as the "X axis." The axis perpendicular to the X and Z axes is defined as the "Y axis." Figure a shows a cross-sectional view from the Y-axis direction, and Figure b shows a plan view from the Z-axis direction.

[0032] An oxide-destroying type antifuse 131 is formed on the silicon substrate Sub. During the first write operation, the oxide film between the gate of the antifuse 131 and the silicon substrate Sub is destroyed.

[0033] Furthermore, a via-type electrical fuse 132 is stacked on the gate of the antifuse 131. The gate of the antifuse 131 is connected to the wiring layer M1 via the electrical fuse 132. The via of the electrical fuse 132 is destroyed by the second write operation.

[0034] Furthermore, in addition to the memory element 130 consisting of an antifuse 131 and an electrical fuse 132, a blow transistor 121 is formed on the silicon substrate Sub. These elements are isolated by STI (Shallow Trench Isolation). As illustrated in figure b, the STI is formed around the silicon substrate Sub. Also, the shaded area in figure a shows the diffusion layer of the silicon substrate Sub. These diffusion layers are via V １ It is connected to the wiring layer M1 via a predetermined number of vias V. ２ It is connected to wiring layer M2 via this.

[0035] As described in Patent Document 1 above, we will consider a case where a polysilicon type electric fuse 11 and an oxide film breakdown type antifuse 12 are connected in series as a point of comparison. In this case, as illustrated in Figures 2A and B of Patent Document 1, the electric fuse 11 is not stacked on the antifuse 12, and in a plan view, the electric fuse 11 is positioned in the vicinity of the antifuse 12.

[0036] In contrast, when a via-type electrical fuse 132 and an oxide film-breaking type antifuse 131 are connected in series, the fuses can be stacked, as illustrated in Figure 2a. This reduces the circuit area and increases the capacity of the semiconductor device 100 compared to Patent Document 1.

[0037] Furthermore, the polysilicon type electric fuse 11 described in Patent Document 1 is difficult to use in advanced processes. In contrast, the via-type electric fuse 132 is suitable for advanced processes.

[0038] [Example of Semiconductor Device Operation] Next, with reference to Figures 3 and 4, the control when writing data to the memory element 130 will be explained. As mentioned above, data can be written to the memory element 130 up to two times.

[0039] Figure 3 is a diagram illustrating the first write operation in the first embodiment of this technology.

[0040] The control circuit 110 supplies a positive voltage Vfuse1, sets the control signal Sw to a low level, and sets the control signal Vblow to a high level. This applies a predetermined voltage between input nodes N1 and N2, and this voltage is designated as the "first stress voltage". The white arrows in the figure indicate the first stress voltage. This first stress voltage is set to a value that destroys the oxide film of the antifuse 131. In addition, current flows from the writing transistor 122 to the ground node via the memory element 130 and the blow transistor 121. The thick dotted lines in the figure indicate the current path.

[0041] This first write control destroys the oxide film of the antifuse 131, changing the resistance state of the antifuse 131 from a high resistance state to a low resistance state. Because the oxide film is destroyed, after the first write control, it is not possible to update the data of the antifuse 131; only reading is possible.

[0042] Figure 4 is a diagram illustrating the second write operation in the first embodiment of this technology.

[0043] After the first write control, the control circuit 110 sets the control signal Sw to a low level and the control signal Vblow to a high level while supplying Vfuse2, which is a positive voltage higher than Vfuse1. Accordingly, a voltage higher than the first stress voltage is applied between the input nodes N1 and N2, and this voltage is referred to as a "second stress voltage". The second stress voltage is set to a value enough to break the via of the electrical fuse 132. The outlined arrow in the figure indicates the second stress voltage. Further, a current flows from the write transistor 122 to the ground node via the memory element 130 and the blow transistor 121. The thick dotted line in the figure indicates the current path.

[0044] By the second write control after the first write control, the via of the electrical fuse 132 is broken, and the resistance state of the electrical fuse 132 changes from a low resistance state to a high resistance state. Since the oxide film has been broken and the via is also broken, the data in the anti-fuse 131 and the electrical fuse 132 cannot be updated after the second write, and can only be read.

[0045] The semiconductor device 100 does not necessarily need to perform the second write control, and may perform only the first write control. However, even if the semiconductor device 100 performs only the second write control without performing the first write control, the via cannot be broken because the anti-fuse 131 is in a high resistance state. For this reason, it is assumed that performing only the second write control without performing the first write control is prohibited.

[0046] As described above, the control circuit 110 performs at least one of: first write control that changes the resistance state of the anti-fuse 131 by applying the first stress voltage; and second write control that changes the resistance state of the electrical fuse 132 by applying the second stress voltage. Accordingly, three-value data can be written to the memory element 130.

[0047] FIG. 5 is a timing chart showing an example of write control of the semiconductor device 100 according to the first embodiment of the present technology. a in the figure shows an example of first write control, and b in the figure shows an example of second write control.

[0048] When performing the first write operation, the control circuit 110 supplies Vfuse1. The blow period during which the first stress voltage is applied is defined as the period from timing T2 to timing T3. The control circuit 110 changes the control signal Sw from a high level to a low level at timing T1, which is immediately before timing T2. Then, the control circuit 110 changes the control signal Vblow from a low level to a high level at timing T2, and changes the control signal Sw to a high level and the control signal Vblow to a low level at timing T3.

[0049] Then, when performing the second write operation after the first write operation, the control circuit 110 supplies Vfuse2 which is higher than Vfuse1. The blow period during which the second stress voltage is applied is defined as the period from timing T12 to timing T13. The control circuit 110 changes the control signal Sw from a high level to a low level at timing T11, which is immediately before timing T12. Then, the control circuit 110 changes the control signal Vblow from a low level to a high level at timing T12, and changes the control signal Sw to a high level and the control signal Vblow to a low level at timing T13.

[0050] It should be noted that although the control circuit 110 changes the voltage Vfuse when performing the second write operation, the control is not limited to this. The control circuit can change at least one of the control signals Sw, Vblow and the voltage Vfuse when performing the second write operation. For example, the control circuit 110 can set the level of the control signal Sw lower than that in the first write operation. Alternatively, the control circuit 110 can set the level of the control signal Vblow higher than that in the first write operation.

[0051] Next, control for reading data from the memory element 130 will be described with reference to FIG. 6 and FIG. 7.

[0052] FIG. 6 is a diagram for explaining the first read operation according to the first embodiment of the present technology.

[0053] When performing the first read operation, the control circuit 110 sets the control signals Sw and Vblow to high levels, the control signal Sr1 to low levels, and the control signal Sr2 to high levels. As a result, current flows from the power supply voltage VDD through the pMOS transistor 141, the nMOS transistor 142, the memory element 130, and the blow transistor 121 to the ground node, and a read voltage Vm corresponding to the resistance value of the memory element 130 is supplied to the comparator 160. The thick dotted lines in the figure indicate the current path.

[0054] Furthermore, the control circuit 110 sets the control signal Sr3 to a low level, the control signals Sr4 and Sr5 to high levels, and the control signal Sr6 to a low level. This generates a reference voltage Vref1 corresponding to the resistance value Rth1 of the resistor element 155, which is supplied to the comparator 160. This resistance value Rth1 is set to a value between the resistance distribution of the memory element 130 before the first write operation and the resistance distribution of the memory element 130 after the first write operation.

[0055] The comparator 160 compares the read voltage Vm with the reference voltage Vref1 and outputs data Sout1 showing the comparison result.

[0056] Figure 7 is a diagram illustrating the second readout in the first embodiment of this technology.

[0057] When performing the second readout, the control circuit 110 sets the control signals Sw and Vblow to high levels, the control signal Sr1 to low levels, and the control signal Sr2 to high levels. As a result, the readout voltage Vm is supplied to the comparator 160.

[0058] Furthermore, the control circuit 110 sets control signal Sr3 to a low level, control signal Sr4 to a high level, control signal Sr5 to a low level, and control signal Sr6 to a high level. This generates a reference voltage Vref2 corresponding to the resistance value Rth2 of the resistor element 156, which is supplied to the comparator 160. This resistance value Rth2 is set to a value between the resistance distribution of the memory element 130 before the first write and the resistance distribution of the memory element 130 after the second write.

[0059] The comparator 160 compares the read voltage Vm with the reference voltage Vref2 and outputs data Sout2 showing the comparison result.

[0060] During the read operation, the control circuit 110 performs the read operation shown in Figure 6 and then in Figure 7 in sequence. This results in the reading of 2-bit data representing three values. The semiconductor device 100 generates Vref1 the first time and Vref2 the second time, but it is not limited to this order; it can also generate Vref2 the first time and Vref1 the second time.

[0061] Figure 8 shows an example of the resistance state of the memory element 130 in the first embodiment of this technology.

[0062] In the initial state before writing, the oxide film breakdown type antifuse 131 is in a high-resistance state, and the via-type electric fuse 132 is in a low-resistance state. Let Rm1 be the resistance value of the memory element 130 at this time.

[0063] The first write operation destroys the oxide film of the antifuse 131, causing the antifuse 131 to transition to a low-resistance state. Meanwhile, the electrical fuse 132 remains in a low-resistance state. Let Rm2 be the resistance value of the memory element 130 at this time. Rm2 is lower than Rm1.

[0064] Then, the via of the electrical fuse 132 is destroyed by the second write operation, and the electrical fuse 132 transitions to a high-resistance state. Meanwhile, the anti-fuse 131 remains in a low-resistance state. Let Rm3 be the resistance value of the memory element 130 at this time. Rm3 is a higher value than Rm1.

[0065] As illustrated in the figure, the resistance value of the memory element 130 is one of three values, and different data values ​​can be assigned to each resistance value. For example, "00" in binary can be assigned to Rm1, "10" in binary can be assigned to Rm2, and "11" in binary can be assigned to Rm3. In this way, the memory element 130 can hold three-value data.

[0066] Figure 9 is a graph showing an example of the variation in the resistance value of the memory element 130 in the first embodiment of this technology. In the figure, the horizontal axis represents the resistance value of the memory element 130, and the vertical axis represents the degree of variation.

[0067] When the oxide film is destroyed by the first write operation, the resistance value Rm2 at that time becomes lower than the resistance value Rm1 before the write operation. Also, when the via is destroyed by the second write operation, the resistance value Rm3 at that time becomes higher than the resistance value Rm1.

[0068] The resistance value Rth1 of the resistor element 155 used during reading is set to a value between the distribution of Rm2 and the distribution of Rm1. Similarly, the resistance value Rth2 of the resistor element 156 is set to a value between the distribution of Rm1 and the distribution of Rm3. By comparing these resistance values ​​Rth1 and Rth2 with reference voltages Vref1 and Vref2, the semiconductor device 100 can read out three-value data.

[0069] Furthermore, instead of storing three values, only two values ​​are stored, and the semiconductor device 100 can be rewritten from "0" to "1" in the first write operation, and then rewritten back from "1" to "0" in the second write operation. In this case, for example, "1" is assigned to the distribution of Rm1, which has a lower resistance value than Rth1, and "0" is assigned to the distribution of Rm2 and Rm3, which have higher resistance values ​​than Rth1. Even if the value is rewritten to "1" by destroying the oxide film in the first write operation, it is possible to rewrite it back to "0" by destroying the vias in the second write operation to increase resistance. In this case, the resistor element 156 and nMOS transistor 154 corresponding to Rth2 may be reduced.

[0070] Furthermore, the resistance values ​​Rm1, Rm2, and Rm3 are examples of the first, second, and third resistance values ​​described in the claims. Also, the reference voltages Vref1 and Vref2 are examples of the first and second reference voltages described in the claims.

[0071] Furthermore, although Figure 5 shows that the control circuit 110 supplied constant voltages Vfuse1 and Vfuse2, the control is not limited to this.

[0072] As illustrated in Figure 10a, the control circuit 110 can change the voltage Vfuse from level 0 to Vfuse1 at timing T0, immediately before timing T1, and then change the voltage Vfuse back to level 0 at timing T3. Also, as illustrated in Figure 10b, the control circuit 110 can change the voltage Vfuse from level 0 to Vfuse2 at timing T10, immediately before timing T11, and then change the voltage Vfuse back to level 0 at timing T13.

[0073] Thus, according to the first embodiment of this technology, since the antifuse 131 and the via-type electric fuse 132 are connected in series, they can be stacked to reduce the circuit area.

[0074] <2. Second Embodiment> In the first embodiment described above, one memory element 130 was placed inside the semiconductor device 100, but multiple memory elements 130 can also be arranged. The semiconductor device 100 in this second embodiment differs from the first embodiment in that multiple memory elements 130 are arranged inside.

[0075] Figure 11 is a circuit diagram showing one example configuration of a semiconductor device 100 in a second embodiment of the present technology. The semiconductor device 100 of the second embodiment comprises a control circuit 110, a plurality of memory cells 170, a plurality of writing transistors 122, a plurality of reading circuits 140, a plurality of reference voltage generation circuits 150, and a plurality of comparators 160.

[0076] The memory cells 170 are arranged in a two-dimensional grid, and one write transistor 122, one read circuit 140, one reference voltage generation circuit 150, and one comparator 160 are placed in each row of memory cells 170.

[0077] The memory cell 170 comprises a blow transistor 121 and a memory element 130. The input node N2 of the memory element 130 is connected to the write transistor 122 and read circuit 140 of the corresponding column via vertically wired signal lines. If the memory cell 170 has M rows (where M is an integer) and N columns (where N is an integer), then a control signal Vblow[m] is supplied to m rows (where m is an integer from 1 to M). Also, a control signal Sw[n] is supplied to n columns (where n is an integer from 1 to N).

[0078] The control circuit 110 can write to the m-row, n-column memory cell 170 using the control signal Vblow[m] and the control signal Sw[n].

[0079] Although a reference voltage generation circuit 150 is provided for each column, the configuration is not limited to this.

[0080] As illustrated in Figure 12, multiple columns (such as all columns) can share a single reference voltage generation circuit 150.

[0081] Thus, according to the second embodiment of this technology, since multiple memory elements 130 are arranged, more data can be stored in the semiconductor device 100 than in the first embodiment.

[0082] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0083] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0084] Furthermore, this technology can also take the following configurations: (1) A semiconductor device comprising: an antifuse with one end connected to a first input node; a via-type electric fuse inserted between the other end of the antifuse and a second input node; and a control circuit that performs at least one of a first write control that changes the resistance state of the antifuse by applying a predetermined first stress voltage between the first input node and the second input node, and a second write control that changes the resistance state of the electric fuse by applying a second stress voltage higher than the first stress voltage between the first input node and the second input node. (2) The semiconductor device according to (1), wherein the control circuit performs the second write control after the first write control when changing the resistance state of the electric fuse. (3) The semiconductor device according to (2), further comprising: a read circuit that generates a read voltage corresponding to the resistance values ​​of memory elements including the antifuse and the electric fuse; a reference voltage generation circuit that generates a predetermined reference voltage; and a comparator that compares the read voltage and the reference voltage and outputs a comparison result. (4) The semiconductor device according to (3), wherein the reference voltage includes first and second reference voltages, the resistance of the memory element includes a first resistance before the first write control, a second resistance after the first write control and before the second write control, and a third resistance after the second write control, the first reference voltage is a voltage corresponding to the resistance between the distribution of the first resistance and the distribution of the second resistance, and the second reference voltage is a voltage corresponding to the resistance between the distribution of the first resistance and the distribution of the third resistance. (5) The semiconductor device according to any one of (1) to (4), wherein the antifuse and the electric fuse are arranged in each of the plurality of memory elements. (6) The semiconductor device according to any one of (1) to (5), wherein the antifuse is an oxide film breakdown type antifuse. (7) A memory element comprising an antifuse with one end connected to a first input node, and a via-type electric fuse inserted between the other end of the antifuse and a second input node.

[0085] 100 Semiconductor device 110 Control circuit 120 Writing circuit 121 Blow transistor 122 Writing transistor 130 Memory element 131 Antifuse 132 Electrical fuse 140 Reading circuit 141, 151 pMOS transistor 142, 152-154 nMOS transistor 150 Reference voltage generation circuit 155, 156 Resistor element 160 Comparator 170 Memory cell

Claims

1. A semiconductor device comprising: an antifuse with one end connected to a first input node; a via-type electric fuse inserted between the other end of the antifuse and a second input node; and a control circuit that performs at least one of a first write control that changes the resistance state of the antifuse by applying a predetermined first stress voltage between the first input node and the second input node, and a second write control that changes the resistance state of the electric fuse by applying a second stress voltage higher than the first stress voltage between the first input node and the second input node.

2. The semiconductor device according to claim 1, wherein the control circuit performs the second write control after the first write control when changing the resistance state of the electrical fuse.

3. The semiconductor device according to claim 2, further comprising: a read circuit that generates a read voltage corresponding to the resistance value of a memory element including the antifuse and the electrical fuse; a reference voltage generation circuit that generates a predetermined reference voltage; and a comparator that compares the read voltage with the reference voltage and outputs a comparison result.

4. The semiconductor device according to claim 3, wherein the reference voltage includes first and second reference voltages, the resistance value of the memory element includes a first resistance value before the first write control, a second resistance value after the first write control and before the second write control, and a third resistance value after the second write control, the first reference voltage is a voltage corresponding to the resistance value between the distribution of the first resistance value and the distribution of the second resistance value, and the second reference voltage is a voltage corresponding to the resistance value between the distribution of the first resistance value and the distribution of the third resistance value.

5. The semiconductor device according to claim 1, wherein the antifuse and the electrical fuse are arranged in each of the plurality of memory elements.

6. The semiconductor device according to claim 1, wherein the antifuse is an oxide film destruction type antifuse.

7. A memory element comprising an antifuse with one end connected to a first input node, and a via-type electrical fuse inserted between the other end of the antifuse and a second input node.

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