Imaging device

Abstract

The present invention addresses the problem of expanding HDR while suppressing an increase in the number of times conversion efficiency is switched.　This imaging device is provided with: first to third floating diffusions; a first switching transistor that switches the connection between the first floating diffusion and the second floating diffusion on the basis of a first switching signal; a second switching transistor that is connected in parallel to the first switching transistor and switches the connection between the first floating diffusion and the second floating diffusion on the basis of a second switching signal; a third switching transistor that switches the connection between the second floating diffusion and the third floating diffusion on the basis of a third switching signal; and a fourth switching transistor that is connected in series to the third switching transistor and switches the connection between the second floating diffusion and the third floating diffusion on the basis of a fourth switching signal.

Description

Image pickup apparatus

[0001] The present technology relates to an image pickup apparatus. More specifically, the present technology relates to an image pickup apparatus capable of switching conversion efficiency.

[0002] In order to realize HDR (High Dynamic Range), there exist image pickup apparatuses capable of switching conversion efficiency. For example, a technique has been proposed that switches the conversion efficiency for converting charges photoelectrically converted by a photoelectric conversion unit into a voltage in accordance with a determination result of illuminance (see, for example, Patent Document 1).

[0003] Japanese Unexamined Patent Publication No. 2023-32311

[0004] However, in the above-described conventional technology, expanding the HDR dynamic range may cause an increase in the number of conversion efficiency switching operations, which may lead to a decrease in frame rate.

[0005] The present technology has been developed in view of such circumstances, and an object of the present technology is to expand an HDR dynamic range while suppressing an increase in the number of conversion efficiency switching operations.

[0006] This technology was developed to solve the above-mentioned problems, and its first aspect is an imaging device comprising: a photoelectric conversion unit provided in a pixel; a first floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred; a second floating diffusion separable from the first floating diffusion; a third floating diffusion separable from the second floating diffusion; a first switching transistor that switches the connection between the first floating diffusion and the second floating diffusion based on a first switching signal; a second switching transistor connected in parallel with the first switching transistor and switching the connection between the first floating diffusion and the second floating diffusion based on a second switching signal; a third switching transistor that switches the connection between the second floating diffusion and the third floating diffusion based on a third switching signal; and a fourth switching transistor connected in series with the third switching transistor and switching the connection between the second floating diffusion and the third floating diffusion based on a fourth switching signal. This results in the connection between the first to third floating diffusions being switched based on the first to fourth switching signals.

[0007] Furthermore, in the first aspect, the first switching signal and the third switching signal may be made common, and the second switching signal and the fourth switching signal may also be made common. This reduces the number of control lines for the first to fourth switching signals, while providing the effect of switching the conversion efficiency in multiple stages based on the switching of the connection between the first to third floating diffusions.

[0008] Furthermore, in the first aspect, the pixels may be arranged in a matrix in the row direction and column direction, and may include horizontal control lines that transmit the first switching signal and the third switching signal in the row direction, and vertical control lines that transmit the second switching signal and the fourth switching signal in the column direction. This results in the conversion efficiency being switched based on the switching of connections between the first to third floating diffusions based on the first to fourth switching signals.

[0009] Furthermore, in the first aspect, the pixel may include a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to a first floating diffusion, a reset transistor that resets the first floating diffusion, an amplifier transistor that outputs a pixel signal corresponding to the charge accumulated in the first floating diffusion, and a selection transistor that selects the output from the amplifier transistor. This results in the operation of reading a signal from the pixel while switching the conversion efficiency in multiple stages based on the switching of the connection between the first to third floating diffusions.

[0010] Furthermore, the first side may include a first chip on which the photoelectric conversion unit, the first floating diffusion, the first switching transistor, the second switching transistor, the transfer transistor, and the amplifier transistor are formed, and a second chip on which the first chip is stacked and on which the reset transistor and the selection transistor are formed. This has the effect of suppressing the decrease in conversion efficiency in HCG while suppressing the increase in the planar size of the pixels.

[0011] Furthermore, in the first aspect, the photoelectric conversion unit may include a first photodiode connected to the first floating diffusion via the transfer transistor, and a second photodiode connected to the third floating diffusion and having lower sensitivity than the first photodiode. This has the effect of expanding the dynamic range in HDR while suppressing a decrease in frame rate.

[0012] Furthermore, in the first aspect, when the gate potential of the transfer transistor is set to an intermediate potential, low or high illumination is determined based on the signal level corresponding to the charge transferred to the first floating diffusion. If low illumination is determined, the first to fourth switching transistors are turned off and the conversion efficiency is set to HCG (High Conversion Gain). The P-phase level and D-phase level are sequentially read out based on the charge accumulated in the first photodiode, the second and fourth switching transistors are turned off, and the first and third switching transistors are turned on to set the conversion efficiency to LCG (Low Conversion Gain). The Gain is set to LCG, and the D-phase level and P-phase level are sequentially read based on the charge accumulated in the first photodiode. If high illumination is determined, the second and fourth switching transistors are turned off, the first and third switching transistors are turned on to set the conversion efficiency to LCG, and the D-phase level and P-phase level are sequentially read based on the charge accumulated in the first photodiode. The first to fourth switching transistors are then turned on to set the conversion efficiency to LCG, and the P-phase level and D-phase level are sequentially read based on the charge accumulated in the second photodiode. This enables CDS (Correlated Double Sampling) or DDS (Double Data Sampling) in pixels provided with the first and second photodiodes, while allowing the conversion efficiency to be switched in three stages based on two D-phase level readouts.

[0013] Furthermore, in the first aspect, the system may include a fifth switching transistor connected in parallel to the third switching transistor, which switches the connection between the second floating diffusion and the third floating diffusion based on a fifth switching signal, and a sixth switching transistor connected in series with the fourth switching transistor, which switches the connection with the third floating diffusion based on a sixth switching signal. This results in the connection between the first to third floating diffusions being switched based on the first to fifth switching signals.

[0014] Furthermore, in the first aspect, the first switching signal and the third switching signal may be made common, and the fifth switching signal and the sixth switching signal may also be made common. This reduces the number of control lines for the first to fifth switching signals, while providing the effect of switching the conversion efficiency in multiple stages based on the switching of the connection between the first to third floating diffusions.

[0015] Furthermore, in the first aspect, the pixels may be arranged in a matrix in the row direction and column direction, and may include horizontal control lines that transmit the first switching signal and the third switching signal in the row direction, and vertical control lines that transmit the fifth switching signal and the sixth switching signal in the column direction. This results in the conversion efficiency being switched based on the switching of connections between the first to third floating diffusions based on the first to sixth switching signals.

[0016] Furthermore, in the first aspect, a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to the first floating diffusion, and a first LOFIC (Lateral Overflow Integration) connected to the third floating diffusion The system comprises a Capacitor and a second LOFIC connected to the third floating diffusion via the sixth switching transistor. When the gate potential of the transfer transistor is set to an intermediate potential, low or high illumination is determined based on the signal level corresponding to the charge transferred to the first floating diffusion. If low illumination is determined, the first to sixth switching transistors are turned off to set the conversion efficiency to HCG. The P-phase level and D-phase level are sequentially read based on the charge accumulated in the photoelectric conversion unit. The second and fourth switching transistors are turned on, the first, third, fifth and sixth switching transistors are turned off to set the conversion efficiency to LCG. The D-phase level is read based on the charge accumulated in the photoelectric conversion unit. The second, fourth, fifth and sixth switching transistors are turned on, the first and third switching transistors are turned off to set the conversion efficiency to LCG. The D-phase level and P-phase level are read sequentially, the second switching transistor is turned on, the first and third to sixth switching transistors are turned off to set the conversion efficiency to LCG, the P-phase level is read based on the charge accumulated in the photoelectric conversion unit, and if high illuminance is determined, the first and third switching transistors are turned on, the second and fourth to sixth switching transistors are turned off to set the conversion efficiency to LCG, the P-phase level and D-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit, the first to fourth switching transistors are turned on, the fifth and sixth switching transistors are turned off to set the conversion efficiency to LCG, the D-phase level is read based on the charge accumulated in the photoelectric conversion unit and the first LOFIC, the first to sixth switching transistors are turned on to set the conversion efficiency to LCG, the D-phase level and P-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit and the second LOFIC, the first to third switching transistors are turned on,The fourth to sixth switching transistors may be turned off to set the conversion efficiency to LCG, and the P-phase level may be read out based on the charge accumulated in the photoelectric conversion unit and the first LOFIC. This results in the ability to switch the conversion efficiency in four stages based on three D-phase level readouts, while enabling CDS or DDS in pixels provided with the first and second LOFICs.

[0017] Furthermore, in the first aspect, an overflow control transistor may be provided connected between the first LOFIC and the photoelectric conversion unit. This suppresses a decrease in frame rate, expands the dynamic range in HDR, and reduces fixed pattern noise caused by dark current.

[0018] Furthermore, in the first aspect, a seventh switching transistor may be provided, which is connected in parallel to the sixth switching transistor and switches the connection between the third floating diffusion and the sixth switching transistor based on a seventh switching signal. This results in the connection between the first to third floating diffusions being switched based on the first to seventh switching signals.

[0019] Furthermore, in the first aspect, the first switching signal, the third switching signal, and the seventh switching signal may be made common, and the fifth switching signal and the sixth switching signal may also be made common. This reduces the number of control lines for the first to seventh switching signals, while providing the effect of switching the conversion efficiency in multiple stages based on the switching of the connection between the first to third floating diffusions.

[0020] Furthermore, in the first aspect, the pixels may be arranged in a matrix in the row and column directions and include horizontal control lines that transmit the first switching signal, the third switching signal, and the seventh switching signal in the row direction, and vertical control lines that transmit the fifth switching signal and the sixth switching signal in the column direction. This results in the conversion efficiency being switched based on the switching of connections between the first to third floating diffusions based on the first to seventh switching signals.

[0021] Furthermore, in the first aspect, a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to the first floating diffusion, and a first LOFIC (Lateral Overflow Integration) connected to the third floating diffusion The device comprises a Capacitor and a second LOFIC connected to the third floating diffusion via the sixth and seventh switching transistors, and when the gate potential of the transfer transistor is set to an intermediate potential, it determines low or high illumination based on the signal level corresponding to the charge transferred to the first floating diffusion, and if low illumination is determined, it turns off the first to seventh switching transistors and sets the conversion efficiency to HCG, reads out the P-phase level and D-phase level sequentially based on the charge accumulated in the photoelectric conversion unit, turns on the second and fourth switching transistors, turns off the first, third and fifth to seventh switching transistors and sets the conversion efficiency to LCG, reads out the D-phase level based on the charge accumulated in the photoelectric conversion unit, turns on the second, fourth, fifth and sixth switching transistors, turns off the first, third and seventh switching transistors and sets the conversion efficiency to LCG, and the photoelectric conversion unit and the first L Based on the charge accumulated in the OFIC, the D-phase level and P-phase level are read sequentially, the second switching transistor is turned on, the first and third to seventh switching transistors are turned off to set the conversion efficiency to LCG, the P-phase level is read based on the charge accumulated in the photoelectric conversion unit, and if high illuminance is determined, the first and third switching transistors are turned on, the second and fourth to seventh switching transistors are turned off to set the conversion efficiency to LCG, the P-phase level and D-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit, the first to fourth and seventh switching transistors are turned on, the fifth and sixth switching transistors are turned off to set the conversion efficiency to LCG, the D-phase level is read based on the charge accumulated in the photoelectric conversion unit and the first LOFIC, the first to seventh switching transistors are turned on to set the conversion efficiency to LCG, the D-phase level and P-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit and the second LOFIC,The first to third and seventh switching transistors may be turned on, and the fourth to sixth switching transistors may be turned off to set the conversion efficiency to LCG. The P-phase level may then be read out based on the charge accumulated in the photoelectric conversion unit and the first LOFIC. This results in the ability to switch the conversion efficiency in four stages based on three D-phase level readouts, while enabling CDS or DDS in pixels provided with the first and second LOFICs.

[0022] Furthermore, in the first aspect, the photoelectric conversion unit may include a first photodiode connected to the first floating diffusion via the transfer transistor, and a second photodiode connected to the second floating diffusion and having lower sensitivity than the first photodiode. This results in an effect in which the dynamic range in HDR is expanded while suppressing a decrease in frame rate in pixels provided with the first and second photodiodes and LOFIC.

[0023] Furthermore, in the first aspect, the device includes a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to a first floating diffusion, a LOFIC connected to the third floating diffusion, and an eighth switching transistor that switches the connection between the second photodiode and the second floating diffusion. When the gate potential of the transfer transistor is set to an intermediate potential, the device determines low or high illumination based on the signal level corresponding to the charge transferred to the first floating diffusion. If low illumination is determined, the first to fourth and eighth switching transistors are turned off to set the conversion efficiency to HCG, and based on the charge accumulated in the first photodiode... The P-phase level and D-phase level are read sequentially, the second and fourth switching transistors are turned on, and the first, third and eighth switching transistors are turned off to set the conversion efficiency to LCG. Based on the charge accumulated in the first photodiode and the LOFIC, the D-phase level and P-phase level are read sequentially, the second and eighth switching transistors are turned on, and the first, third and fourth switching transistors are turned off to set the conversion efficiency to HCG. Based on the charge accumulated in the second photodiode, the D-phase level and P-phase level are read sequentially, and if high illumination is determined, the first and third switching transistors are turned on, and the second, fourth and eighth switching transistors are turned off to set the conversion efficiency to MCG (Middle The conversion efficiency may be set to LCG by setting the Conversion Gain to LCG, sequentially reading the P-phase level and D-phase level based on the charge accumulated in the first photodiode, turning on the first to fourth switching transistors and turning off the eighth switching transistor, sequentially reading the D-phase level and P-phase level based on the charge accumulated in the first photodiode and the LOFIC, turning on the first to third and eighth switching transistors and turning off the fourth switching transistor to LCG, and sequentially reading the D-phase level and P-phase level based on the charge accumulated in the second photodiode.This results in a pixel equipped with the first and second photodiodes and LOFIC, enabling CDS or DDS, while allowing the conversion efficiency to be switched in four stages based on three D-phase level readouts.

[0024] Furthermore, the second aspect is an imaging device comprising a transistor with a gate electrode provided on the channel region, wherein the channel region comprises three or more distinct paths. This results in the formation of three or more paths beneath the gate electrode.

[0025] Furthermore, in a second aspect, the transistor may be used as a transfer transistor that transfers the charge accumulated in the photoelectric conversion section to the floating diffusion, and the gate electrode of the transfer transistor may have multiple sides through the channel region to which the charge flows to different outflow destinations. This results in the formation of different outflow destinations under the gate electrode of the transfer transistor.

[0026] Furthermore, in a second aspect, the transfer transistor may include two impurity diffusion layers that branch off from the channel region to two different outflow destinations. This results in charge flowing out from the channel region beneath the gate electrode of the transfer transistor to two different outflow destinations.

[0027] Furthermore, in a second aspect, the transistor may be used as a switching transistor to switch the conversion efficiency of the pixels, and the gate electrode of the switching transistor may have multiple edges through which charge flows in from different inflow sources via the channel region. This results in the formation of a confluence point for charges from different inflow sources beneath the gate electrode of the switching transistor.

[0028] Furthermore, in a second aspect, the switching transistor may include two impurity diffusion layers into which charge from two inflow sources converges in the channel region. This results in charge flowing into the channel region beneath the gate electrode of the switching transistor from mutually different inflow sources.

[0029] Furthermore, in a second aspect, the two impurity diffusion layers may be short-circuited within the semiconductor layer in which the two impurity diffusion layers are formed. This eliminates the need for wiring while short-circuiting the two impurity diffusion layers.

[0030] Furthermore, in a second aspect, the two impurity diffusion layers may be short-circuited via wiring. This improves the flexibility of the layout while also providing the effect of short-circuiting the two impurity diffusion layers.

[0031] Furthermore, in a second aspect, the two impurity diffusion layers do not necessarily have to be short-circuited. This eliminates the need for wiring while improving the flexibility of the layout.

[0032] Furthermore, the third aspect is an imaging device comprising a photoelectric conversion unit provided in the pixel, a floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred, and a LOFIC to which the charge overflowing from the photoelectric conversion unit is accumulated, wherein the LOFIC comprises vias embedded in a semiconductor substrate and a dielectric layer formed between the semiconductor substrate and the vias, and the vias and the semiconductor substrate are used as counter electrodes for the LOFIC. This results in the LOFIC being formed based on the reuse of the via formation process.

[0033] This is a block diagram showing an example of the configuration of an imaging device according to the first embodiment. This is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment. This is a diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the first embodiment. This is a block diagram showing an example of the configuration of an AD conversion unit according to the first embodiment. This is a diagram showing an example of the circuit configuration of a comparator according to the first embodiment. This is a diagram showing the relationship between illuminance and mode in a solid-state imaging device according to the first embodiment. This is a timing chart showing the waveforms of each part of the signal readout process according to the first embodiment. This is a plan view showing an example of the first layout of a solid-state imaging device according to the first embodiment. This is a plan view showing an example of the second layout of a solid-state imaging device according to the first embodiment. This is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the first embodiment. This is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the second embodiment. This is a plan view showing an example of the layout of a solid-state imaging device according to the third embodiment. This is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the third embodiment. This is a diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the fourth embodiment. This is a timing chart showing the waveforms of each part of the signal readout process according to the fourth embodiment. This is a plan view showing an example of the layout of a solid-state imaging device according to the fourth embodiment. This is a plan view showing another example of the layout of the solid-state imaging device according to the fourth embodiment. This is a plan view showing yet another example of the layout of the solid-state imaging device according to the fourth embodiment. This is a diagram showing an example of the circuit configuration of pixels provided in the solid-state imaging device according to the fifth embodiment. This is a plan view showing an example of the layout of the solid-state imaging device according to the fifth embodiment. This is a plan view showing another example of the layout of the solid-state imaging device according to the fifth embodiment. This is a diagram showing an example of the circuit configuration of pixels provided in the solid-state imaging device according to the sixth embodiment. This is a timing chart showing the waveforms of each part of the signal readout process according to the sixth embodiment. This is a plan view showing an example of the layout of the solid-state imaging device according to the sixth embodiment. This is a diagram showing an example of the circuit configuration of pixels provided in the solid-state imaging device according to the seventh embodiment. This is a timing chart showing the waveforms of each part of the signal readout process according to the seventh embodiment. This is a plan view showing an example of the layout of the solid-state imaging device according to the seventh embodiment.This is a diagram showing an example of the circuit configuration of pixels provided in a solid-state imaging device according to the eighth embodiment. This is a plan view showing an example of the layout of a solid-state imaging device according to the eighth embodiment. This is a cross-sectional view showing an example of the configuration of timing chart showing the waveforms of each part of the signal readout process according to the eighth embodiment. This is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the ninth embodiment. This is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the tenth embodiment. This is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the eleventh embodiment. This is a perspective view showing an example of stacking of a solid-state imaging device according to the twelfth embodiment. This is a block diagram showing a schematic example of the configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of the imaging unit.

[0034] The following describes the embodiments for implementing this technology (hereinafter referred to as embodiments). The description will be in the following order: 1. First embodiment (an example in which a switching transistor is provided in the pixel to selectively switch between reading from a high-sensitivity photodiode and a low-sensitivity photodiode based on the illuminance determination result, and the pixel is divided and arranged on an upper layer chip and a lower layer chip) 2. Second embodiment (an example in which an overflow capacitance is formed in the pixel using a semiconductor substrate and vias embedded in the semiconductor substrate as counter electrodes) 3. Third embodiment (an example in which a pixel equipped with a switching transistor to switch between reading from a high-sensitivity photodiode and a low-sensitivity photodiode is arranged on a single-layer chip) 4. Fourth embodiment (an example in which a switching transistor is provided to selectively switch between reading from multiple LOFICs based on the illuminance determination result) 5. Fifth embodiment (an example in which a switching transistor is provided to selectively switch between reading from multiple LOFICs based on the illuminance determination result, and to select the LOFIC when reading the pixel signal) 6. 7. Seventh Embodiment (An example in which a switching transistor is provided to selectively switch readouts from multiple LOFICs based on the illuminance determination result, and an overflow control transistor is also provided) 8. Eighth Embodiment (An example in which a switching transistor is provided to selectively switch readouts from a LOFIC, a high-sensitivity photodiode, and a low-sensitivity photodiode based on the illuminance determination result) 9. Ninth Embodiment (An example in which a gate electrode of a transfer transistor is provided with multiple edges through which charge flows to different outflow destinations via a channel region, and a gate electrode of a switching transistor is provided with multiple edges through which charge flows in from different inflow sources via a channel region) 10. Ninth Embodiment (An example in which an upper layer chip equipped with a photodiode and a LOFIC is bonded to a lower layer chip based on face-to-face connection) 11. Tenth Embodiment (An example in which an upper layer chip equipped with a photodiode is bonded to a middle layer chip equipped with a LOFIC based on face-to-face connection, and the middle layer chip is bonded to a lower layer chip based on face-to-bottom connection)11. Eleventh Embodiment (An example in which an upper chip equipped with a photodiode is bonded to a middle chip equipped with a LOFIC based on face-to-bottom connection, and the middle chip is bonded to a lower chip based on face-to-face connection) 12. Twelfth Embodiment (An example in which pixel arrays are stacked) 13. Application Examples to Mobile Devices

[0035] <1. First Embodiment> Figure 1 is a block diagram showing an example of the configuration of an imaging device according to the first embodiment.

[0036] The figure shows a block diagram illustrating an example of the configuration of an imaging device according to the first embodiment.

[0037] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging device 100 also includes a drive control unit 109. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, operation unit 107, and drive control unit 109 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into a vehicle or drone.

[0038] The optical system 101 directs light from the subject into the solid-state imaging device 102 and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0039] The solid-state imaging device 102 converts an optical image formed on a light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs the digitized signal. In this process, the solid-state imaging device 102 can output pixel signals by switching the conversion efficiency of pixels. For example, the solid-state imaging device 102 may switch the pixel conversion efficiency between two levels, three levels, or four or more levels. In addition, the solid-state imaging device 102 may include, for each pixel, a plurality of floating diffusions to which electric charges are transferred from the pixel. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a backside illumination type image sensor or a frontside illumination type image sensor.

[0040] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on a command from the operation unit 107. In this process, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, and the like of the solid-state imaging device 102.

[0041] The image processing unit 104 performs image processing based on an output from the solid-state imaging device 102. The image processing is, for example, gamma correction, white balance processing, sharpness processing, or gradation conversion processing. The image processing unit 104 may include a processor that executes processing based on software. The image processing unit 104 includes an HDR processing unit 104A.

[0042] The HDR processing unit 104A performs HDR processing based on pixel signals read from the solid-state imaging device 102. For example, in a dark environment, the HDR processing unit 104A can generate an HDR image based on combining an HCG output and an MCG output generated by the solid-state imaging device 102. In addition, in a bright environment, the HDR processing unit 104A can generate an HDR image based on combining an MCG output and an LCG output generated by the solid-state imaging device 102.

[0043] The storage unit 105 stores captured images captured by the solid-state imaging device 102, and also stores imaging parameters and the like of the solid-state imaging device 102. Further, the storage unit 105 can store a program for operating the imaging apparatus 100 based on software. The storage unit 105 may include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.

[0044] The display unit 106 displays the captured image and displays various types of information supporting imaging operations. The display unit 106 may be a liquid crystal display, an organic EL (Electro Luminescence) display, or a micro LED display.

[0045] The operation unit 107 provides a user interface for operating the imaging apparatus 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging apparatus 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0046] The drive control unit 109 controls driving of the optical system 101 based on pixel signals read from the solid-state imaging device 102 and operation information operated via the operation unit 107. For example, the drive control unit 109 can implement manual focus and control zoom magnification based on operation information operated via the operation unit 107.

[0047] Note that depending on the configuration of the imaging apparatus 100, some of the above-described functions may be omitted, or conversely, functions not disclosed herein may be additionally provided.

[0048] FIG. 2 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment.

[0049] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116.

[0050] The pixel array section 111 comprises a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel PX comprises a plurality of floating diffusions. Each pixel PX may comprise a plurality of photodiodes with different sensitivities, or a plurality of LOFICs. A pixel PX can constitute a source follower with the column readout circuit 113 when reading a signal. Each pixel PX is connected to a horizontal control line 131 in the row direction and to vertical signal lines 132 and vertical control lines 133 in the column direction. The horizontal control line 131 drives each pixel PX horizontally when reading a signal from each pixel PX. At this time, the horizontal control line 131 transmits a switching signal to each pixel PX to switch the conversion efficiency of each pixel contained in the pixel PX. The vertical signal line 132 transmits a potential based on the current flowing when reading a signal from a pixel PX vertically to the column signal processing unit 114. The vertical control line 133 transmits a switching signal perpendicularly to each pixel PX to switch the conversion efficiency of each pixel included in the pixel PX. The switching signal can, for example, switch the conversion efficiency of the pixel PX between HCG and MCG, or between MCG and LCG. The switching signal can also selectively switch the readout from multiple photodiodes with different sensitivities, or selectively switch the readout from multiple LOFICs.

[0051] Each pixel in a pixel PX may form a Bayer array or a quad-Bayer array. The light received by each pixel in each pixel PX may be visible light, near-infrared (NIR), short-wavelength infrared (SWIR), ultraviolet light, or X-rays, etc.

[0052] The vertical scanning circuit 112 scans each pixel in the pixel PX to be read vertically. The vertical scanning circuit 112 may be configured using vertical registers. The vertical scanning circuit 112 may include an address decoder, or it may include a driver that drives the horizontal control line 131 selected via the address decoder row by row.

[0053] The column readout circuit 113 can configure a source follower with each pixel PX when reading a signal from the pixel PX. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel PX.

[0054] The column signal processing unit 114 processes signals transmitted vertically from the pixel PX. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on signals transmitted vertically from the pixel PX. Furthermore, the column signal processing unit 114 can perform analog-to-digital (AD) conversion processing based on signals transmitted vertically from each pixel PX and output an imaging signal Gout.

[0055] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PX and the reference signal.

[0056] The column ADC unit 114A includes a determination unit 114B. The determination unit 114B determines the illuminance based on the determination result of the signal level corresponding to the charge transferred to the floating diffusion when the gate potential of the transfer transistor that transfers the charge accumulated in the photoelectric conversion unit provided in the pixel PX to the floating diffusion is set to an intermediate potential. Based on the illuminance determination result by the determination unit 114B, the column ADC unit 114A can switch the conversion efficiency of the pixel PX, selectively switch the readout from multiple photodiodes with different sensitivities, or selectively switch the readout from multiple LOFICs. The intermediate potential is the potential at which the charge accumulated in the photoelectric conversion unit is not transferred to the floating diffusion when it is below a certain value. Switching the conversion efficiency of the pixel PX based on the determination result of the pixel signal level can be performed via the horizontal control line 131 and the vertical control line 133.

[0057] The horizontal scanning circuit 115 scans each pixel included in the pixel PX to be read out in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0058] The control circuit 116 controls the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column reading circuit 113, and the processing timing of the column signal processing unit 114. In this case, the control circuit 116 can coordinate the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

[0059] Figure 3 shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the first embodiment.

[0060] In the figure, the pixel PX comprises photodiodes PD1 and PD2, a transfer transistor TG, a reset transistor 121, an amplifier transistor 122, a selection transistor 123, switching transistors 124 to 127, a capacitive reset transistor 128, an overflow capacitor CF, and floating diffusion transistors FD1 to FD3. The transfer transistor TG, the reset transistor 121, the amplifier transistor 122, the selection transistor 123, the switching transistors 124 to 127, and the capacitive reset transistor 128 may be MOS (Metal Oxide Semiconductor) transistors.

[0061] Each photodiode PD1 and PD2 performs photoelectric conversion and stores the converted charge. The sensitivity of photodiode PD1 can be made higher than the sensitivity of photodiode PD1. In this case, the planar size of photodiode PD1 may be larger than the planar size of photodiode PD12. The transfer transistor TG transfers the charge stored in photodiode PD1 to the floating diffusion FD1. The reset transistor 121 resets FD3 from the floating diffusion FD1. The amplifier transistor 122 outputs a signal that follows the potential corresponding to the capacitance of FD3 from the floating diffusion FD1. The selection transistor 123 selects the output of the amplifier transistor 122. The capacitance reset transistor 128 resets the overflow capacitance CF. The overflow capacitance CF can constitute LOFIC.

[0062] Each switching transistor 124 to 127 switches the conversion efficiency of the amplifier transistor 122. At this time, each switching transistor 124 to 127 can switch the capacitance added to the gate of the amplifier transistor 122. For example, each switching transistor 124 and 125 adds the capacitance of floating diffusion FD2 to floating diffusion FD1. Switching transistors 126 and 127 add the capacitance of floating diffusion FD3 to floating diffusion FD2. In addition, each switching transistor 124 to 127 can selectively switch the readout from each photodiode PD1 and PD2, or selectively switch the readout from the overflow capacitance CF.

[0063] The transfer transistor TG is connected between the cathode of the photodiode PD1 and the floating diffusion FD1. The amplifier transistor 122 and the selection transistor 123 are connected in series. The drain of the amplifier transistor 122 is connected to the power supply potential VDD. The gate of the amplifier transistor 122 is connected to the floating diffusion FD1. The source of the selection transistor 123 is connected to the vertical signal line 132.

[0064] The reset transistor 121 is connected between the floating diffusion FD2 and the power supply potential VDD. The switching transistors 124 and 125 are connected in parallel to each other between the floating diffusion FD1 and FD2. The switching transistors 126 and 127 are connected in series to each other. The series circuit of switching transistors 126 and 127 is connected between the floating diffusion FD2 and FD3. The cathode of the photodiode PD12 is connected to the floating diffusion FD3. The overflow capacitance CF is connected to the control voltage FVD. The capacitance reset transistor 128 is connected between one end of the overflow capacitance CF and the power supply potential VDD.

[0065] The transfer signal TGL is applied to the gate of the transfer transistor TG. The reset signal RST is applied to the gate of the reset transistor 121. The selection signal SEL is applied to the gate of the selection transistor 123. The capacitive reset signal MRT is applied to the gate of the capacitive reset transistor 128. The switching signal FDGV is applied to the gate of the switching transistor 124. The switching signal FDGH is applied to the gate of the switching transistor 125. The switching signal FCGV is applied to the gate of the switching transistor 126. The switching signal FCGH is applied to the gate of the switching transistor 127.

[0066] The gates of each switching transistor 125 and 127 are connected to the horizontal control line 131. In this case, the switching signals FDGH and FCGH can be made common based on the switching signal FGH transmitted via the horizontal control line 131. The gates of switching transistors 124 and 126 are connected to the vertical control line 133. In this case, the switching signals FDGV and FCGV can be made common based on the switching signal FGV transmitted via the vertical control line 133. The transfer signal TGL, reset signal RST, selection signal SEL, and capacitance reset signal MRT can be transmitted to the pixel PX via the horizontal control line 131.

[0067] Figure 4 is a block diagram showing an example configuration of the AD conversion unit according to the first embodiment. Note that the figure shows an example configuration of the AD conversion unit for one column.

[0068] In the figure, the column ADC section 114A includes a comparator CM, a latch circuit 151, a multiplexer 152, a counter 153, and a switching control unit 154 for each column. Each comparator CM can be configured as a two-input comparator. In this case, the non-inverting input of the comparator CM is connected to the vertical signal line 132 via the input capacitor C2. The inverting input of the comparator CM is to which the reference signal REF is applied via the input capacitor C1. The vertical signal line 132 and the vertical control line 133 are provided for each column.

[0069] The comparator CM compares the pixel signal transmitted via the vertical signal line 132 with the reference signal REF when reading out the pixel signal. The comparator CM also compares the signal level corresponding to the charge transferred to the floating diffusion FD1 when the gate potential of the transfer transistor TG is set to an intermediate potential during illuminance determination with the threshold SH. The comparator CM also receives an auto-zero signal AZ. The auto-zero signal AZ activates the auto-zero operation of the comparator CM during the auto-zero period. During auto-zero operation, charges that balance the non-inverting and inverting inputs of the comparator CM can be accumulated in the respective input capacitors C1 and C2.

[0070] The latch circuit 151 latches the output of the comparator CM and inputs it to the multiplexer 152 and the switching control unit 154. The latch circuit 151 can latch the illuminance determination result. The multiplexer 152 inputs the output of the comparator CM and the output of the latch circuit 151 as a single signal to the counter 153.

[0071] The switching control unit 154 switches the switching signals FGV and FGH based on the illuminance determination result latched by the latch circuit 151. The switching control unit 154 may also switch the switching signal FGH via the control circuit 116 and the horizontal scanning circuit 115. For example, when the illuminance is low, the switching control unit 154 switches the conversion efficiency in reading the signal from the photodiode PD1 to high conversion efficiency or low conversion efficiency. On the other hand, when the illuminance is high, the switching control unit 154 switches the conversion efficiency in reading the signal from the photodiode PD1 to low conversion efficiency, or switches to reading the signal from the photodiode PD12.

[0072] The counter 153 performs a counting operation based on the output timing of the comparison result of the comparator CM. Then, based on the count value generated by the counting operation, the counter 153 digitizes the pixel signal transmitted via the vertical signal line 132 and outputs the digitized digital signal ADO.

[0073] Figure 5 shows an example of a comparator circuit configuration according to the first embodiment.

[0074] In the figure, the comparator CM balances the comparator inputs DV1 and DV2 based on auto-zero operation, and then outputs a voltage VC corresponding to the difference between the comparator inputs DV1 and DV2. The comparator CM comprises PMOS transistors 231 and 232, NMOS transistors 233, 234 and 242, a capacitor 238, and switches 236 and 237.

[0075] PMOS transistor 231 and NMOS transistor 233 are connected in series with each other. PMOS transistor 232 and NMOS transistor 234 are also connected in series with each other. The sources of each PMOS transistor 231 and 232 are connected to the power supply potential VDD, and the gates of each PMOS transistor 231 and 232 are connected to the drain of PMOS transistor 231. In this configuration, PMOS transistors 231 and 232 can form a current mirror.

[0076] A reference signal REF is input to the gate of NMOS transistor 233 via input capacitor C1. Vertical signal lines 132 are connected to the gate of NMOS transistor 234 column by column via input capacitor C2.

[0077] A switch 236 is connected between the gate and drain of NMOS transistor 233, and a switch 237 is connected between the gate and drain of NMOS transistor 234. The sources of each NMOS transistor 233 and 234 are connected to ground potential via NMOS transistor 242.

[0078] Each switch 236 and 237 is opened and closed based on the auto-zero signal AZ. During the auto-zero period, each switch 236 and 237 is turned on based on the auto-zero signal AZ. At this time, current flows through each PMOS transistor 231 and 232 based on the current mirror operation of the PMOS transistors 231 and 232. Charge is then accumulated in each input capacitor C1 and C2 so that the non-inverting and inverting inputs of the comparator CM are balanced.

[0079] Capacitor 238 is connected in parallel with PMOS transistor 232. Capacitor 238 can limit the bandwidth. A bias voltage VBN is applied to the gate of NMOS transistor 242. NMOS transistor 242 can operate as a constant current source based on the bias voltage VBN.

[0080] Figure 6 shows the relationship between illuminance and mode of a solid-state imaging device according to the first embodiment.

[0081] In figure a, when the illumination is low, the switching signal FGV is set to the L level. At this time, the conversion efficiency is switched between high conversion efficiency and low conversion efficiency when reading the signal from the photodiode PD1, according to the level of the switching signal FGH.

[0082] In figure b, when the illumination is high, the switching signal FGV is set to the H level. At this time, depending on the level of the switching signal FGH, the conversion efficiency is switched to a low conversion efficiency when reading the signal from photodiode PD1, or the signal is switched to be read from photodiode PD12.

[0083] Figure 7 is a timing chart showing the waveforms of each part of the signal readout process according to the first embodiment. Note that this figure shows an example of the waveform for a 1H period (1 horizontal synchronization period).

[0084] In the figure, this signal readout process includes a determination processing period T11, a selective conversion efficiency P-phase readout period T12, a selective conversion efficiency D-phase readout period T13, a selective sensitivity D-phase readout period T14, a selective sensitivity P-phase readout period T15, a short-cycle P-phase readout period T16, and a short-cycle D-phase readout period T17, all within a 1H period. The determination processing period T11 includes an illuminance determination period HK. During the selective conversion efficiency P-phase readout period T12, low conversion efficiency or high conversion efficiency is selected for reading the P-phase level from photodiode PD1 according to the illuminance determination result. During the selective conversion efficiency D-phase readout period T13, low conversion efficiency or high conversion efficiency is selected for reading the D-phase level from photodiode PD1 according to the illuminance determination result. During the selective sensitivity D-phase readout period T14, low conversion efficiency is selected for reading the D-phase level from photodiode PD1 or reading the D-phase level from photodiode PD12 according to the illuminance determination result. During the selective sensitivity P-phase readout period T15, depending on the illuminance determination result, either low conversion efficiency or reading the P-phase level from photodiode PD12 is selected for reading the P-phase level from photodiode PD1. During the short storage P-phase readout period T16 and the short storage D-phase readout period T17, the storage period is shortened. During the illuminance determination period HK, the reference signal REF is set to the threshold SH. During the selective conversion efficiency P-phase readout period T12, the selective conversion efficiency D-phase readout period T13, the selective sensitivity D-phase readout period T14, the selective sensitivity P-phase readout period T15, the short storage P-phase readout period T16, and the short storage P-phase readout period T17, the reference signal REF is set to a ramp wave.

[0085] During the determination processing period T11, after the reset signal RST falls, the transfer signal TGL rises to an intermediate potential. At this time, if the transfer transistor TG is half-on and a charge exceeding a certain value is accumulated in the photodiode PD1, that charge is transferred to the floating diffusion FD1. If the charge accumulated in the photodiode PD1 is below a certain value, that charge is not transferred to the floating diffusion FD1.

[0086] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, the potential of the vertical signal line 132 is set based on the source follower operation when a level corresponding to the presence or absence of charge in the floating diffusion FD1 is applied to the gate of the amplifier transistor 122. During the level determination period HK, the comparator CM compares the level corresponding to the presence or absence of charge in the floating diffusion FD1 with the threshold level SH, and the comparison result is input to the switching control unit 154 via the latch circuit 151.

[0087] Then, when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is above the threshold level SH (high illumination), the switching control unit 154 raises the switching signal FGV and applies it to the pixel PX via the vertical control line 133. At this time, the switching transistors 124 and 126 are turned on, the capacitance of the floating diffusion FD2 is added to the floating diffusion FD1, and the switching transistor 127 is connected to the floating diffusion FD3.

[0088] On the other hand, when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is less than the threshold level SH (low illumination), the switching control unit 154 maintains the L level of the switching signal FGV and applies it to the pixel PX via the vertical control line 133. At this time, the switching transistors 124 and 126 are turned off, the floating diffusion FD1 is disconnected from the floating diffusion FD2, and the switching transistor 127 is disconnected from the floating diffusion FD3.

[0089] Next, during the selective conversion efficiency P-phase readout period T12, the potential of the floating diffusion FD1 is set based on the charge transferred from the photodiode PD1. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0090] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the high conversion efficiency P-phase level read from the pixel PX is AD converted column by column.

[0091] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0092] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency P-phase level read from the pixel PX is AD converted column by column.

[0093] Next, during the selective conversion efficiency D-phase readout period T13, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.

[0094] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0095] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the high-conversion-efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the high-conversion-efficiency D-phase level read from the pixel PX is AD converted column by column. At this time, CDS processing can be performed based on the high-conversion-efficiency P-phase level and the high-conversion-efficiency D-phase level.

[0096] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0097] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency D-phase level read from the pixel PX is AD converted column by column. At this time, CDS processing can be performed based on the low conversion efficiency P-phase level and the low conversion efficiency D-phase level.

[0098] Next, during the selective sensitivity D-phase readout period T14, the switching signal FGH rises and is applied to the pixel PX via the horizontal control line 131. At this time, the switching transistors 125 and 127 turn on, adding the capacitance of floating diffusion FD2 to floating diffusion FD1, and the switching transistor 126 is connected to floating diffusion FD2. Then, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in photodiode PD1 is transferred to floating diffusion FD1.

[0099] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0100] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency D-phase level read from the pixel PX is AD converted column by column.

[0101] On the other hand, when the illumination is high, the charge accumulated in the photodiode PD12 is transferred to the floating diffusion FD1. Then, based on the source follower operation when the D-phase level of FD3 from the floating diffusion FD1, which is based on the charge transferred from the photodiode PD12, is applied to the gate of the amplifier transistor 122, the potential of the vertical signal line 132 is set.

[0102] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the D-phase level read from the photodiode PD 12 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the D-phase level read from the photodiode PD 12 is AD converted column by column.

[0103] Next, during the selective sensitivity P-phase readout period T15, the reset signal RST rises. At this time, the reset transistor 121 turns on, and floating diffusion FD1 to FD3 are reset. Then, the reset signal RST falls, and the reset transistor 121 turns off. When the illumination is low, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0104] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency P-phase level read from the pixel PX is AD converted column by column.

[0105] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of the floating diffusion FD1 to FD3, which are based on the charge transferred from the photodiode PD12, are applied to the gate of the amplifier transistor 122.

[0106] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the P-phase level read from the photodiode PD 12 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the P-phase level read from the photodiode PD 12 is AD converted column by column. At this time, DDS (Double Data Sampling) processing can be performed based on the P-phase level and D-phase level read from the photodiode PD 12.

[0107] Next, during the short-cycle P-phase readout period T16, the switching signal FGH falls and is applied to the pixel PX via the horizontal control line 131. At this time, the switching transistors 125 and 127 are turned off, the floating diffusion FD2 is disconnected from the floating diffusion FD1, and the switching transistor 126 is disconnected from the floating diffusion FD2.

[0108] Next, the reset signal RST rises. At this time, the reset transistor 121 turns on, and the floating diffusions FD1 and FD2 are reset. Then, the reset signal RST falls, and the reset transistor 121 turns off. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the short-pass P-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0109] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the short-cycle P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the short-cycle P-phase levels read from the pixel PX are AD converted column by column.

[0110] Next, during the short-duration D-phase readout period T17, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.

[0111] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the short-pass D-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0112] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the short-cycle D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the short-cycle D-phase levels read from the pixel PX are AD converted column by column.

[0113] Figures 8 and 9 are plan views showing an example of the layout of a solid-state imaging device according to the first embodiment, and Figure 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the first embodiment.

[0114] In the figure, a pixel PX comprises semiconductor chips CP1 to CP3. A semiconductor chip CP2 is stacked on semiconductor chip CP3, and a semiconductor chip CP1 is stacked on semiconductor chip CP2. Each of the semiconductor chips CP1 to CP3 comprises a semiconductor substrate SUB1 to SUB3. P-type semiconductor substrates can be used for semiconductor substrates SUB1 to SUB3. A pixel isolation layer GIS is provided on semiconductor substrate SUB1 to isolate the pixel PX. The pixel isolation layer GIS may be FTI (Full-thickness Trench Isolation) or RDTI (Rear Deep Trench Isolation).

[0115] An active region AK1 is provided on the semiconductor substrate SUB1, and the active region AK1 is isolated by an element isolation region ISA1. The element isolation region ISA1 may be STI (Shallow Trench Isolation). Photodiodes PD1 and PD2, a channel region, and an impurity diffusion layer are formed in the active region AK1. The impurity diffusion layer of the active region AK1 may include a floating diffusion FD1, a transfer transistor TG, an amplifier transistor 124, and source / drain layers for switching transistors 124 to 126.

[0116] On the active region AK1, gate electrodes GT, G2, G4 to G6 are formed via a gate insulating film. In the floating diffusion FD1, N ＋ A concentrated N-type impurity diffusion layer is formed. An N-type impurity diffusion layer DF1 is formed adjacent to the channel region below each gate electrode GT, G2, G4 to G6.

[0117] Each gate electrode GT, G2, and G4 through G6 are embedded in the insulating layer ZL1. Wiring H1, via BA1, and junction electrode DE1 are formed within the insulating layer ZL1. The junction electrode DE1 can be connected to the N-type impurity concentrated diffusion layer DF1 via BA1. The junction electrode DE1 is exposed from the surface of the insulating layer ZL1.

[0118] An active region AK2 is provided on the semiconductor substrate SUB2, and the active region AK2 is isolated by an element isolation region ISA2. The element isolation region ISA2 may also be an STI. A channel region and an impurity diffusion layer are formed in the active region AK2. The impurity diffusion layer of the active region AK2 may include the source / drain layers of the reset transistor 123, the selection transistor 125, the switching transistor 127, and the capacitive reset transistor 132.

[0119] On the active region AK2, gate electrodes G1, G3, G7, and G8 are formed via a gate insulating film. An N-type impurity-concentrated diffusion layer DF2 is formed adjacent to the channel region beneath each gate electrode G1, G3, G7, and G8. An overflow capacitance CF is formed on the device isolation region ISA2. The overflow capacitance CF may also be a folded structure of the counter electrode.

[0120] Each gate electrode G1, G3, G7, and G8 is embedded in the insulating layer ZL2. Wiring H2, via BA2, and junction electrodes DE2A and DE2B are formed within the insulating layer ZL2. A through electrode KD is also formed within the insulating layer ZL2, penetrating the semiconductor substrate SUB2. Junction electrode DE2A can be connected to wiring H2 and overflow capacitance CF via the through electrode KD. Junction electrode DE2B can be connected to wiring H2 via via BA2. Junction electrode DE2A is exposed from the back surface of the insulating layer ZL2. Junction electrode DE2B is exposed from the front surface of the insulating layer ZL2.

[0121] A gate electrode GR is formed on the semiconductor substrate SUB3 via a gate insulating film. An N-type impurity concentration diffusion layer DF3 is formed adjacent to the channel region beneath the gate electrode GR. The gate electrode GR may be a logic gate. The gate electrode GR is embedded in an insulating layer ZL3. A via BA3 and a junction electrode DE3 are formed within the insulating layer ZL3. The via BA3 is connected to the gate electrode GR. The junction electrode DE3 is exposed from the surface of the insulating layer ZL3.

[0122] Bonding electrodes DE1 and DE2A are joined to each other. Bonding electrodes DE2B and DE3 are joined to each other. The joining of bonding electrodes DE1 and DE2A, and the joining of bonding electrodes DE2B and DE3 may be Cu-Cu bonding.

[0123] The gate electrode GT is used in the transfer transistor TG. The gate electrode G1 is used in the reset transistor 121. The gate electrode G2 is used in the amplifier transistor 122. The gate electrode G3 is used in the selection transistor 123. Each of the gate electrodes G4 to G7 is used in the switching transistors 124 to 127, respectively. The gate electrode G8 is used in the capacitive reset transistor 128.

[0124] Here, by arranging the floating diffusion FD1, transfer transistor TG, and amplifier transistor 122 on the semiconductor chip CP1 on which the photodiodes PD1 and PD2 are formed, it is possible to suppress the increase in parasitic capacitance added to the floating diffusion FD1 when the pixel PX is set to a high conversion efficiency setting. Therefore, it is possible to arrange the pixel PX by dividing it into an upper layer chip and a lower layer chip while suppressing the decrease in conversion efficiency when the pixel PX is set to a high conversion efficiency setting.

[0125] The materials for semiconductor substrates SUB1 to SUB3 may be Si, InGaAs, InP, InSb, HgCdTe, etc. For gate electrodes GT, GR, G1 to G8, for example, polycrystalline silicon can be used. The materials for pixel isolation layer GIS and element isolation regions ISA1 and ISA2 are SiO ２ Insulators such as the above can be used. To suppress color mixing between pixels PX, the material of the pixel separation layer GIS may be blackened or may have light-shielding properties.

[0126] As described above, in the first embodiment, switching transistors 124 to 127 are provided in the pixel PX to selectively switch between reading from a high-sensitivity photodiode and a low-sensitivity photodiode based on the illuminance determination result. This makes it possible to switch the conversion efficiency in three stages based on two D-phase level readouts while enabling CDS or DDS in the pixel PX equipped with a high-sensitivity photodiode and a low-sensitivity photodiode. As a result, it becomes possible to expand HDR while suppressing a decrease in frame rate.

[0127] Furthermore, by dividing the pixel PX into an upper layer chip and a lower layer chip and arranging them accordingly, it is possible to suppress an increase in the planar size of the pixel PX while arranging the switching transistors 124 to 127 in the pixel PX.

[0128] <2. Second Embodiment> In the first embodiment described above, switching transistors 124 to 127 are provided to selectively switch between reading from a high-sensitivity photodiode and a low-sensitivity photodiode based on the illuminance determination result. In this second embodiment, an overflow capacitance is formed in the pixel using a semiconductor substrate and vias embedded in the semiconductor substrate as counter electrodes.

[0129] Figure 11 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the second embodiment.

[0130] In the figure, this pixel PX2 is equipped with a conductive chip CP2' instead of the semiconductor chip CP2 of the first embodiment described above. The other configurations of the pixel PX2 of the second embodiment are the same as those of the pixel PX of the first embodiment described above.

[0131] The semiconductor chip CP2' is equipped with an overflow capacitance CF' instead of the overflow capacitance CF of the first embodiment described above. The other configurations of the semiconductor chip CP2' of the second embodiment are the same as those of the semiconductor chip CP2 of the first embodiment described above.

[0132] The overflow capacitance CF' is embedded in the semiconductor substrate SUB2. At this time, vias BAC embedded in the semiconductor substrate SUB2 are provided in the overflow capacitance CF'. A dielectric layer DIE is formed between the via BAC and the semiconductor substrate SUB2. The material of the dielectric layer DIE is SiO ２ Insulating films such as SiN are also acceptable, or barium titanate (BaTiO ３ ) and lead zirconate titanate Pb(Zr,Ti)O ３ Other ferroelectric materials may also be used. The semiconductor substrate SUB2 and via BAC can be used as counter electrodes for the overflow capacitance CF2.

[0133] Thus, in the second embodiment described above, an overflow capacitance CF' is formed in the pixel PX2 using a semiconductor substrate SUB2 and a via BAC embedded in the semiconductor substrate SUB2 as a counter electrode. This makes it possible to form the overflow capacitance CF' in the pixel PX2 by reusing the via formation process, thereby suppressing an increase in the number of steps in the manufacturing process and enabling HDR based on the overflow charge that overflows from the photodiode PD1 to the overflow capacitance CF'.

[0134] <3. Third Embodiment> In the first embodiment described above, the pixel PX, which is provided with switching transistors 124 to 127 that selectively switch between reading from high-sensitivity photodiodes and low-sensitivity photodiodes based on the illuminance determination result, is divided and arranged on an upper chip and a lower chip. In this third embodiment, the pixels, which are provided with switching transistors 124 to 127 that selectively switch between reading from high-sensitivity photodiodes and low-sensitivity photodiodes based on the illuminance determination result, are arranged on a single chip.

[0135] Figure 12 is a plan view showing an example of the layout of a solid-state imaging device according to the third embodiment, and Figure 13 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the third embodiment.

[0136] In the figure, the pixel PX3 comprises a semiconductor chip CP. The semiconductor chip CP comprises a semiconductor substrate SUB. The semiconductor substrate SUB can be a P-type semiconductor substrate. The semiconductor substrate SUB is provided with a pixel isolation layer GIS4 that separates the pixels PX3.

[0137] An active region AK is provided in the semiconductor substrate SUB, and the active region AK is isolated by an element isolation region ISA. Photodiodes PD1 and PD2, a channel region, and an impurity diffusion layer are formed in the active region AK. The impurity diffusion layer of the active region AK may include the source / drain layers of floating diffusion transistors FD1 to FD3, transfer transistor TG, amplifier transistor 124 and switching transistors 124 to 127, reset transistor 123, selection transistor 125, and capacitive reset transistor 132.

[0138] On the active region AK, gate electrodes GT, G1 to G8 are formed via a gate insulating film. In the floating diffusion FD1, N ＋ A concentrated N-type impurity diffusion layer is formed. An N-type impurity diffusion layer DF4 is formed adjacent to the channel region below each gate electrode GT, G1 to G8. Each gate electrode GT, G1 to G8 is embedded in an insulating layer ZL4. Wiring H4 and via BA4 are formed within the insulating layer ZL4.

[0139] Thus, in the third embodiment described above, a pixel PX3 equipped with switching transistors 124 to 127 that selectively switch between reading from a high-sensitivity photodiode and a low-sensitivity photodiode based on the illuminance determination result is arranged on a single chip CP. This makes it possible to arrange the switching transistors 124 to 127 on the pixel PX3 while suppressing an increase in the number of manufacturing steps for the pixel PX3.

[0140] <4. Fourth Embodiment> In the first embodiment described above, switching transistors 124 to 127 are provided in the pixel PX to selectively switch between reading from a high-sensitivity photodiode and a low-sensitivity photodiode based on the illuminance determination result. In this fourth embodiment, switching transistors are provided in the pixel to selectively switch between reading from a plurality of LOFICs based on the illuminance determination result.

[0141] Figure 14 shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the fourth embodiment.

[0142] In the figure, this pixel PX4 is equipped with switching transistors 421, 422, 424, 425 and overflow capacitors CF1, CF2, instead of the switching transistors 126, 127 and overflow capacitors CF of the first embodiment described above. In addition, the capacitance reset transistor 128 is removed from this pixel PX4 compared to the pixel PX of the first embodiment described above. The other configurations of the pixel PX4 of the fourth embodiment are the same as those of the pixel PX of the first embodiment described above.

[0143] Each switching transistor 124, 125, 421, 422, 424, and 425 switches the conversion efficiency of the amplifier transistor 122. At this time, each switching transistor 124, 125, 421, 422, 424, and 425 can switch the capacitance added to the gate of the amplifier transistor 122. For example, each switching transistor 421, 422, 424, and 425 adds the capacitance of floating diffusion FD3 to floating diffusion FD2. In addition, each switching transistor 124, 125, 421, 422, 424, and 425 can selectively switch the reading from each overflow capacitance CF1 and CF2. Each overflow capacitance CF1 and CF2 can constitute a LOFIC. Each overflow capacitance CF1 and CF2 may be composed of MIM (Metal Insulator Metal), wiring capacitance, or junction capacitance.

[0144] Switching transistors 424 and 425 are connected in parallel to each other. The parallel circuit of switching transistors 424 and 425 is connected in series to switching transistor 421. The parallel circuit of switching transistors 424 and 425 and the series circuit of switching transistor 421 are connected between floating diffusions FD2 and FD3. Switching transistors 421 and 422 are connected in series to each other. A floating diffusion FD3 is provided at the connection point of switching transistors 421 and 422. Overflow capacitor CF1 is connected to floating diffusion FD3. Overflow capacitor CF2 is connected to floating diffusion FD3 via switching transistor 422. One end of each overflow capacitor CF1 and CF2 is connected to the control voltage FVD.

[0145] A switching signal FCGV is applied to the gates of each switching transistor 124 and 424. A switching signal FDG is applied to the gate of switching transistor 125. A switching signal FCG is applied to the gate of switching transistor 421. A switching signal FCG2 is applied to the gates of each switching transistor 422 and 425. The gates of each switching transistor 422 and 425 are connected to the horizontal control line 131. The gates of switching transistors 124 and 424 are connected to the vertical control line 133.

[0146] Figure 15 is a timing chart showing the waveforms of each part of the signal readout process according to the fourth embodiment.

[0147] In the figure, this signal readout process includes a determination processing period T21, a selective conversion efficiency P-phase readout period T22, a selective conversion efficiency D-phase readout period T23, a selective capacitance D-phase readout period T24, a second capacitance D-phase readout period T25, a second capacitance P-phase readout period T26, and a selective capacitance P-phase readout period T27, all within a 1H period. The determination processing period T21 includes an illuminance determination period HK. During the selective conversion efficiency P-phase readout period T22, low conversion efficiency or high conversion efficiency is selected in the P-phase level readout from the photodiode PD1 according to the illuminance determination result. During the selective conversion efficiency D-phase readout period T23, low conversion efficiency or high conversion efficiency is selected in the D-phase level readout from the photodiode PD1 according to the illuminance determination result. During the selective capacitance D-phase readout period T24, depending on the illuminance determination result, either low conversion efficiency or reading the D-phase level from overflow capacitance CF1 is selected for reading the D-phase level from photodiode PD1. During the second capacitance D-phase readout period T25, reading the D-phase level from overflow capacitance CF2 is selected. During the second capacitance P-phase readout period T26, reading the P-phase level from overflow capacitance CF2 is selected. During the selective capacitance P-phase readout period T27, depending on the illuminance determination result, either low conversion efficiency or reading the P-phase level from overflow capacitance CF1 is selected for reading the P-phase level from photodiode PD1.

[0148] During the judgment processing period T21, after the exposure period EX has elapsed, the transfer signal TGL rises to an intermediate potential. At this time, if the transfer transistor TG is half-on and a charge exceeding a certain value has accumulated in the photodiode PD1, that charge is transferred to the floating diffusion FD1. If the charge accumulated in the photodiode PD1 is below a certain value, that charge is not transferred to the floating diffusion FD1.

[0149] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, the potential of the vertical signal line 132 is set based on the source follower operation when a level corresponding to the presence or absence of charge in the floating diffusion FD1 is applied to the gate of the amplifier transistor 122. During the level determination period HK, the comparator CM compares the level corresponding to the presence or absence of charge in the floating diffusion FD1 with the threshold level SH, and the comparison result is input to the switching control unit 154 via the latch circuit 151.

[0150] Then, when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is above the threshold level SH (high illumination), the switching control unit 154 raises the switching signal FCGV and applies it to the pixel PX4 via the vertical control line 133. At this time, the switching transistors 124 and 424 are turned on, the capacitance of the floating diffusion FD2 is added to the floating diffusion FD1, and the switching transistor 421 is connected to the floating diffusion FD2.

[0151] On the other hand, when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is less than the threshold level SH (low light), the switching control unit 154 maintains the L level of the switching signal FCGV and applies it to the pixel PX4 via the vertical control line 133. At this time, the switching transistors 124 and 424 are turned off, the floating diffusion FD1 is disconnected from the floating diffusion FD2, and the switching transistor 421 is disconnected from the floating diffusion FD2.

[0152] Next, during the selective conversion efficiency P-phase readout period T22, the selection signal SEL rises, and the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0153] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the high conversion efficiency P-phase level read from the pixel PX4 is AD converted column by column.

[0154] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase levels of the floating diffusion FD1 and FD2 are applied to the gate of the amplifier transistor 122.

[0155] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency P-phase level read from the pixel PX4 is AD converted column by column. Then, the selection signal SEL falls, and the selection transistor 123 turns off.

[0156] Next, during the selective conversion efficiency D-phase readout period T23, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.

[0157] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, the selection signal SEL rises, and the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. When the light level is low, the potential of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0158] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the high-efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the high-efficiency D-phase level read from the pixel PX4 is AD converted column by column. At this time, CDS processing can be performed based on the high-efficiency P-phase level and the high-efficiency D-phase level.

[0159] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase levels of the floating diffusion FD1 and F2 are applied to the gate of the amplifier transistor 122.

[0160] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency D-phase level read from the pixel PX4 is AD converted column by column. Then, the selection signal SEL falls, and the selection transistor 123 turns off. At this time, CDS processing can be performed based on the low conversion efficiency P-phase level and the low conversion efficiency D-phase level.

[0161] Next, during the selective capacitance D-phase readout period T24, the switching signal FDG rises and is applied to the pixel PX4 via the horizontal control line 131. At this time, the switching transistor 125 turns on, and the capacitance of floating diffusion FD2 is added to floating diffusion FD1. Then, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in photodiode PD1 is transferred to floating diffusion FD1.

[0162] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, the switching signal FCG rises and is applied to the pixel PX4 via the horizontal control line 131. At this time, the switching transistor 421 turns on, and the parallel circuit of switching transistors 424 and 425 is connected to the floating diffusion FD3. Also, when the selection signal SEL rises, the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase level of the floating diffusion FD1 and FD2 is applied to the gate of the amplifier transistor 122.

[0163] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency D-phase level read from the pixel PX4 is AD converted column by column.

[0164] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase level of the floating diffusion FD1 to FD3, which is based on the charge read from the overflow capacitance CF1, is applied to the gate of the amplifier transistor 122.

[0165] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the D-phase level read from the overflow capacitor CF1 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the D-phase level read from the overflow capacitor CF1 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132.

[0166] Next, during the second capacitance D-phase readout period T25, the switching signal FCG2 rises and is applied to the pixel PX4 via the horizontal control line 131. At this time, the switching transistors 422 and 424 are turned on, the capacitance of floating diffusion FD3 is added to floating diffusion FD2, and the overflow capacitance CF2 is connected to floating diffusion FD3 via the switching transistor 422. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase levels of floating diffusion FD1 to FD3, based on the charge read from overflow capacitance CF2, are applied to the gate of amplifier transistor 122.

[0167] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the D-phase level read from the overflow capacitor CF2 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the D-phase level read from the overflow capacitor CF2 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132. Then, the selection signal SEL falls, and the selection transistor 123 turns off.

[0168] Next, during the second capacitance P-phase readout period T26, the reset signal RST rises, the reset transistor 121 turns on, and the floating diffusion FD1 to FD3 and the overflow capacitance CF2 are reset. Then, the reset signal RST falls, and the reset transistor 121 turns off. Then, the selection signal SEL rises, and the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of the floating diffusion FD1 to FD3, based on the charge read from the overflow capacitance CF2, are applied to the gate of the amplifier transistor 122.

[0169] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the P-phase level read from the overflow capacitor CF2 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the P-phase level read from the overflow capacitor CF2 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132.

[0170] Next, during the selective capacitance P-phase readout period T27, the switching signal FCG2 falls. At this time, switching transistors 422 and 424 turn off, and the overflow capacitance CF2 is disconnected from the floating diffusion FD3. Then, the switching signal FCG falls, and switching transistor 421 turns off. At this time, the parallel circuit of switching transistors 424 and 425 is disconnected from the floating diffusion FD3. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase levels of the floating diffusion FD1 and FD2 are applied to the gate of amplifier transistor 122.

[0171] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency P-phase level read from the pixel PX4 is AD converted column by column.

[0172] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of the floating diffusion FD1 to FD3, which are based on the charge read from the overflow capacitance CF1, are applied to the gate of the amplifier transistor 122.

[0173] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the P-phase level read from the overflow capacitor CF1 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the P-phase level read from the overflow capacitor CF1 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132.

[0174] Figure 16 is a plan view showing an example of the layout of a solid-state imaging device according to the fourth embodiment.

[0175] In the figure, pixel PX4 comprises a semiconductor substrate SUB5. The semiconductor substrate SUB5 is provided with a pixel isolation layer GIS5 that isolates the pixel PX4. The semiconductor substrate SUB5 is also provided with an active region AK5, which is isolated by an element isolation region ISA5. A photodiode PD1, a channel region, and an impurity diffusion layer are formed in the active region AK5. Floating diffusion FD1 to FD3, the source layer and drain layer of the transistor of pixel PX4 are formed in the impurity diffusion layer of the active region AK5.

[0176] On the active region AK5, gate electrodes GT, G1 to G5, G11, G12, G14, and G15 are formed via a gate insulating film. The gate electrode GT is positioned near the center of the pixel PX4 to improve the efficiency of data transfer from the photodiode PD1. Each gate electrode G4 and G5 is positioned adjacent to the gate electrode GT. In this case, each gate electrode G4 and G5 can be positioned close to each other. Each gate electrode G1 to G3, G11, G12, G14, and G15 is positioned around the gate electrode GT. In this case, each gate electrode G14 and G15 can be positioned close to each other. Each gate electrode G11, G12, G14, and G15 is used in the switching transistors 421, 422, 424, and 425, respectively.

[0177] Figure 17 is a plan view showing another example of the layout of the solid-state imaging device according to the fourth embodiment.

[0178] In the figure, pixel PX4A includes an active region AK6 and an element isolation region ISA6 instead of the active region AK5 and element isolation region ISA5 in Figure 16. On the active region AK6, gate electrodes GT, G1 to G5, G11, G12, G14, and G15 are formed via a gate insulating film. At this time, gate electrodes G11 and G15 can be placed in close proximity to each other on the active region AK6. This allows the impurity diffusion layer adjacent to the channel region under each gate electrode G11 and G15 to be connected via the active region AK6, thereby reducing the number of wirings.

[0179] Figure 18 is a plan view showing yet another example of the layout of a solid-state imaging device according to the fourth embodiment.

[0180] In the figure, pixel PX4B includes gate electrodes G21, G22, active region AK7, and element isolation region ISA5 instead of gate electrodes G4, G12, G14, G15, active region AK5, and element isolation region ISA5 in Figure 16. On the active region AK7, gate electrodes GT, G1 to G3, G5, G11, G21, and G22 are formed via a gate insulating film. At this time, the active region AK7 on which gate electrode G21 is located is isolated, and the active region AK7 on which gate electrode G22 is located is also isolated. Gate electrode G21 can also serve as gate electrodes G4 and G14 in Figure 16, and gate electrode G22 can also serve as gate electrodes G12 and G15 in Figure 16. At this time, gate electrode GT can be located in the corner of pixel PX4B.

[0181] As described above, in the fourth embodiment, switching transistors 124, 125, 421, 422, 424, and 425 are provided in the pixel PX4 to selectively switch the readout from multiple LOFICs based on the illuminance determination result. This makes it possible to switch the conversion efficiency in four stages based on three D-phase level readouts while enabling CDS or DDS in the pixel PX4 equipped with multiple LOFICs. As a result, it is possible to expand HDR while suppressing a decrease in frame rate, and to reduce power consumption.

[0182] <5. Fifth Embodiment> In the fourth embodiment described above, switching transistors 124, 125, 421, 422, 424, and 425 are provided in the pixel PX4 to selectively switch the reading from a plurality of LOFICs based on the illuminance determination result. In this fifth embodiment, the reading from a plurality of LOFICs is selectively switched based on the illuminance determination result, and a switching transistor is provided in the pixel that can select the LOFIC to be read.

[0183] Figure 19 shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the fifth embodiment.

[0184] In the figure, this pixel PX5 has a switching transistor 521 added to the pixel PX4 of the fourth embodiment described above. The other configurations of the pixel PX5 of the fifth embodiment are the same as those of the pixel PX4 of the fourth embodiment described above.

[0185] The switching transistor 521 is connected between the switching transistor 422 and the floating diffusion FD3. The switching signal FCGV is applied to the gate of the switching transistor 521. At this time, the switching signal FCGV can be shared by the switching transistors 124, 424, and 521. The timing chart for signal readout of pixel PX5 is the same as the timing chart for signal readout of pixel PX4 in the fourth embodiment described above.

[0186] Figure 20 is a plan view showing an example of the layout of a solid-state imaging device according to the fifth embodiment.

[0187] In the same figure, pixel PX5 has an active region AK8 and an element isolation region ISA8 instead of the active region AK5 and element isolation region ISA5 in Figure 16. Also, pixel PX5 has a gate electrode G21 added to PX4 in Figure 16. On the active region AK8, gate electrodes GT, G1 to G5, G11, G12, G14, G15, and G21 are formed via a gate insulating film. At this time, gate electrodes G11 and G21 can be placed in close proximity to each other on the active region AK8.

[0188] Figure 21 is a plan view showing another example of the layout of a solid-state imaging device according to the fifth embodiment.

[0189] In the same figure, pixel PX5A includes a gate electrode G31, an active region AK9, and an element isolation region ISA5 instead of the gate electrodes G4, G14, G21, active region AK5, and element isolation region ISA5 of Figure 20. On the active region AK9, gate electrodes GT, G1 to G3, G5, G11, G12, G15, and G31 are formed via a gate insulating film. In this case, the active region AK7 on which gate electrode G31 is located is separated into three parts. Gate electrode G31 can also be used for gate electrodes G4, G14, and G21 of Figure 16. In this case, gate electrode GT can be located in the corner of pixel PX5A.

[0190] As described above, in the fifth embodiment, based on the illuminance determination result, the reading from multiple LOFICs is selectively switched, and switching transistors 124, 125, 421, 422, 424, 425, and 521 that can select the LOFIC to be read are provided in the pixel PX5. This makes it possible to switch the conversion efficiency in four stages based on three D-phase level readings while enabling CDS or DDS in the pixel PX5 equipped with multiple LOFICs, thereby enabling HDR expansion while suppressing a decrease in frame rate.

[0191] <6. Sixth Embodiment> In the fourth embodiment described above, switching transistors 124, 125, 421, 422, 424, and 425 are provided in the pixel PX4 to selectively switch the reading from multiple LOFICs based on the illuminance determination result. In this sixth embodiment, switching transistors 124, 125, 421, 422, 424, and 425 are provided in the pixel to selectively switch the reading from multiple LOFICs, and an overflow control transistor is also provided.

[0192] Figure 22 is a diagram showing an example of a pixel circuit configuration provided in a solid-state imaging device according to the sixth embodiment.

[0193] In the figure, this pixel PX6 has an overflow control transistor 601 added to the pixel PX4 of the fourth embodiment described above. The other configurations of the pixel PX6 of the sixth embodiment are the same as those of the pixel PX4 of the fourth embodiment described above.

[0194] The overflow control transistor 601 sets the path for the charge that overflows from the photodiode PD1 to the overflow capacitor CF1. The overflow control transistor 601 is connected between the cathode of the photodiode PD1 and the floating diffusion capacitor FD3. An overflow control signal OFG is applied to the gate of the overflow control transistor 601. The overflow control signal OFG may be set to a fixed potential.

[0195] Figure 23 is a timing chart showing the waveforms of each part of the signal readout process according to the sixth embodiment.

[0196] In the figure, the signal readout process of the sixth embodiment includes a determination processing period T21' instead of the determination processing period T21 of the fourth embodiment described above. The other signal readout processes of the sixth embodiment are the same as those of the signal readout process of the fourth embodiment described above.

[0197] During the determination processing period T21', the reset signal RST and the switching signal FDG rise before the transfer signal TGL rises to an intermediate potential after the exposure period EX. At this time, the reset transistor 121 and the switching transistor 125 are turned on, and the floating diffusion transistors FD1 and FD2 are reset. By providing the overflow control transistor 601, the charge overflowing from the photodiode PD1 can be stored in the overflow capacitor CF1 without the need for the floating diffusion transistors FD1 and FD2 to be intervened. This prevents the loss of charge overflowing from the photodiode PD1 when the floating diffusion transistors FD1 and FD2 are reset.

[0198] Figure 24 is a plan view showing an example of the layout of a solid-state imaging device according to the sixth embodiment.

[0199] In the same figure, pixel PX6 has an active region AK10 and an element isolation region ISA10 instead of the active region AK5 and element isolation region ISA5 of Figure 16. Furthermore, pixel PX6 has a gate electrode G41 added to pixel PX4 of Figure 16. On the active region AK10, gate electrodes GT, G1 to G5, G11, G12, G14, G15, and G41 are formed via a gate insulating film. In this case, gate electrode G41 can be positioned in close proximity to gate electrodes GT, G12 on the active region AK10.

[0200] As described above, in the sixth embodiment, switching transistors 124, 125, 421, 422, 424, and 425 that selectively switch the readout from multiple LOFICs are provided in the pixel PX6, and an overflow control transistor 601 is also provided. This makes it possible to expand the dynamic range in HDR while suppressing a decrease in frame rate, and to reduce fixed pattern noise caused by dark current.

[0201] <7. Seventh Embodiment> In the fourth embodiment described above, switching transistors 124, 125, 421, 422, 424, and 425 are provided in the pixel PX4 to selectively switch the readout from a plurality of LOFICs based on the illuminance determination result. In this sixth embodiment, switching transistors are provided in the pixel to selectively switch the readout from a LOFIC, a high-sensitivity photodiode, and a low-sensitivity photodiode based on the illuminance determination result.

[0202] Figure 25 shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the seventh embodiment.

[0203] In the figure, this pixel PX7 includes switching transistors 721 to 723 instead of the switching transistors 421, 422, 424, and 425 of the fourth embodiment described above. In addition, this pixel PX7 has a photodiode PD2 added to the pixel PX4 of the fourth embodiment described above. The other configurations of the pixel PX7 of the seventh embodiment are the same as those of the pixel PX4 of the fourth embodiment described above.

[0204] The switching transistors 124, 125, and 721 to 723 switch the conversion efficiency of the amplifier transistor 122. At this time, each of the switching transistors 124, 125, and 721 to 723 can switch the capacitance added to the gate of the amplifier transistor 122. For example, switching transistor 721 adds the capacitance of floating diffusion FD3 to floating diffusion FD2. In addition, each of the switching transistors 721 to 723 can selectively switch between reading from overflow capacitance CF1 and reading from photodiode PD2.

[0205] The switching transistors 722 and 723 are connected in series with each other. The series circuit of switching transistors 722 and 723 is connected between the reset transistor 121 and the floating diffusion FD2. An overflow capacitor CF1 is connected at the connection point between the reset transistor 121 and the switching transistor 723. The switching transistor 721 is connected between the floating diffusion FD2 and FD3. The cathode of the photodiode PD2 is connected to the floating diffusion FD3. Also, the overflow capacitor CF2 is connected to the floating diffusion FD3.

[0206] A switching signal FCG is applied to the gate of switching transistor 721. A switching signal FDG is applied to the gate of switching transistor 125. A switching signal LCG is applied to the gate of switching transistor 722. A switching signal FCGV is applied to the gate of each switching transistor 723. The gates of switching transistors 723 are connected to the vertical control line 133.

[0207] Figure 26 is a timing chart showing the waveforms of each part of the signal readout process according to the seventh embodiment.

[0208] In the figure, this signal readout process includes a determination processing period T31, a selective conversion efficiency P-phase readout period T32, a selective conversion efficiency D-phase readout period T33, a selective capacitance D-phase readout period T34, a selective capacitance P-phase readout period T35, a low-sensitivity D-phase readout period T36, and a low-sensitivity P-phase readout period T37, all within a 1H period. The determination processing period T31 includes an illuminance determination period HK. During the selective conversion efficiency P-phase readout period T32, low conversion efficiency or high conversion efficiency is selected in the P-phase level readout from the photodiode PD1 according to the illuminance determination result. During the selective conversion efficiency D-phase readout period T33, low conversion efficiency or high conversion efficiency is selected in the D-phase level readout from the photodiode PD1 according to the illuminance determination result. During the selective capacitance D-phase readout period T34, depending on the illuminance determination result, either low conversion efficiency or reading the D-phase level from overflow capacitance CF1 is selected for reading the D-phase level from photodiode PD1. During the selective capacitance P-phase readout period T35, depending on the illuminance determination result, either low conversion efficiency or reading the P-phase level from overflow capacitance CF1 is selected for reading the P-phase level from photodiode PD1. During the low sensitivity D-phase readout period T36, reading the D-phase level from photodiode PD2 is selected. During the low sensitivity P-phase readout period T37, reading the P-phase level from photodiode PD2 is selected.

[0209] During the judgment processing period T31, after the exposure period EX has elapsed, the reset signal RST and switching signals FDG, LCG, and FCGV rise. At this time, the reset transistor 121 and switching transistors 124, 125, 722, and 723 are turned on, and the floating diffusion FD1, F2, and overflow capacitance CF1 are reset. Then, the reset signal RST and switching signals FDG, LCG, and FCGV fall, and after the reset transistor 121 and switching transistors 124, 125, 722, and 723 turn off, the transfer signal TGL rises to an intermediate potential. At this time, the transfer transistor TG is half-on, and if a charge exceeding a certain value is accumulated in the photodiode PD1, that charge is transferred to the floating diffusion FD1. If the charge accumulated in the photodiode PD1 is below a certain value, that charge is not transferred to the floating diffusion FD1.

[0210] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, the potential of the vertical signal line 132 is set based on the source follower operation when a level corresponding to the presence or absence of charge in the floating diffusion FD1 is applied to the gate of the amplifier transistor 122. During the level determination period HK, the comparator CM compares the level corresponding to the presence or absence of charge in the floating diffusion FD1 with the threshold level SH, and the comparison result is input to the switching control unit 154 via the latch circuit 151.

[0211] Then, when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is above the threshold level SH (high illumination), the switching control unit 154 raises the switching signal FCGV and applies it to the pixel PX7 via the vertical control line 133. At this time, the switching transistors 124 and 723 are turned on, the capacitance of the floating diffusion FD2 is added to the floating diffusion FD1, and the switching transistor 722 is connected to the overflow capacitance CF1.

[0212] On the other hand, when the level of the floating diffusion FD1, depending on whether or not it has charge, is less than the threshold level SH (low light), the switching control unit 154 maintains the L level of the switching signal FCGV and applies it to the pixel PX7 via the vertical control line 133. At this time, the switching transistors 124 and 723 are turned off, the floating diffusion FD1 is disconnected from the floating diffusion FD2, and the switching transistor 722 is disconnected from the overflow capacitance CF1.

[0213] Next, during the selective conversion efficiency P-phase readout period T32, the selection signal SEL rises, and the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0214] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the high conversion efficiency P-phase level read from the pixel PX7 is AD converted column by column.

[0215] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase levels of the floating diffusion FD1 and FD2 are applied to the gate of the amplifier transistor 122.

[0216] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency P-phase level read from the pixel PX7 is AD converted column by column. Then, the selection signal SEL falls, and the selection transistor 123 turns off.

[0217] Next, during the selective conversion efficiency D-phase readout period T33, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.

[0218] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, the selection signal SEL rises, and the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. When the light level is low, the potential of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0219] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the high-conversion-efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the high-conversion-efficiency D-phase level read from the pixel PX7 is AD converted column by column. At this time, CDS processing can be performed based on the high-conversion-efficiency P-phase level and the high-conversion-efficiency D-phase level.

[0220] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase levels of the floating diffusion FD1 and F2 are applied to the gate of the amplifier transistor 122.

[0221] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency D-phase level read from the pixel PX7 is AD converted column by column. Then, the selection signal SEL falls, and the selection transistor 123 turns off. At this time, CDS processing can be performed based on the low conversion efficiency P-phase level and the low conversion efficiency D-phase level.

[0222] Next, during the selective capacitance D-phase readout period T34, the switching signal FDG rises and is applied to the pixel PX7 via the horizontal control line 131. At this time, the switching transistor 125 turns on, and the capacitance of floating diffusion FD2 is added to floating diffusion FD1. Then, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in photodiode PD1 is transferred to floating diffusion FD1.

[0223] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, the switching signal LCG rises and is applied to the pixel PX7 via the horizontal control line 131. At this time, the switching transistor 722 turns on, and the overflow capacitance CF1 is added to the floating diffusion FD2. Then, the selection signal SEL rises, and the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. When the illumination is low, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase level of the floating diffusions FD1 and FD2 is applied to the gate of the amplifier transistor 122.

[0224] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency D-phase level read from the pixel PX7 is AD converted column by column.

[0225] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase levels of the floating diffusion FD1 and FD2, which are based on the charge read from the overflow capacitance CF1, are applied to the gate of the amplifier transistor 122.

[0226] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the D-phase level read from the overflow capacitor CF1 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the D-phase level read from the overflow capacitor CF1 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132.

[0227] Next, during the selective capacitance P-phase readout period T35, the reset signal RST rises, the reset transistor 121 turns on, and the floating diffusions FD1 and F2 are reset. Then, the reset signal RST falls, and the reset transistor 121 turns off. After that, the selection signal SEL rises, and the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplifier transistor 122.

[0228] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency P-phase level read from the pixel PX7 is AD converted column by column.

[0229] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of floating diffusions FD1 and FD2, which are based on the charge read from the overflow capacitance CF1, are applied to the gate of the amplifier transistor 122.

[0230] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the P-phase level read from the overflow capacitor CF1 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the P-phase level read from the overflow capacitor CF1 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132.

[0231] Next, the selection signal SEL falls, and the selection transistor 123 turns off. Then, the reset signal RST rises, and the reset transistor 121 turns on, resetting the floating diffusions FD1 and F2. Then, the reset signal RST falls, and the reset transistor 121 turns off. Furthermore, the switching signal LCG falls, and the switching transistor 722 turns off. At this point, the overflow capacitance CF1 is disconnected from the floating diffusion FD2.

[0232] Next, during the low-sensitivity D-phase readout period T36, the switching signal FCG rises and is applied to the pixel PX7 via the horizontal control line 131. At this time, the switching transistor 721 turns on, adding the capacitance of floating diffusion FD3 to floating diffusion FD2, and simultaneously connecting photodiode PD2 to floating diffusion FD2 via the switching transistor 721. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase levels of floating diffusion FD1 to FD3, based on the charge read from photodiode PD2, are applied to the gate of amplifier transistor 122.

[0233] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the D-phase level read from the photodiode PD2 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the D-phase level read from the photodiode PD2 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132. Then, the selection signal SEL falls, and the selection transistor 123 turns off.

[0234] Next, during the low-sensitivity P-phase readout period T37, the reset signal RST rises, the reset transistor 121 turns on, and the floating diffusion FD1 to FD3 and the overflow capacitance CF2 are reset. Then, the reset signal RST falls, and the reset transistor 121 turns off. Then, the selection signal SEL rises, and the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of the floating diffusion FD1 to FD3, based on the charge read from the photodiode PD2, are applied to the gate of the amplifier transistor 122.

[0235] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the P-phase level read from the photodiode PD2 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the P-phase level read from the photodiode PD2 is AD converted column by column.

[0236] Figure 27 is a plan view showing an example of the layout of a solid-state imaging device according to the seventh embodiment.

[0237] In the same figure, pixel PX7 comprises gate electrodes G71 to G73, active region AK11, element isolation region ISA11, and pixel isolation layer GIS7, instead of gate electrodes G11, G12, G14, G15, active region AK5, element isolation region ISA5, and pixel isolation layer GIS5 of Figure 16. The pixel isolation layer GIS7 separates pixel PX7 and also separates photodiodes PD1 and PD2. On the active region AK11, gate electrodes GT, G1 to G5, and G71 to G73 are formed via a gate insulating film. Gate electrodes G4 and G5 can be placed close to each other. In this case, gate electrode GT can be placed in the corner of pixel PX7. Gate electrode G71 can be placed inside the element isolation region ISA11 surrounding photodiode PD2.

[0238] As described above, in the seventh embodiment, switching transistors 124, 125, 721 to 723 are provided in the pixel PX7 to selectively switch the readout from the LOFIC, high-sensitivity photodiode, and low-sensitivity photodiode based on the illuminance determination result. This makes it possible to switch the conversion efficiency in four stages based on three D-phase level readouts while enabling CDS or DDS in the pixel PX7 equipped with the LOFIC, high-sensitivity photodiode, and low-sensitivity photodiode, thereby expanding HDR while suppressing a decrease in frame rate.

[0239] <8. Eighth Embodiment> In the fourth embodiment described above, switching transistors 124, 125, 421, 422, 424, and 425 are provided on the pixel PX4 to selectively switch the readout from a plurality of LOFICs based on the illuminance determination result. In this eighth embodiment, a plurality of edges through which charge flows to different outflow destinations are provided on the gate electrode of the transfer transistor, and a plurality of edges through which charge flows in from different inflow sources are provided on the gate electrode of the switching transistor.

[0240] Figure 28 shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the eighth embodiment.

[0241] In the figure, this pixel PX has a capacitance reset transistor 128 added to the pixel PX6 of the sixth embodiment described above. The capacitance reset transistor 128 is connected between one end of the overflow capacitance CF1 and the power supply potential VDD. The other configurations of the pixel PX8 of the eighth embodiment are the same as those of the pixel PX6 of the sixth embodiment described above.

[0242] Figures 29 and 31 are plan views showing an example of the layout of a solid-state imaging device according to the eighth embodiment, and Figures 30 and 32 are cross-sectional views showing an example of the configuration of a solid-state imaging device according to the eighth embodiment. Note that in Figure 30, a is cut along the line A1-A2 in Figure 29, and in Figure 30, b is cut along the line B1-B2 in Figure 29. In Figure 32, a is cut along the line C1-C2 in Figure 31, and in Figure 32, b is cut along the line D1-D2 in Figure 31.

[0243] In the figure, each pixel PX comprises semiconductor chips CP21 and CP22. Semiconductor chip CP21 is stacked on semiconductor chip CP22. Each semiconductor chip CP21 and CP22 comprises semiconductor substrates SUB21 and SUB22, respectively. Each semiconductor substrate SUB21 and SUB22 is provided with pixel isolation layers GIS21 and GIS22, respectively, which separate the pixels PX8.

[0244] An active region AK21 is provided on the semiconductor substrate SUB21, and the active region AK21 is isolated by an element isolation region ISA21. A photodiode PD1, a channel region, and an impurity diffusion layer are formed in the active region AK21. A contact CN1 is formed on the active region AK21. The impurity diffusion layer of the active region AK21 may include a floating diffusion FD1, a transfer transistor TG, an amplifier transistor 124, a selection transistor 125, and source / drain layers for switching transistors 124 and 125.

[0245] On the active region AK21, gate electrodes GT, G2, G3, G4, G5, and G41 are formed via a gate insulating film. Gate electrodes G2, G3, G4, G5, and G41 can be arranged around gate electrode GT. In the floating diffusion FD1, N ＋ A concentrated diffusion layer of type impurities is formed.

[0246] Here, the channel region of the gate electrode GT of the transfer transistor TG has three or more distinct paths. In this case, the gate electrode GT may have multiple edges through which charge flows to different destinations via the channel region beneath the gate electrode GT. These destinations may be the impurity-concentrated diffusion layers of each switching transistor 124, 125. Alternatively, the transfer transistor TG may have two impurity diffusion layers branching from the channel region beneath the gate electrode GT to two destinations. These two impurity diffusion layers may be short-circuited via the active region AK21 or via wiring.

[0247] An active region AK22 is provided on the semiconductor substrate SUB22, and the active region AK22 is isolated by an element isolation region ISA22. A channel region and an impurity diffusion layer are formed in the active region AK22. A contact CN2 is formed on the active region AK22. The impurity diffusion layer of the active region AK22 may include the source / drain layers of the reset transistor 123, switching transistors 126, 422, 424, 425 and the capacitive reset transistor 132.

[0248] On the active region AK22, gate electrodes G1, G8, G11, G12, G14, and G15 are formed via a gate insulating film. Gate electrodes G1, G8, G12, G14, and G15 can be arranged around gate electrode G11.

[0249] Here, the channel region of the gate electrode G11 of the switching transistor 411 has three or more distinct paths. In this case, the gate electrode G11 may have multiple edges through which charge flows from different sources via the channel region beneath the gate electrode G11. These sources may be the impurity-concentrated diffusion layers of each switching transistor 424, 425. The switching transistor 411 may also have two impurity diffusion layers through which charge from two sources converges in the channel region beneath the gate electrode G11. These two impurity diffusion layers may be short-circuited via the active region AK22, short-circuited via wiring, or not short-circuited at all.

[0250] Figure 33 is a timing chart showing the waveforms of each part of the signal readout process according to the eighth embodiment.

[0251] In the figure, this signal readout process includes a determination processing period T41, a selective conversion efficiency P-phase readout period T42, a selective conversion efficiency D-phase readout period T43, a selective capacitance D-phase readout period T44, a second capacitance D-phase readout period T45, a second capacitance P-phase readout period T46, and a selective capacitance P-phase readout period T47, all within a 1H period. The determination processing period T41 includes an illuminance determination period HK. During the selective conversion efficiency P-phase readout period T42, low conversion efficiency or high conversion efficiency is selected in the P-phase level readout from the photodiode PD1 according to the illuminance determination result. During the selective conversion efficiency D-phase readout period T43, low conversion efficiency or high conversion efficiency is selected in the D-phase level readout from the photodiode PD1 according to the illuminance determination result. During the selective capacitance D-phase readout period T44, depending on the illuminance determination result, either low conversion efficiency or reading the D-phase level from overflow capacitance CF1 is selected for reading the D-phase level from photodiode PD1. During the second capacitance D-phase readout period T45, reading the D-phase level from overflow capacitance CF2 is selected. During the second capacitance P-phase readout period T46, reading the P-phase level from overflow capacitance CF2 is selected. During the selective capacitance P-phase readout period T47, depending on the illuminance determination result, either low conversion efficiency or reading the P-phase level from overflow capacitance CF1 is selected for reading the P-phase level from photodiode PD1.

[0252] During the judgment processing period T41, the reset signal RST rises after the exposure period EX. At this time, the reset transistor 121 turns on, and the floating diffusion FD1 is reset. Then, the selection signal SEL rises, and the selection transistor 123 turns on. At this time, the amplifier transistor 122 is connected to the vertical signal line 132 via the selection transistor 123. Also, the control voltage FVD rises and is applied to the overflow capacitors CF1 and CF2. After that, the transfer signal TGL rises to an intermediate potential. At this time, the transfer transistor TG is half-on, and if a charge exceeding a certain value is accumulated in the photodiode PD1, that charge is transferred to the floating diffusion FD1. If the charge accumulated in the photodiode PD1 is below a certain value, that charge is not transferred to the floating diffusion FD1.

[0253] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, the potential of the vertical signal line 132 is set based on the source follower operation when a level corresponding to the presence or absence of charge in the floating diffusion FD1 is applied to the gate of the amplifier transistor 122. During the level determination period HK, the comparator CM compares the level corresponding to the presence or absence of charge in the floating diffusion FD1 with the threshold level SH, and the comparison result is input to the switching control unit 154 via the latch circuit 151.

[0254] Then, when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is above the threshold level SH (high illumination), the switching control unit 154 raises the switching signal FCGV and applies it to the pixel PX4 via the vertical control line 133. At this time, the switching transistors 124 and 424 are turned on, the capacitance of the floating diffusion FD2 is added to the floating diffusion FD1, and the switching transistor 421 is connected to the floating diffusion FD2.

[0255] On the other hand, when the level corresponding to the presence or absence of charge in the floating diffusion FD1 is less than the threshold level SH (low illumination), the switching control unit 154 maintains the L level of the switching signal FCGV and applies it to the pixel PX8 via the vertical control line 133. At this time, the switching transistors 124 and 424 are turned off, the floating diffusion FD1 is disconnected from the floating diffusion FD2, and the switching transistor 421 is disconnected from the floating diffusion FD2.

[0256] Next, during the selective conversion efficiency P-phase readout period T42, when the illumination is low, the potential of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0257] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the high conversion efficiency P-phase level read from the pixel PX8 is AD converted column by column.

[0258] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase levels of the floating diffusion FD1 and FD2 are applied to the gate of the amplifier transistor 122.

[0259] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency P-phase level read from the pixel PX8 is AD converted column by column.

[0260] Next, during the selective conversion efficiency D-phase readout period T43, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.

[0261] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplifier transistor 122.

[0262] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the high-efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the high-efficiency D-phase level read from the pixel PX8 is AD converted column by column. At this time, CDS processing can be performed based on the high-efficiency P-phase level and the high-efficiency D-phase level.

[0263] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase levels of the floating diffusion FD1 and F2 are applied to the gate of the amplifier transistor 122.

[0264] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency D-phase level read from the pixel PX8 is AD converted column by column. At this time, CDS processing can be performed based on the low conversion efficiency P-phase level and the low conversion efficiency D-phase level.

[0265] Next, during the selective capacitance D-phase readout period T44, the switching signal FDG rises and is applied to the pixel PX8 via the horizontal control line 131. At this time, the switching transistor 125 turns on, and the capacitance of floating diffusion FD2 is added to floating diffusion FD1. Also, the switching signal FCG rises and is applied to the pixel PX8 via the horizontal control line 131. At this time, the switching transistor 421 turns on, and the parallel circuit of switching transistors 424 and 425 is connected to floating diffusion FD3. Then, the transfer signal TGL rises, the transfer transistor TG turns on, and the charge accumulated in photodiode PD1 is transferred to floating diffusion FD1.

[0266] Next, when the transfer signal TGL falls, the transfer transistor TG turns off. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gate of the amplifier transistor 122.

[0267] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency D-phase level read from the pixel PX8 is AD converted column by column.

[0268] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase level of the floating diffusion FD1 to FD3, which is based on the charge read from the overflow capacitance CF1, is applied to the gate of the amplifier transistor 122.

[0269] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the D-phase level read from the overflow capacitor CF1 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the D-phase level read from the overflow capacitor CF1 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132.

[0270] Next, during the second capacitance D-phase readout period T45, the switching signal FCG2 rises and is applied to the pixel PX8 via the horizontal control line 131. At this time, the switching transistors 422 and 424 are turned on, the capacitance of floating diffusion FD3 is added to floating diffusion FD2, and the overflow capacitance CF2 is connected to floating diffusion FD3 via the switching transistor 422. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase levels of floating diffusion FD1 to FD3, based on the charge read from overflow capacitance CF2, are applied to the gate of amplifier transistor 122.

[0271] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the D-phase level read from the overflow capacitor CF2 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the D-phase level read from the overflow capacitor CF2 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132.

[0272] Next, during the second capacitance P-phase readout period T46, the reset signal RST rises, the reset transistor 121 turns on, and the floating diffusion FD1 to FD3 and the overflow capacitance CF2 are reset. Also, the capacitance reset signal MRT rises, the capacitance reset transistor 128 turns on, and the overflow capacitance CF1 is reset. Then, the reset signals RST and MRT fall, and the reset transistors 121 and 128 turn off. Finally, the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of the floating diffusion FD1 to FD3, based on the charge read from the overflow capacitance CF2, are applied to the gate of the amplifier transistor 122.

[0273] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the P-phase level read from the overflow capacitor CF2 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the P-phase level read from the overflow capacitor CF2 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132.

[0274] Next, during the selective capacitance P-phase readout period T47, the switching signal FCG2 falls. At this time, the switching transistors 422 and 424 are turned off, and the overflow capacitance CF2 is disconnected from the floating diffusion FD3. Then, in low light conditions, the potential of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase levels of the floating diffusion FD1 and FD2 are applied to the gate of the amplifier transistor 122.

[0275] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, based on the count operation until the ramp wave level matches the potential of the vertical signal line 132, the low conversion efficiency P-phase level read from the pixel PX8 is AD converted column by column.

[0276] On the other hand, when the illumination is high, the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of the floating diffusion FD1 to FD3, which are based on the charge read from the overflow capacitance CF1, are applied to the gate of the amplifier transistor 122.

[0277] Next, in the comparator CM, the potential of the vertical signal line 132 corresponding to the P-phase level read from the overflow capacitor CF1 is compared with the ramp wave, and the timing when the ramp wave level matches the potential of the vertical signal line 132 is output as the comparison result. At this time, the P-phase level read from the overflow capacitor CF1 is AD converted column by column based on the count operation until the ramp wave level matches the potential of the vertical signal line 132.

[0278] As described above, in the eighth embodiment, multiple edges are provided on the gate electrode GT of the transfer transistor TG, through which charge flows to different outflow destinations via the channel region, and multiple edges are provided on the gate electrode of the switching transistor 421, through which charge flows in from different inflow sources via the channel region. This makes it possible to form different outflow destinations under the gate electrode GT of the transfer transistor TG, and to form confluence destinations from different inflow sources under the gate electrode G11 of the switching transistor 421. As a result, it is possible to reduce the path from the transfer transistor TG to each switching transistor 124, 125, and to reduce the path from each switching transistor 424, 425 to the switching transistor 421, thereby reducing the layout area of ​​the pixel PX8.

[0279] <9. Ninth Embodiment> In the eighth embodiment described above, multiple edges from which charge flows out to different outflow destinations are provided on the gate electrode GT of the transfer transistor TG via the channel region, and multiple edges from which charge flows in from different inflow sources are provided on the gate electrode of the switching transistor 421 via the channel region. In this ninth embodiment, the upper layer chip on which the photodiode and LOFIC are provided is joined to the lower layer chip based on face-to-face connection.

[0280] Figure 34 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the ninth embodiment. In this figure, an example of the configuration of four pixels PX9 is shown.

[0281] In the figure, pixel PX9 comprises semiconductor chips CP11 to CP13. A semiconductor chip CP12 is stacked on semiconductor chip CP13, and a semiconductor chip CP11 is stacked on semiconductor chip CP12. Each of the semiconductor chips CP11 to CP13 comprises a semiconductor substrate SUB11 to SUB13. A pixel isolation layer GIS11 is provided on the semiconductor substrate SUB11 to separate the pixels PX9.

[0282] A photodiode PD1 is formed on the semiconductor substrate SUB11. On the semiconductor substrate SUB11, gate electrodes GT, G2, G3, G4, G5, and G41 are formed via a gate insulating film. An N-type impurity concentration diffusion layer DF11 is formed adjacent to the channel region beneath each gate electrode GT, G2, G3, G4, G5, and G41. Each gate electrode GT, G2, G3, G4, G5, and G41 is embedded in an insulating layer ZL11.

[0283] A color filter CFL is formed on the back side of the semiconductor substrate SUB11 for each pixel PX9. An on-chip lens OCL is formed on the color filter CFL for each pixel PX9. The material for the color filter CFL and the on-chip lens OCL is, for example, SiO ２Insulating films such as SiN and SiCN, or transparent resins such as acrylic or polycarbonate can be used. The color filter CFL may contain pigments. The color filter CFL may, for example, form a Bayer array or a quad Bayer array. The color filter CFL may include an RGB filter, a complementary color filter, or a white filter. Lenses, color splitters, or deflectors made of metasurfaces may be formed on the back side of the semiconductor substrate SUB1.

[0284] On the semiconductor substrate SUB12, gate electrodes G1, G8, G11, G12, G14, and G15 are formed via a gate insulating film. Each gate electrode G1, G8, G11, G12, G14, and G15 is embedded in an insulating layer ZL12. Within the insulating layer ZL12, wiring H12, via BA12, junction electrode DE12, and overflow capacitors CF1 and CF2 are formed. The overflow capacitors CF1 and CF2 may also be folded structures of opposing electrodes. Furthermore, a through electrode KD11 that penetrates the semiconductor substrate SUB12 is formed within the insulating layer ZL12. The junction electrode DE12 can be connected to wiring H2 via via BA12. The junction electrode DE12 is exposed from the surface of the insulating layer ZL12.

[0285] A gate electrode GR is formed on the semiconductor substrate SUB13 via a gate insulating film. The gate electrode GR may be a logic gate. The gate electrode GR is embedded in an insulating layer ZL13. A via BA13, wiring H13, and junction electrode DE13 are formed within the insulating layer ZL13. The junction electrode DE13 is exposed from the surface of the insulating layer ZL13. The via BA13 is connected to the gate electrode GR. The junction electrodes DE12 and DE13 are joined to each other. The joining of the junction electrodes DE12 and DE13 may be a Cu-Cu junction. In this case, the semiconductor chips CP12 and CP13 can be connected face to face.

[0286] Thus, in the ninth embodiment described above, the upper chip on which the photodiode and LOFIC are provided is joined to the lower chip based on face-to-face connection. This makes it possible to provide the switching transistors 124, 125, 421, 422, 424, and 425 on the pixel PX9 while suppressing an increase in the planar size of the pixel PX9, and also makes it possible to increase the capacitance of the LOFIC.

[0287] <10. Tenth Embodiment> In the ninth embodiment described above, the upper layer chip on which the photodiode and LOFIC are provided was bonded to the lower layer chip based on face-to-face connection. In this tenth embodiment, the upper layer chip on which the photodiode is provided is bonded to the middle layer chip on which the LOFIC is provided based on face-to-face connection, and the middle layer chip is bonded to the lower layer chip based on face-to-bottom connection.

[0288] Figure 35 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the tenth embodiment. In this figure, an example of the configuration of four pixels PX10 is shown.

[0289] In the figure, this pixel PX10 is equipped with semiconductor chips CP11' and CP12' instead of semiconductor chips CP11 and CP12 in the ninth embodiment described above. The other configurations of the pixel PX10 in the tenth embodiment are the same as those of the pixel PX9 in the ninth embodiment described above.

[0290] A semiconductor chip CP12' is stacked on semiconductor chip CP13, and a semiconductor chip CP11' is stacked on semiconductor chip CP12'. Semiconductor chip CP11' is the semiconductor chip CP11 of the ninth embodiment described above, with the addition of wiring H21, via BA21, and junction electrode DE21. The other configurations of semiconductor chip CP11' of the tenth embodiment are the same as those of semiconductor chip CP11 of the ninth embodiment described above.

[0291] The wiring H21, via BA21, and junction electrode DE21 are embedded within the insulating layer ZL11. The junction electrode DE21 can be connected to the wiring H21 via BA21. The junction electrode DE21 is exposed from the surface of the insulating layer ZL11.

[0292] The semiconductor chip CP12' includes junction electrodes DE12A, DE12B, and a through electrode KD22, instead of the junction electrode DE12 and through electrode KD11 of the ninth embodiment described above. The other configurations of the semiconductor chip CP12' of the tenth embodiment are the same as those of the semiconductor chip CP12 of the ninth embodiment described above.

[0293] The junction electrodes DE12A, DE12B, and through electrode KD22 are embedded in the insulating layer ZL12. The through electrode KD22 penetrates the semiconductor substrate SUB12 and is connected to the junction electrode DE12A. The junction electrode DE12B can be connected to the wiring H12 via via BA12. The junction electrode DE21B is exposed from the surface of the insulating layer ZL11. The junction electrode DE21A is exposed from the back surface of the insulating layer ZL11.

[0294] The bonding electrodes DE21 and DE12B are bonded to each other. The bonding electrodes DE13 and DE12A are bonded to each other. The bonding of bonding electrodes DE21 and DE12B, the bonding of bonding electrode DE13, and DE12A may be Cu-Cu bonding. In this case, semiconductor chips CP11' and CP12' can be connected face to face. Semiconductor chips CP12' and CP13 can be connected face to bottom.

[0295] Thus, in the tenth embodiment described above, the upper layer chip on which the photodiode is provided is joined to the middle layer chip on which the LOFIC is provided based on face-to-face connection, and the middle layer chip is joined to the lower layer chip based on face-to-bottom connection. This makes it possible to provide the switching transistors 124, 125, 421, 422, 424, and 425 on the pixel PX10 while suppressing an increase in the planar size of the pixel PX10, and also makes it possible to increase the capacity of the LOFIC.

[0296] <11. Eleventh Embodiment> In the tenth embodiment described above, the upper chip on which the photodiode is provided is bonded to the middle chip on which the LOFIC is provided based on face-to-face connection, and the middle chip is bonded to the lower chip based on face-to-bottom connection. In this eleventh embodiment, the upper chip on which the photodiode is provided is bonded to the middle chip on which the LOFIC is provided based on face-to-bottom connection, and the middle chip is bonded to the lower chip based on face-to-face connection.

[0297] Figure 36 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to the eleventh embodiment. In this figure, an example of the configuration of four pixels PX11 is shown.

[0298] In the figure, the pixel PX11 is formed by inverting the semiconductor chip CP12' of the 10th embodiment described above and bonding it between semiconductor chips CP11' and CP13. At this time, semiconductor chips CP11' and CP12' can be connected face to bottom. Semiconductor chips CP12' and CP13 can be connected face to face. The other configurations of the pixel PX11 of the 11th embodiment are the same as those of the pixel PX9 of the 9th embodiment described above.

[0299] Thus, in the 11th embodiment described above, the upper layer chip on which the photodiode is provided is joined to the middle layer chip on which the LOFIC is provided based on face-to-bottom connection, and the middle layer chip is joined to the lower layer chip based on face-to-face connection. This makes it possible to provide the switching transistors 124, 125, 421, 422, 424, and 425 on the pixel PX11 while suppressing an increase in the planar size of the pixel PX11, and also makes it possible to increase the capacity of the LOFIC.

[0300] <12. Twelfth Embodiment> In the first embodiment described above, switching transistors 124 to 127 are provided in the pixel PX to selectively switch between reading from a high-sensitivity photodiode and a low-sensitivity photodiode based on the illuminance determination result. In this twelfth embodiment, semiconductor chips are stacked, each having a pixel array section in which pixels are arranged in a matrix.

[0301] Figure 37 is a perspective view showing an example of stacking of pixel arrays according to the twelfth embodiment.

[0302] In the figure, the solid-state imaging device comprises semiconductor chips 921 and 922. Semiconductor chip 922 is stacked on semiconductor chip 921.

[0303] A pixel array section 923 is formed on the semiconductor chip 922. Pixels 931 are arranged in a matrix in the row and column directions within the pixel array section 923. Each pixel 931 may be any of the pixels PX1 to PX11 described in the first to eleventh embodiments above. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0304] Peripheral circuits 924 are formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed on the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction.

[0305] The semiconductor chips 921 and 922 may be directly bonded. Hybrid bonding can be used for the direct bonding of the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu connections. The semiconductor substrate material used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0306] Thus, in the twelfth embodiment described above, the semiconductor chip 922 on which the pixel array portion 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the dynamic range of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0307] <13. Examples of Application to Mobile Devices> The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be realized as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0308] Figure 38 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0309] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 38, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0310] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0311] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0312] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0313] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0314] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0315] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0316] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0317] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0318] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 38, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0319] Figure 39 shows an example of the installation position of the imaging unit 12031.

[0320] In Figure 39, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0321] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0322] Figure 39 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0323] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0324] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0325] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0326] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0327] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, the imaging device of the above embodiment can be applied to the imaging unit 12031. By applying the technology described herein to the vehicle control system 12000, it becomes possible to expand HDR while suppressing a decrease in frame rate.

[0328] Furthermore, any of the imaging devices described in the first to third embodiments above may be applied not only to imaging devices, but also to electronic circuits used in communication devices, display devices, data processing devices, control devices, measuring devices, or printing devices.

[0329] Furthermore, the embodiments described above are merely examples of how to realize the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology that bear the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the present technology. Also, the effects described herein are merely examples and are not limiting, and there may be other effects.

[0330] Furthermore, this technology can also take the following configuration: (1) An imaging device comprising: a photoelectric conversion unit provided in a pixel; a first floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred; a second floating diffusion separate from the first floating diffusion; a third floating diffusion separate from the second floating diffusion; a first switching transistor that switches the connection between the first floating diffusion and the second floating diffusion based on a first switching signal; a second switching transistor connected in parallel with the first switching transistor and switching the connection between the first floating diffusion and the second floating diffusion based on a second switching signal; a third switching transistor that switches the connection between the second floating diffusion and the third floating diffusion based on a third switching signal; and a fourth switching transistor connected in series with the third switching transistor and switching the connection between the second floating diffusion and the third floating diffusion based on a fourth switching signal. (2) The imaging apparatus according to (1), wherein the first switching signal and the third switching signal are common, and the second switching signal and the fourth switching signal are common. (3) The imaging apparatus according to (1) or (2), wherein the pixels are arranged in a matrix in the row direction and the column direction, and the apparatus comprises a horizontal control line for transmitting the first switching signal and the third switching signal in the row direction, and a vertical control line for transmitting the second switching signal and the fourth switching signal in the column direction. (4) The imaging apparatus according to (3), wherein the pixels comprises a transfer transistor for transferring the charge accumulated in the photoelectric conversion unit to a first floating diffusion, a reset transistor for resetting the first floating diffusion, an amplifier transistor for outputting a pixel signal corresponding to the charge accumulated in the first floating diffusion, and a selection transistor for selecting the output from the amplifier transistor.(5) The imaging apparatus according to (4), further comprising: a first chip on which the photoelectric conversion unit, the first floating diffusion, the first switching transistor, the second switching transistor, the transfer transistor, and the amplifier transistor are formed; and a second chip on which the first chip is stacked and on which the reset transistor and the selection transistor are formed. (6) The imaging apparatus according to (4) or (1), further comprising: a first photodiode connected to the first floating diffusion via the transfer transistor, and a second photodiode connected to the third floating diffusion and having lower sensitivity than the first photodiode. (7) When the gate potential of the transfer transistor is set to an intermediate potential, the system determines whether the illumination is low or high based on the signal level corresponding to the charge transferred to the first floating diffusion, If low illumination is determined, the system turns off the first to fourth switching transistors and sets the conversion efficiency to HCG (High Conversion Gain), and sequentially reads out the P-phase level and D-phase level based on the charge accumulated in the first photodiode, Turns off the second and fourth switching transistors, turns on the first and third switching transistors and sets the conversion efficiency to LCG (Low Conversion Gain), and sequentially reads out the D-phase level and P-phase level based on the charge accumulated in the first photodiode, If high illumination is determined, the system turns off the second and fourth switching transistors, turns on the first and third switching transistors and sets the conversion efficiency to LCG, and sequentially reads out the D-phase level and P-phase level based on the charge accumulated in the first photodiode, The imaging apparatus according to (6), wherein the first to fourth switching transistors are turned on to set the conversion efficiency to LCG, and the P-phase level and D-phase level are sequentially read out based on the charge accumulated in the second photodiode. (8) A fifth switching transistor connected in parallel with the third switching transistor, which switches the connection between the second floating diffusion and the third floating diffusion based on a fifth switching signal,The imaging apparatus according to (1), further comprising a sixth switching transistor connected in series with the fourth switching transistor, the connection to the third floating diffusion being switched based on a sixth switching signal. (9) The imaging apparatus according to (8), wherein the first switching signal and the third switching signal are common, and the fifth switching signal and the sixth switching signal are common. (10) The imaging apparatus according to (9), wherein the pixels are arranged in a matrix in the row direction and the column direction, and further comprising a horizontal control line for transmitting the first switching signal and the third switching signal in the row direction, and a vertical control line for transmitting the fifth switching signal and the sixth switching signal in the column direction. (11) A transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to a first floating diffusion, a first LOFIC (Lateral Overflow Integration Capacitor) connected to the third floating diffusion, and a second LOFIC connected to the third floating diffusion via a sixth switching transistor, wherein low or high illumination is determined based on the signal level corresponding to the charge transferred to the first floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, if low illumination is determined, the first to sixth switching transistors are turned off and the conversion efficiency is set to HCG, and the P-phase level and D-phase level are read out sequentially based on the charge accumulated in the photoelectric conversion unit, the second and fourth switching transistors are turned on, the first, third, fifth and sixth switching transistors are turned off and the conversion efficiency is set to LCG, and the D-phase level is read out based on the charge accumulated in the photoelectric conversion unit, The second, fourth, fifth, and sixth switching transistors are turned on, and the first and third switching transistors are turned off to set the conversion efficiency to LCG, and the D-phase level and P-phase level are sequentially read out based on the charge accumulated in the photoelectric conversion unit and the second LOFIC, the second switching transistor is turned on, and the first and third to sixth switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level is read out based on the charge accumulated in the photoelectric conversion unit, and if high illuminance is determined,The imaging apparatus according to any one of (8) to (11) above, wherein the first and third switching transistors are turned on, the second and fourth to sixth switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level and D-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit; the first to fourth switching transistors are turned on, the fifth and sixth switching transistors are turned off to set the conversion efficiency to LCG, and the D-phase level is read based on the charge accumulated in the photoelectric conversion unit and the first LOFIC; the first to sixth switching transistors are turned on to set the conversion efficiency to LCG, and the D-phase level and P-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit and the second LOFIC; the first to third switching transistors are turned on, the fourth to sixth switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level is read based on the charge accumulated in the photoelectric conversion unit and the first LOFIC. (12) The imaging apparatus according to (11), further comprising an overflow control transistor connected between the first LOFIC and the photoelectric conversion unit. (13) The imaging apparatus according to (8), further comprising a seventh switching transistor connected in parallel to the sixth switching transistor, which switches the connection between the third floating diffusion and the sixth switching transistor based on a seventh switching signal. (14) The imaging apparatus according to (13), wherein the first switching signal, the third switching signal and the seventh switching signal are common, and the fifth switching signal and the sixth switching signal are common. (15) The imaging apparatus according to (14), wherein the pixels are arranged in a matrix in the row direction and the column direction, and further comprising a horizontal control line for transmitting the first switching signal, the third switching signal and the seventh switching signal in the row direction, and a vertical control line for transmitting the fifth switching signal and the sixth switching signal in the column direction. (16) A transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to the first floating diffusion, and a first LOFIC (Lateral Overflow Integration Capacitor) connected to the third floating diffusion,The system comprises a second LOFIC connected to the third floating diffusion via the sixth switching transistor and the seventh switching transistor, and determines low or high illumination based on the signal level corresponding to the charge transferred to the first floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, and if low illumination is determined, the first to seventh switching transistors are turned off and the conversion efficiency is set to HCG, and the P-phase level and D-phase level are read out sequentially based on the charge accumulated in the photoelectric conversion unit, the second and fourth switching transistors are turned on, the first, third and fifth to seventh switching transistors are turned off and the conversion efficiency is set to LCG, and the D-phase level is read out based on the charge accumulated in the photoelectric conversion unit, the second, fourth, fifth and sixth switching transistors are turned on, the first, third and seventh switching transistors are turned off and the conversion efficiency is set to LCG, and the D-phase level and P-phase level are read out sequentially based on the charge accumulated in the photoelectric conversion unit and the first LOFIC. The second switching transistor is turned on, the first and third to seventh switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level is read based on the charge accumulated in the photoelectric conversion unit. If high illumination is determined, the first and third switching transistors are turned on, the second and fourth to seventh switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level and D-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit. The first to fourth and seventh switching transistors are turned on, the fifth and sixth switching transistors are turned off to set the conversion efficiency to LCG, and the D-phase level is read based on the charge accumulated in the photoelectric conversion unit and the first LOFIC. The first to seventh switching transistors are turned on to set the conversion efficiency to LCG, and the D-phase level and P-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit and the second LOFIC. The imaging apparatus according to (15), wherein the first to third switching and seventh switching transistors are turned on, the fourth to sixth switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level is read based on the charge accumulated in the photoelectric conversion unit and the first LOFIC. (17) The photoelectric conversion unit is,The imaging apparatus according to (8), comprising a first photodiode connected to the first floating diffusion via the transfer transistor, and a second photodiode connected to the second floating diffusion and having lower sensitivity than the first photodiode. (18) A transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to a first floating diffusion, a LOFIC connected to the third floating diffusion, and an eighth switching transistor that switches the connection between the second photodiode and the second floating diffusion, wherein when the gate potential of the transfer transistor is set to an intermediate potential, low or high illumination is determined based on the signal level corresponding to the charge transferred to the first floating diffusion, if low illumination is determined, the first to fourth and eighth switching transistors are turned off and the conversion efficiency is set to HCG, and the P-phase level and D-phase level are read out sequentially based on the charge accumulated in the first photodiode, the second and fourth switching transistors are turned on, the first, third and eighth switching transistors are turned off and the conversion efficiency is set to LCG, and the D-phase level and P-phase level are read out sequentially based on the charge accumulated in the first photodiode and the LOFIC, The second and eighth switching transistors are turned on, the first, third and fourth switching transistors are turned off, and the conversion efficiency is set to HCG. The D-phase level and P-phase level are read sequentially based on the charge accumulated in the second photodiode. If high illumination is determined, the first and third switching transistors are turned on, the second, fourth and eighth switching transistors are turned off, and the conversion efficiency is set to MCG (Middle Conversion Gain). The P-phase level and D-phase level are read sequentially based on the charge accumulated in the first photodiode. The first to fourth switching transistors are turned on, the eighth switching transistor is turned off, and the conversion efficiency is set to LCG. The D-phase level and P-phase level are read sequentially based on the charge accumulated in the first photodiode and the LOFIC.The imaging apparatus according to (17), wherein the first to third and eighth switching transistors are turned on, the fourth switching transistor is turned off to set the conversion efficiency to LCG, and the D-phase level and P-phase level are sequentially read out based on the charge accumulated in the second photodiode. (19) The imaging apparatus comprising a transistor having a gate electrode on a channel region, wherein the channel region comprises three or more paths that are different from each other. (20) The imaging apparatus according to (19), wherein the transistor is used as a transfer transistor to transfer the charge accumulated in the photoelectric conversion unit to a floating diffusion, and the gate electrode of the transfer transistor has a plurality of edges through which the charge flows to different outflow destinations via the channel region. (21) The imaging apparatus according to (20), wherein the transfer transistor comprises two impurity diffusion layers that branch from the channel region to two outflow destinations. (22) The imaging apparatus according to (19), wherein the transistor is used as a switching transistor to switch the conversion efficiency of a pixel, and the gate electrode of the switching transistor has a plurality of edges through which the charge flows in from different inflow sources via the channel region. (23) The imaging apparatus according to (22), wherein the switching transistor comprises two impurity diffusion layers that merge into the channel region from two inflow sources. (24) The imaging apparatus according to (21) or (23), wherein the two impurity diffusion layers are short-circuited within the semiconductor layer in which the two impurity diffusion layers are formed. (25) The imaging apparatus according to (21) or (23), wherein the two impurity diffusion layers are short-circuited via wiring. (26) The imaging apparatus according to (21) or (23), wherein the two impurity diffusion layers are not short-circuited. (27) The imaging apparatus comprising a photoelectric conversion unit provided in a pixel, a floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred, and a LOFIC to which the charge overflowing from the photoelectric conversion unit is accumulated, wherein the LOFIC comprises a via embedded in a semiconductor substrate and a dielectric layer formed between the semiconductor substrate and the via, and the via and the semiconductor substrate are used as counter electrodes of the LOFIC.

[0331] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Storage unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column reading circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit PX Pixel 131 Horizontal control line 132 Vertical signal line 133 Vertical control line C1, C2 Input capacitance CM Comparator 151 Latch circuit 152 Multiplexer 153 Counter 154 Switching control unit

Claims

1. An imaging device comprising: a photoelectric conversion unit provided in a pixel; a first floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred; a second floating diffusion separate from the first floating diffusion; a third floating diffusion separate from the second floating diffusion; a first switching transistor that switches the connection between the first floating diffusion and the second floating diffusion based on a first switching signal; a second switching transistor connected in parallel to the first switching transistor and switching the connection between the first floating diffusion and the second floating diffusion based on a second switching signal; a third switching transistor that switches the connection between the second floating diffusion and the third floating diffusion based on a third switching signal; and a fourth switching transistor connected in series with the third switching transistor and switching the connection between the second floating diffusion and the third floating diffusion based on a fourth switching signal.

2. The imaging apparatus according to claim 1, wherein the first switching signal and the third switching signal are common, and the second switching signal and the fourth switching signal are common.

3. The imaging apparatus according to claim 1, wherein the pixels are arranged in a matrix in the row direction and the column direction, and the apparatus comprises a horizontal control line for transmitting the first switching signal and the third switching signal in the row direction, and a vertical control line for transmitting the second switching signal and the fourth switching signal in the column direction.

4. The imaging apparatus according to claim 3, wherein the pixel comprises a transfer transistor for transferring the charge accumulated in the photoelectric conversion unit to a first floating diffusion; a reset transistor for resetting the first floating diffusion; an amplifier transistor for outputting a pixel signal corresponding to the charge accumulated in the first floating diffusion; and a selection transistor for selecting the output from the amplifier transistor.

5. The imaging apparatus according to claim 4, comprising: a first chip on which the photoelectric conversion unit, the first floating diffusion, the first switching transistor, the second switching transistor, the transfer transistor, and the amplifier transistor are formed; and a second chip on which the first chip is stacked and on which the reset transistor and the selection transistor are formed.

6. The imaging apparatus according to claim 4, wherein the photoelectric conversion unit comprises a first photodiode connected to the first floating diffusion via the transfer transistor, and a second photodiode connected to the third floating diffusion and having lower sensitivity than the first photodiode.

7. When the gate potential of the transfer transistor is set to an intermediate potential, low or high illumination is determined based on the signal level corresponding to the charge transferred to the first floating diffusion; if low illumination is determined, the first to fourth switching transistors are turned off and the conversion efficiency is set to HCG (High Conversion Gain), and the P-phase level and D-phase level are read out sequentially based on the charge accumulated in the first photodiode; the second and fourth switching transistors are turned off, the first and third switching transistors are turned on and the conversion efficiency is set to LCG (Low Conversion Gain), and the D-phase level and P-phase level are read out sequentially based on the charge accumulated in the first photodiode; if high illumination is determined, the second and fourth switching transistors are turned off, the first and third switching transistors are turned on and the conversion efficiency is set to LCG, and the D-phase level and P-phase level are read out sequentially based on the charge accumulated in the first photodiode. The imaging apparatus according to claim 6, wherein the first to fourth switching transistors are turned on to set the conversion efficiency to LCG, and the P-phase level and D-phase level are sequentially read out based on the charge accumulated in the second photodiode.

8. The imaging apparatus according to claim 1, further comprising: a fifth switching transistor connected in parallel to the third switching transistor for switching the connection between the second floating diffusion and the third floating diffusion based on a fifth switching signal; and a sixth switching transistor connected in series with the fourth switching transistor for switching the connection with the third floating diffusion based on a sixth switching signal.

9. The imaging apparatus according to claim 8, wherein the first switching signal and the third switching signal are common, and the fifth switching signal and the sixth switching signal are common.

10. The imaging apparatus according to claim 9, wherein the pixels are arranged in a matrix in the row direction and the column direction, and the apparatus comprises a horizontal control line for transmitting the first switching signal and the third switching signal in the row direction, and a vertical control line for transmitting the fifth switching signal and the sixth switching signal in the column direction.

11. The photoelectric conversion unit comprises a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to a first floating diffusion, a first LOFIC (Lateral Overflow Integration Capacitor) connected to the third floating diffusion, and a second LOFIC connected to the third floating diffusion via a sixth switching transistor, wherein low or high illumination is determined based on the signal level corresponding to the charge transferred to the first floating diffusion when the gate potential of the transfer transistor is set to an intermediate potential, if low illumination is determined, the first to sixth switching transistors are turned off to set the conversion efficiency to HCG, and the P-phase level and D-phase level are read out sequentially based on the charge accumulated in the photoelectric conversion unit, the second and fourth switching transistors are turned on, the first, third, fifth and sixth switching transistors are turned off to set the conversion efficiency to LCG, and the D-phase level is read out based on the charge accumulated in the photoelectric conversion unit. The second, fourth, fifth, and sixth switching transistors are turned on, and the first and third switching transistors are turned off to set the conversion efficiency to LCG, and the D-phase level and P-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit and the second LOFIC, The second switching transistor is turned on, and the first and third to sixth switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level is read based on the charge accumulated in the photoelectric conversion unit, If high illuminance is determined, the first and third switching transistors are turned on, and the second and fourth to sixth switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level and D-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit, The first to fourth switching transistors are turned on, and the fifth and sixth switching transistors are turned off to set the conversion efficiency to LCG, and the D-phase level is read based on the charge accumulated in the photoelectric conversion unit and the first LOFIC, The first to sixth switching transistors are turned on to set the conversion efficiency to LCG, and the D-phase level and P-phase level are sequentially read out based on the charge accumulated in the photoelectric conversion unit and the second LOFIC.The imaging apparatus according to claim 8, wherein the first to third switching transistors are turned on, the fourth to sixth switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level is read out based on the charge accumulated in the photoelectric conversion unit and the first LOFIC.

12. The imaging apparatus according to claim 11, further comprising an overflow control transistor connected between the first LOFIC and the photoelectric conversion unit.

13. The imaging apparatus according to claim 8, further comprising a seventh switching transistor connected in parallel to the sixth switching transistor, which switches the connection between the third floating diffusion and the sixth switching transistor based on a seventh switching signal.

14. The imaging apparatus according to claim 13, wherein the first switching signal, the third switching signal, and the seventh switching signal are common, and the fifth switching signal and the sixth replacement signal are common.

15. The imaging apparatus according to claim 14, wherein the pixels are arranged in a matrix in the row direction and the column direction, and the apparatus comprises a horizontal control line for transmitting the first switching signal, the third switching signal and the seventh switching signal in the row direction, and a vertical control line for transmitting the fifth switching signal and the sixth switching signal in the column direction.

16. The photoelectric conversion unit comprises a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to a first floating diffusion, a first LOFIC (Lateral Overflow Integration Capacitor) connected to the third floating diffusion, and a second LOFIC connected to the third floating diffusion via the sixth and seventh switching transistors, wherein when the gate potential of the transfer transistor is set to an intermediate potential, low or high illumination is determined based on the signal level corresponding to the charge transferred to the first floating diffusion, if low illumination is determined, the first to seventh switching transistors are turned off and the conversion efficiency is set to HCG, and the P-phase level and D-phase level are read out sequentially based on the charge accumulated in the photoelectric conversion unit, the second and fourth switching transistors are turned on, the first, third and fifth to seventh switching transistors are turned off and the conversion efficiency is set to LCG, and the D-phase level is read out based on the charge accumulated in the photoelectric conversion unit. The second, fourth, fifth, and sixth switching transistors are turned on, the first, third, and seventh switching transistors are turned off to set the conversion efficiency to LCG, and the D-phase level and P-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit and the first LOFIC, the second switching transistor is turned on, the first and third to seventh switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level is read based on the charge accumulated in the photoelectric conversion unit, If high illuminance is determined, the first and third switching transistors are turned on, the second and fourth to seventh switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level and D-phase level are read sequentially based on the charge accumulated in the photoelectric conversion unit, the first to fourth switching and seventh switching transistors are turned on, the fifth and sixth switching transistors are turned off to set the conversion efficiency to LCG, and the D-phase level is read based on the charge accumulated in the photoelectric conversion unit and the first LOFIC, The first to seventh switching transistors are turned on to set the conversion efficiency to LCG, and the D-phase level and P-phase level are sequentially read out based on the charge accumulated in the photoelectric conversion unit and the second LOFIC.The imaging apparatus according to claim 15, wherein the first to third switching and seventh switching transistors are turned on, the fourth to sixth switching transistors are turned off to set the conversion efficiency to LCG, and the P-phase level is read based on the charge accumulated in the photoelectric conversion unit and the first LOFIC.

17. The imaging apparatus according to claim 8, wherein the photoelectric conversion unit comprises a first photodiode connected to the first floating diffusion via the transfer transistor, and a second photodiode connected to the second floating diffusion and having lower sensitivity than the first photodiode.

18. The device comprises a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit to a first floating diffusion, a LOFIC connected to the third floating diffusion, and an eighth switching transistor that switches the connection between the second photodiode and the second floating diffusion, wherein when the gate potential of the transfer transistor is set to an intermediate potential, low or high illumination is determined based on the signal level corresponding to the charge transferred to the first floating diffusion, and if low illumination is determined, the first to fourth and eighth switching transistors are turned off to set the conversion efficiency to HCG, and the P-phase level and D-phase level are read out sequentially based on the charge accumulated in the first photodiode, the second and fourth switching transistors are turned on, the first, third and eighth switching transistors are turned off to set the conversion efficiency to LCG, and the D-phase level and P-phase level are read out sequentially based on the charge accumulated in the first photodiode and the LOFIC. The imaging apparatus according to claim 17, wherein the second and eighth switching transistors are turned on, the first, third and fourth switching transistors are turned off to set the conversion efficiency to HCG, and the D-phase level and P-phase level are sequentially read out based on the charge accumulated in the second photodiode, and if high illumination is determined, the first and third switching transistors are turned on, the second, fourth and eighth switching transistors are turned off to set the conversion efficiency to MCG (Middle Conversion Gain), and the P-phase level and D-phase level are sequentially read out based on the charge accumulated in the first photodiode, the first to fourth switching transistors are turned on, the eighth switching transistor is turned off to set the conversion efficiency to LCG, and the D-phase level and P-phase level are sequentially read out based on the charge accumulated in the first photodiode and the LOFIC, and the first to third and eighth switching transistors are turned on, the fourth switching transistor is turned off to set the conversion efficiency to LCG, and the D-phase level and P-phase level are sequentially read out based on the charge accumulated in the second photodiode.

19. An imaging device comprising a transistor having a gate electrode on a channel region, wherein the channel region comprises three or more paths that are distinct from each other.

20. The imaging apparatus according to claim 19, wherein the transistor is used as a transfer transistor for transferring the charge accumulated in the photoelectric conversion unit to a floating diffusion, and the gate electrode of the transfer transistor has a plurality of sides through the channel region to which the charge flows to different outflow destinations.

21. The imaging apparatus according to claim 20, wherein the transfer transistor comprises two impurity diffusion layers branched from the channel region to two outflow destinations.

22. The imaging apparatus according to claim 19, wherein the transistor is used as a switching transistor to switch the conversion efficiency of the pixels, and the gate electrode of the switching transistor has a plurality of sides through which charge flows from mutually different sources via the channel region.

23. The imaging apparatus according to claim 22, wherein the switching transistor comprises two impurity diffusion layers that merge into the channel region from two inflow sources.

24. The imaging apparatus according to claim 23, wherein the two impurity diffusion layers are short-circuited within the semiconductor layer on which the two impurity diffusion layers are formed.

25. The imaging apparatus according to claim 23, wherein the two impurity diffusion layers are short-circuited via wiring.

26. The imaging apparatus according to claim 23, wherein the two impurity diffusion layers are not short-circuited.

27. An imaging device comprising: a photoelectric conversion unit provided in a pixel; a floating diffusion to which the charge accumulated in the photoelectric conversion unit is transferred; and a LOFIC to which the charge overflowing from the photoelectric conversion unit is accumulated, wherein the LOFIC comprises vias embedded in a semiconductor substrate and a dielectric layer formed between the semiconductor substrate and the vias, and the vias and the semiconductor substrate are used as counter electrodes of the LOFIC.

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