Da conversion circuit and imaging device

Abstract

The present invention makes it possible to reduce power consumption in a DA conversion circuit that operates at a low voltage and a current-output DA conversion circuit that has a wide output voltage range.　The present invention comprises a current switching cell configured from a current source transistor and two current switching transistors for switching a current supplied by the current source transistor. The current switching cell is characterized by having the gates of the current switching transistors, switches for intermittently supplying a bias voltage to the gates, and a node to which one terminal of each of capacitors is connected, and is characterized in that: a digital signal is applied to the other terminal of each of the capacitors; and an operation in which one of the current switching transistors is turned on and the other is turned off in accordance with the digital signal is performed.

Description

DA conversion circuit and imaging device

[0001] This technology relates to a DA conversion circuit and an imaging device. More specifically, this technology relates to a DA conversion circuit capable of converting a digital signal to an analog signal based on current summation, and an imaging device using the same.

[0002] There are various types of DA conversion circuits commonly used in integrated circuits. For example, there are voltage-output DA conversion circuits composed of multiple resistors connected in series and parallel and one operational amplifier, voltage-output DA conversion circuits based on switched-capacitor operation composed of multiple capacitors and one operational amplifier, and current-output DA conversion circuits (Current-Steering DACs) composed of multiple current sources and current selector switches. Among these, current-output DA conversion circuits are high-speed and highly accurate and are used in the ramp waveform output DA conversion circuits of CMOS image sensors, which will be discussed later. In addition, a voltage output can be obtained by passing the output current of a current-output DA conversion circuit through a reference resistor. Cascode transistors are sometimes used in each current source that makes up a current-output DA conversion circuit to improve PSRR (Power Supply Rejection Ratio), INL (Integral Non-Linearity), and DNL (Differential Non-Linearity). However, using cascode transistors requires a higher power supply voltage and limits the voltage output range, so there are techniques to reduce the voltage by eliminating the cascode transistors. For example, a technology has been disclosed that provides a cascode switch that integrates the functions of a cascode transistor and a current switching switch (see, for example, Patent Documents 1 and 2). This cascode switch functions as a cascode transistor with respect to a current source and simultaneously performs a current switching operation from the current source.

[0003] U.S. Patent Application Publication No. 2011 / 0221620, U.S. Patent No. 7023367

[0004] However, in the above-described conventional technology, when operating a DA converter circuit at high speed, a high-speed current switching operation is required for the cascode switch. In this case, there is a problem that the power consumption of the voltage generation circuit or buffer circuit that applies the cascode voltage to the gate of the cascode switch is large.

[0005] In particular, when the current from the current source switched by the cascode switch is large, the size of the cascode switch is inevitably large, and the parasitic capacitance added to the gate of the cascode switch also becomes large, making it difficult to increase the speed of the DA converter circuit as described later.

[0006] In this case, when current is switched by the cascode switches, it is necessary to cause the voltages at the gates of the two cascode switches to transition at high speed between two voltage levels. To achieve this, a charge balancing function for accelerating charge injection and extraction to / from the parasitic capacitance added to the gate (corresponding to the two charge balancing circuits BAL1 and BAL2 in Fig. 4 of Patent Document 1), and a capacitor as a Charge Reservoir for compensating charge injection and extraction to / from the gate (corresponding to the capacitor C1 in Fig. 4 of Patent Document 1 and the capacitor CL disclosed in Fig. 4 and Fig. 6 of Patent Document 2) are often required.

[0007] In order to cause the voltage at the gate of the cascode switch to transition at high speed between two voltage levels, the area and power consumption of the voltage generation circuit are large. For example, the current consumption of the voltage generation circuits in Patent Document 1 and Patent Document 2 (corresponding to the voltage generation circuit composed of M5 and M4 in Fig. 3 of Patent Document 1 and the common source voltage adjustment circuit 210 in Fig. 4 of Patent Document 2) increases. In addition, since the voltage generation circuit is disposed for each current switching cell, the circuit scale and power consumption of the DA converter circuit increase.

[0008] The present technology has been created in view of such circumstances, and aims to enable low power consumption in a DA converter circuit operating at low voltage and a current-output DA converter circuit having a wide output voltage range.

[0009] This technology was developed to solve the aforementioned problems, and its first aspect is a DA conversion circuit equipped with a current switching cell comprising a current source transistor and two current switching transistors for switching the current supplied by the current source transistor, the current switching cell having a gate of the current switching transistor, a switch that intermittently supplies a bias voltage to the gate, and a node to which one terminal of a capacitor is connected, and a digital signal is applied to the other terminal of the capacitor, and in response to the digital signal, one of the current switching transistors is made conductive and the other is made non-conductive. This results in the DA conversion circuit being able to operate at a low power supply voltage and expand the output voltage range. Furthermore, it results in reduced power consumption and reduced area.

[0010] Furthermore, in the first aspect, the current switching cell may be characterized in that when the switch is opened and a bias voltage is applied to the gate, the current switching transistor conducts and operates as a cascode transistor with respect to the current source transistor, and after the switch is turned off and the charge of the node is held, the digital signal is transitioned to boost or step down the voltage of the gate to a voltage different from the bias voltage, thereby turning off the current switching transistor. The operation as a cascode transistor when conducting has the effect of enabling high-precision DA conversion circuitry.

[0011] Furthermore, in the first aspect, the current switching cell may be provided, characterized in that, before the DA conversion operation, the switch is opened to apply the bias voltage to one terminal of the capacitor, and then the switch is closed to hold the charge at the node, and during the subsequent DA conversion operation, the digital signal controls the voltage at the gate through the capacitor using the charge hold. This allows the voltage at the gate to be controlled based on charge hold and storage. It also results in faster and lower power consumption of the conduction and disconnection operation (switching operation) of the current switching transistor.

[0012] Furthermore, in the first aspect, the capacitor and the switch may be provided with a current switching cell, characterized in that they are provided at the gates of the two current switching transistors, respectively. This provides the effect of enabling boost and buck operations based on charge retention and storage of both gates.

[0013] Furthermore, in the first aspect, the capacitor and the switch may be provided on the gate of one of the two current switching transistors, and a bias voltage may be applied to the gate of the other current switching transistor, thereby providing a current switching cell. This results in the ability to perform boost and buck operations based on charge retention and storage of one gate.

[0014] Furthermore, in the first aspect, the current switching cell may be characterized by performing an operation in which the switch connected to the gate of one current switching transistor conducts and a bias voltage is applied to the gate, while simultaneously disconnecting the switch connected to the gate of the other current switching transistor. This results in the two current switching transistors being configured in a differential configuration, enabling reciprocal switching operations (one conducts and the other disconnects).

[0015] Furthermore, in the first aspect, the power supply voltage of the digital circuit that generates the digital signal may be lower than the power supply voltage of the current switching cell. This results in the digital power supply voltage being smaller than the analog power supply voltage.

[0016] Furthermore, the second aspect is an imaging device comprising a pixel array section in which pixels are arranged in a matrix in the row direction and column direction, an AD conversion section that performs AD (Analog to Digital) conversion of the pixel signal based on the comparison result between the pixel signal read from the pixel and a reference signal, and a DA conversion section that generates the reference signal based on DA (Digital to Analog) conversion of the digital signal, wherein the DA conversion section comprises a current switching cell composed of a current source transistor and two current switching transistors for switching the current supplied by the current source transistor, the current switching cell having a gate of the current switching transistor, a switch that intermittently supplies a bias voltage to the gate, and a node to which one terminal of a capacitor is connected, a digital signal is applied to the other terminal of the capacitor, and in accordance with the digital signal, one of the current switching transistors is made conductive and the other is made non-conductive. This results in reduced power consumption and reduced area, the generation of a reference signal to be compared with the pixel signal, and improvements in PSRR, INL, and DNL.

[0017] This is a block diagram showing an example configuration of a DA conversion circuit according to the first embodiment. This is a diagram showing an example configuration of a current switching cell applied to a DA conversion circuit according to the second embodiment. This is a timing chart showing the waveforms of each part of the current switching cell applied to a DA conversion circuit according to the second embodiment. This is a diagram showing an example configuration of a current switching cell applied to a DA conversion circuit according to the third embodiment. This is a diagram showing an example configuration of a current switching cell applied to a DA conversion circuit according to the fourth embodiment. This is a diagram showing the conduction state of the current switching cell applied to a DA conversion circuit according to the fourth embodiment in comparison with the conduction state of the current switching cell of the second embodiment. This is a diagram showing an example of switch switching during the DA conversion period of a current switching cell applied to a DA conversion circuit according to the fifth embodiment. This is a timing chart showing the waveforms of each part of the current switching cell applied to a DA conversion circuit according to the fifth embodiment. This is a diagram showing an example of switch switching during the DA conversion period of a current switching cell applied to a DA conversion circuit according to the sixth embodiment. This is a timing chart showing the waveforms of each part of the current switching cell applied to a DA conversion circuit according to the sixth embodiment. This is a block diagram showing an example configuration of an imaging device according to the seventh embodiment. This is a block diagram showing an example configuration of a solid-state imaging device according to the seventh embodiment. This figure shows an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the seventh embodiment. This is a block diagram showing an example of the configuration of the AD conversion unit according to the seventh embodiment. This is a timing chart showing an example of the waveforms of each part when reading out the pixel signal according to the seventh embodiment.

[0018] The following describes the embodiments for implementing this technology (hereinafter referred to as embodiments). The description will be in the following order: 1. First embodiment (an example in which a current output type DA conversion circuit is configured using multiple current switching cells that apply a bias voltage to a capacitor and disconnect the bias voltage from the capacitor in accordance with the switching operation of a current switching transistor) 2. Second embodiment (an example in which a switch is provided in the current switching cell that applies a bias voltage to a capacitor and disconnects the bias voltage from the capacitor in accordance with the switching operation of a current switching transistor, and the switch is switched on and off based on a switching signal that sets the bias voltage to the capacitor) 3. Third embodiment (an example in which a switch that disconnects the bias voltage from the capacitor in accordance with the switching operation of the capacitor to which the bias voltage is applied is provided in only one transistor included in the current switching transistor) 4. Fourth embodiment (an example in which a switch is provided in the current switching cell that applies a bias voltage to a capacitor and disconnects the bias voltage from the capacitor in accordance with the switching operation of a current switching transistor, and the switch is switched on and off based on an inversion signal of a digital signal) 5. 5th Embodiment (An example in which a non-overlap period is set between the period during which a bias voltage is applied to a capacitor and the period during which the gate of a current switching transistor is boosted or de-voltaged based on the charge retention and storage of the capacitor, based on the delay operation of a digital signal using an inverter and a NOR circuit) 6. 6th Embodiment (An example in which a non-overlap period is set between the period during which a bias voltage is applied to a capacitor and the period during which the gate of a current switching transistor is boosted or de-voltaged based on the charge retention and storage of the capacitor, based on the delay operation of a digital signal using an inverter and a transistor) 7. 7th Embodiment (An example in which a DA conversion circuit configured using multiple current switching cells that apply a bias voltage to a capacitor and disconnect the bias voltage from the capacitor in accordance with the switching operation of a current switching transistor is applied to an imaging device)

[0019] <1. First Embodiment> Figure 1 is a block diagram showing an example of the configuration of a DA conversion circuit according to the first embodiment.

[0020] In the figure, the DA conversion circuit comprises multiple current switching cells CEL1 to CELn (where n is an integer of 2 or more). Each current switching cell CEL1 to CELn receives a digital input signal DIN1 to DINn. Each current switching cell CEL1 to CELn outputs current ION1 to IONn and IOP1 to IOPn. By connecting the current switching cells CEL1 to CELn in parallel, a current output type n-bit DA conversion circuit can be constructed. In this case, the currents ION1 to IONn are added together and flow through resistor RON to generate output voltage VON. Similarly, the currents IOP1 to IOPn are added together and flow through resistor ROP to generate output voltage VOP. A differential analog voltage VOP-VON can be generated by DA conversion of the digital input signal DIN1 to DINn. The DA conversion circuit may support binary wait codes or thermometer codes.

[0021] Each current switching cell CEL1 to CELn can have the same circuit configuration. Each current switching cell CEL1 to CELn can be manufactured based on a CMOS process. If the DA conversion circuit supports binary waitcode, the size of each current switching cell CEL1 to CELn can be increased in powers of 2. Here, for example, current switching cell CEL1 comprises a current source transistor MP, current switching transistors MSN, MSP, capacitors CN, CP, and switches SWN, SWP.

[0022] The current switching transistors MSN and MSP are switched reciprocally based on the digital input signal DIN1. Here, switching is the operation of outputting a voltage or current input to one input node to one of two output nodes. In switching operation, one transistor conducts, allowing current or voltage to pass, while the other transistor is disconnected, blocking the current or voltage.

[0023] Capacitor CN is connected between nodes EN1 and EN2, and capacitor CP is connected between nodes EP1 and EP2. The gates of current switching transistors MSN and MSP are connected to nodes EN2 and EP2, respectively. The digital control circuit CTRL1 generates two opposing digital signals DN2 and DP2 from the digital input signal DIN1 via inverters DV1 and DV3, and each of these signals is applied to one node of each capacitor CN and CP.

[0024] A constant current is supplied from the drain of the current source transistor MP to the current switching transistors MSN and MSP. When the switches SWN and SWP conduct, they apply a cascode voltage VCASL to the other node of each capacitor CN and CP connected to each node EN2 and EP2, and are interrupted in accordance with the switching operation of the current switching transistors MSN and MSP, disconnecting the cascode voltage VCASL from each capacitor CN and CP. At this time, each capacitor CN and CP retains a charge corresponding to the cascode voltage VCASL. The charge retention operation of each capacitor CN and CP sets the gate of the current switching transistors MSN and MSP to an intermediate voltage between the ground voltage and the power supply voltage, and allows the voltages VN2 and VP2 of each node EN2 and EP2 to be changed in accordance with the digital signals DN2 and DP2. Note that P-channel field-effect transistors can be used for the current switching transistors MSN and MSP and the current source transistor MP.

[0025] The sources of the current switching transistors MSN and MSP are connected to the drains of the current source transistor MP. The source of the current source transistor MP is connected to the high power supply voltage VDD. A bias voltage VF1 is applied to the gate of the current source transistor MP. The low power supply voltage VSS may be the ground voltage, and in the following description, it will be assumed to be 0V. The drain of the current switching transistor MSN is connected to the low power supply voltage VSS via a resistor RON. A resistor RON is connected in series with the drain of the current switching transistor MSN. An analog voltage VON is output from the connection point between the drain of the current switching transistor MSN and the resistor RON. The drain of the current switching transistor MSP is connected to the low power supply voltage VSS via a resistor ROP. A resistor ROP is connected in series with the drain of the current switching transistor MSP. An analog voltage VOP is output from the connection point between the drain of the current switching transistor MSP and the resistor ROP.

[0026] The gate of the current switching transistor MSN is connected to the capacitor CN. Node EN2, which is the connection point between the gate of the current switching transistor MSN and the capacitor CN, is connected to the switch SWN. The gate of the current switching transistor MSP is connected to the capacitor CP. Node EP2, which is the connection point between the gate of the current switching transistor MSP and the capacitor CP, is connected to the switch SWP.

[0027] The cascode voltage VCASL is output via buffer BF and supplied to one node of each switch SWN and SWP. Buffer BF may be placed in each current switching cell CEL1 to CELn, as shown in Figure 1, or a common buffer may be placed outside each current switching cell and its output supplied to one node of each switch SWN and SWP. Alternatively, in Figure 1, the input and output nodes of the buffer BF placed in each current switching cell CEL1 to CELn may be short-circuited and connected in parallel from CEL1 to CELn for sharing. In this case, each switch SWN and SWP can be switched on and off based on a switching signal that applies the cascode voltage VCASL to one end of each capacitor CN and CP.

[0028] During the voltage setting period or DA conversion period described later, switch SWN conducts, supplying VCASL to capacitor CN through node EN2, to which the gates of capacitor CN and current switching transistor MSN are connected, and supplying an L level to the other node of capacitor CN through node EN1. After that, switch SWN is turned off. The same applies to capacitor CP, current switching transistor MSP, switch SWP, and nodes EP2 and EP1.

[0029] The operation of switches SWN and SWP allows the gate voltage of the current switching transistor MSN to be set to the cascode voltage VCASL by setting the voltage at node EN1 to a low level when the current switching transistor MSN conducts during DA conversion. Conversely, when the current switching transistor MSN is disconnected, setting the voltage at node EN1 to a high level boosts the gate voltage of the current switching transistor MSN, setting it to a voltage higher than the cascode voltage VCASL, VCASH. The same applies to the current switching transistor MSP, which operates inversely. This operation allows the current switching transistors MSN and MSP to operate as cascode transistors with respect to the current source transistor MP when they conduct.

[0030] As described above, in the first embodiment, a cascode voltage VCASL is applied to each capacitor CN and CP, and switches SWN and SWP are provided in the current switching cell to disconnect the cascode voltage VCASL from each capacitor CN and CP in accordance with the switching operation of the current switching transistors MSN and MSP. The switches SWN and SWP are switched on and off based on one or both of the digital control signal DIS and the digital input signal DIN1. This allows the gate voltage to be set to the cascode voltage VCASL when the current switching transistors MSN and MSP conduct during DA conversion, and the gate voltage to be boosted to a voltage VCASH that is sufficiently higher than the cascode voltage VCASL when the current switching transistors MSN and MSP are shut off.

[0031] The current switching transistors MSN and MSP perform switching operations for the current supplied from the current source transistor MP, and can also operate as cascode transistors when the current switching transistors MSN and MSP are conducting.

[0032] Furthermore, without requiring a separate cascode transistor for the current source transistor MP, it is possible to achieve high precision (PSRR, INL, DNL, ​​resolution, etc.), low voltage operation, and an expanded output voltage range for the DA conversion circuit. In addition, since the buffer BF performs only static operation, it is possible to reduce the power consumption and area of ​​the buffer BF.

[0033] In Figure 1, an example is shown in which P-channel field-effect transistors are used for the current switching transistors MSN and MSP and the current source transistor MP, but a complementary configuration is also possible. N-channel field-effect transistors are used as the current switching transistors MSN and MSP and the current source transistor MP. In this case, the current source transistor MP is placed on the low power supply voltage VSS side, and the resistors ROP and RON are placed on the high power supply voltage VDD side.

[0034] Figure 1 shows an example of using the differential analog voltage VOP-VON as the analog output of a DA conversion circuit. If only one output of VOP or VON is needed, for example, VOP may be used as the analog output of the DA conversion circuit. In this case, the resistor RON may be removed and the node indicated by the analog voltage VON may be short-circuited to the low power supply voltage VSS.

[0035] Furthermore, to achieve even higher precision, a cascode transistor may be provided between the current switching transistors MSN and MSP and the current source transistor MP. This allows for further improvement of PSRR, INL, and DNL.

[0036] <2. Second Embodiment> In the first embodiment described above, a DA conversion circuit was configured using current switching cells CEL1 to CELn, characterized by intermittently applying a cascode voltage VCASL to nodes EN2, EP2 and capacitors CN, CP by controlling the conduction and disconnection of switches SWN and SWP connected to nodes EN2 and EP2, to which the gates of current switching transistors MSN and MSP and capacitors CN and CP are connected, in accordance with the digital input signal DINn and the digital control signal DIS. In the second embodiment, the digital control signal DIS causes switches SWN and SWP to conduct before the DA conversion operation, and a bias voltage is applied to each capacitor CN and CP (sample operation). Then, SWN and SWP are disconnected to hold the desired charge in nodes EN2, EP2 and each capacitor CN and CP (hold operation), and then the DA conversion operation is performed. During the capacitor voltage setting period before the DA conversion operation, each capacitor CN and CP performs a sample and hold operation of the cascode voltage VCASL, and when the voltage of nodes EN1 and EP1 becomes L level, each capacitor CN and CP is made to hold the desired charge so that nodes EN2 and EP2 of each capacitor CN and CP become the cascode voltage VCASL.

[0037] Figure 2 shows an example of the configuration of a current switching cell applied to a DA conversion circuit according to the second embodiment.

[0038] In the figure, this current switching cell is the case where the digital control circuit CTRL1 of the first embodiment described above is composed of an inverter IV and NOR circuits NRN and NRP. The other configurations of this current switching cell are the same as those of the current switching cell of the first embodiment described above.

[0039] The output of the NOR circuit NRN is applied to capacitor CN. The output of the NOR circuit NRP is applied to capacitor CP. Switches SWN and SWP are switched on and off based on the digital control signal DIS. The digital control signal DIS turns on switches SWN and SWP when a cascode voltage is applied to capacitors CN and CP (capacitor voltage setting period), and turns off switches SWN and SWP when the current switching transistors MSN and MSP are switching (DA conversion period).

[0040] The power supplies for each NOR circuit, NRN and NRP, are connected between the power supply voltage VDDL and the low power supply voltage VSS. The power supply voltage VDDL can be set to a value lower than the high power supply voltage VDD. The NOR circuit NRN receives the digital control signal DIS as input, along with the inverted signal of the digital input signal DIN via inverter IV. The NOR circuit NRP receives the digital control signal DIS and the digital input signal DIN as input.

[0041] The drain of the current switching transistor MSN is connected to the low power supply voltage VSS via resistor RON. In this case, an analog voltage VON is output from the drain of the current switching transistor MSN. The drain of the current switching transistor MSP is connected to the low power supply voltage VSS via resistor ROP. In this case, an analog voltage VOP is output from the drain of the current switching transistor MSP.

[0042] Figure 3 is a timing chart showing the waveforms of each part of the current switching cell applied to the DA conversion circuit according to the second embodiment.

[0043] In the figure, a capacitor voltage setting period T11 and a DA conversion period T12 are provided when the current switching cell is in operation. During the DA conversion period T12, switching periods T13 and T14 are provided in which the current switching transistors MSN and MSP are switched in opposition to each other.

[0044] In the capacitor voltage setting period T11, the digital control signal DIS is set to the H level. At this time, each of the switches SWN and SWP conducts, the cascode voltage VCASL is applied to one end of each of the capacitors CN and CP via the buffer BF, and the voltage VN1 (the voltage at the node EN1) and VP1 (the voltage at the node EP1) at the other end of each of the capacitors CN and CP are fixed to the L level (0 V) via the NOR circuits NRN and NRP respectively. Accordingly, the cascode voltage VCASL is sampled by each of the capacitors CN and CP, and the voltages VN2 and VP2 at the gates of the current switching transistors MSN and MSP are set to the cascode voltage VCASL. At the end of the capacitor voltage setting period T11, the digital control signal DIS changes from the H level to the L level, and the switches SWN and SWP are turned off, whereby charges corresponding to the cascode voltage VCASL are held in each of the capacitors CN and CP.

[0045] In the DA conversion period T12, the digital control signal DIS is fixed to the L level, and each of the switches SWN and SWP is kept in the off state. That is, charges corresponding to the cascode voltage VCASL are held in the two nodes EN2 and EP2 of each of the capacitors CN and CP, respectively.

[0046] In the switching period T13, the digital input signal DIN is set to the L level. At this time, the voltage VN1 at the other end of the capacitor CN is set to the L level via the NOR circuit NRN, and the voltage VP1 at the other end of the capacitor CP is set to the H level via the NOR circuit NRP. Since the voltage VN1 becomes the L level (0 V), the voltage VN2 at the gate of the current switching transistor MSN is set to the cascode voltage VCASL. On the other hand, since the voltage VP1 becomes the H level (VDDL voltage), as will be described later, the voltage VP2 at the gate of the current switching transistor MSP is set to VCASH, which is a voltage higher than the cascode voltage VCASL.

[0047] A voltage VP2 at the gate of the current switching transistor MSP is sufficiently higher than a voltage VN2 at the gate of the current switching transistor MSN, so that the current ITL does not flow through MSP (is cut off) and flows through MSN (is conducted). Further, since the current switching transistor MSN functions as a cascode transistor for the current source transistor MP, fluctuations in the voltage at the drain of the current source transistor MP can be suppressed, and fluctuations in ITL can be suppressed to keep ITL constant.

[0048] Accordingly, the voltage of VOP becomes 0 V, the voltage of VON becomes ITL×ROUT, and a differential output voltage of the current switching cell is obtained as VOP−VON=−(ITL×ROUT). Here, the current ITL represents a drain current output from the current source transistor MP. Further, the resistance value ROUT represents the resistance value of each of the resistors RON and ROP.

[0049] In a switching period T14, the digital input signal DIN is set to an H level. At this time, a voltage VN1 at the other end of the capacitor CN is set to the H level via the NOR circuit NRN, and a voltage VP1 at the other end of the capacitor CP is set to an L level via the NOR circuit NRP. Since the voltage VP1 is at the L level (0 V), the voltage VP2 at the gate of the current switching transistor MSP is set to a cascode voltage VCASL. Since the voltage VN1 is at the H level (VDDL voltage), as described later, VN2, which is the gate voltage of the current switching transistor MSN, is set to VCASH that is higher than the cascode voltage VCASL.

[0050] The gate voltage VN2 of the current switching transistor MSN is sufficiently higher than the gate voltage VP2 of the current switching transistor MSP. As a result, the current ITL does not flow through the current switching transistor MSN (it is blocked) but flows through the current switching transistor MSP (it conducts). Furthermore, since the current switching transistor MSP functions as a cascode transistor with respect to the current source transistor MP, fluctuations in the drain voltage of the current source transistor MP can be suppressed, and fluctuations in ITL can be suppressed and kept constant. Therefore, the voltage of VON becomes 0V, the voltage of VOP becomes ITL × ROUT, and the differential output voltage of the current switching cell is VOP - VON = + (ITL × ROUT).

[0051] Here, during the DA conversion operation of the current switching cell, switches SWN and SWP are shut off, and the output of buffer BF is disconnected from the gates of current switching transistors MSN and MSP. In other words, buffer BF is not involved when the voltages VN2 and VP2 at the gates of current switching transistors MSN and MSP are changed in accordance with the digital input signal DIN. Furthermore, the digital input signal DIN is transmitted to the gates of current switching transistors MSN and MSP through capacitors CN and CP. This allows the voltages VN2 and VP2 at the gates of current switching transistors MSN and MSP to be changed rapidly between two opposing voltages, VCASL and VCASH.

[0052] The buffer BF only needs to have the driving capability (output impedance) to apply the DC voltage cascode voltage VCASL to each capacitor CN and CP during the capacitor voltage setting period T11, which reduces the power consumption of the buffer BF.

[0053] Furthermore, the output current of the current switching cell can be directly controlled using the digital input signal DIN, which operates at a power supply voltage VDDL lower than the high power supply voltage VDD. This eliminates the need for a voltage level conversion circuit for the digital input signal DIN, enabling lower power consumption and a smaller footprint for the current switching cell.

[0054] Furthermore, since the current switching transistors MSN and MSP function as cascode transistors with respect to the current source transistor MP, the output range of the current switching cell can be expanded even under low power supply voltages. Here, the power supply voltage is VDD-VSS, and the output range is the variable voltage range of VON and VOP.

[0055] As described above, in the second embodiment, a cascode voltage VCASL is applied to each capacitor CN and CP, and switches SWN and SWP are provided in the current switching cell to disconnect the cascode voltage VCASL from each capacitor CN and CP in accordance with the switching operation of the current switching transistors MSN and MSP, and the on and off of switches SWN and SWP are switched based on the digital control signal DIS. As a result, when the current switching transistors MSN and MSP conduct during DA conversion operation, the gate voltage can be set to VCASL, and when the current switching transistors MSN and MSP are shut off, the gate voltage can be boosted to VCASH, which is sufficiently higher than VCASL. The current switching transistors MSN and MSP perform switching operations of the current supplied from the current source transistor MP, and can also operate as cascode transistors when the current switching transistors MSN and MSP conduct.

[0056] Furthermore, without requiring a separate cascode transistor for the current source transistor MP, it is possible to achieve high precision (PSRR, INL, DNL, ​​resolution, etc.), low voltage operation, and an expanded output voltage range for the DA conversion circuit. In addition, since the buffer BF performs only static operation, it is possible to reduce the power consumption and area of ​​the buffer BF.

[0057] <3. Third Embodiment> In the second embodiment described above, a cascode voltage VCASL is applied to each capacitor CN and CP, and switches SWN and SWP are provided in the current switching cell to disconnect the bias voltage from each capacitor CN and CP in accordance with the switching operation of the current switching transistors MSN and MSP. In this third embodiment, an example is shown in which a capacitor that holds a charge corresponding to the cascode voltage VCASL and a switch that disconnects the cascode voltage VCASL from the capacitor are provided only in the current switching transistor MSN.

[0058] Figure 4 shows an example of the configuration of a current switching cell applied to a DA conversion circuit according to the third embodiment.

[0059] In the figure, this current switching cell has the switch SWP, capacitor CP, and NOR circuit NRP removed from the current switching cell of the second embodiment described above. The other configurations of this current switching cell are the same as those of the current switching cell of the second embodiment described above.

[0060] A bias voltage VF3 is applied to the gate of the current switching transistor MSP. Capacitor CN samples and holds a voltage corresponding to the cascode voltage VCASL during the capacitor voltage setting period. Based on the cascode voltage VCASL, capacitor CN can set the gate of the current switching transistor MSN to an intermediate voltage between the ground voltage and the power supply voltage.

[0061] As described above, in the third embodiment, a cascode voltage VCASL is applied to the capacitor CN, and a switch SWN is provided in the current switching cell to disconnect the cascode voltage VCASL from the capacitor CN in accordance with the switching operation of the current switching transistors MSN and MSP, and the switch SWN is switched on and off based on the digital control signal DIS. As a result, when the current switching transistor MSN conducts during DA conversion, the gate voltage can be set to the cascode voltage VCASL, and when the current switching transistor MSN is shut off, its gate voltage can be boosted to VCASH, which is sufficiently higher than the cascode voltage VCASL. The current switching transistors MSN and MSP perform switching operations of the current supplied from the current source transistor MP, and can also operate as cascode transistors when the current switching transistors MSN and MSP conduct.

[0062] Furthermore, without requiring a separate cascode transistor for the current source transistor MP, it is possible to achieve high precision (PSRR, INL, DNL, ​​resolution, etc.), low voltage operation, and an expanded output voltage range for the DA conversion circuit. In addition, since the buffer BF performs only static operation, it is possible to reduce the power consumption and area of ​​the buffer BF.

[0063] <4. Fourth Embodiment> In the second embodiment described above, after maintaining an appropriate bias voltage for each capacitor CN and CP during the capacitor voltage setting period, the DA conversion operation is performed during the DA conversion period. In other words, the capacitor voltage setting period and the DA conversion period are arranged separately. To this end, a cascode voltage VCASL is applied to each capacitor CN and CP, and switches SWN and SWP are provided to disconnect the bias voltage from each capacitor CN and CP according to the switching operation of the current switching transistors MSN and MSP, and the on and off of switches SWN and SWP are switched based on the digital control signal DIS. In this fourth embodiment, the DA conversion operation is performed during the DA conversion period, and at the same time, an appropriate cascode voltage VCASL is applied to and maintained for each capacitor CN and CP. To achieve this, a cascode voltage VCASL is applied to each capacitor CN and CP, and switches SWN and SWP are provided to disconnect the cascode voltage VCASL from each capacitor CN and CP in accordance with the switching operation of current switching transistors MSN and MSP. Switches SWN and SWP are switched on and off based on the digital input signal DIN.

[0064] Figure 5 shows an example of the configuration of a current switching cell applied to a DA conversion circuit according to the fourth embodiment.

[0065] In the figure, this current switching cell is the case where the digital control circuit CTRL1 of the first embodiment described above is composed of inverters IVN, IVP, and IV11. The other configurations of this current switching cell are the same as those of the current switching cell of the first embodiment described above.

[0066] One end of each capacitor CN and CP is applied to the forward and inverted signals of the digital input signal DIN, respectively. Switch SWN is switched on and off based on the digital input signal DIN. At this time, the inverted signal of the digital input signal DIN is input to the control node of switch SWN via inverter IVN. Switch SWP is switched on and off based on the digital input signal DIN. At this time, the forward signal of the digital input signal DIN is input to the control node of switch SWP via inverters IV11 and IVP. The sample-and-hold operation of the cascode voltage by each capacitor CN and CP can be performed in synchronization with the digital input signal DIN. At this time, during the DA conversion operation, one of each capacitor CN and CP samples the cascode voltage VCASL, and the other holds the cascode voltage VCASL. For example, when the current switching transistor MSP conducts, a cascode voltage VCASL is applied to its gate, and when the current switching transistor MSP is shut off, its gate is kept in a floating state (charge holding / storage state) and the voltage is boosted to VCASH, which is higher than the cascode voltage VCASL.

[0067] Specifically, when the digital input signal DIN is set to a high level, the voltage VP1 at the other end of the capacitor CP becomes low (power supply voltage VSS), and the switch SWP conducts. At this time, the cascode voltage VCASL is applied to the gate of the current switching transistor MSP via the switch SWP, and the voltage VP2 at the gate of the current switching transistor MSP is set to the cascode voltage VCASL.

[0068] Switch SWN is disconnected, and the charge at node EN2, to which the gate of current switching transistor MSN and capacitor CN are connected, is maintained. The voltage VN1 at the other end of capacitor CN is set to a high level, so the voltage VN2 at the gate of current switching transistor MSN is boosted to a voltage VCASH, which is higher than the cascode voltage VCASL. At this time, the voltage VP2 at the gate of current switching transistor MSP is set to the cascode voltage VCASL, and current switching transistor MSP conducts, allowing the current ITL output from current source transistor MP to flow. Also, current switching transistor MSN is disconnected, and the gate EN2 of current switching transistor MSN is held in a floating state. When the digital input signal DIN is set to a low level, the current switching cell operates in the reverse order of the above operation.

[0069] Here, when the digital input signal DIN is at a high level, the differential output voltage of the current switching cell VOP - VON = +ITL * ROUT, and when the digital input signal DIN is at a low level, the differential output voltage of the current switching cell VOP - VON = -ITL * ROUT, and the current switching cell performs a 1-bit DA conversion operation.

[0070] Here, we will describe the voltage VCASH applied to the gate of the current switching transistor MSN when the voltage VN1 at the other end of capacitor CN transitions from L level to H level, while the switch SWN is closed and the charges of node EN2 and capacitor CN are conserved.

[0071] When switch SWN conducts, the gate voltage VN2 of current switching transistor MSN is set to the cascode voltage VCASL, and the voltage VN1 at the other end of capacitor CN is set to 0V (L level, power supply voltage VSS). When switch SWN is closed, the charge at node EN2, to which the gate of current switching transistor MSN is connected, is conserved. At this time, the following charge conservation equation holds. For simplicity of explanation, the parasitic capacitances of current switching transistor MSN, switch SWN, and current switching transistor MSN are not considered and are ignored. CN・VCASL = CN・(VN2 - VN1) VN2 = VCASL + VN1

[0072] As can be seen from the above equation, when the switch SWN is closed and the charge at node EN2 is conserved, the gate voltage VN2 of the current switching transistor MSN is the sum of the voltage VN1 at the other end of the capacitor CN and the cascode voltage VCASL. Therefore, as shown in the following equation, by transitioning the voltage VN1 at the other end of the capacitor CN from the low level to the high level, the gate voltage VN2 of the current switching transistor MSN can be transitioned from the cascode voltage VCASL to the voltage VCASH. Here, VDDL is the high-level voltage of the logic signal applied to the other end of the capacitor CN. VCASH = VCASL + VDDL

[0073] Figure 6 is a diagram showing the conduction state of a current switching cell applied to a DA conversion circuit according to the fourth embodiment, in comparison with the conduction state of a current switching cell according to the second embodiment.

[0074] In Figures (a) and (b), the current source transistor MP is driven based on current mirror operation with the mirror transistor MC1. That is, the drain-source current supplied from the current source LM1 to the mirror transistor MC1 and the current determined by the size ratio of the mirror transistor MC1 and the current source transistor MP flow between the drain and source of the current source transistor MP. A bias voltage is generated, determined by the drain-source current supplied from the current source LM2 to the mirror transistor MC2 and the transistor size of the cascode bias voltage generating transistor MC2, and this is input to the input node of buffer BF. Buffer BF, receiving this bias voltage, generates a cascode voltage VCASL at its output node, which is intermittently applied to the gates of the current switching transistors MSN and MSP.

[0075] In this configuration, a current source LM1 is connected in series with the mirror transistor MC1. The drain of mirror transistor MC1 is connected to the gate of mirror transistor MC1 and the gate of current source transistor MP. A current source LM2 is connected in series with mirror transistor MC2. The drain of mirror transistor MC2 is connected to the gate of mirror transistor MC2 and the input of buffer BF. Each of the mirror transistors MC1 and MC2 can be a P-channel field-effect transistor.

[0076] Figure (a) shows the state during the AD conversion period T13 in Figure 2 of the second embodiment, where DIN = L. At this time, the output of the NOR circuit NRN is at an L level (VSS voltage 0V), so the voltage at node EN1 of capacitor CN is also 0V. In other words, node EN1 of capacitor CN is equivalent to being connected to the low power supply voltage VSS, so in Figure (a), one node of capacitor CN is connected to the low power supply voltage VSS. Since the digital control signal DIS is held at an L level, switches SWN and SWP are shut off, and nodes EN2 and EP2 are in a floating state (high impedance state). At this time, due to the charge conservation law of node EN2 to which capacitor CN is connected, the voltage VN2 at node EN2 is close to the cascode voltage VCASL. Meanwhile, the voltage at node EP2 is boosted to a voltage close to VCASH, the current switching transistor MSN conducts, the current switching transistor MSP is shut off, and the current from ITL flows to VON via the current switching transistor MSN.

[0077] Figure (b) shows the state during the period when DIN = L in Figure 5 of Embodiment 4. Since node EN1 of CN is equivalent to being connected to VSS, in Figure (b), one node of capacitor CN is connected to VSS. Also, the voltage VN2 of node EN2 becomes the cascode voltage VCASL through buffer BF and conducting SWN, while the voltage VP2 of node EP2 is boosted to a voltage close to VCASH, MSN conducts, MSP is shut off, and the current ITL flows to the output voltage VON via the current switching transistor MSN.

[0078] In the current switching cell of the second embodiment shown in Figure 6(a), it is preferable that the gate voltage VN2 of the current switching transistor MSN is kept constant at the cascode voltage VCASL. A parasitic capacitance CK exists between the gate and drain of the current switching transistor MSN. When the analog voltage VON fluctuates, the gate voltage VN2 of the current switching transistor MSN fluctuates via the parasitic capacitance CK due to the charge conservation law of node EN2 to which the capacitor CN is connected. This fluctuation in the gate voltage VN2 of the current switching transistor MSN is transmitted to the current source transistor MP, causing the drain voltage of the current source transistor MP to fluctuate. As a result, the current ITL output from the current source transistor MP fluctuates depending on the analog voltage VON, and the INL characteristics of the DA conversion circuit deteriorate.

[0079] Furthermore, in the current switching cell of the second embodiment described above, shown in Figure 6(a), when the high power supply voltage VDD fluctuates by ΔVDD relative to the low power supply voltage VSS, the gate voltage VBP of the current source transistor MP also fluctuates by ΔVDD, so the gate-source voltage VGS of the current source transistor MP is kept constant. Since the voltage VN1 at the other end of the capacitor CN is at the L level, the gate voltage VN2 of the current switching transistor MSN becomes a voltage close to the cascode voltage VCASL, but the fluctuation of ΔVDD is not transmitted and remains constant. At this time, the drain voltage of the current source transistor MP to which the source of the current switching transistor MSN is connected also does not fluctuate. Consequently, the drain-source voltage VDS of the current source transistor MP fluctuates by ΔVDD. As a result, the current ITL output from the current source transistor MP fluctuates depending on the output impedance characteristics of the drain of the current source transistor MP, causing the analog voltage VON to fluctuate and the PSSR characteristics to deteriorate.

[0080] In the current switching cell of the fourth embodiment described above, shown in Figure 6(b), the switch SWN and the current switching transistor MSN conduct during AD conversion, while the switch SWP and the current switching transistor MSP are closed. At this time, the gate of the current switching transistor MSN is connected to the output of the buffer BF and fixed at the cascode voltage VCASL. Therefore, even if the analog voltage VON fluctuates, the gate voltage VN2 of the current switching transistor MSN does not fluctuate via the parasitic capacitance CK. Consequently, the gate voltage VN2 of the current switching transistor MSN is maintained at the cascode voltage VCASL regardless of the analog voltage VON, thus avoiding deterioration of the INL characteristics.

[0081] Furthermore, in the current switching cell of the fourth embodiment described above, shown in Figure 6(b), when the high power supply voltage VDD fluctuates by ΔVDD relative to the low power supply voltage VSS, the gate voltage VBP of the current source transistor MP also fluctuates by ΔVDD. At this time, the output of the buffer BF and the gate voltage VN2 of the current switching transistor MSN also fluctuate by ΔVDD, so the drain voltage of the current source transistor MP also fluctuates by ΔVDD. Consequently, since both the source and drain of the current source transistor MP fluctuate by ΔVDD, the drain-source voltage VDS of the current source transistor MP remains constant. As a result, the current ITL output from the current source transistor MP is also kept constant, and deterioration of the PSRR characteristics can be avoided.

[0082] As described above, in the fourth embodiment, a cascode voltage VCASL is applied to each capacitor CN and CP, and switches SWN and SWP are provided in the current switching cell to disconnect the cascode voltage VCASL from each capacitor CN and CP in accordance with the switching operation of the current switching transistors MSN and MSP, and the on and off of switches SWN and SWP are switched based on the digital input signal DIN. As a result, when the current switching transistors MSN and MSP conduct during DA conversion operation, the gate voltage can be set to the cascode voltage VCASL, and when the current switching transistors MSN and MSP are shut off, the gate voltage can be boosted to a voltage VCASH that is sufficiently higher than the cascode voltage VCASL. The current switching transistors MSN and MSP perform switching operations of the current supplied from the current source transistor MP, and can also operate as cascode transistors when the current switching transistors MSN and MSP conduct.

[0083] Furthermore, without requiring a separate cascode transistor for the current source transistor MP, it is possible to achieve high precision (PSRR, INL, DNL, ​​resolution, etc.), low voltage operation, and an expanded output voltage range for the DA conversion circuit. In addition, since the buffer BF performs only static operation, it is possible to reduce the power consumption and area of ​​the buffer BF.

[0084] <5. Fifth Embodiment> In the fourth embodiment described above, during the DA conversion period, the DA conversion operation is performed, and at the same time, an appropriate cascode voltage VCASL is applied to and held on each capacitor CN and CP. To this end, the cascode voltage VCASL is applied to each capacitor CN and CP, and switches SWN and SWP are provided in the current switching cell to disconnect the cascode voltage VCASL from each capacitor CN and CP in accordance with the switching operation of the current switching transistors MSN and MSP, and the switches SWN and SWP are switched on and off based on the digital input signal DIN. In this fifth embodiment, similar to the fourth embodiment, during the DA conversion period, the DA conversion operation is performed, and at the same time, an appropriate cascode voltage VCASL is applied to and held on each capacitor CN and CP. To achieve this, a cascode voltage VCASL is applied to each capacitor CN and CP, and transistors MSN1 and MSP1 are provided to disconnect the cascode voltage VCASL from each capacitor CN and CP according to the switching operation of current switching transistors MSN and MSP, and the on and off states of transistors MSN1 and MSP1 are switched based on the digital input signal DIN. Furthermore, a non-overlap period is set between the period during which the cascode voltage VCASL is applied to each capacitor CN and CP and the period during which VN2 or VP2 is boosted and set to VCASH, based on the delay operation of the digital input signal DIN using an inverter and a NOR circuit.

[0085] Figure 7 shows an example of the configuration of a current switching cell applied to a DA conversion circuit according to the fifth embodiment.

[0086] In the figure, this current switching cell includes inverters IVN1, IVN2, IVP1, IVP2 and NOR circuits NRN, NRP, instead of the inverters IVN, IVP of the fourth embodiment described above. In this current switching cell, transistors MSN1, MSP1 are used as the switches SWN, SWP of the fourth embodiment described above. Each transistor MSN1, MSP1 can be an N-channel field-effect transistor. The other configurations of this current switching cell are the same as those of the current switching cell of the fourth embodiment described above.

[0087] Inverters IVN1 and IVN2 are connected in series. In this configuration, inverters IVN1 and IVN2 act as delay circuits, allowing for a non-overlap period between the application of the cascode voltage VCASL to capacitor CN and the period during which VN2 is boosted and set to VCASH. The preceding inverter IVN1 receives a digital input signal DIN. Capacitor CN receives the output of the subsequent inverter IVN2. The drain and source of transistor MSN1 are connected between the gate of current switching transistor MSN and the output of buffer BF. The gate of transistor MSN1 receives the output of NOR circuit NRN. The NOR circuit NRN receives the digital input signal DIN and node EN1. Node EN3 is provided at the connection point between the gate of transistor MSN1 and NOR circuit NRN. The voltage of node EN3 is set to VN3. Node EP3 is provided at the connection point between the gate of transistor MSP1 and the NOR circuit NRP. The voltage at node EP3 is set to VP3.

[0088] Inverters IVP1 and IVP2 are connected in series. In this configuration, inverters IVP1 and IVP2 act as a delay circuit, allowing a non-overlap period to be set between the period during which the cascode voltage VCASL is applied to capacitor CP and the period during which voltage VP2 is boosted to set voltage VCASH. The inverted signal DINB of the digital input signal DIN is input to the preceding inverter IVP1 via inverter IV11. The output of the subsequent inverter IVP2 is applied to capacitor CP. The drain and source of transistor MSP1 are connected between the gate of current switching transistor MSP and the output of buffer BF. The output of NOR circuit NRP is connected to the gate of transistor MSP1. The inverted signal DINB of the digital input signal DIN and node EP1 are input to NOR circuit NRP.

[0089] Figure 8 is a timing chart showing the voltage waveforms of each part of the current switching cell applied to the DA conversion circuit according to the fifth embodiment.

[0090] In the figure, when the output DINB of inverter IV11 transitions from a high level to a low level (t1), the voltage VP1 at the other end of capacitor CP is delayed by inverters IVP1 and IVP2 before transitioning from a high level to a low level (t2). Subsequently, since the output DINB of inverter IV11 is at a low level, the gate voltage VP3 of transistor MSP1 transitions from a low level to a high level via the NOR circuit NRP after the voltage VP1 at the other end of capacitor CP has transitioned from a high level to a low level (t3).

[0091] On the other hand, when the output DINB of inverter IV11 transitions from L level to H level (t4), the voltage VP1 at the other end of capacitor CP is at L level, so the gate voltage VP3 of transistor MSP1 transitions from H level to L level via the NOR circuit NRP (t5). Subsequently, the voltage VP1 at the other end of capacitor CP is delayed by inverters IVP1 and IVP2 before transitioning from L level to H level (t6). This operation makes it possible to set a non-overlap period in which the H level period of the voltage VP1 at the other end of capacitor CP and the H level period of the gate voltage VP3 of transistor MSP1 do not overlap.

[0092] When the gate voltage VP3 of transistor MSP1 is at a high level, it conducts, and the cascode voltage VCASL is applied to node EP2. On the other hand, when the voltage VP1 at the other end of capacitor CP is at a high level, the gate voltage VP2 of current switching transistor MSP is boosted to voltage VCASH. When voltage VP1 becomes high and the gate voltage VP2 of current switching transistor MSP is boosted, the gate voltage VP3 is held at a low level due to the non-overlap period, MSP1 is shut off, and the charge on the gate of current switching transistor MSP is retained. This non-overlap operation makes it possible to efficiently boost the gate voltage VP2 of current switching transistor MSP to a voltage VCASH that is higher than the cascode voltage VCASL.

[0093] During the period when the voltage VP1 at the other end of capacitor CP is at a low level and the voltage VP3 is at a high level, the gate of current switching transistor MSP is conducted by transistor MSP1 and the cascode voltage VCASL is applied.

[0094] Transistor MSP1 conducts only during the period when the gate voltage VP2 of the current switching transistor MSP is set to the cascode voltage VCASL, and is shut off during the period when it is set to a voltage higher than the cascode voltage VCASL, VCASH. Here, during the transition time of the gate voltage VP2 of the current switching transistor MSP (e.g., t2) and the time when it is boosted to transition to voltage VCASH (e.g., t6), the gate of the current switching transistor MSP and the output of buffer BF are shut off. Similarly, the control of the gate voltage VN2 of the current switching transistor MSN by transistor MSN1 operates in opposition to the gate voltage VP2 of the current switching transistor MSP, as shown in Figure 8 with the digital input signal DIN, voltages VN1 and VN3, and the ON / OFF state of transistor MSN1.

[0095] As described above, in the fifth embodiment, a cascode voltage VCASL is applied to each capacitor CN and CP, and switches SWN and SWP are provided in the current switching cell to disconnect the cascode voltage VCASL from each capacitor CN and CP in accordance with the switching operation of the current switching transistors MSN and MSP, and the on and off of switches SWN and SWP are switched based on the digital input signal DIN. In this embodiment, switch SWN corresponds to transistor MSN1, and switch SWP corresponds to transistor MSP1. As a result, when the current switching transistors MSN and MSP conduct during DA conversion operation, the gate voltage can be set to the cascode voltage VCASL, and when the current switching transistors MSN and MSP are shut off, their gate voltage can be boosted to a voltage VCASH that is sufficiently higher than the cascode voltage VCASL. The current switching transistors MSN and MSP perform switching operations of the current supplied from the current source transistor MP, and can also operate as cascode transistors when the current switching transistors MSN and MSP conduct.

[0096] Furthermore, without requiring a separate cascode transistor for the current source transistor MP, it is possible to improve the precision of the DA conversion circuit (PSRR, INL, DNL, ​​resolution, etc.), enable low-voltage operation, and expand the output voltage range. In addition, since the buffer BF performs only static operation, it is possible to reduce the power consumption and area of ​​the buffer BF.

[0097] Furthermore, by providing a non-overlap period between the period during which the cascode voltage VCASL is applied to each capacitor CN and CP, and the period during which voltages VN2 and VP2 are boosted and set to voltage VCASH, the current switching transistors MSN and MSP can be efficiently boosted to a voltage higher than the cascode voltage VCASL.

[0098] <6. Sixth Embodiment> In the fifth embodiment described above, the non-overlap period between the period during which the cascode voltage VCASL is applied to each capacitor CN and CP and the period during which the voltages VN2 and VP2 are boosted to set to voltage VCASH is set based on the delay operation of the digital input signal DIN using inverters IVN1, IVN2, IVP1, IVP2 and NOR circuits NRN and NRP. In this sixth embodiment, the non-overlap period between the period during which the cascode voltage VCASL is applied to each capacitor CN and CP and the period during which the voltages VN2 and VP2 are boosted to set to voltage VCASH is set based on the delay operation of the digital input signal DIN using inverters and the switch operation consisting of transistors connected in series.

[0099] Figure 9 shows an example of the configuration of a current switching cell applied to a DA conversion circuit according to the sixth embodiment.

[0100] In the figure, this current switching cell includes inverters IVN3 and IVP3 and transistors MSN2 and MSP2, instead of the NOR circuits NRN and NRP of the fifth embodiment described above. Each of the transistors MSN2 and MSP2 can be an N-channel field-effect transistor. The other configurations of this current switching cell are the same as those of the current switching cell of the fifth embodiment described above.

[0101] Transistors MSN1 and MSN2 are connected in series. The series circuit of transistors MSN1 and MSN2 is connected between the gate EN2 of the current switching transistor MSN and the output of buffer BF. The gate EN4 of transistor MSN1 is connected to the connection point of inverters IVN1 and IVN2. The gate EN5 of transistor MSN2 is connected to the other end EN1 of capacitor CN via inverter IVN3.

[0102] Transistors MSP1 and MSP2 are connected in series with each other. The series circuit of transistors MSP1 and MSP2 is connected between the gate EP2 of the current switching transistor MSP and the output of buffer BF. The gate EP4 of transistor MSP1 is connected to the connection point of inverters IVP1 and IVP2. The gate EP5 of transistor MSP2 is connected to the other end EP1 of capacitor CP via inverter IVP3. Node EN4 is provided at the connection point between the gate of transistor MSN1 and inverter IVN1. The voltage of node EN4 is set to VN4. Node EN5 is provided at the connection point between the gate of transistor MSN2 and inverter IVN3. The voltage of node EN5 is set to VN5. Node EP4 is provided at the connection point between the gate of transistor MSP1 and inverter IVP1. The voltage of node EP4 is set to VP4. Node EP5 is provided at the connection point between the gate of transistor MSP2 and inverter IVP3. The voltage at node EP5 is set to VP5.

[0103] Figure 10 is a timing chart showing the voltage waveforms of each part of the current switching cell applied to the DA conversion circuit according to the sixth embodiment.

[0104] In the figure, when the output DINB of inverter IV11 transitions from a high level to a low level (t11), the gate voltage VP4 of transistor MSP1 is delayed by inverter IVP1 before transitioning from a low level to a high level (t12). Also, the voltage VP1 at the other end of capacitor CP is delayed by inverters IVP1 and IVP2 before transitioning from a high level to a low level (t13). Furthermore, the gate voltage VP5 of transistor MSP2 transitions from a low level to a high level after the voltage VP1 at the other end of capacitor CP has transitioned from a high level to a low level, and is delayed by inverter IVP3 (t14).

[0105] On the other hand, when the output DINB of inverter IV11 transitions from L level to H level (t15), the gate voltage VP4 of transistor MSP1 is delayed by inverter IVP1 before transitioning from H level to L level (t16). Also, the voltage VP1 at the other end of capacitor CP is delayed by inverters IVP1 and IVP2 before transitioning from L level to H level (t17). Furthermore, the gate voltage VP5 of transistor MSP2 is delayed by inverter IVP3 after the voltage VP1 at the other end of capacitor CP transitions from L level to H level before transitioning from H level to L level (t18). This operation makes it possible to set a non-overlap period in which the period when voltage VP1 is at H level does not overlap with the period when both voltages VP4 and VP5 are at H level.

[0106] When the gate voltages VP4 of transistor MSP1 and VP5 of transistor MSP2 are both set to a high level, both transistors MSP1 and MSP2 conduct, and the cascode voltage VCASL is applied to capacitor CP. On the other hand, when the other end EP1 of capacitor CP is at a high level, the gate voltage VP2 of current switching transistor MSP is boosted to the cascode voltage VCASH. When voltage VP1 becomes high and the voltage VP2 at node EP2 is boosted, one or both of voltages VP4 and VP5 are held at a low level due to the non-overlap period, one or both of transistors MSP1 or MSP2 are shut off, and the charge on the gate of current switching transistor MSP is retained. This non-overlap operation makes it possible to efficiently boost the voltage VP2 at node EP2.

[0107] When the voltage VP1 at the other end of capacitor CP is at a low level, and voltages VP4 and VP5 are both at a high level, both transistors MSP1 and MSP2 conduct to the gate of current switching transistor MSP, and a cascode voltage VCASL is applied.

[0108] Transistors MSP1 and MSP2 conduct during the period when the gate voltage VP2 of the current switching transistor MSP is set to the cascode voltage VCASL, and at least one of transistors MSP1 and MSP2 is closed during the period when the voltage is boosted to a higher voltage VCASH than the cascode voltage VCASL. Here, the gate of the current switching transistor MSP and the output of buffer BF are closed during the transition time of the gate voltage VP2 of the current switching transistor MSP (e.g., t13) and the transition time when it is boosted to voltage VCASH (e.g., t17). The control of the gate voltage VN2 of the current switching transistor MSN by transistors MSN1 and MSN2 operates in opposition to the gate voltage VP2 of the current switching transistor MSP. In Figure 10, the timing charts for voltages VN1, VN2, etc. are omitted.

[0109] As described above, in the sixth embodiment, a cascode voltage VCASL is applied to each capacitor CN and CP, and switches SWN and SWP are provided in the current switching cell to disconnect the cascode voltage VCASL from each capacitor CN and CP according to the switching operation of the current switching transistors MSN and MSP, and the on and off of switches SWN and SWP are switched based on the digital input signal DIN. In this embodiment, switch SWN corresponds to transistors MSN1 and MSN2 connected in series, and switch SWP corresponds to transistors MSP1 and MSP2 connected in series. As a result, when the current switching transistors MSN and MSP conduct during DA conversion operation, the gate voltage can be set to the cascode voltage VCASL, and when the current switching transistors MSN and MSP are shut off, their gate voltage can be boosted to a voltage VCASH that is sufficiently higher than the cascode voltage VCASL. The current switching transistors MSN and MSP perform switching operations for the current supplied from the current source transistor MP, and can also operate as cascode transistors when the current switching transistors MSN and MSP are conducting.

[0110] Furthermore, without requiring a separate cascode transistor for the current source transistor MP, it is possible to improve the precision of the DA conversion circuit (PSRR, INL, DNL, ​​resolution, etc.), enable low-voltage operation, and expand the output voltage range. In addition, since the buffer BF performs only static operation, it is possible to reduce the power consumption and area of ​​the buffer BF.

[0111] Furthermore, by providing a non-overlap period between the period during which the cascode voltage VCASL is applied to each capacitor CN and CP and the period during which the voltages VN2 and VP2 are boosted and set to the voltage VCASH, the current switching transistors MSN and MSP can be efficiently boosted to a voltage higher than the cascode voltage VCASL. <7. Seventh Embodiment> Figure 11 is a block diagram showing an example of the configuration of an imaging device according to the seventh embodiment.

[0112] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, and operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into a vehicle or drone.

[0113] The optical system 101 directs light from the subject into the solid-state imaging device 102 and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0114] The solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, and outputs the electrical signal digitized. Single-slope AD conversion may be used for the digitization of the electrical signal. Each pixel may be equipped with a single photodiode, or it may be equipped with multiple photodiodes with different sensitivities. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a LOFIC (Lateral Overflow Integration Capacitor) type image sensor.

[0115] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging timing of the solid-state imaging device 102.

[0116] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and grayscale conversion processing. The image processing unit 104 may also include a processor that performs processing based on software.

[0117] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0118] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display or an organic EL (Electro-Luminescence) display.

[0119] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0120] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may be omitted, or conversely, it may have additional functions that are not disclosed.

[0121] Figure 12 is a block diagram showing an example configuration of a solid-state imaging device according to the seventh embodiment.

[0122] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116.

[0123] The pixel array section 111 comprises a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when reading a signal. Each pixel PX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PX row by row when reading a signal from each pixel PX. The vertical signal line VSL transmits the pixel signals read from the pixel PX to the column signal processing unit 114 column by column.

[0124] Each pixel PX may be a single pixel, a shared pixel with two pixels, a shared pixel with four pixels, or a shared pixel with eight pixels. Furthermore, each pixel PX may include an image plane phase-difference pixel. Each pixel PX may support rolling shutter readout or global shutter readout. Each pixel PX may be an HDR (High Dynamic Range) pixel capable of switching conversion efficiency for output. Furthermore, each pixel PX may constitute a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near-infrared (NIR), short-wavelength infrared (SWIR), ultraviolet light, or X-rays, etc.

[0125] The vertical scanning circuit 112 scans the pixels PX to be read out in the column direction. The vertical scanning circuit 112 may include a vertical register. Here, the vertical scanning circuit 112 can drive each pixel PX row by row via the horizontal drive line HSL when reading a signal from each pixel PX.

[0126] The column readout circuit 113 can configure a source follower with each pixel PX when reading a signal from each pixel PX. In this case, the column readout circuit 113 can change the voltage of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0127] The column signal processing unit 114 processes the signals transmitted from each pixel PX in the column direction. For example, the column signal processing unit 114 can perform CDS (Correlated Double Sampling) processing based on the signals transmitted from each pixel PX in the column direction. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted from each pixel PX in the column direction and output an imaging signal Gout. The column signal processing unit 114 includes a column ADC unit 114A.

[0128] The column ADC unit 114A can perform AD conversion processing in parallel for each column. In this case, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF. This AD conversion may be single-slope AD conversion.

[0129] The horizontal scanning circuit 115 scans the pixels PX to be read out in the row direction. The horizontal scanning circuit 115 may also include a horizontal register.

[0130] The control circuit 116 controls the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column reading circuit 113, and the processing timing of the column signal processing unit 114. In this case, the control circuit 116 can coordinate the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

[0131] Figure 13 is a block diagram showing an example of a pixel circuit configuration provided in a solid-state imaging device according to the seventh embodiment.

[0132] In the figure, the pixel PX comprises a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.

[0133] The photodiode PD stores the charge converted by photoelectric conversion. The transfer transistor 122 transfers the charge stored in the photodiode PD to the floating diffusion FD. The reset transistor 123 resets the floating diffusion FD. The amplification transistor 124 outputs a pixel signal based on the voltage of the floating diffusion FD. The selection transistor 125 selects the output of the amplification transistor 124.

[0134] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to the power supply voltage VDD via the reset transistor 123. The power supply voltage VDD is connected to the vertical signal line VSL via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0135] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, the reset signal RST, and the selection signal SEL can be transmitted to each pixel PX via the horizontal drive line HSL shown in Figure 12.

[0136] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. Then, when the selection transistor 125 is turned on, the source voltage of the amplification transistor 124 changes according to the voltage of the floating diffusion FD. The source voltage of the amplification transistor 124 is then applied to the vertical signal line VSL via the selection transistor 125 and transmitted through the vertical signal line VSL. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0137] Figure 14 is a block diagram showing an example configuration of the AD conversion unit according to the seventh embodiment. In this figure, two columns of vertical signal lines VSL1 and VSL2 are shown, but the same method can be applied even if there are more vertical signal lines.

[0138] In the figure, pixels PX1 and PX2 are connected to the respective vertical signal lines VSL1 and VSL2. At this time, the amplification transistors 124 of each pixel PX1 and PX2 are connected to the respective vertical signal lines VSL1 and VSL2 via the selection transistors 125.

[0139] The column readout circuit 113 includes current sources LM1 and LM2. Each current source LM1 and LM2 is provided for each column. Each current source LM1 and LM2 is connected to the vertical signal lines VSL1 and VSL2, respectively. During signal readout, each current source LM1 and LM2 can form a source follower with each pixel PX1 and PX2 via the vertical signal lines VSL1 and VSL2, respectively. Each current source LM1 and LM2 may be a MOS transistor.

[0140] The column ADC section 114A includes comparators CM1 and CM2 and counters CN1 and CN2. Comparators CM1 and CM2 and counters CN1 and CN2 are provided for each column.

[0141] Comparator CM1 compares the pixel signal transmitted via the vertical signal line VSL1 with the reference signal REF. Comparator CM2 compares the pixel signal transmitted via the vertical signal line VSL2 with the reference signal REF.

[0142] Furthermore, an auto-zero signal AZ is input to each of the comparators CM1 and CM2. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. At this time, in comparator CM1, a DC-blocking capacitor CA1 is connected to the non-inverting input node, and a DC-blocking capacitor CB1 is connected to the inverting input node. Similarly, in comparator CM2, a DC-blocking capacitor CA2 is connected to the non-inverting input node, and a DC-blocking capacitor CB2 is connected to the inverting input node.

[0143] In auto-zero operation, the charge stored in each DC-blocking capacitor CA1 and CB1 is controlled so that the non-inverting and inverting inputs of comparator CM1 are balanced. Similarly, in auto-zero operation, the charge stored in each DC-blocking capacitor CA2 and CB2 is controlled so that the non-inverting and inverting inputs of comparator CM2 are balanced.

[0144] Each counter CN1 and CN2 performs a counting operation column by column until the level of the pixel signal read from each pixel PX1 and PX2 matches the level of the ramp wave of the reference signal REF, and holds the digital values ​​D1 and D2 of the pixel signal read from each pixel PX1 and PX2 for each column. At this time, the digitization of the pixel signal read from each pixel PX1 and PX2 can be performed row by row in each comparator CM1 and CM2. The digital values ​​D1 and D2 held in each counter CN1 and CN2 can then be updated row by row.

[0145] During this time, in each comparator CM1 and CM2, the pixel signals read from each pixel PX1 and PX2 are compared column by column with the ramp wave included in the reference signal REF during the AD conversion period provided for each horizontal scanning period. Based on the comparison results in each comparator CM1 and CM2 during that AD conversion period, the digital values ​​D1 and D2 of the pixel signals read from each pixel PX1 and PX2 are stored in each counter CN1 and CN2.

[0146] Furthermore, the column signal processing unit 114 includes a reference voltage generation circuit 114B. The reference voltage generation circuit 114B generates a reference signal REF and supplies it to each comparator CM1 and CM2. The reference voltage generation circuit 114B includes a DA conversion circuit 114C. The DA conversion circuit 114C performs DA conversion on the digital input signal DIN and generates a reference signal REF including a ramp wave. The DA conversion circuit 114C may be configured as in the first embodiment described above. Also, the current switching cell used in the DA conversion circuit 114C may be configured as in any of the second to sixth embodiments described above.

[0147] Figure 15 is a timing chart showing an example of the waveforms of each part during pixel signal readout according to the seventh embodiment. In this figure, an example of the waveform including P-phase readout and D-phase readout within a 1H period (1 horizontal synchronization period) is shown.

[0148] In the figure, the P-phase readout period PRD and the D-phase readout period DRD are set during the 1H period. The P-phase AD conversion period TAP is set during the P-phase readout period PRD. The D-phase AD conversion period TAD is set during the D-phase readout period DRD.

[0149] Here, the reset signal RST rises before the P-phase readout period PRD (t1), the reset transistor 123 turns on, and the floating diffusion FD is reset. Also, the selection signal SEL rises, and the selection transistor 125 turns on.

[0150] Next, the reset signal RST falls (t2), and the reset transistor 123 turns off. At this time, the voltage of the vertical signal line VSL is set based on the source follower operation when the P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0151] Then, during the P-phase AD conversion period TAP, the ramp wave RAP is applied to each comparator CM1 and CM2 as the reference signal REF. In each comparator CM1 and CM2, the voltage of the vertical signal line VSL corresponding to the P-phase level is compared with the ramp wave RAP, and the timing when the level of the ramp wave RAP matches the voltage of the vertical signal line VSL is output as the comparison result CMP. At this time, based on the count operation until the level of the ramp wave RAP matches the voltage of the vertical signal line VSL, the P-phase level read from the pixel PX is AD converted column by column, and the P-phase count value CNP is generated.

[0152] Next, the transfer signal TGL rises before the D-phase readout period DRD (t3), the transfer transistor 122 turns on, and the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. At this time, the voltage of the vertical signal line VSL is set based on the source follower operation when the cathode voltage of the photodiode PD is applied to the gate of the amplification transistor 124.

[0153] Next, when the transfer signal TGL falls (t4), the transfer transistor 122 turns off. At this time, the voltage of the vertical signal line VSL is set based on the source follower operation when the D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0154] Then, during the D-phase AD conversion period TAD, the ramp wave RAD is applied to each comparator CM1 and CM2 as the reference signal REF. In each comparator CM1 and CM2, the voltage of the vertical signal line VSL corresponding to the D-phase level is compared with the ramp wave RAD, and the timing when the level of the ramp wave RAD matches the voltage of the vertical signal line VSL is output as the comparison result CMP. At this time, based on the count operation until the level of the ramp wave RAD matches the voltage of the vertical signal line VSL, the D-phase level read from the pixel PX is AD converted column by column, and the D-phase count value CND is generated.

[0155] The above describes an example of an imaging device to which the technology of this disclosure may be applied. The DA conversion circuits of the above embodiments, which are the technology of this disclosure, can be applied to the DA conversion circuit 114C among the configurations described above.

[0156] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0157] Furthermore, this technology can also take the following configurations: (1) A DA conversion circuit comprising a current switching cell comprising a current source transistor and two current switching transistors for switching the current supplied by the current source transistor, wherein the current switching cell has a gate of the current switching transistor, a switch that intermittently supplies a bias voltage to the gate, and a node to which one terminal of a capacitor is connected, and a digital signal is applied to the other terminal of the capacitor, and in accordance with the digital signal, one of the current switching transistors is made to conduct and the other to be made (3) A DA conversion circuit according to (1), comprising a current switching cell characterized in that the switch is opened before the DA conversion operation to apply the bias voltage to one terminal of the capacitor, then the switch is turned off to hold the charge at the node, and during the subsequent DA conversion operation, the digital signal controls the voltage at the gate through the capacitor by utilizing the charge holding. (4) A DA conversion circuit according to any one of (1) to (3), comprising a current switching cell characterized in that the capacitor and the switch are provided at the gates of the two current switching transistors, respectively. (5) A DA conversion circuit according to any one of (1) to (3), comprising a current switching cell characterized in that the capacitor and the switch are provided at the gate of one of the two current switching transistors, and a bias voltage is applied to the gate of the other current switching transistor.(6) The DA conversion circuit according to (2) or (4), comprising a current switching cell characterized by performing an operation to open the switch connected to the gate of one current switching transistor to apply a bias voltage to the gate, and at the same time, to disconnect the switch connected to the gate of the other current switching transistor. (7) The DA conversion circuit according to any one of (1) to (6), comprising a current switching cell characterized in that the power supply voltage of the digital circuit that generates the digital signal is lower than the power supply voltage of the current switching cell. (8) Imaging apparatus comprising: a pixel array section in which pixels are arranged in a matrix in the row direction and column direction; an AD conversion section that performs AD (Analog to Digital) conversion of the pixel signals based on the comparison result of the pixel signals read from the pixels and a reference signal; and a DA conversion section that generates the reference signal based on DA (Digital to Analog) conversion of the digital signals, wherein the DA conversion section comprises a current switching cell composed of a current source transistor and two current switching transistors for switching the current supplied by the current source transistor, the current switching cell having a gate of the current switching transistor, a switch that intermittently supplies a bias voltage to the gate, and a node to which one terminal of a capacitor is connected, a digital signal is applied to the other terminal of the capacitor, and the current switching cell performs an operation of conducting one of the current switching transistors and blocking the other in accordance with the digital signal.

[0158] CEL1 to CELn: Current switching cell; MP: Current source transistor; MSN, MSP: Current switching transistor; CN, CP: Capacitor; BF: Buffer; SWN, SWP: Switch; IV1 to IV3: Inverter

Claims

1. A DA conversion circuit comprising a current switching cell comprising a current source transistor and two current switching transistors for switching the current supplied by the current source transistor, wherein the current switching cell has a gate for the current switching transistors, a switch for intermittently supplying a bias voltage to the gate, and a node to which one terminal of a capacitor is connected, and a digital signal is applied to the other terminal of the capacitor, and the current switching cell operates by conducting one of the current switching transistors and blocking the other in accordance with the digital signal.

2. The DA conversion circuit according to claim 1, comprising a current switching cell characterized in that when the switch is opened and a bias voltage is applied to the gate, the current switching transistor conducts and operates as a cascode transistor with respect to the current source transistor, and after the switch is turned off and the charge of the node is held, the digital signal is transitioned to boost or step down the voltage of the gate to a voltage different from the bias voltage, thereby turning off the current switching transistor.

3. The DA conversion circuit according to claim 1, comprising a current switching cell characterized in that, before the DA conversion operation, the switch is turned on to apply the bias voltage to one terminal of the capacitor, and then the switch is turned off to hold the charge of the node, and during the subsequent DA conversion operation, the digital signal controls the voltage of the gate through the capacitor by utilizing the charge holding.

4. The DA conversion circuit according to claim 1, comprising a current switching cell characterized in that the capacitor and the switch are provided at the gates of the two current switching transistors, respectively.

5. The DA conversion circuit according to claim 1, comprising a current switching cell characterized in that the capacitor and the switch are provided at the gate of one of the two current switching transistors, and a bias voltage is applied to the gate of the other current switching transistor.

6. The DA conversion circuit according to claim 2, characterized by a current switching cell that conducts the switch connected to the gate of one current switching transistor to apply a bias voltage to the gate, while simultaneously disconnecting the switch connected to the gate of the other current switching transistor.

7. The DA conversion circuit according to claim 1, comprising a current switching cell characterized in that the power supply voltage of the digital circuit that generates the digital signal is lower than the power supply voltage of the current switching cell.

8. An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in the row direction and column direction; an AD conversion section that performs AD (Analog to Digital) conversion of the pixel signals based on the comparison result of the pixel signals read from the pixels and a reference signal; and a DA conversion section that generates the reference signal based on DA (Digital to Analog) conversion of the digital signals, wherein the DA conversion section comprises a current switching cell composed of a current source transistor and two current switching transistors for switching the current supplied by the current source transistor, the current switching cell having a gate of the current switching transistor, a switch that intermittently supplies a bias voltage to the gate, and a node to which one terminal of a capacitor is connected, a digital signal is applied to the other terminal of the capacitor, and the current switching cell operates by conducting one of the current switching transistors and blocking the other in accordance with the digital signal.

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