Imaging device

Abstract

The present invention enables edge detection based on a result of comparing pixel signals, while also enabling detection of the illuminance of the pixel signals.　This imaging device comprises: a plurality of pixels that output pixel signals; and a detection unit that detects an edge in an image on the basis of the result of comparing two pixel signals, and detects the illuminance of the image on the basis of the results of comparing each pixel signal to a reference signal. The imaging device may also comprise a level setting circuit that uses a prescribed gain to set the signal level of at least one of the two pixel signals. The detection unit may also comprise a first comparison unit that compares the two pixel signals, and a second comparison unit that compares each pixel signal to the reference signal.

Description

Imaging apparatus

[0001] The present technology relates to an imaging apparatus. More specifically, the present technology relates to an imaging apparatus capable of edge detection and illuminance detection.

[0002] In an imaging apparatus, edge determination of an image may be performed based on a comparison result of two pixel signals. For example, a technique for determining the presence or absence of an edge based on a comparison result of a pair of pixel signals in which one signal level of the pair of pixel signals is increased or decreased by a predetermined gain is disclosed (see, for example, Patent Document 1).

[0003] International Publication No. 2021 / 090538

[0004] However, although the above-mentioned conventional technology can perform edge detection based on the comparison result of pixel signals, it does not disclose a technology for detecting the illuminance of the pixel signals.

[0005] The present technology has been developed in view of such circumstances, and an object of the present technology is to enable edge detection based on a comparison result of pixel signals, and also enable illuminance detection of the pixel signals.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect of the present technology is an imaging apparatus including: a plurality of pixels that output pixel signals; and a detection unit that detects an edge of an image based on a comparison result of two pixel signals, and detects illuminance of the image based on a comparison result of the pixel signal and a reference signal. This brings about an effect of enabling edge detection based on the comparison result of pixel signals, and also enabling detection of the illuminance of the pixel signals.

[0007] Furthermore, in the first aspect, the imaging apparatus may further include a level setting circuit that sets a signal level of at least one of the two pixel signals by a predetermined gain. This brings about an effect of enabling edge detection even when the magnitude relationship between the two pixel signals is unknown, and also enabling detection of the illuminance of the pixel signals.

[0008] Furthermore, in the first aspect, the detection unit may include a first comparison unit that compares the two pixel signals and a second comparison unit that compares the pixel signal with the reference signal. This results in the parallel execution of edge detection based on the comparison result of the pixel signals and illuminance detection of the pixel signal.

[0009] Furthermore, in the first aspect, the detection unit may include a determination unit that determines the edges of the image based on the comparison result of the two pixel signals, and determines the illuminance of the image based on the comparison result of the pixel signal and the reference signal. This enables edge determination based on the comparison result of the pixel signals, and also enables determination of the illuminance of the pixel signals.

[0010] Furthermore, in the first aspect, a potential fixing circuit may be provided that fixes one of the input potentials of the first comparison unit based on the comparison result between the pixel signal and the reference signal. This results in the comparison result between the pixel signal and the reference signal being output via the first comparison unit.

[0011] Furthermore, in the first aspect, the detection unit may include a comparison unit that receives the two pixel signals and the reference signal as input, compares the two pixel signals, and compares the pixel signals with the reference signal. This allows the two pixel signals to be compared and the pixel signals with the reference signal to be compared using a single comparison unit.

[0012] Furthermore, in the first aspect, the reference signal may include at least one of a threshold signal, a step signal, and a ramp wave. This results in a change in the illuminance resolution of the pixel signal based on the switching of the reference signal.

[0013] Furthermore, the first aspect may include a holding unit for holding the detection results from the detection unit. This ensures that edge detection based on the comparison results of the pixel signals and illuminance detection of the pixel signals are performed without losing the detection results from the detection unit.

[0014] Furthermore, in the first aspect, a combination circuit may be provided that combines the comparison result of the two pixel signals and the comparison result of the pixel signals with the reference signal. This has the effect of reducing the amount of data required to store the comparison result of the two pixel signals and the comparison result of the pixel signals with the reference signal.

[0015] Furthermore, in the first aspect, the detection unit may multi-levelize the illuminance of the pixel signal within the edge detection area. This has the effect of reducing the amount of data required to maintain the illuminance of the pixel signal outside the edge detection area.

[0016] Furthermore, in the first aspect, the detection unit may multi-levelize the illuminance of the pixel signal outside the edge detection area. This has the effect of reducing the amount of data required to maintain the illuminance of the pixel signal within the edge detection area.

[0017] Furthermore, in the first aspect, the detection unit may output the detection result of the illuminance of the pixel signal without detecting the edge when the illuminance of the pixel signal is above a threshold. This improves the accuracy of edge detection while still allowing the illuminance of the pixel signal to be detected.

[0018] Furthermore, in the first aspect, the detection unit may include an amplitude detection unit that detects the amplitude of the pixel signal based on the pixel signal and the reference signal. This results in the detection result of the amplitude of the pixel signal being obtained as a comparison result between the pixel signal and the reference signal.

[0019] Furthermore, in the first aspect, the amplitude detection unit may include a source follower transistor that takes the reference signal as the gate input and the pixel signal as the source input. This allows the comparison result between the pixel signal and the reference signal to be obtained by using a single source follower transistor.

[0020] Furthermore, in the first aspect, a voltage generation unit connected to the drain of the source follower transistor may be provided. This results in the generation of a power supply for the source follower transistor.

[0021] Furthermore, in the first aspect, the system may include a current source that constitutes a source follower with the pixel via a transmission line through which the pixel signal is transmitted, and the source follower transistor may constitute a source follower with the current source. This results in the current source constituting the source follower being shared by the pixel and the source follower transistor.

[0022] Furthermore, in the first aspect, the source follower transistor may also be used as a dummy source follower transistor connected to the transmission line. This eliminates the need to provide a separate dummy source follower transistor in addition to the source follower transistor.

[0023] Furthermore, in the first aspect, when the source follower transistor is used as the dummy source follower transistor, a switching transistor may be provided to disconnect the source follower transistor from the power supply. This provides the effect of ensuring that the source follower transistor can be used as both a source follower and a dummy source follower transistor while still functioning as a source follower transistor.

[0024] Furthermore, in the first aspect, the system may include a positive feedback unit that sets the potential of the detected amplitude of the pixel signal based on the positive feedback of the detection result of the amplitude of the pixel signal, and an amplitude control unit that blocks the detection of the amplitude of the pixel signal based on the setting of the potential of the detected amplitude of the pixel signal. This results in the source follower transistor being disconnected from the transmission line through which the pixel signal is transmitted after the amplitude of the pixel signal has been detected.

[0025] This is a block diagram showing an example configuration of an imaging device according to the first embodiment. This is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment. This is a diagram showing an example of a pixel circuit configuration provided in a solid-state imaging device according to the first embodiment. This is a cross-sectional view showing an example configuration of a pixel array section provided in a solid-state imaging device according to the first embodiment. This is a cross-sectional view showing a modified example of a pixel array section provided in a solid-state imaging device according to the first embodiment. This is a block diagram showing an example configuration of a signal readout circuit according to the first embodiment. This is a diagram showing a first example of data assignment according to edge and level determination results according to the first embodiment. This is a diagram showing a first example of edge and level determination results according to the output of a comparison unit according to the first embodiment. This is a diagram showing a second example of data assignment according to edge and level determination results according to the first embodiment. This is a diagram showing a second example of edge and level determination results according to the output of a comparison unit according to the first embodiment. This is a diagram showing a third example of data assignment according to edge and level determination results according to the first embodiment. This is a diagram showing a third example of edge and level determination results according to the output of a comparison unit according to the first embodiment. This is a diagram showing a fourth example of data assignment according to edge and level determination results according to the first embodiment. This is a diagram showing a fourth example of edge and level determination results according to the output of a comparison unit according to the first embodiment. This figure shows a fifth example of data assignment according to edge and level determination results according to the first embodiment. This figure shows a fifth example of edge and level determination results according to the output of the comparison unit according to the first embodiment. This is a block diagram showing an example of the configuration of a signal readout circuit according to the second embodiment. This is a block diagram showing an example of the configuration of a signal readout circuit according to the third embodiment. This figure shows an example of the configuration of a potential fixing circuit according to the third embodiment. This figure shows an example of the output of a combination circuit according to the third embodiment. This figure shows an example of the output of a potential fixing circuit according to the third embodiment. This figure shows an example of the output of a determination circuit according to the third embodiment. This figure shows an example of the configuration of a comparison circuit according to the fourth embodiment. This figure shows an example of the configuration of a voltage generation unit according to the fourth embodiment. This is a timing chart showing the waveforms of each part during the operation of the comparator according to the fourth embodiment.This is a block diagram showing an example configuration of a signal readout circuit according to the fifth embodiment. This is a timing chart showing the waveforms of each part during operation of the signal readout circuit according to the fifth embodiment. This is a diagram showing an example configuration of an amplitude detection unit according to the sixth embodiment. This is a timing chart showing the waveforms of each part during operation of the signal readout circuit according to the sixth embodiment. This is a diagram showing an example of data assignment according to edge and level judgment results according to the sixth embodiment. This is a flowchart showing an accumulation time control method based on level judgment results according to the seventh embodiment. This is a block diagram showing an example configuration of a signal readout circuit according to the eighth embodiment. This is a diagram showing the waveform of the reference signal of the signal readout circuit according to the eighth embodiment. This is a diagram showing an example of data assignment according to edge and level judgment results according to the eighth embodiment. This is a diagram showing an example configuration of a comparator according to the eighth embodiment. This is a timing chart showing a first example of the waveforms of each part during operation of the signal readout circuit according to the eighth embodiment. This is a diagram showing a first example of the signal levels of each part during operation of the signal readout circuit according to the eighth embodiment. This is a timing chart showing a second example of the waveforms of each part during operation of the signal readout circuit according to the eighth embodiment. This is a diagram showing a second example of the signal levels of each part during operation of the signal readout circuit according to the eighth embodiment. This is a timing chart showing a third example of the waveforms of each part during operation of the signal readout circuit according to the eighth embodiment. This is a diagram showing a third example of the signal levels of each part during operation of the signal readout circuit according to the eighth embodiment. This is a block diagram showing an example of the configuration of the signal readout circuit according to the ninth embodiment. This is a diagram showing an example of the configuration of the comparator according to the ninth embodiment. This is a timing chart showing an example of the waveforms of each part during operation of the signal readout circuit according to the ninth embodiment. This is a timing chart showing an example of the waveforms of each part during pipeline operation of the signal readout circuit according to the ninth embodiment. This is a perspective view showing an example of the configuration of the imaging device according to the tenth embodiment. This is a block diagram showing a schematic example of the configuration of the vehicle control system. This is an explanatory diagram showing an example of the installation position of the imaging unit.

[0026] The following describes the embodiments for implementing this technology (hereinafter referred to as embodiments). The description will proceed in the following order. 1. First Embodiment (An example in which image edges are detected based on the comparison result of two pixel signals, and image illuminance is detected based on the comparison result of the pixel signal and a reference signal, and data corresponding to the edge and level determination results is assigned by a combinational circuit) 2. Second Embodiment (An example in which image edges are detected based on the comparison result of two pixel signals, and image illuminance is detected based on the comparison result of the pixel signal and a reference signal, and the edge and level determination results are retained) 3. Third Embodiment (An example in which image edges are detected based on the comparison result of two pixel signals, and image illuminance is detected based on the comparison result of the pixel signal and a reference signal, and one input potential of a comparator is fixed based on the comparison result of the pixel signal and a reference signal) 4. Fourth Embodiment (An example in which the amplitude of a pixel signal is detected based on the pixel signal and a reference signal) 5. Fifth Embodiment (An example in which the detection result of the illuminance of a pixel signal is multi-leveled based on the potential fluctuation of the gate input of a source follower transistor) 6. 7. Seventh Embodiment (Example of multi-leveling the illuminance detection result of a pixel signal based on the switching of a source follower transistor) 8. Eighth Embodiment (Example of controlling the storage time based on the level determination result) 9. Ninth Embodiment (Example of comparing two pixel signals and comparing the pixel signal with a reference signal using a three-input comparator) 10. Ninth Embodiment (Example of comparing two pixel signals and comparing the pixel signal with a reference signal using a four-input comparator) 11. Tenth Embodiment (Example of stacking pixel array sections) 12. Application examples to mobile devices

[0027] <1. First Embodiment> Figure 1 is a block diagram showing an example of the configuration of an imaging device according to the first embodiment.

[0028] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, and operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into a vehicle or drone.

[0029] The optical system 101 directs light from the subject into the solid-state imaging device 102 and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0030] The solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, and outputs the electrical signal digitized. At this time, the solid-state imaging device 102 can detect the edges of the image based on the comparison result of two pixel signals, and can also detect the illuminance of the image based on the comparison result of the pixel signal and a reference signal. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.

[0031] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging timing of the solid-state imaging device 102.

[0032] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and grayscale conversion processing. The image processing unit 104 may also include a processor that performs processing based on software.

[0033] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0034] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display, an organic EL (Electro Luminescence) display, or a micro LED display.

[0035] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0036] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may be omitted, or conversely, it may have additional functions that are not disclosed.

[0037] Figure 2 is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment.

[0038] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116.

[0039] The pixel array section 111 comprises a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when reading a signal. Each pixel PX is connected to a horizontal drive line HCL for each row and to a vertical signal line VSL for each column. The horizontal drive line HCL drives each pixel PX row by row when reading a signal from each pixel PX. The vertical signal line VSL transmits the pixel signals read from the pixel PX to the column signal processing unit 114 column by column.

[0040] Each pixel PX may be a single pixel, a shared pixel with two pixels, a shared pixel with four pixels, or a shared pixel with eight pixels. Furthermore, the pixel PX may form a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near-infrared (NIR), short-wavelength infrared (SWIR), ultraviolet light, or X-rays, etc.

[0041] The vertical scanning circuit 112 scans the pixels PX to be read out in the column direction. The vertical scanning circuit 112 may include a vertical register. Here, the vertical scanning circuit 112 can drive each pixel PX row by row via the horizontal drive line HCL when reading a signal from each pixel PX.

[0042] The column readout circuit 113 can configure a source follower with each pixel PX when reading a signal from each pixel PX. In this case, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0043] The column signal processing unit 114 processes a signal transmitted in the column direction from each pixel PX. At this time, the column signal processing unit 114 detects an edge of an image based on a comparison result of two pixel signals transmitted in the column direction from each pixel PX, and detects illuminance of the image based on a comparison result between the pixel signal and a reference signal REF. Further, the column signal processing unit 114 can perform CDS (Correlated Double Sampling) processing based on a signal transmitted in the column direction from each pixel PX. Further, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on a signal transmitted in the column direction from each pixel PX, and output an imaging signal Gout. The imaging signal Gout can include an edge image and a luminance image. In the luminance image, the illuminance of the pixel signal may be multi-valued. At this time, data may be allocated to the imaging signal Gout according to the edge and level determination result. For example, 2 bits may be allocated to a directional edge and binary illuminance, or 1.5 bits may be allocated to a non-directional edge and binary illuminance. The column signal processing unit 114 includes a column ADC unit 114A.

[0044] The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on a comparison result between the pixel signal read from the pixel PX and the reference signal REF. This AD conversion may be single-slope AD conversion.

[0045] The horizontal scanning circuit 115 scans pixels PX to be read in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0046] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. In this case, the control circuit 116 can cause the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 to cooperate with each other such that an accumulation operation, a shutter operation, and a read operation are performed for each row in each frame.

[0047] FIG. 3 is a diagram showing a circuit configuration example of a pixel provided in the solid-state imaging device according to the first embodiment.

[0048] In the drawing, the pixel PX includes a photodiode PD, a transfer transistor TG, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. MOS transistors can be used as the transfer transistor TG, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.

[0049] The photodiode PD accumulates photoelectrically converted charge. The transfer transistor TG transfers the charge accumulated in the photodiode PD to the floating diffusion FD. The reset transistor 123 resets the floating diffusion FD. The amplification transistor 124 outputs a pixel signal based on the potential of the floating diffusion FD. The selection transistor 125 selects the output of the amplification transistor 124.

[0050] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor TG. The floating diffusion FD is connected to the power supply potential VDD via the reset transistor 123. The power supply potential VDD is connected to the vertical signal line 132 via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0051] A transfer signal TRG is applied to the gate of the transfer transistor TG. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TRG, the reset signal RST, and the selection signal SEL can be transmitted row by row to the pixel PX via the horizontal drive line HCL shown in Figure 2.

[0052] Figure 4 is a cross-sectional view showing an example of the configuration of a pixel array section provided in a solid-state imaging device according to the first embodiment. Figure 4 shows an example of a surface-illuminated solid-state imaging device. Furthermore, Figure 4 shows an example of a configuration for three pixels.

[0053] In the figure, a photodiode 232 is formed on the semiconductor substrate 231 for each pixel PX. The material of the semiconductor substrate 231 may be Si, InGaAs, or InP.

[0054] A gate electrode 214 and a wiring layer 210 are formed on the semiconductor substrate 231. The gate electrode 214 is formed on the semiconductor substrate 231 via a gate insulating film 213. A sidewall 215 is formed on the side wall of the gate electrode 214. The material of the gate electrode 214 can be, for example, polycrystalline silicon with impurities introduced. The material of the gate insulating film 213 can be, for example, a silicon oxide film. The material of the sidewall 215 can be, for example, a silicon oxide film or a silicon nitride film.

[0055] The gate electrode 214 can be used in a pixel transistor. The pixel transistor includes a transfer transistor TG, a reset transistor 123, an amplification transistor 124, and a selection transistor 125, as shown in Figure 3.

[0056] A wiring 216 is formed on the gate electrode 214. Figure 4 shows an example of a three-layer wiring. In this case, the wiring 216 is provided with an aperture OP1 that allows light to enter the photodiode 232. The gate electrode 214 and the wiring 216 are insulated via an insulating layer 217. The insulating layer 217 can be, for example, a silicon oxide film. The material of the wiring 216 can be, for example, a metal such as Al or Cu.

[0057] A color filter 218 is formed on the wiring layer 210 for each pixel PX. A microlens 219 is formed on the color filter 218 for each pixel PX. The material for the color filter 218 and microlens 219 can be, for example, a transparent resin such as acrylic or polycarbonate. Pigments may be added to the color filter 218 for coloring. The color filter 218 can be configured, for example, in a Bayer array.

[0058] Figure 5 is a cross-sectional view showing a modified pixel array portion of a solid-state imaging device according to the first embodiment. Figure 5 shows an example of a back-illuminated solid-state imaging device. Furthermore, Figure 5 shows an example configuration for three pixels.

[0059] In the figure, a photodiode 222 is formed in the semiconductor layer 221 for each pixel PX. The material of the semiconductor layer 221 may be Si, InGaAs, or InP. The semiconductor layer 221 can be formed, for example, by thinning a semiconductor substrate with the photodiode 222 formed on the front side from the back side.

[0060] A gate electrode 224 and a wiring layer 220 are formed on the semiconductor layer 221. The gate electrode 224 is formed on the semiconductor layer 221 via a gate insulating film 223. A sidewall 225 is formed on the side wall of the gate electrode 224.

[0061] The gate electrode 224 can be used in a pixel transistor. The pixel transistor includes a transfer transistor TG, a reset transistor 123, an amplification transistor 124, and a selection transistor 125, as shown in Figure 3.

[0062] A wiring 226 is formed on the gate electrode 224. Figure 5 shows an example of a three-layer wiring. The gate electrode 224 and the wiring 226 are insulated via an insulating layer 227. The semiconductor layer 221 is supported on a support substrate 230 via the insulating layer 227. The support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.

[0063] A color filter 228 is formed on the back side of the semiconductor layer 221 for each pixel PX. A microlens 229 is formed on the color filter 228 for each pixel PX. The color filter 228 can be configured, for example, in a Bayer array.

[0064] Figure 6 is a block diagram showing an example configuration of a signal readout circuit according to the first embodiment. In this figure, two columns of vertical signal lines VSL1 and VSL2 are shown, but there may be more vertical signal lines.

[0065] In the figure, pixels PX1 and PX2 are connected to vertical signal lines VSL1 and VSL2, respectively. Current sources GA1 and GA2 are also connected to vertical signal lines VSL1 and VSL2, respectively. Each current source GA1 and GA2 can form a source follower with each pixel PX1 and PX2. In this case, each pixel PX1 and PX2 can output pixel signals SG1 and SG2 via vertical signal lines VSL1 and VSL2, respectively.

[0066] The signal readout circuit includes a detection unit that detects image edges based on the comparison result of two pixel signals SG1 and SG2, and also detects the illuminance of the image based on the comparison result of each pixel signal SG1 and SG2 with a reference signal. In the following embodiment, an example is shown in which a threshold voltage VT is used as the reference signal. This detection unit includes comparators CP1 and CP2 and threshold comparison units CT1 and CT2.

[0067] Both comparators CP1 and CP2 are connected to vertical signal lines VSL1 and VSL2, respectively. A level setting unit LKB may be connected prior to comparators CP1 and CP2.

[0068] The level setting unit LKB sets the signal level of at least one of the two pixel signals by a predetermined gain. The level setting unit LKB includes level setting circuits LA1, LB1, LA2, LB2 and variable capacitors CA1, CB1, CA2, CB2.

[0069] Level setting circuit LA1 sets the signal level of the non-inverting input of comparator CP1 by a predetermined gain. In this case, level setting circuit LA1 can set the signal level of the non-inverting input of comparator CP1 by a predetermined gain based on the set value of variable capacitor CA1. Level setting circuit LB1 sets the signal level of the inverting input of comparator CP1 by a predetermined gain. In this case, level setting circuit LB1 can set the signal level of the inverting input of comparator CP1 by a predetermined gain based on the set value of variable capacitor CB1. Level setting circuit LA2 sets the signal level of the non-inverting input of comparator CP2 by a predetermined gain. In this case, level setting circuit LA2 can set the signal level of the non-inverting input of comparator CP2 by a predetermined gain based on the set value of variable capacitor CA2. Level setting circuit LB2 sets the signal level of the inverting input of comparator CP2 by a predetermined gain. In this case, the level setting circuit LB2 can set the signal level of the inverting input of the comparator CP2 by a predetermined gain based on the set value of the variable capacitor CB2. For example, the level setting circuits LA1 and LA2 may be set to a gain of G (where G is a value of 1 or less), and the level setting circuits LB1 and LB2 may be set to a gain of 1.

[0070] Vertical signal line VSL1 is connected to the inverting input of comparator CP1 via level setting circuit LB1 and variable capacitor CB1. Vertical signal line VSL1 is also connected to the non-inverting input of comparator CP2 via level setting circuit LA2 and variable capacitor CA2. Vertical signal line VSL2 is connected to the non-inverting input of comparator CP1 via level setting circuit LA1 and variable capacitor CA1. Vertical signal line VSL2 is also connected to the inverting input of comparator CP2 via level setting circuit LB2 and variable capacitor CB2. At this time, G*SG2 is applied to the non-inverting input of comparator CP1. SG1 is applied to the inverting input of comparator CP1. G*SG1 is applied to the non-inverting input of comparator CP2. SG2 is applied to the inverting input of comparator CP2.

[0071] Each comparator, CP1 and CP2, detects the difference in the comparator inputs. If the difference in the comparator inputs exceeds a threshold value after each comparator, CP1 and CP2, an edge can be determined to exist.

[0072] An auto-zero signal AZ is input to each comparator CP1 and CP2. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. In auto-zero operation, a charge that balances the non-inverting and inverting inputs of each comparator CP1 and CP2 can be accumulated in the input capacitances of each comparator CP1 and CP2, respectively.

[0073] The threshold comparison unit CT1 compares the pixel signal SG1 read from pixel PX1 with the threshold voltage VT and outputs its output FG1 to the combination circuit BN1. Each threshold comparison unit CT2 compares the pixel signal SG2 read from pixel PX2 with the threshold voltage VT and outputs its output FG2 to the combination circuit BN1. The comparison operations of each threshold comparison unit CT1 and CT2, and the comparison operations of each comparator CP1 and CP2 may be parallelized.

[0074] The combinational circuit BN1 combines the comparison results of the two pixel signals SG1 and SG2 and the comparison results of each pixel signal SG1 and SG2 with the threshold voltage VT. In this case, the combinational circuit BN1 may, for example, assign two bits to the directional edge and the binary illuminance in the two pixel signals SG1 and SG2.

[0075] The holding unit H1 holds the combination of the comparison result from the threshold comparison unit CT1 and the comparison result from the comparator CP1. The holding unit H2 holds the combination of the comparison result from the threshold comparison unit CT2 and the comparison result from the comparator CP2.

[0076] The determination circuit HX1 determines the edge and illuminance based on the comparison result of two pixel signals SG1 and SG2, and the combination of the comparison result of each pixel signal SG1 and SG2 with the threshold voltage VT.

[0077] The following describes the 2-bit assignment method for the comparison results of the two pixel signals SG1 and SG2, and the combination of the comparison results of each pixel signal SG1 and SG2 with the threshold voltage VT.

[0078] Figure 7 shows a first example of data allocation according to edge and level determination results according to the first embodiment.

[0079] In the figure, if the pixel signals SG1 and SG2 are below the threshold voltage VT, they are determined to be low level (LL). If the pixel signals SG1 and SG2 are equal to or greater than the threshold voltage VT, they are determined to be high level (HL). In the edge detection region RE1, low-level edges are assigned [1,0] and [0,1] respectively, depending on the direction. Also in the edge detection region RE1, high-level edges are assigned [0,0]. Outside the edge detection region, [1,1] is assigned.

[0080] Figure 8 shows a first example of edge and level determination results according to the output of the comparison unit according to the first embodiment.

[0081] In the figure, at [1,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 are 1 and 1, and the outputs OUT1 and OUT2 of the combinational circuit BN1 are 1 and 1. At this time, the edge detection result is 0. Also, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are undefined, and the level detection result is undefined. As a result, the detection result is no edge.

[0082] In [1,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 1 and 0, respectively, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become undefined and 0, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 1 and 0. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is left edge present LL.

[0083] At [0,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 are 1 and 0, respectively, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are undefined and 1, respectively, and the outputs OUT1 and OUT2 of the combinational circuit BN1 are 0 and 0. At this time, the edge detection result is 1, and the level detection result is high level. As a result, the detection result is edge present (HL).

[0084] Furthermore, at [0,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 0 and 1, respectively, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become 1 and undefined, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 0 and 0. At this time, the edge detection result becomes 1, and the level detection result becomes high level. As a result, the detection result is edge present (HL).

[0085] At [0,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 0 and 1, respectively, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become 0 and undefined, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 0 and 1. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is LL with a right edge.

[0086] Figure 9 shows a second example of data allocation according to edge and level determination results according to the first embodiment.

[0087] In the figure, if the pixel signals SG1 and SG2 are below the threshold voltage VT, they are determined to be low level LL. If the pixel signals SG1 and SG2 are above the threshold voltage VT, they are determined to be high level HL. In the edge detection region RE1, high-level edges are assigned [1,0] and [0,1] respectively, depending on the direction. Also in the edge detection region RE1, low-level edges are assigned [0,0]. Outside the edge detection region, [1,1] is assigned.

[0088] Figure 10 shows a second example of edge and level determination results corresponding to the output of the comparison unit according to the first embodiment.

[0089] In the figure, at [1,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 are 1 and 1, and the outputs OUT1 and OUT2 of the combinational circuit BN1 are 1 and 1. At this time, the edge detection result is 0. Also, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are undefined, and the level detection result is undefined. As a result, the detection result is no edge.

[0090] In [1,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 are 1 and 0, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are undefined and 0, and the outputs OUT1 and OUT2 of the combinational circuit BN1 are 1 and 0. At this time, the edge detection result is 1, and the level detection result is high level. As a result, the detection result is left edge present HL.

[0091] At [0,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 are 1 and 0, respectively, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are undefined and 1, respectively, and the outputs OUT1 and OUT2 of the combinational circuit BN1 are 0 and 0. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is edge present LL.

[0092] Furthermore, at [0,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 0 and 1, respectively, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become 1 and undefined, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 0 and 0. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is edge present LL.

[0093] At [0,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 0 and 1, respectively, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become 0 and undefined, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 0 and 1. At this time, the edge detection result becomes 1, and the level detection result becomes high level. As a result, the detection result is HL with a right edge.

[0094] Figure 11 shows a third example of data allocation according to edge and level determination results according to the first embodiment.

[0095] In the figure, the edge detection region RE2 is set when the pixel signals SG1 and SG2 are less than the threshold voltage VT. In the edge detection region RE2, [1,0] and [0,1] are assigned to the presence of an edge, depending on the direction. Outside the edge detection region, [1,1] is assigned when the pixel signals SG1 and SG2 are less than the threshold voltage VT, and [0,0] is assigned when the pixel signals SG1 and SG2 are greater than or equal to the threshold voltage VT.

[0096] Figure 12 shows a third example of edge and level determination results corresponding to the output of the comparison unit according to the first embodiment.

[0097] In the figure, at [1,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 are 1 and 1, and the outputs OUT1 and OUT2 of the combinational circuit BN1 are 1 and 1. At this time, the edge detection result is 0. Also, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are 1 and 1, and the level detection result is undefined. As a result, the detection result is no edge.

[0098] In [1,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 1 and 0, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become 1 and 1, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 1 and 1. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is left edge present LL.

[0099] At [0,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 0 and 1, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become 1 and 1, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 0 and 0. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is LL with a right edge.

[0100] At [0,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 are undefined, undefined; the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are 0 and undefined; and the outputs OUT1 and OUT2 of the combinational circuit BN1 are 0 and 0. At this time, the edge determination result is undefined, and the level determination result is high level. As a result, the detection result is HL.

[0101] Furthermore, at [0,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 become undefined, undefined; the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become undefined and 0; and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 0, 0. At this time, the edge determination result becomes undefined, and the level determination result becomes high level. As a result, the detection result becomes HL.

[0102] Figure 13 shows a fourth example of data allocation according to edge and level determination results according to the first embodiment.

[0103] In the figure, the edge detection region RE2 is set when the pixel signals SG1 and SG2 are less than the threshold voltage VT. In the edge detection region RE2, [1,0] and [0,1] are assigned to the presence of an edge, depending on the direction. Outside the edge detection region, [1,1] is assigned.

[0104] Figure 14 shows a fourth example of edge and level determination results corresponding to the output of the comparison unit according to the first embodiment.

[0105] In the figure, at [1,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 are 1 and 1, and the outputs OUT1 and OUT2 of the combinational circuit BN1 are 1 and 1. At this time, the edge detection result is 0. Also, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are 1 and 1, and the level detection result is undefined. As a result, the detection result is no edge.

[0106] Furthermore, in [1,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 become undefined, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 1 and 1. In this case, the edge detection result is undefined. Also, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become 0 and undefined, and the level detection result becomes high level. As a result, the detection result is no edge.

[0107] Furthermore, in [1,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 become undefined, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 1 and 1. In this case, the edge detection result is undefined. Also, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become undefined and 0, and the level detection result becomes high level. As a result, the detection result is no edge.

[0108] In [1,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 1 and 0, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become 1 and 1, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 1 and 0. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is left edge present LL.

[0109] At [0,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 0 and 1, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become 1 and 1, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 0 and 1. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is LL with a right edge.

[0110] Figure 15 shows a fifth example of data allocation according to edge and level determination results according to the first embodiment.

[0111] In the figure, within the edge detection region RE1, [1,0] and [0,1] are assigned to edges regardless of the level, depending on the direction. Outside the edge detection region, [1,1] is assigned when the level is low, and [0,0] is assigned when the level is high.

[0112] Figure 16 shows a fifth example of edge and level determination results corresponding to the output of the comparison unit according to the first embodiment.

[0113] In the figure, at [1,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 are 1 and 1, and the outputs OUT1 and OUT2 of the combinational circuit BN1 are 1 and 1. At this time, the edge detection result is 0. Also, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are 1 and 1, and the level detection result is undefined. As a result, the detection result is edge-less LL.

[0114] At [0,0], the outputs PO1 and PO2 of comparators CP1 and CP2 become 1 and 1, respectively, and the outputs OUT1 and OUT2 of combinational circuit BN1 become 0 and 0. In this case, the edge detection result is 0. Also, the outputs FG1 and FG2 of threshold comparison units CT1 and CT2 become undefined and 0, respectively, and the level detection result becomes high level. As a result, the detection result is no edge (HL).

[0115] Furthermore, at [0,0], the outputs PO1 and PO2 of comparators CP1 and CP2 become 1 and 1, respectively, and the outputs OUT1 and OUT2 of combinational circuit BN1 become 0 and 0. In this case, the edge detection result is 0. Also, the outputs FG1 and FG2 of threshold comparison units CT1 and CT2 become 0 and undefined, and the level detection result becomes high level. As a result, the detection result is no edge (HL).

[0116] In [1,0], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 1 and 0, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become undefined and undefined, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 1 and 0. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is a left edge present.

[0117] At [0,1], the outputs PO1 and PO2 of the comparators CP1 and CP2 become 0 and 1, respectively, the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 become undefined and undefined, and the outputs OUT1 and OUT2 of the combinational circuit BN1 become 0 and 1. At this time, the edge detection result is 1, and the level detection result is low level. As a result, the detection result is a right edge present.

[0118] As described above, in the first embodiment, image edges are detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image is detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT. The combination circuit BN1 then assigns data according to the edge and level determination results. This makes it possible to detect edges based on the comparison result of pixel signals SG1 and SG2 while also detecting the illuminance of each pixel signal SG1 and SG2, and to compress the data of the edge and level determination results.

[0119] <2. Second Embodiment> In the first embodiment described above, image edges were detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image was detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT. In this second embodiment, image edges are detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image is detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT, and the edge and level determination results are stored.

[0120] Figure 17 is a block diagram showing an example configuration of a signal readout circuit according to the second embodiment.

[0121] In the figure, this imaging device includes holding units HA1, HB1, HA2, HB2 and a determination circuit HX2, instead of the combination circuit BN1, holding units H1, H2 and determination circuit HX1 of the first embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the first embodiment described above.

[0122] The storage unit HA1 stores the comparison results from the threshold comparison unit CT1. The storage unit HB1 stores the comparison results from the comparator CP1. The storage unit HA2 stores the comparison results from the threshold comparison unit CT2. The storage unit HB2 stores the comparison results from the comparator CP2.

[0123] The determination circuit HX2 determines the edge based on the outputs PO1 and PO2 of the comparators CP1 and CP2, and determines the illuminance based on the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2.

[0124] As described above, in the second embodiment, image edges are detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image is detected based on the comparison result of each pixel signal SG1 and SG2 with the threshold voltage VT, and the edge and level determination results are stored. This makes it possible to detect edges based on the comparison result of pixel signals SG1 and SG2 without losing the edge and level determination results, and also makes it possible to detect the illuminance of each pixel signal SG1 and SG2.

[0125] <3. Third Embodiment> In the first embodiment described above, image edges were detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image was detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT. In this third embodiment, image edges are detected based on the comparison result of two pixel signals SG1 and SG2, the illuminance of the image is detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT, and one input potential of the comparator is fixed based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT.

[0126] Figure 18 is a block diagram showing an example of the configuration of a signal readout circuit according to the third embodiment.

[0127] In the figure, this imaging device includes a combination circuit BN3 and a determination circuit HX3 instead of the combination circuit BN1 and determination circuit HX1 of the first embodiment described above. Furthermore, this imaging device has potential fixing circuits FV1 and FV2 added to the imaging device of the first embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the first embodiment described above.

[0128] The combinational circuit BN3 combines the comparison results of each pixel signal SG1, SG2 and the threshold voltage VT. In this case, one bit may be assigned to the directional edge.

[0129] The determination circuit HX3 determines the edge and illuminance based on the comparison result of two pixel signals SG1 and SG2, and the combination of the comparison result of each pixel signal SG1 and SG2 with the threshold voltage VT.

[0130] The potential fixing circuit FV1 fixes the potential of the non-inverting input of the comparator CP1 based on the comparison result between the pixel signal SG1 and the threshold voltage VT. In this case, the potential fixing circuit FV1 can fix the potential of the non-inverting input of the comparator CP1 to ground potential when the level of the pixel signal SG1 is less than the threshold voltage VT, and can fix the potential of the non-inverting input of the comparator CP1 to the power supply potential when the level of the pixel signal SG1 is equal to or greater than the threshold voltage VT. This allows the output PO1 of the comparator CP1 to be set according to the comparison result between the pixel signal SG1 and the threshold voltage VT.

[0131] The potential-fixing circuit FV2 fixes the potential of the non-inverting input of the comparator CP2 based on the comparison result between the pixel signal SG2 and the threshold voltage VT. In this case, the potential-fixing circuit FV2 can fix the potential of the non-inverting input of the comparator CP2 to ground potential when the level of the pixel signal SG2 is less than the threshold voltage VT, and can fix the potential of the non-inverting input of the comparator CP2 to the power supply potential when the level of the pixel signal SG2 is equal to or greater than the threshold voltage VT. This allows the output PO2 of the comparator CP2 to be set according to the comparison result between the pixel signal SG2 and the threshold voltage VT.

[0132] Figure 19 shows an example of the configuration of a potential fixing circuit according to the third embodiment.

[0133] In the figure, the potential fixing circuit FV1 comprises a transmission gate TM1, selectors SP1 and SN1, a PMOS transistor MP1, and an NMOS transistor MN1.

[0134] The transmission gate TM1 disconnects the non-inverting input of comparator CP1 from the vertical signal line VSL1 when the potential of the non-inverting input of comparator CP1 is fixed. The input of the transmission gate TM1 is connected to the vertical signal line VSL1, and the output of the transmission gate TM1 is connected to the non-inverting input of comparator CP1. The output FG of combinational circuit BN3 is applied to the non-inverting gate of the transmission gate TM1, and the inverting output XFG of combinational circuit BN3 is applied to the inverting gate of the transmission gate TM1.

[0135] The PMOS transistor MP1 and the NMOS transistor MN1 are connected in series with each other. The connection point between the PMOS transistor MP1 and the NMOS transistor MN1 is connected to the output of the transmission gate TM1.

[0136] Selector SP1 switches between the inverted output XFG of the combinational circuit BN3 and the power supply potential VDD based on the switching signal FX and applies it to the gate of the PMOS transistor MP1. Selector SN1 switches between the output FG of the combinational circuit BN3 and the ground potential GND based on the switching signal FX and applies it to the gate of the PMOS transistor MP1.

[0137] The potential-fixing circuit FV2 comprises a transmission gate TM2, selectors SP2 and SN2, a PMOS transistor MP2, and an NMOS transistor MN2.

[0138] The transmission gate TM2 disconnects the non-inverting input of comparator CP2 from the vertical signal line VSL2 when the potential of the non-inverting input of comparator CP2 is fixed. The input of the transmission gate TM2 is connected to the vertical signal line VSL2, and the output of the transmission gate TM2 is connected to the non-inverting input of comparator CP2. The output FG of combinational circuit BN3 is applied to the non-inverting gate of the transmission gate TM2, and the inverting output XFG of combinational circuit BN3 is applied to the inverting gate of the transmission gate TM2.

[0139] The PMOS transistor MP2 and the NMOS transistor MN2 are connected in series with each other. The connection point between the PMOS transistor MP2 and the NMOS transistor MN2 is connected to the output of the transmission gate TM2.

[0140] Selector SP2 switches between the inverted output XFG of the combinational circuit BN3 and the power supply potential VDD based on the switching signal FX and applies it to the gate of the PMOS transistor MP2. Selector SN2 switches between the output FG of the combinational circuit BN3 and the ground potential GND based on the switching signal FX and applies it to the gate of the PMOS transistor MP2.

[0141] Figure 20 shows an example of the output of a combinational circuit according to the third embodiment.

[0142] In the figure, when the level determination on both sides is performed, if the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are H and H, the output FG of the combination circuit BN3 is set to H. If the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are H and L, the output FG of the combination circuit BN3 is set to L. If the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are L and H, the output FG of the combination circuit BN3 is set to L. If the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are L and L, the output FG of the combination circuit BN3 is set to L.

[0143] In one-sided level determination, when the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are H and H, the output FG of the combination circuit BN3 is set to H. When the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are H and L, the output FG of the combination circuit BN3 is set to H. When the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are L and H, the output FG of the combination circuit BN3 is set to H. When the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2 are L and L, the output FG of the combination circuit BN3 is set to L.

[0144] Figure 21 shows an example of the output of a potential-fixing circuit according to the third embodiment.

[0145] In the figure, when the switching signal FX is 0 and the output FG of the combination circuit BN3 is H, the outputs PO1 and PO2 of the comparators CP1 and CP2 are set to H and H. When the switching signal FX is 0 and the output FG of the combination circuit BN3 is L, the outputs PO1 and PO2 of the comparators CP1 and CP2 are set to pass-through. When the switching signal FX is 1 and the output FG of the combination circuit BN3 is H, the outputs PO1 and PO2 of the comparators CP1 and CP2 are set to L and L. When the switching signal FX is 1 and the output FG of the combination circuit BN3 is L, the outputs PO1 and PO2 of the comparators CP1 and CP2 are set to pass-through.

[0146] Figure 22 shows an example of the output of the determination circuit according to the third embodiment.

[0147] In the figure, when the switching signal FX is 0, the edge detection result is 0 and the level detection result is undefined when the outputs PO1 and PO2 of each comparator CP1 and CP2 are H and H. As a result, the detection result is no edge. When the outputs PO1 and PO2 of each comparator CP1 and CP2 are H and L, the edge detection result is 1 and the level detection result is undefined. As a result, the detection result is edge present LL. When the outputs PO1 and PO2 of each comparator CP1 and CP2 are L and H, the edge detection result is 1 and the level detection result is undefined. As a result, the detection result is edge present LL. When the outputs PO1 and PO2 of each comparator CP1 and CP2 are H and H, the edge detection result is 0 and the level detection result is undefined. As a result, the detection result is undefined.

[0148] When the switching signal FX is 1, the edge detection result is 0 and the level detection result is high level when the outputs PO1 and PO2 of each comparator CP1 and CP2 are L and L. As a result, the detection result is edgeless (HL). When the outputs PO1 and PO2 of each comparator CP1 and CP2 are H and L, the edge detection result is 1 and the level detection result is low level. As a result, the detection result is edge present (LL). When the outputs PO1 and PO2 of each comparator CP1 and CP2 are L and H, the edge detection result is 1 and the level detection result is low level. As a result, the detection result is edge present (LL). When the outputs PO1 and PO2 of each comparator CP1 and CP2 are H and H, the edge detection result is 0 and the level detection result is low level. As a result, the detection result is edgeless (LL).

[0149] As described above, in the third embodiment, the edges of the image are detected based on the comparison result of two pixel signals SG1 and SG2, the illuminance of the image is detected based on the comparison result of each pixel signal SG1 and SG2 with the threshold voltage VT, and the input potential of one of the comparators CP1 and CP2 is fixed based on the comparison result of each pixel signal SG1 and SG2 with the threshold voltage VT. This makes it possible to output the comparison result of the pixel signals SG1 and SG2 and the comparison result of each pixel signal SG1 and SG2 with the threshold voltage VT from each comparator CP1 and CP2.

[0150] <4. Fourth Embodiment> In the first embodiment described above, image edges were detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image was detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT. In this fourth embodiment, the amplitude of the pixel signal is detected based on the pixel signal and a reference signal.

[0151] Figure 23 shows an example of the configuration of a comparison circuit according to the fourth embodiment, and Figure 24 shows an example of the configuration of a voltage generation unit according to the fourth embodiment.

[0152] In Figure 23, this comparison circuit detects the amplitude of the pixel signal based on the pixel signal read from the pixel PX and the reference signal Vb, and stops the detection operation based on the detection result. This comparison circuit comprises an amplitude detection unit 401, a positive feedback unit 402, and an amplitude control unit 403. This comparison circuit may also be used for the threshold comparison units CT1 and CT2 of the first to third embodiments described above. Furthermore, in this comparison circuit, the positive feedback unit 402 and the amplitude control unit 403 are not necessarily required, and only the amplitude detection unit 401 may be provided.

[0153] The vertical signal line VSL1 is connected to the current source GA3. The current source GA3 may be shared with the current source GA1 that forms a source follower with the pixel PX1.

[0154] The amplitude detection unit 401 detects the amplitude of the pixel signal based on the pixel signal read from the pixel PX and the reference signal Vb. The amplitude detection unit 401 includes a switching transistor 411, a source follower transistor 412, a cutoff transistor 413, and a voltage generation unit 414. MOS transistors can be used for the switching transistor 411, the source follower transistor 412, and the cutoff transistor 413.

[0155] The switching transistor 411 cuts off the power supply to the source follower transistor 412 based on the switching signal CB. The source follower transistor 412 can also be used as a dummy source follower transistor connected to the vertical signal line VSL1. When operating as a source follower transistor 412, the switching transistor 411 is turned off, and voltage can be supplied to the drain of the source follower transistor 412 via the voltage generation unit 414.

[0156] The source follower transistor 412 generates a current corresponding to the amplitude of the pixel signal based on the reference signal Vb. The source follower transistor 412 can use the reference signal Vb as its gate input and the pixel signal SG1 as its source input. In this case, the source follower transistor 412 can form a source follower with the current source GA3 via the vertical signal line VSL1.

[0157] The cutoff transistor 413 disconnects the source follower transistor 412 from the vertical signal line VSL1 based on the output of the selector 432. At this time, the source follower transistor 412 can stop detecting the potential of the vertical signal line VSL1.

[0158] The voltage generation unit 414 generates a voltage to be supplied to the drain of the source follower transistor 412. At this time, the voltage generation unit 414 can decrease the voltage supplied to the drain of the source follower transistor 412 in accordance with the increase in the current flowing through the source follower transistor 412. The voltage generation unit 414 may be a capacitor 441 as shown in Figure 24 a, a MOS transistor 442 as shown in Figure 24 b, a resistor 443 as shown in Figure 24 c, or a diode-connected transistor 444 as shown in Figure 24 d.

[0159] The switching transistor 411, the source follower transistor 412, and the cutoff transistor 413 are connected in series sequentially. The drain of the switching transistor 411 is connected to the power supply, and the source of the cutoff transistor 413 is connected to the vertical signal line VSL1. A voltage generator 414 is connected to the connection point of the switching transistor 411 and the source follower transistor 412. A switching signal CB is applied to the gate of the switching transistor 411. A reference signal Vb is applied to the gate of the source follower transistor 412. The reference signal Vb may be a threshold voltage VT. The reference signal Vb may vary over time. The output of the selector 432 is applied to the gate of the cutoff transistor 413.

[0160] The positive feedback unit 402 sets the potential of the detected amplitude of the pixel signal based on the positive feedback of the detected amplitude of the pixel signal read from the pixel PX. The positive feedback unit 402 includes initialization transistors 421, 422, a feedback transistor 423, and a NOR circuit 424. MOS transistors can be used for the initialization transistors 421, 422 and the feedback transistor 423.

[0161] Initialization transistors 421 and 422 initialize the output of the amplitude detection unit 401 based on the initialization signal XIN. Feedback transistor 423 provides positive feedback from the output of the positive feedback unit 402 to the input of the positive feedback unit 402. NOR circuit 424 performs threshold determination based on the enable signal DEN.

[0162] Initialization transistors 421, 422 and feedback transistor 423 are connected in series sequentially. The drain of initialization transistor 421 is connected to the power supply, and the source of feedback transistor 423 is connected to ground potential. One input of NOR circuit 424 is connected to the connection point of initialization transistors 421 and 422. The other input of NOR circuit 424 is input to the enable signal DEN. The gates of each switching transistor 411 and 422 are applied to the initialization signal XIN. The gate of feedback transistor 423 is connected to the output of NOR circuit 424.

[0163] The amplitude control unit 403 blocks the detection of the pixel signal amplitude based on the output from the positive feedback unit 402. The amplitude control unit 403 includes an inverter 431 and a selector 432.

[0164] The inverter 431 inverts the output IFG of the NOR circuit 424 and outputs an inverted output XFG. Based on the enable signal DEN, the selector 432 switches between the inverted output XFG and the cutoff signal SEK and applies them to the gate of the cutoff transistor 413.

[0165] Figure 25 is a timing chart showing the waveforms of each part during the operation of the comparator according to the fourth embodiment. The figure shows examples of the waveforms for high-level incident IR1 and solar incident IR2.

[0166] In the figure, when the enable signal DEN rises (t11), the output IFG of the NOR circuit 424 is set to a low level, and the feedback transistor 423 is turned off. Also, the cutoff signal SEK is selected by the selector 432, and the cutoff transistor 413 is turned off.

[0167] Next, when the reset signal RST rises (t12), the reset transistor 123 turns on, and the floating diffusion FD is reset. Also, the auto-zero signal AZ rises, and charges to balance the non-inverting and inverting inputs of each comparator CP1 and CP2 are accumulated in the input capacitances of each comparator CP1 and CP2, respectively. Furthermore, the initialization signal XIN falls, and the initialization transistor 421 turns on while the initialization transistor 422 turns off. At this time, the output of the voltage generation unit 414 is set to the power supply potential.

[0168] Next, in the high-level incident IR1, when the reset signal RST falls (t13), the reset transistor 123 turns off. At this time, the potential of the vertical signal line VSL1 is set to the reset level of pixel PX1. Also, when the initialization signal XIN rises, the initialization transistor 421 turns off and the initialization transistor 422 turns on.

[0169] Next, after the auto-zero signal AZ falls, the transfer signal TRG rises (t15), and the transfer transistor TG turns on. At this time, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD.

[0170] Next, the transfer signal TRG falls (t16), and the transfer transistor TG turns off. At this time, the potential of the vertical signal line VSL1 is set to the signal level of pixel PX1.

[0171] Next, the enable signal DEN falls (t17), the output IFG of the NOR circuit 424 is set to a high level, and the feedback transistor 423 is turned on. Also, the inverting output XFG is selected by the selector 432, and the cutoff transistor 413 is turned on. Then, current flows through the source follower transistor 412 in accordance with the potential of the vertical signal line VSL1 and the reference signal Vb, and the output potential of the voltage generation unit 414 decreases in accordance with this current. Then, as the output IFG of the NOR circuit 424 is set to a high level in accordance with the decrease in the output potential of the voltage generation unit 414, the feedback transistor 423 is turned on. At this time, the output potential of the voltage generation unit 414 decreases further in accordance with the current flowing through the feedback transistor 423, and as the drain potential of the source follower transistor 412 decreases in accordance with the decrease in the output potential of the voltage generation unit 414, the source follower transistor 412 is turned off.

[0172] On the other hand, in solar incident IR2, when the reset signal RST falls (t13), the reset transistor 123 turns off. At this time, charge overflows from pixel PX1 and flows into the floating diffusion FD. As a result, the potential of the vertical signal line VSL1 is set to the saturation level. Also, when the initialization signal XIN rises, the initialization transistor 421 turns off and the initialization transistor 422 turns on. Furthermore, when the enable signal DEN falls, the output IFG of the NOR circuit 424 is set to a high level and the feedback transistor 423 turns on. In addition, the inverting output XFG is selected by the selector 432 and the cutoff transistor 413 turns on.

[0173] Next, after the auto-zero signal AZ falls, the enable signal DEN rises (t14), the output IFG of the NOR circuit 424 is set to a low level, and the feedback transistor 423 is turned off. Also, the cutoff signal SEK is selected by the selector 432, and the cutoff transistor 413 is turned off.

[0174] As described above, in the fourth embodiment, the amplitude of the pixel signal is detected based on the pixel signal read from the pixel PX and the reference signal Vb. This makes it possible to compare the pixel signal and the reference signal Vb based on the operation of the source follower transistor 412. As a result, it is possible to reduce the number of elements in the comparator circuit, thereby achieving lower power consumption and a smaller area.

[0175] <5. Fifth Embodiment> In the first embodiment described above, image edges were detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image was detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT. In this fifth embodiment, the detection result of the illuminance of the pixel signal is multi-leveled based on the potential fluctuation of the gate input of the source follower transistor 412.

[0176] Figure 26 is a block diagram showing an example configuration of a signal readout circuit according to the fifth embodiment.

[0177] In the figure, this imaging device includes a combination circuit BN6, holding units HE1 to HE6, and a determination circuit HX6, instead of the combination circuit BN1, holding units H1 and H2, and determination circuit HX1 of the first embodiment described above. Also, the level of the reference signal Vb changes in two stages. The other configurations of this imaging device are the same as those of the imaging device of the first embodiment described above.

[0178] The combinational circuit BN6 combines the comparison results of the two pixel signals SG1 and SG2 and the comparison results of each pixel signal SG1 and SG2 with multiple threshold voltages VT. In this case, the combinational circuit BN6 may, for example, assign 3 bits to the directional edge and the 4-level illuminance in the two pixel signals SG1 and SG2.

[0179] The holding units HE1, HE3, and HE5 each store a combination of the comparison results from the threshold comparison unit CT1 and the comparator CP1, based on the respective enable signals EN1 to EN3, for each threshold of the threshold comparison unit CT1. The holding units HE2, HE4, and HE6 each store a combination of the comparison results from the threshold comparison unit CT2 and the comparator CP2, based on the respective enable signals EN1 to EN3, for each threshold of the threshold comparison unit CT2.

[0180] The determination circuit HX6 determines the edge based on the outputs PO1 and PO2 of the comparators CP1 and CP2, and also determines the illuminance in multiple stages based on the outputs FG1 and FG2 of the threshold comparison units CT1 and CT2.

[0181] Figure 27 is a timing chart showing the waveforms of each part during operation of the signal readout circuit according to the fifth embodiment.

[0182] In the same figure, the processing from time T11 to T16 is the same as the processing of high-level incident IR1 in Figure 25. However, the level of the reference signal Vb changes from Vb1 to Vb2 to Vb3.

[0183] Next, the enable signal DEN falls (t17), the output IFG of the NOR circuit 424 is set to a high level, and the feedback transistor 423 is turned on. Also, the inverting output XFG is selected by the selector 432, and the cutoff transistor 413 is turned on. Furthermore, the enable signal EN1 rises, and the holding unit HE1 holds the combination of the comparison result from the threshold comparison unit CT1 and the comparison result from the comparator CP1, while the holding unit HE2 holds the combination of the comparison result from the threshold comparison unit CT2 and the comparison result from the comparator CP2. At this time, the level of the reference signal Vb is set to Vb1.

[0184] Next, as the enable signal EN1 falls and the enable signal EN2 rises, the holding unit HE3 holds the combination of the comparison result from the threshold comparison unit CT1 and the comparison result from the comparator CP1, while the holding unit HE4 holds the combination of the comparison result from the threshold comparison unit CT2 and the comparison result from the comparator CP2. At this time, the level of the reference signal Vb is set to Vb2.

[0185] Next, as the enable signal EN2 falls and the enable signal EN3 rises (t18), the holding unit HE5 holds the combination of the comparison result from the threshold comparison unit CT1 and the comparison result from the comparator CP1, while the holding unit HE6 holds the combination of the comparison result from the threshold comparison unit CT2 and the comparison result from the comparator CP2. At this time, the level of the reference signal Vb is set to Vb3.

[0186] Here, the output IFG of the NOR circuit 424 is set based on the relative magnitudes of the levels VB1 to Vb3 of the reference signal Vb and the potential of the vertical signal line VSL1. For example, as the levels of the reference signal Vb change from Vb1 to Vb2 to Vb3, the output IFG of the NOR circuit 424 changes from L to L to H. This makes it possible to multi-level the detection result of the illuminance of the pixel signal based on the switching of the levels of the reference signal Vb.

[0187] Thus, in the fifth embodiment described above, the detection result of the illuminance of the pixel signal is multi-leveled based on the potential fluctuation of the gate input of the source follower transistor 412. This makes it possible to improve the detection accuracy of the illuminance of the pixel signal while suppressing an increase in the circuit size of the comparator circuit.

[0188] <6. Sixth Embodiment> In the first embodiment described above, image edges were detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image was detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT. In this sixth embodiment, the detection result of the illuminance of the pixel signal is multi-leveled based on the switching of a source follower transistor.

[0189] Figure 28 shows an example of the configuration of the amplitude detection unit according to the sixth embodiment.

[0190] In the figure, this amplitude detection unit includes switching transistors 611, 621, 631, source follower transistors 612, 622, 632, and cutoff transistors 613, 623, 633, instead of the switching transistor 411, source follower transistor 412, and cutoff transistor 413 of the fourth embodiment described above. The other configurations of this imaging device are the same as those of the amplitude detection unit of the fourth embodiment described above.

[0191] The switching transistor 611, source follower transistor 612, and cutoff transistor 613 are connected in series sequentially. The switching transistor 621, source follower transistor 622, and cutoff transistor 623 are connected in series sequentially. The switching transistor 631, source follower transistor 632, and cutoff transistor 633 are connected in series sequentially.

[0192] The drains of each switching transistor 611, 621, and 631 are connected to the power supply, and the sources of each cutoff transistor 613, 623, and 633 are connected to the vertical signal line VSL1. The connection points of the switching transistor 611 and the source follower transistor 612, the connection points of the switching transistor 621 and the source follower transistor 622, and the connection points of the switching transistor 631 and the source follower transistor 632 are connected to the voltage generation unit 414. Switching signals CB1 to CB3 are applied to the gates of each switching transistor 611, 621, and 631, respectively. Reference signals Vb1 to Vb3 are applied to the gates of each source follower transistor 612, 622, and 632. Outputs SL1 to SL3 of the selector 432 are applied to the gates of each cutoff transistor 613, 623, and 633. At this time, the selector 432 switches between the inverting output XFG and the cutoff signal SEK based on the switching signal XEN and applies them to the gates of the respective cutoff transistors 613, 623, and 633.

[0193] Figure 29 is a timing chart showing the waveforms of each part during operation of the signal readout circuit according to the sixth embodiment.

[0194] In this figure, the processing from time T11 to T16 is the same as the processing in Figure 27. However, reference signals Vb1 to Vb3 are used as reference signals Vb. In addition, the configuration in Figure 26 can be used for this processing.

[0195] Next, the enable signal DEN falls (t17), the output IFG of the NOR circuit 424 is set to a high level, and the feedback transistor 423 is turned on. Also, the output SL1 of the selector 432 rises, and the cutoff transistor 613 is turned on based on the inverting output XFG selected by the selector 432. At this time, the source follower transistor 612 operates based on the reference signal Vb1. Furthermore, the enable signal EN1 rises, and the holding unit HE1 holds the combination of the comparison result from the threshold comparison unit CT1 and the comparison result from the comparator CP1, while the holding unit HE2 holds the combination of the comparison result from the threshold comparison unit CT2 and the comparison result from the comparator CP2.

[0196] Next, as the output SL1 of selector 432 falls and the output SL2 of selector 432 rises, the cutoff transistor 623 is turned on based on the inverting output XFG selected by selector 432. At this time, the source follower transistor 622 operates based on the reference signal Vb2. Also, as the enable signal EN1 falls and the enable signal EN2 rises, the holding unit HE3 holds the combination of the comparison result from the threshold comparison unit CT1 and the comparison result from the comparator CP1, while the holding unit HE4 holds the combination of the comparison result from the threshold comparison unit CT2 and the comparison result from the comparator CP2.

[0197] Next, as the output SL2 of selector 432 falls and the output SL3 of selector 432 rises (t18), the cutoff transistor 633 is turned on based on the inverting output XFG selected by selector 432. At this time, the source follower transistor 632 operates based on the reference signal Vb3. Also, as the enable signal EN2 falls and the enable signal EN3 rises, the holding unit HE5 holds the combination of the comparison result from the threshold comparison unit CT1 and the comparison result from the comparator CP1, while the holding unit HE6 holds the combination of the comparison result from the threshold comparison unit CT2 and the comparison result from the comparator CP2.

[0198] Here, the output IFG of the NOR circuit 424 is set based on the relative magnitudes of the reference signals VB1 to Vb3 and the potential of the vertical signal line VSL1. For example, according to the switching of the reference signals VB1 to Vb3, the output IFG of the NOR circuit 424 changes from L to L to H. This makes it possible to multi-level the detection result of the illuminance of the pixel signal based on the switching of the reference signals VB1 to Vb3.

[0199] Figure 30 shows an example of data allocation according to edge and level determination results according to the sixth embodiment.

[0200] In the figure, the thresholds of pixel signals SG1 and SG2 are set from VT1 to VT3 in accordance with the switching of reference signals Vb1 to Vb3. In the edge detection region RE1, when pixel signals SG1 and SG2 are below the threshold voltage VT1, HL1[1,0,1,1,1] and HL1[0,1,1,1,1] are assigned to high-level edges depending on the direction. Also, when pixel signals SG1 and SG2 are above the threshold voltage VT1 and below the threshold voltage VT2, HL2[1,0,1,1,0] and HL2[0,1,1,1,0] are assigned to high-level edges depending on the direction. Also, when pixel signals SG1 and SG2 are above the threshold voltage VT2 and below the threshold voltage VT3, HL3[1,0,1,0,0] and HL3[0,1,1,0,0] are assigned to high-level edges depending on the direction. Furthermore, when the pixel signals SG1 and SG2 have a threshold voltage of VT3 or higher, HL4[1,0,0,0,0] and HL4[0,1,0,0,0] are assigned to high-level edges, depending on the direction.

[0201] Thus, in the sixth embodiment described above, the detection result of the illuminance of the pixel signal is multi-leveled based on the switching of source follower transistors 612, 622, and 632. This makes it possible to improve the detection accuracy of the illuminance of the pixel signal while suppressing an increase in the circuit size of the comparator circuit.

[0202] <7. Seventh Embodiment> In the first embodiment described above, image edges were detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image was detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT. In this seventh embodiment, the storage time of each pixel PX1 and PX2 is controlled based on the level determination result of each pixel signal SG1 and SG2.

[0203] Figure 31 is a flowchart showing the storage time control method based on the level determination result according to the seventh embodiment. Note that the storage time control method based on the level determination result may be applied to any of the solid-state imaging devices of the first to sixth embodiments described above.

[0204] In the figure, the solid-state imaging device acquires an edge signal level image (S101). Any of the methods described in the first to sixth embodiments above may be used to acquire the edge signal level image.

[0205] Next, the solid-state imaging device performs region designation (S102). In this region designation, the range of pixels PX of the pixel array section 111 can be specified.

[0206] Next, the solid-state imaging device calculates the expected value of the signal level within the specified area (S103). This expected value can be calculated according to the input / output characteristics shown in Figures 7, 11, 15, and 34.

[0207] In the input / output characteristics shown in Figure 7, if the number of LL edges (the number of outputs at [0,1], [1,0]) is NL1 and the number of HL edges (the number of outputs at [0,0]) is NH1, then the expected value can be given by NH1 / (NL1+NH1).

[0208] In the input / output characteristics shown in Figure 11, if we let NT1 be the total number of outputs and NH1 be the number of outputs at [0,0], then the expected value can be given by NH1 / NT1.

[0209] In the input / output characteristics of Figure 15, if we let NL2 be the number of outputs without LL edges (the number of outputs in the [1,1] region) and NH2 be the number of outputs without HL edges (the number of outputs in the [0,0] region), then the expected value can be given by NH2 / (NL2+NH2).

[0210] In the input / output characteristics of Figure 34, if we let NT2 be the total number of edges (outputs of [0,1,-,-,-], [1,0,-,-,-], NE1 be the number of edges in the HL1 region (outputs of [0,1,1,1,1], [1,0,1,1,1]), NE2 be the number of edges in the HL2 region (outputs of [0,1,1,1,0], [1,0,1,1,0]), NE3 be the number of edges in the HL3 region (outputs of [0,1,1,0,0], [1,0,1,0,0]), and NE4 be the number of edges in the HL4 region (outputs of [0,1,0,0,0], [1,0,0,0,0]), then the expected value can be given by (K1・NE1 + K2・NE2 + K3・NE3 + K4・NE4) / NT2. However, K1 to K4 are values ​​corresponding to the sizes of the HL1 to HL4 regions.

[0211] Next, the solid-state imaging device determines whether the expected value is within the specified level (S104). If the expected value is within the specified level, the process is terminated.

[0212] On the other hand, if the expected value is outside the specified level, the solid-state imaging device controls the storage time of each pixel PX1, PX2 (S105) and returns to S101.

[0213] Thus, in the seventh embodiment described above, the accumulation time of each pixel PX1 and PX2 is controlled based on the level determination results of each pixel signal SG1 and SG2. This makes it possible to optimize the amount of charge accumulated in each pixel PX1 and PX2 according to the incident intensity, thereby improving edge detection accuracy.

[0214] <8. Eighth Embodiment> In the first embodiment described above, image edges were detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image was detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT. In this eighth embodiment, a three-input comparator is used to compare the two pixel signals SG1 and SG2, and to compare the pixel signals SG1 and SG2 with a reference signal REF.

[0215] Figure 32 is a block diagram showing an example of the configuration of a signal readout circuit according to the eighth embodiment.

[0216] In the figure, this imaging device includes comparators CM1 and CM2 instead of comparators CP1 and CP2 and threshold comparison units CT1 and CT2 of the first embodiment described above. Furthermore, this imaging device includes gain setting units GN1, GP1, GR1, GN2, GP2, and GR2 instead of level setting circuits LA1, LB1, LA2, LB2 and variable capacitors CA1, CB1, CA2, CB2 of the first embodiment described above. In addition, this imaging device removes the combination circuit BN1, holding units H1 and H2, and determination circuit HX1 from the imaging device of the first embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the first embodiment described above.

[0217] Each comparator CM1 and CM2 can be configured as a three-input comparator. In this case, each comparator CM1 and CM2 may have one non-inverting input and two inverting inputs.

[0218] Each comparator CM1 and CM2 compares two pixel signals transmitted via their respective vertical signal lines VSL1 and VSL2. Each comparator CM1 and CM2 also compares a pixel signal transmitted via VSL1 with a reference signal REF. At this time, the gains of the two pixel signals and the reference signal REF input to comparator CM1 can be set via gain setting units GN1, GP1, and GR1. Similarly, the gains of the two pixel signals and the reference signal REF input to comparator CM2 can be set via gain setting units GN2, GP2, and GR2. The reference signal REF may be a fixed value, a ramp wave, or a signal whose level changes in steps.

[0219] The non-inverting input of comparator CM1 is connected to the vertical signal line VSL1 via the gain setting unit GP1. The first inverting input of comparator CM1 is connected to the vertical signal line VSL2 via the gain setting unit GN1. The reference signal REF is applied to the second inverting input of comparator CM1 via the gain setting unit GR1.

[0220] The non-inverting input of comparator CM2 is connected to the vertical signal line VSL2 via the gain setting unit GP2. The first inverting input of comparator CM2 is connected to the vertical signal line VSL1 via the gain setting unit GN2. The reference signal REF is applied to the second inverting input of comparator CM2 via the gain setting unit GR2.

[0221] Figure 33 shows the waveform of the reference signal of the signal readout circuit according to the eighth embodiment.

[0222] As shown in figure a, the reference signal REF may be a ramp wave RAP, as shown in figure b, the reference signal REF may be a step signal STP, or the reference signal REF may be a fixed voltage DC.

[0223] Figure 34 shows an example of data allocation according to edge and level determination results according to the eighth embodiment.

[0224] In the figure, the ramp wave RAP is used as the reference signal REF. In this case, in the edge detection region RE1, [A1, 0] and [0, A2] are assigned depending on the edge direction. Outside the edge detection region, [A1, A2] is assigned. A1 and A2 are AD conversion values ​​based on the comparison result between the two pixel signals transmitted via the respective vertical signal lines VSL1 and VSL2 and the reference signal REF.

[0225] Figure 35 shows an example of the configuration of a comparator according to the eighth embodiment.

[0226] In the figure, comparator CM1 balances the comparator inputs based on auto-zero operation and then outputs a voltage VO1 corresponding to the difference in the comparator inputs. Comparator CM1 includes PMOS transistors 811, 812, 818, NMOS transistors 813, 814, 817, 819, input capacitors CA3, CB3, CB4, switches 842, 851, 852, 862 and a NAND circuit 861.

[0227] PMOS transistor 811 and NMOS transistor 813 are connected in series with each other. PMOS transistor 812 and NMOS transistor 814 are connected in series with each other. PMOS transistor 812 and NMOS transistor 816 are connected in series with each other. The sources of each PMOS transistor 811 and 812 are connected to the power supply potential VDD, and the gates of each PMOS transistor 811 and 812 are connected to the drain of PMOS transistor 811. The sources of each NMOS transistor 813, 814, and 816 are grounded via NMOS transistor 817. In this case, NMOS transistor 817 is shared by NMOS transistors 813, 814, and 816.

[0228] The gate of NMOS transistor 813 is connected to the vertical signal line VSL1 via input capacitor CA3. The gate of NMOS transistor 814 is connected to the vertical signal line VSL2 via input capacitor CB3. The gate of NMOS transistor 816 is input to the reference signal REF via input capacitor CB4.

[0229] PMOS transistor 818 and NMOS transistor 819 are connected in series with each other. The source of PMOS transistor 818 is connected to the power supply potential VDD, and the gate of PMOS transistor 818 is connected to the drain of PMOS transistor 812. The gate of NMOS transistor 819 is connected to the drain of NMOS transistor 819 via switch 862. The source of NMOS transistor 819 is grounded. One input to NAND circuit 861 is connected to the drain of PMOS transistor 818, and the other input to NAND circuit 861 is the selection signal XST.

[0230] Each switch 842, 851, and 852 is opened and closed based on the auto-zero signal AZ. A bias voltage VBN is applied to the gate of NMOS transistor 817. NMOS transistor 817 can operate as a constant current source based on the bias voltage VBN. An initial voltage VIT is applied to the gate of NMOS transistor 816 via switch 852.

[0231] Figure 36 is a timing chart showing a first example of the waveforms of each part during operation of the signal readout circuit according to the eighth embodiment.

[0232] In the same figure, the signal readout circuit is provided with a ramp wave RAP as the reference signal REF. At this time, the initial voltage VIT applied to the gate of NMOS transistor 816 is set to a voltage lower than the auto-zero voltage VZ applied to the gates of NMOS transistors 813 and 814 at auto-zero, so that no current flows through NMOS transistor 816.

[0233] Then, when the auto-zero signal AZ rises (t21), the gate potentials V1 and V2 of the NMOS transistors 813 and 814 and the drain potential VO1 of the PMOS transistor 812 are set to the auto-zero voltage VZ. At this time, charges that balance the non-inverting input and the two inverting inputs of the comparator CM1 are accumulated in the input capacitors CA3, CB3, and CB4 of the comparator CM1.

[0234] Next, when the reset signal RST rises (t22), the reset transistor 123 turns on, and the floating diffusion FD is reset.

[0235] Next, after the auto-zero signal AZ falls, the transfer signal TRG rises (t23), and the transfer transistor TG turns on. At this time, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD.

[0236] Next, the transfer signal TRG falls (t24), and the transfer transistor TG turns off. At this time, the potentials of each vertical signal line VSL1 and VSL2 are set to the signal levels of each pixel PX1 and PX2. Then, the gate potentials V1 and V2 of NMOS transistors 813 and 814 are set based on the potentials of each vertical signal line VSL1 and VSL2. At this time, the drain potential VO1 of PMOS transistor 812 is set based on the difference between the gate potentials V1 and V2 of NMOS transistors 813 and 814. Then, PMOS transistor 818 is driven based on the drain potential VO1 of PMOS transistor 812, and the output PO1 of comparator CM1 is set via NAND circuit 861.

[0237] Next, the selection signal XST rises (t25), and the output PO1 of the comparator CM1 is set based on the comparison result between the gate potential V1 of the NMOS transistor 813 and the ramp wave RAP. At this time, the gate potential VR of the NMOS transistor 816 is set based on the ramp wave RAP. Then, after the delay time TD1 has elapsed from the rise of the selection signal XST, when the gate potential V1 of the NMOS transistor 813 matches the gate potential VR of the NMOS transistor 816 (t26), the drain potential VO1 of the PMOS transistor 812 is set to a low level. At this time, the PMOS transistor 818 turns on, and the output PO1 of the comparator CM1 falls via the NAND circuit 861.

[0238] Next, when the selection signal XST falls (t27), the output PO1 of the comparator CM1 rises via the NAND circuit 861.

[0239] Figure 37 shows a first example of the signal levels of each part during operation of the signal readout circuit according to the eighth embodiment.

[0240] In the figure, if we let VD1 be the AD conversion voltage, VDM be the maximum count voltage, and ΔV1 be the amplitude of the vertical signal line VSL1, then ΔV1 can be given by ΔV1 = VDM - VD1. Therefore, by subtracting the AD conversion result from the maximum count value, the amplitude information of the vertical signal line VSL1 can be obtained.

[0241] Figure 38 is a timing chart showing a second example of the waveforms of each part during operation of the signal readout circuit according to the eighth embodiment.

[0242] In the same figure, the processing from time T21 to T24 is the same as the processing in Figure 36. However, in this signal readout circuit, a step signal STP is provided as the reference signal REF. At this time, the initial voltage VIT applied to the gate of NMOS transistor 816 is set to a voltage lower than the auto-zero voltage VZ applied to the gates of NMOS transistors 813 and 814 at auto-zero, so that no current flows to NMOS transistor 816. The step signal STP can rise along with the falling edge of the transfer signal TRG.

[0243] Then, the selection signal XST rises (t25), and the output PO1 of the comparator CM1 is set based on the comparison result between the gate potential V1 of the NMOS transistor 813 and the step signal STP. At this time, the gate potential VR of the NMOS transistor 816 is set based on the step signal STP. When the gate potential V1 of the NMOS transistor 813 falls below the gate potential VR of the NMOS transistor 816, the drain potential VO1 of the PMOS transistor 812 is set to a low level. At this time, the PMOS transistor 818 turns on, and the output PO1 of the comparator CM1 falls via the NAND circuit 861.

[0244] Next, when the selection signal XST falls (t26), the output PO1 of the comparator CM1 rises via the NAND circuit 861.

[0245] Figure 39 shows a second example of the signal levels of each part during operation of the signal readout circuit according to the eighth embodiment.

[0246] In the figure, based on the comparison result between the illuminance threshold voltage VTL controlled by the amplitude VS1 of the step signal STP and the amplitude ΔV1 of the vertical signal line VSL1, it is possible to determine whether the amplitude ΔV1 of the vertical signal line VSL1 is greater than the illuminance threshold voltage VTL.

[0247] Figure 40 is a timing chart showing a third example of the waveforms of each part during operation of the signal readout circuit according to the eighth embodiment.

[0248] In the same figure, the processing from time T21 to T24 is the same as the processing in Figure 36. However, in this signal readout circuit, a fixed voltage DC is provided as the reference signal REF. At this time, the initial voltage VIT applied to the gate of NMOS transistor 816 is set to a voltage lower than the auto-zero voltage VZ applied to the gates of NMOS transistors 813 and 814 at auto-zero, so that no current flows to NMOS transistor 816.

[0249] Then, the selection signal XST rises (t25), and the output PO1 of comparator CM1 is set based on the comparison result between the gate potential V1 of NMOS transistor 813 and the fixed voltage DC. At this time, the gate potential VR of NMOS transistor 816 is set based on the fixed voltage DC. When the gate potential V1 of NMOS transistor 813 falls below the gate potential VR of NMOS transistor 816, the drain potential VO1 of PMOS transistor 812 is set to a low level. At this time, PMOS transistor 818 turns on, and the output PO1 of comparator CM1 falls via the NAND circuit 861.

[0250] Next, when the selection signal XST falls (t26), the output PO1 of the comparator CM1 rises via the NAND circuit 861.

[0251] Figure 41 shows a third example of the signal levels of each part during operation of the signal readout circuit according to the eighth embodiment.

[0252] In the figure, it is possible to determine whether the amplitude ΔV1 of the vertical signal line VSL1 is greater than the illuminance threshold voltage VTL based on the comparison result between the illuminance threshold voltage VTL and the amplitude ΔV1 of the vertical signal line VSL1. In this case, the illuminance threshold voltage VTL can be given by VZ-VIT.

[0253] Thus, in the eighth embodiment described above, a comparator CM1 is used to compare the two pixel signals SG1 and SG2, and to compare the pixel signal SG1 with the reference signal REF. This makes it possible to compare the two pixel signals SG1 and SG2, and to compare the pixel signals SG1 and SG2 with the reference signal REF, while suppressing an increase in circuit size and power consumption.

[0254] <9. Ninth Embodiment> In the eighth embodiment described above, a three-input comparator was used to compare the two pixel signals SG1 and SG2, and to compare the pixel signals SG1 and SG2 with the reference signal REF. In this ninth embodiment, a four-input comparator is used to compare the two pixel signals SG1 and SG2, and to compare the pixel signals SG1 and SG2 with the reference signal REF.

[0255] Figure 42 is a block diagram showing an example configuration of a signal readout circuit according to the ninth embodiment.

[0256] In the figure, this imaging device is equipped with a comparator CM3 in place of the comparators CM1 and CM2 of the eighth embodiment described above. Furthermore, this imaging device has a multiplexer MPX added to the imaging device of the eighth embodiment described above. In addition, the gain setting units GR1 and GR2 are removed from the imaging device of the first embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the eighth embodiment described above.

[0257] The multiplexer MPX switches between two pixel signals and two reference signals REF that are input to the comparator CM3.

[0258] The comparator CM3 can be configured as a four-input comparator. In this case, the comparator CM3 may have two non-inverting inputs and two inverting inputs. In this case, the gains of the two pixel signals and two reference signals REF input to the comparator CM3 can be set via gain setting units GN1, GP1, GN2, and GP2. The two reference signals REF may be fixed values, ramp waves, or have levels that change in steps.

[0259] The potential of the vertical signal line VSL2, switched by the multiplexer MPX, is input to the first inverting input of comparator CM3 via the gain setting unit GN1. The potential of the vertical signal line VSL1, switched by the multiplexer MPX, is input to the second inverting input of comparator CM3 via the gain setting unit GN2. The reference signal REF, switched by the multiplexer MPX, is input to the first non-inverting input of comparator CM3 via the gain setting unit GP1. The reference signal REF, switched by the multiplexer MPX, is input to the second non-inverting input of comparator CM3 via the gain setting unit GP2.

[0260] Figure 43 shows an example of the configuration of a comparator according to the ninth embodiment.

[0261] In the figure, comparator CM3 compares two pixel signals transmitted via vertical signal lines VSL1 and VSL2. Comparator CM3 also compares each pixel signal transmitted via vertical signal lines VSL1 and VSL2 with the reference signal REF.

[0262] Comparator CM3 balances the comparator inputs based on auto-zero operation and outputs a voltage VO3 corresponding to the difference in the comparator inputs. Comparator CM3 comprises PMOS transistors 811, 812, 818, NMOS transistors 813 to 817, 819, input capacitors CA3, CA4, CB3, CB4, and switches 821, 822, 831, 832, 841, 842, 851, 852, 862.

[0263] PMOS transistor 811 and NMOS transistor 813 are connected in series via switch 821. PMOS transistor 812 and NMOS transistor 814 are connected in series via switch 831. PMOS transistor 811 and NMOS transistor 815 are connected in series via switch 822. PMOS transistor 812 and NMOS transistor 816 are connected in series via switch 832. The sources of each PMOS transistor 811 and 812 are connected to the power supply potential VDD, and the gates of each PMOS transistor 811 and 812 are connected to the drain of PMOS transistor 811. In this configuration, PMOS transistors 811 and 812 can form a current mirror. The sources of each NMOS transistor 813 through 816 are grounded via NMOS transistor 817. In this configuration, NMOS transistor 817 is shared by NMOS transistors 813 through 816.

[0264] The gate of NMOS transistor 813 is connected to the vertical signal line VSL1 via input capacitor CA3. The gate of NMOS transistor 814 is connected to the vertical signal line VSL2 via input capacitor CB3. The gate of NMOS transistor 815 is input to the reference signal REF via input capacitor CA4. The gate of NMOS transistor 816 is input to the reference signal REF via input capacitor CB4.

[0265] Each switch 842, 851 is opened and closed based on the auto-zero signal AZ1. Each switch 841, 852 is opened and closed based on the auto-zero signal AZ2. Each switch 821, 831 is opened and closed based on the switching signal SE1. Each switch 822, 832 is opened and closed based on the switching signal SE2. The rest of the configuration of this comparator CM3 is the same as that of the comparator CM1 in the eighth embodiment described above.

[0266] Figure 44 is a timing chart showing an example of the waveforms of each part during operation of the signal readout circuit according to the ninth embodiment.

[0267] In the same figure, the processing of this signal readout circuit is the same as the processing in Figure 36. However, in this signal readout circuit, in the processing in Figure 36, switches 821, 831, 822, and 832 are switched based on switching signals SE1 and SE2. At this time, by keeping switches 821, 831, 822, and 832 constantly on, the two pixel signals can be compared using NMOS transistors 813 and 814, and a reference signal REF can be input via NMOS transistors 815 and 816.

[0268] Figure 45 is a timing chart showing an example of the waveforms of each part during pipeline operation of the signal readout circuit according to the ninth embodiment.

[0269] In the figure, the pipeline operation of this signal readout circuit includes P-phase AD conversion periods PA1 and PA2 and D-phase AD conversion periods DA1 and DA2. At this time, a ramp wave RNP is applied as a reference signal REF to the second non-inverting input of the comparator CM3. Then, pipeline readout is achieved by alternately switching switches 821, 831, 822, and 832 based on switching signals SE1 and SE2 according to the transitions between the P-phase AD conversion periods PA1 and PA2 and the D-phase AD conversion periods DA1 and DA2.

[0270] Thus, in the ninth embodiment described above, a four-input comparator is used for comparing the two pixel signals SG1 and SG2, and for comparing each pixel signal SG1 and SG2 with the reference signal REF. This makes it possible to compare the two pixel signals SG1 and SG2, and to compare each pixel signal SG1 and SG2 with the reference signal REF, while suppressing an increase in circuit size and power consumption.

[0271] <10. Tenth Embodiment> In the first embodiment described above, the edges of the image were detected based on the comparison result of two pixel signals SG1 and SG2, and the illuminance of the image was detected based on the comparison result of each pixel signal SG1 and SG2 with a threshold voltage VT. In this tenth embodiment, substrates on which a solid-state imaging device is formed, each having a pixel array section in which pixels PX are arranged in a matrix, are stacked.

[0272] Figure 46 is a perspective view showing an example of the configuration of an imaging device according to the tenth embodiment.

[0273] In figure a, the solid-state imaging device 901 comprises a support substrate 911 and a semiconductor substrate 912. The semiconductor substrate 912 is laminated on the support substrate 911. A pixel array section 913 and peripheral circuits 914 are formed on the semiconductor substrate 912. A column readout circuit 915 and a column ADC 916 are formed on the peripheral circuits 914. The column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array section 913 in the column direction.

[0274] In the pixel array section 913, pixels PX are arranged in a matrix along the row direction and the column direction. The column readout circuit 915 can use any of the configurations of the first to ninth embodiments described above. The column ADC 916 can perform AD conversion on each column of the signals read out via the column readout circuit 915. In this case, the solid-state imaging device 901 can be configured as a back-illuminated image sensor.

[0275] In figure b, the solid-state imaging device 902 comprises semiconductor substrates 921 and 922. The semiconductor substrate 922 is laminated on the semiconductor substrate 921. A pixel array section 923 is formed on the semiconductor substrate 922. A peripheral circuit 924 is formed on the semiconductor substrate 922. A column readout circuit 925 and a column ADC 926 are formed on the peripheral circuit 924. The column readout circuit 925 can be configured in any of the first to ninth embodiments described above. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. In this case, the solid-state imaging device 902 can be configured as a back-illuminated image sensor.

[0276] As described above, in the twelfth embodiment, the substrates on which each solid-state imaging device 901 and 902 is formed are stacked. This makes it possible to thin the semiconductor substrates 912 and 922 on which each pixel array portion 913 and 923 is formed, while supporting each pixel array portion 913 and 923, thereby forming a back-illuminated image sensor.

[0277] <11. Examples of Application to Mobile Devices> The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0278] Figure 47 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0279] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 47, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0280] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0281] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0282] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0283] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0284] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0285] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0286] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0287] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0288] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 47, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0289] Figure 48 shows an example of the installation position of the imaging unit 12031.

[0290] In Figure 48, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0291] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0292] Figure 48 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0293] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0294] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0295] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0296] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0297] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, each imaging device of the above embodiment can be applied to the imaging unit 12031. By applying the technology of this disclosure to the vehicle control system 12000, it is possible to detect image edges and illumination while suppressing increases in the size and power consumption of the imaging unit 12031.

[0298] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0299] Furthermore, this technology can also take the following configurations: (1) An imaging device comprising a plurality of pixels that output pixel signals, and a detection unit that detects the edges of an image based on the comparison result of two pixel signals and detects the illuminance of the image based on the comparison result of the pixel signals and a reference signal. (2) The imaging device according to (1), further comprising a level setting circuit that sets the signal level of at least one of the two pixel signals by a predetermined gain. (3) The imaging device according to (1) or (2), wherein the detection unit comprises a first comparison unit that compares the two pixel signals and a second comparison unit that compares the pixel signals and the reference signal. (4) The imaging device according to (3), wherein the detection unit comprises a determination unit that determines the edges of the image based on the comparison result of the two pixel signals and determines the illuminance of the image based on the comparison result of the pixel signals and the reference signal. (5) The imaging device according to (3) or (4), further comprising a potential fixing circuit that fixes one of the input potentials of the first comparison unit based on the comparison result of the pixel signals and the reference signal. (6) The imaging apparatus according to (1) or (2), wherein the detection unit is input to the two pixel signals and the reference signal, compares the two pixel signals, and includes a comparison unit that compares the pixel signals with the reference signal. (7) The imaging apparatus according to any one of (1) to (6), wherein the reference signal includes at least one of a threshold, a step signal, and a ramp wave. (8) The imaging apparatus according to any one of (1) to (7), further comprising a holding unit that holds the detection result by the detection unit. (9) The imaging apparatus according to any one of (1) to (8), further comprising a combination circuit that combines the comparison result of the two pixel signals and the comparison result of the pixel signals with the reference signal. (10) The imaging apparatus according to any one of (1) to (9), wherein the detection unit multi-levels the detection result of the illuminance of the pixel signal within the detection area of ​​the edge. (11) The imaging apparatus according to any one of (1) to (9), wherein the detection unit multi-levels the detection result of the illuminance of the pixel signal outside the detection area of ​​the edge. (12) The imaging apparatus according to any one of (1) to (11) above, wherein the detection unit does not detect the edge when the illuminance of the pixel signal is equal to or greater than a threshold.(13) The imaging apparatus according to any one of (1) to (12), wherein the detection unit comprises an amplitude detection unit that detects the amplitude of the pixel signal based on the pixel signal and the reference signal. (14) The imaging apparatus according to (13), wherein the amplitude detection unit comprises a source follower transistor that takes the reference signal as a gate input and the pixel signal as a source input. (15) The imaging apparatus according to (14), further comprising a voltage generation unit connected to the drain of the source follower transistor. (16) The imaging apparatus according to (14) or (15), further comprising a current source that constitutes a source follower with the pixel via a transmission line through which the pixel signal is transmitted, wherein the source follower transistor constitutes a source follower with the current source. (17) The imaging apparatus according to any one of (14) to (16), wherein the source follower transistor is also used as a dummy source follower transistor connected to the transmission line. (18) The imaging apparatus according to any one of (14) to (17), further comprising a switching transistor for disconnecting the source follower transistor from the power supply when the source follower transistor is used as the dummy source follower transistor. (19) The imaging apparatus according to any one of (13) to (18), further comprising a positive feedback unit for setting the potential of the detection result of the amplitude of the pixel signal based on positive feedback of the amplitude detection result of the pixel signal, and an amplitude control unit for blocking the detection of the amplitude of the pixel signal based on the setting of the potential of the detection result of the amplitude of the pixel signal.

[0300] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Storage unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column reading circuit 114 Column signal processing unit 114A Column ADC unit 115 Horizontal scanning circuit 116 Control circuit PX Pixel HCL Horizontal drive line VSL Vertical signal line PD Photodiode FD Floating diffusion TG Transfer transistor 123 Reset transistor 124 Amplifier transistor 125 Selection transistor CT1, CT2 Threshold comparison unit LA1, LB1, LA2, LB2 Level setting circuit CP1, CP2 Comparator BN1 Combination circuit HB1, HB2 Holding unit HX1 Judgment circuit

Claims

1. An imaging device comprising: a plurality of pixels that output pixel signals; and a detection unit that detects image edges based on the comparison result of two pixel signals and detects the illuminance of the image based on the comparison result of the pixel signals and a reference signal.

2. The imaging apparatus according to claim 1, further comprising a level setting circuit for setting the signal level of at least one of the two pixel signals by a predetermined gain.

3. The imaging apparatus according to claim 1, wherein the detection unit comprises a first comparison unit for comparing the two pixel signals and a second comparison unit for comparing the pixel signal with the reference signal.

4. The imaging apparatus according to claim 3, wherein the detection unit determines the edges of the image based on the comparison result of the two pixel signals, and the determination unit determines the illuminance of the image based on the comparison result of the pixel signal and the reference signal.

5. The imaging apparatus according to claim 3, further comprising a potential fixing circuit that fixes one of the input potentials of the first comparison unit based on the comparison result of the pixel signal and the reference signal.

6. The imaging apparatus according to claim 1, wherein the detection unit is input to the two pixel signals and the reference signal, compares the two pixel signals, and includes a comparison unit that compares the pixel signals with the reference signal.

7. The imaging apparatus according to claim 1, wherein the reference signal includes at least one of a threshold signal, a step signal, and a ramp wave.

8. The imaging apparatus according to claim 1, further comprising a holding unit for holding the detection result from the detection unit.

9. The imaging apparatus according to claim 1, further comprising a combination circuit that combines the comparison result of the two pixel signals and the comparison result of the pixel signal and the reference signal.

10. The imaging apparatus according to claim 1, wherein the detection unit multi-levels the detection result of the illuminance of the pixel signal within the detection area of ​​the edge.

11. The imaging apparatus according to claim 1, wherein the detection unit multi-levels the detection result of the illuminance of the pixel signal outside the detection area of ​​the edge.

12. The imaging apparatus according to claim 1, wherein the detection unit outputs the detection result of the illuminance of the pixel signal without detecting the edge when the illuminance of the pixel signal is equal to or greater than a threshold.

13. The imaging apparatus according to claim 1, wherein the detection unit comprises an amplitude detection unit that detects the amplitude of the pixel signal based on the pixel signal and the reference signal.

14. The imaging apparatus according to claim 13, wherein the amplitude detection unit comprises a source follower transistor that takes the reference signal as a gate input and the pixel signal as a source input.

15. The imaging apparatus according to claim 14, further comprising a voltage generating unit connected to the drain of the source follower transistor.

16. The imaging apparatus according to claim 14, comprising a current source that constitutes a source follower with the pixel via a transmission line through which the pixel signal is transmitted, wherein the source follower transistor constitutes a source follower with the current source.

17. The imaging apparatus according to claim 14, wherein the source follower transistor is also used as a dummy source follower transistor connected to the transmission line.

18. The imaging apparatus according to claim 14, further comprising a switching transistor for disconnecting the source follower transistor from the power supply when the source follower transistor is used as the dummy source follower transistor.

19. The imaging apparatus according to claim 13, comprising: a positive feedback unit that sets the potential of the detected amplitude of the pixel signal based on positive feedback of the detection result of the amplitude of the pixel signal; and an amplitude control unit that blocks the detection of the amplitude of the pixel signal based on the setting of the potential of the detected amplitude of the pixel signal.

Images