Power amplifier circuit

Abstract

Provided is a power amplifier circuit capable of generating an appropriate bias and achieving an ideal operation. The power amplifier circuit comprises: a pre-stage amplifier that amplifies an input high-frequency signal; a first post-stage amplifier and a second post-stage amplifier to which an output of the pre-stage amplifier is input; a generation circuit that generates a reference current; a detection circuit that detects a current corresponding to a bias current to be supplied to the pre-stage amplifier; and a first bias circuit that inputs a current corresponding to the current detected by the detection circuit to the second post-stage amplifier as a first bias current, if the current corresponding to the bias current exceeds a current value of the reference current. The output of the first post-stage amplifier and the output of the second post-stage amplifier are combined and output.

Description

Power amplifier circuit

[0001] The present disclosure relates to a power amplifier circuit.

[0002] As a high-efficiency power amplifier circuit, for example, a Doherty amplifier is known (see Patent Document 1, for example). A Doherty amplifier generally has a configuration in which a carrier amplifier that operates regardless of the power level of an input signal and a peak amplifier that is turned off when the power level of the input signal is low and turned on when the power level is high are connected in parallel. In this configuration, when the power level of the input signal is high, the carrier amplifier operates while maintaining saturation at the saturated output power level. Thereby, the Doherty amplifier can improve efficiency compared to a conventional power amplifier circuit.

[0003] Japanese Unexamined Patent Publication No. 2019-41277

[0004] To realize ideal operation of a Doherty amplifier, it is necessary to turn off the bias current of the peak amplifier when the power level of the input signal is low (during back-off), and change the bias current of the peak amplifier in proportion to the input signal when the power level of the input signal is high (when the level exceeds the back-off level). However, in a peak amplifier, self-bias alone makes it difficult to obtain a desired bias current when the power level of the input signal is high, resulting in poor linearity of the bias current. In this regard, the power amplifier circuit disclosed in Patent Document 1 can only generate a bias current that changes in proportion to the input signal. By generating an appropriate bias, ideal operation can be expected to be realized in Doherty amplifiers and other power amplifier circuits.

[0005] The present disclosure has been made in view of the above, and an object thereof is to provide a power amplifier circuit that can generate an appropriate bias and realize ideal operation.

[0006] To solve the above-mentioned problems and achieve the objective, a power amplifier circuit according to one aspect of the present disclosure includes: a preamplifier that amplifies an input high-frequency signal; a first and second postamplifiers that take the output of the preamplifier as input; a generation circuit that generates a reference current; a detection circuit that detects a current corresponding to a bias current supplied to the preamplifier; and a first bias circuit that, when the current corresponding to the bias current exceeds the current value of the reference current, inputs the current corresponding to the current detected by the detection circuit as a first bias current to the second postamplifier, and outputs a combined output of the output of the first postamplifier and the output of the second postamplifier.

[0007] The power amplifier circuit described herein can generate an appropriate bias and achieve ideal operation.

[0008] Figure 1 shows a power amplifier circuit of a comparative example. Figure 2 shows an example of bias current supplied to the peak amplifier of a Doherty amplifier. Figure 3 shows a power amplifier circuit according to the first embodiment of the present disclosure. Figure 4 is a diagram illustrating the operation of the power amplifier circuit shown in Figure 3. Figure 5 is a diagram illustrating the operation of the power amplifier circuit shown in Figure 3. Figure 6 shows an example of a bias circuit configured with an operational amplifier or the like. Figure 7 shows a power amplifier circuit according to the second embodiment of the present disclosure. Figure 8 is a diagram illustrating the operation of each part of the power amplifier circuit shown in Figure 7. Figure 9 is a magnified view of a part of Figure 8. Figure 10 shows a power amplifier circuit according to the third embodiment of the present disclosure. Figure 11 is a diagram illustrating the operation of the power amplifier circuit shown in Figure 10. Figure 12 is a diagram illustrating the operation of the power amplifier circuit shown in Figure 10. Figure 13 is a diagram illustrating the operation of the power amplifier circuit shown in Figure 10.

[0009] The embodiments of this disclosure will be described in detail below with reference to the drawings. In the following descriptions of each embodiment, the same or equivalent components as those in other embodiments will be denoted by the same reference numerals, and their descriptions will be simplified or omitted. This disclosure is not limited by each embodiment. Furthermore, the components of each embodiment include those that are easily substituted or substantially identical to those that a person skilled in the art can do. The configurations described below can be combined as appropriate. Configurations can be omitted, substituted, or modified without departing from the spirit of the invention. In addition, in the second and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted as appropriate, and only the differences will be described. In particular, similar effects and advantages due to similar configurations will not be mentioned sequentially for each embodiment.

[0010] To facilitate understanding of each embodiment, a comparative example will be described first. Then, each embodiment will be described.

[0011] [Comparative Example] Figure 1 shows a comparative example power amplifier circuit 100. In Figure 1, the comparative example power amplifier circuit 100 amplifies the input signal Pin and outputs it as an output signal Pot.

[0012] The power amplifier circuit 100 includes a matching circuit MN1, a preamplifier PA10, a matching circuit MN2, postamplifiers PA11 and PA12, and a matching circuit MN3. The preamplifier PA10 corresponds to the preamplifier of this disclosure. The postamplifier PA11 corresponds to the first postamplifier of this disclosure. The postamplifier PA12 corresponds to the second postamplifier of this disclosure.

[0013] The preamplifier PA10 and the postamplifiers PA11 and PA12 can be implemented by, for example, bipolar transistors, but are not limited to these. Examples of bipolar transistors include heterojunction bipolar transistors (HBTs), but are not limited to these. The transistors may also be, for example, field-effect transistors (FETs). The transistors may also be multi-finger transistors, where multiple unit transistors are electrically connected in parallel. A unit transistor is the minimum configuration that makes up a transistor. If each transistor is an FET, the source corresponds to the emitter of the bipolar transistor, the gate corresponds to the base of the bipolar transistor, and the drain corresponds to the collector of the bipolar transistor.

[0014] The matching circuit MN2 outputs signals with a phase difference of 90 degrees to the subsequent amplifiers PA11 and PA12. In other words, the signals input to subsequent amplifier PA11 and subsequent amplifier PA12 have a phase difference of 90 degrees from each other.

[0015] Furthermore, the power amplifier circuit 100 includes a bias circuit B1 and a bias circuit B2. Bias circuit B1 is connected to the preamplifier PA10. Bias circuit B1 supplies bias current to the preamplifier PA10. Bias circuit B2 is connected to the subsequent amplifier PA11. Bias circuit B2 supplies bias current to the subsequent amplifier PA11.

[0016] Furthermore, the power amplifier circuit 100 includes a constant current source 10, diodes D21 and D22, and transistor Tr2.

[0017] The collector terminal of transistor Tr2 is connected to the battery voltage Vbat. The battery voltage Vbat is the power supply voltage of the portable terminal device on which the power amplification circuit 100 is provided.

[0018] The base terminal of transistor Tr2 is connected to the constant current source 10. A constant current IB_peak output from the constant current source 10 is applied to the base terminal of transistor Tr2. The base terminal of transistor Tr2 is connected to the anode of diode D21. The cathode of diode D21 is connected to the anode of diode D22. The cathode of diode D22 is connected to a reference potential. The reference potential is exemplified by ground potential, but is not limited to this disclosure. The same applies in the following description.

[0019] The emitter terminal of transistor Tr2 is connected to the subsequent amplifier PA12. The current output from the emitter terminal of transistor Tr2 is supplied to the subsequent amplifier PA12 as a bias current.

[0020] Here, the preamplifier PA10 and the subsequent amplifiers PA11 and PA12 operate as, for example, Doherty amplifiers. The preamplifier PA10 is the driver stage. The subsequent amplifiers PA11 and PA12 are the power stages. The subsequent amplifier PA11 operates as a carrier amplifier. The subsequent amplifier PA12 operates as a peak amplifier.

[0021] An ideal Doherty amplifier has its peak amp bias off when the input signal Pin level is low (i.e., during back-off), and a bias current proportional to the input signal Pin when the input signal Pin level is high (exceeding the back-off level). However, in a peak amplifier, it is difficult to achieve the desired bias when the input signal Pin level is high using only the amplifier's self-bias. Therefore, there is a problem of poor linearity when the input signal Pin level is high.

[0022] Generally, in a Doherty amplifier, a constant level of bias current is supplied to the peak amplifier. Figure 2 shows an example of the bias current supplied to the peak amplifier of a Doherty amplifier. As shown in Figure 2, a constant current IB_peak is always supplied to the peak amplifier. Therefore, even when the level of the input signal Pin is small, the peak amplifier remains ON. As a result, the peak amplifier is always consuming current, which reduces the overall efficiency of the power amplification circuit. As will be discussed later, when the bias circuit is configured using an operational amplifier, there is a problem of large operational delay in the operational amplifier.

[0023] Furthermore, in power amplifier circuits other than Doherty amplifiers, gain compression tends to occur when the level of the input signal pin increases. In recent years, the increase in the peak-to-average power ratio (PAPR) of the modulated signal has made it difficult to achieve both high efficiency in average power and high linearity in peak power. That is, reducing the bias current increases the efficiency of average power, but worsens the linearity of peak power. Conversely, increasing the bias current improves the linearity of peak power, but worsens the efficiency of average power.

[0024] [First Embodiment] (Configuration) Figure 3 shows a power amplifier circuit 100a according to the first embodiment of the present disclosure. In Figure 3, the power amplifier circuit 100a according to the first embodiment adds a generation circuit Ref and a current mirror circuit CM10 to the power amplifier circuit 100 of Figure 1. In addition, the power amplifier circuit 100a is provided with a constant current source B12, diodes D11 and D12, and transistor Tr1 instead of bias circuit B1. Note that each part within the region 50 shown by the dashed line in Figure 3 is a CMOS (Comprehensive Metal Oxide Semiconductor) structure.

[0025] The generation circuit Ref generates a reference current Iref. The generation circuit Ref includes transistor Q1, transistor Q2, and a constant current source 10.

[0026] The source terminal of transistor Q1 is connected to the battery voltage Vbat. The gate terminal and drain terminal of transistor Q1 are connected and further connected to one end of the constant current source 10. The other end of the constant current source 10 is connected to a reference potential.

[0027] The source terminal of transistor Q2 is connected to the battery voltage Vbat. The gate terminal of transistor Q2 is connected to the gate and drain terminals of transistor Q1. A reference current Iref is output from the drain terminal of transistor Q2.

[0028] The current mirror circuit CM10 includes transistor Q3 and transistor Q4. The source terminal of transistor Q3 is connected to the battery voltage Vbat. The gate terminal and drain terminal of transistor Q3 are connected.

[0029] The source terminal of transistor Q4 is connected to the battery voltage Vbat. The gate terminal of transistor Q4 is connected to the gate and drain terminals of transistor Q3.

[0030] The drain terminals of transistor Q2 and transistor Q3 are connected at connection point P1. At this connection point P1, the detection current Idet output from the drain terminal of transistor Q3 and the reference current Iref are added together to form current IEC1. Current IEC1 is input to the collector terminal of transistor Tr1, and a bias current corresponding to current IEC1 is supplied to the preamplifier PA10.

[0031] A current mirror current Icm is output from the drain terminal of transistor Q4. The current value of the current mirror current Icm is the current value obtained by multiplying the detection current Idet of transistor Q3 by a predetermined Miller ratio. The current mirror current Icm becomes the base current IB_PA2 to transistor Tr2, and a bias current corresponding to current IB_PA2 is supplied to the subsequent amplifier PA12.

[0032] The Miller ratio described above can be set, for example, during the design phase of the current mirror circuit CM10 by the ratio of the emitter area of ​​transistor Q3 to the emitter area of ​​transistor Q4. The same applies to the Miller ratios of transistors Q1 and Q2.

[0033] (Operation) The generating circuit Ref outputs a reference current Iref. The current value of the reference current Iref is a constant current value determined based on the current flowing through the constant current source 10 and the Miller ratio of transistors Q1 and Q2.

[0034] Transistor Q3 of the current mirror circuit CM10 outputs a detection current Idet. Focusing on the connection point P1, the detection current Idet and the reference current Iref are added together to form current IEC1. As mentioned above, the reference current Iref is a constant value due to the generation circuit Ref. Therefore, if the current value of current IEC1 is less than or equal to the current value of the reference current Iref, the detection current Idet is 0 [mA]. ​​On the other hand, if the current value of current IEC1 exceeds the current value of the reference current Iref, the current value that exceeds the reference current Iref, i.e., the current value obtained by subtracting the current value of the reference current Iref from the current value of current IEC1, is the detection current Idet. The current value that exceeds the current value of current IEC1 increases proportionally to current IEC1 (i.e., changes proportionally).

[0035] Transistor Q4 of the current mirror circuit CM10 outputs a current mirror current Icm. The value of the current mirror current Icm is determined based on the detection current Idet and the mirror ratio of transistors Q3 and Q4. The current mirror current Icm becomes the current IB_PA2 to the base terminal of transistor Tr2, and the bias current output from the emitter terminal of transistor Tr2 is supplied to the subsequent amplifier PA12.

[0036] In other words, transistor Q3 operates as a detection circuit that detects the current IEC1 corresponding to the bias current supplied to the preamplifier PA10. The current IEC1 is proportional to the input signal Pin. Therefore, transistor Q3 of the current mirror circuit CM10 operates as a fast and compact detection circuit. In short, this disclosure focuses on the fact that the current IEC1 supplied to the preamplifier PA10 is proportional to the input signal Pin, and utilizes transistor Q3 of the current mirror circuit CM10 as a circuit that detects the current IEC1.

[0037] Incidentally, in a Doherty amplifier, it is preferable that the bias current of the peak amplifier is turned off when the input signal Pin is small (back-off), and that the bias current becomes proportional to the input signal Pin when the input signal Pin is large (exceeding the current level during back-off).

[0038] Figures 4 and 5 illustrate the operation of the power amplifier circuit 100a shown in Figure 3. Figure 4 shows the relationship between the input signal Pin and the current IEC1. The horizontal axis of Figure 4 represents the level of the input signal Pin [mW]. The vertical axis of Figure 4 represents the level of the current IEC1 [mA].

[0039] As shown in Figure 4, the input signal Pin changes in proportion to the current IEC1 supplied to the preamplifier PA10. That is, when the level of the input signal Pin increases, the level of the current IEC1, which corresponds to the bias current supplied to the preamplifier PA10, increases. When the level of the input signal Pin decreases, the level of the current IEC1 supplied to the preamplifier PA10 decreases. In this way, the current IEC1 changes approximately in proportion to the input signal Pin.

[0040] Figure 5 shows the relationship between the signal Pin envelope, which corresponds to the envelope of the input signal Pin, and the current IB_PA2, which is the bias current to the subsequent amplifier PA12. The horizontal axis of Figure 5 represents the level of the signal Pin envelope. The vertical axis of Figure 5 represents the level of the current IB_PA2.

[0041] As shown in FIG. 5, the region where the level of the signal Pin envelope is low corresponds to a backoff period. During backoff, almost no current IB_PA2 flows, and for example, it is 0 [mA]. On the other hand, in a region where the level of the signal Pin envelope is high, the current IB_PA2 changes linearly in proportion to the signal Pin envelope. In FIG. 5, in the region where the signal Pin envelope exceeds the value P, the current IB_PA2 changes linearly in proportion to the signal Pin envelope.

[0042] (Effect) In the operation described with reference to FIG. 5, when the signal Pin envelope is equal to or less than the value P, the current IB_PA2 is 0 [mA], and when the signal Pin envelope exceeds the value P, the current IB_PA2 changes linearly. It is also conceivable that the bias circuit that realizes this operation is configured by an operational amplifier or the like.

[0043] FIG. 6 is a diagram showing an example of a bias circuit configured by an Operational Amplifier or the like. The bias circuit shown in FIG. 6 includes a comparator 61, a subtraction circuit 62, a multiplication circuit 63, and a selector 64.

[0044] The comparator 61 receives a current IEC1 proportional to input power and a reference current Iref as inputs. The comparator 61 compares the level of the current IEC1 with the level of the reference current Iref.

[0045] The subtraction circuit 62 receives the current IEC1 and the reference current Iref as inputs. The subtraction circuit 62 outputs the difference between the level of the current IEC1 and the level of the reference current Iref. The multiplication circuit 63 multiplies the output of the subtraction circuit 62 by a current mirror ratio CM and outputs the resulting product.

[0046] The selector 64 takes 0 [A] as one input and the output of the multiplication circuit 63 as the other input. Based on the output of the comparator 61, the selector 64 selects one of the two inputs and outputs it as the current IB_PA2.

[0047] In the configuration shown in FIG. 6, when the current IEC1 is equal to or less than the reference current Iref, the selector 64 selects 0 [A], which is one of the inputs. Therefore, when the current IEC1 is equal to or less than the reference current Iref, the current IB_PA2 is 0 [A].

[0048] When the current IEC1 exceeds the reference current Iref, the selector 64 selects the output of the multiplication circuit 63, which is the other of the inputs. Therefore, the current IB_PA2 is a current obtained by multiplying the difference between the current IEC1 and the reference current Iref by the current mirror ratio CM. That is, according to the bias circuit shown in FIG. 6, the current IEC1 is compared with the reference current Iref, and the current IB_PA2 having a level corresponding to the comparison result can be generated.

[0049] However, in the bias circuit shown in FIG. 6, if an operational amplifier is used for each of the comparator 61, the subtraction circuit 62, and the multiplication circuit 63, adopting the configuration of FIG. 6 increases the circuit scale, making it difficult to mount the circuit on a mobile terminal device. In addition, since the operation delay of the operational amplifier is large, it is difficult to perform an operation that follows the frequency of the signal Pin envelope.

[0050] In contrast, the generation circuit Ref and the current mirror circuit CM10 described with reference to FIG. 3 do not use an operational amplifier. Therefore, the operation is faster than that in the case of adopting the circuit of FIG. 6 described above, and the operation can follow the frequency of the signal Pin envelope. Therefore, if the generation circuit Ref and the current mirror circuit CM10 are employed, a region where the current IB_PA2 is constant with respect to the signal Pin envelope (hereinafter referred to as a constant region) and a region where the current IB_PA2 changes linearly with respect to the signal Pin envelope (hereinafter referred to as a linear region) can be realized, and the above-described problems of circuit scale and operation do not occur. Therefore, according to the power amplifier circuit 100a of the first embodiment, an appropriate bias can be generated and an ideal operation can be realized.

[0051] [Second Embodiment] (Configuration) Figure 7 shows a power amplifier circuit 100b according to the second embodiment of the present disclosure. In Figure 7, the power amplifier circuit 100b according to the second embodiment has a configuration in which a constant current source B13 is added to the power amplifier circuit 100a shown in Figure 3. The constant current source B13 is connected to the base terminal of transistor Tr2. The constant current source B13 is connected to the base terminal of transistor Tr2 and the drain terminal of transistor Q4. The constant current source B13 corresponds to the constant current circuit of the present disclosure.

[0052] (Operation) The constant current source B13 operates as a constant current circuit that applies a constant current in the path that supplies the bias current, current mirror current Icm, from the first bias circuit, transistor Q4, to the subsequent amplifier PA12.

[0053] Figure 8 is a diagram illustrating the operation of each part of the power amplifier circuit 100b shown in Figure 7. As explained with reference to Figure 7, in the power amplifier circuit 100b of the second embodiment, a constant current source B13 is added, and a constant current is applied in the middle of the path that supplies the bias current. For this reason, the current IB_PA2 is not 0 [mA] during backoff, but is at a level increased by the current value ΔI. As shown by the solid line J in Figure 8, the current IB_PA2 has a constant region of current value ΔI with respect to the signal Pin envelope, and a linear region that is greater than the value P of the signal Pin envelope. By making the current IB_PA2 a constant region of current value ΔI instead of 0 [mA] during backoff, the response performance when transitioning from the constant region to the linear region can be improved. This will be explained with reference to Figure 9.

[0054] Figure 9 is an enlarged view of a portion of Figure 8. Figure 9 shows an enlarged view of the portion where the solid line J in Figure 8 intersects with the value P. In the power amplifier circuit 100b of the second embodiment, Δt1 is the time taken to transition from a constant current region to a linear region.

[0055] In the bias circuit shown in Figure 6, if one of the inputs of the selector 64 is set to a value higher than 0A, both a constant region and a linear region of the current value ΔI can be achieved. The dashed line H in Figure 9 shows the linear region according to the comparative example shown in Figure 6. Let Δt2 be the time it takes to transition from the constant region to the linear region shown by the dashed line H. As shown in Figure 9, Δt1 < Δt2, and the time Δt1 in the case of the solid line J is shorter than the time Δt2. Therefore, the response performance can be improved according to the power amplifier circuit 100b of the second embodiment.

[0056] (Effect) According to the power amplification circuit 100b of the second embodiment, by supplying bias to the subsequent amplifier PA12 even during back-off, the effect of improving response performance can be obtained.

[0057] [Third Embodiment] (Configuration) Figure 10 shows a power amplifier circuit 100c according to the third embodiment of the present disclosure. In Figure 10, the power amplifier circuit 100c according to the third embodiment has the same configuration as the power amplifier circuit 100a shown in Figure 3, with the addition of a constant current source B13, diodes D31 and D32, and transistor Tr3. The collector terminal of transistor Tr3 is connected to the battery voltage Vbat. The constant current source B13 corresponds to the constant current circuit of the present disclosure.

[0058] The emitter terminals of transistor Tr2 and transistor Tr3 are connected. This connection of emitter terminals causes the current Ibias2a output from the emitter terminal of transistor Tr1 and the current Ibias2b output from the emitter terminal of transistor Tr2 to be added together to form current Ibias2. Current Ibias2 is supplied to the subsequent amplifier PA12.

[0059] In other words, the current Ibias2, which is the sum of the current Ibias2a, corresponding to the current mirror current Icm output from the transistor Q4 (the first bias circuit), and the current Ibias2b, corresponding to the constant current output from the constant current source B13, is supplied to the subsequent amplifier PA12. That is, the constant current output from the constant current circuit is added to the first bias current output from the first bias circuit and supplied to the subsequent amplifier PA12. In this way, the power amplifier circuit 100c combines the output currents of the two bias circuits to obtain the bias current for the subsequent amplifier PA12.

[0060] (Operation) Figures 11 to 13 illustrate the operation of the power amplifier circuit 100c shown in Figure 10. Figures 11 to 13 show examples of current changes in each part of the power amplifier circuit 100c shown in Figure 10.

[0061] Figure 11 shows an example of the current Ibias 2a in Figure 10. As shown in Figure 11, the current Ibias 2a hardly flows in the region where the level of the signal Pin envelope is small. The current Ibias 2a is a current that changes proportionally to the signal Pin envelope when the current value of the signal Pin envelope is greater than the value P.

[0062] Figure 12 shows an example of current Ibias2b in Figure 10. Current Ibias2a is a constant current level regardless of the level of the signal Pin envelope.

[0063] Figure 13 shows an example of current Ibias2 in Figure 10. Current Ibias2 shown in Figure 13 is the sum of current Ibias2a shown in Figure 11 and current Ibias2b shown in Figure 12. Current Ibias2 shown in Figure 13 is at a constant level when the level of the signal Pin envelope is less than or equal to value P, and changes in proportion to the signal Pin envelope when the current value of the signal Pin envelope is greater than value P.

[0064] (Effect) The power amplifier circuit 100c according to the third embodiment has the effect of improving response performance by supplying bias to the subsequent amplifier PA12 even when back-off, similar to the power amplifier circuit 100b of the second embodiment.

[0065] [Modification] In each of the embodiments described above, the constant current source 10 may be a variable current source. By employing a variable current source that can control the current value, it is possible to adjust the value P at which the current IB_PA2 changes linearly from a constant current value.

[0066] Furthermore, a temperature sensor (not shown) may be added, and the current value of the variable current source may be controlled by a signal corresponding to the temperature detected by the temperature sensor. With this configuration, the generation circuit Ref can generate a constant reference current Iref without being affected by temperature changes. This modified example provides a power amplifier circuit that operates similarly to each embodiment without being affected by temperature changes.

[0067] 10, B12, B13 Constant current source 61 Comparator 62 Subtractor circuit 63 Multiplier circuit 64 Selector 100, 100a, 100b, 100c Power amplifier circuit B1, B2 Bias circuit CM10 Current mirror circuit D11, D12, D21, D22, D31, D32 Diodes MN1, MN2, MN3 Matching circuit PA10 Preamplifier PA11, PA12 Postamplifier Q1, Q2, Q3, Q4, Tr1, Tr2, Tr3 Transistor Ref generation circuit

Claims

1. A power amplification circuit comprising: a preamplifier that amplifies an input high-frequency signal; a first and second postamplifier that take the output of the preamplifier as input; a generation circuit that generates a reference current; a detection circuit that detects a current corresponding to the bias current supplied to the preamplifier; and a first bias circuit that, when the current corresponding to the bias current exceeds the current value of the reference current, inputs the current corresponding to the current detected by the detection circuit as a first bias current to the second postamplifier, wherein the output of the first postamplifier and the output of the second postamplifier are combined and output.

2. The power amplifier circuit according to claim 1, wherein the first bias circuit, together with the detection circuit, constitutes a current mirror circuit, and the current mirror circuit supplies to the second downstream amplifier a current amplified by a predetermined mirror ratio from the current detected by the detection circuit as a first bias current.

3. The power amplification circuit according to claim 1 or claim 2, wherein the first downstream amplifier is a carrier amplifier, the second downstream amplifier is a peak amplifier, and the first downstream amplifier and the second downstream amplifier constitute a Doherty amplifier.

4. The power amplifier circuit according to any one of claims 1 to 3, further comprising a constant current circuit that outputs a constant current, wherein the constant current circuit applies the constant current in the middle of the path that supplies the first bias current from the first bias circuit to the second subsequent amplifier.

5. A power amplifier circuit according to any one of claims 1 to 3, further comprising a constant current circuit that outputs a constant current, wherein the constant current output by the constant current circuit is added to the first bias current output from the first bias circuit and supplied to the second subsequent amplifier.

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