MEMS device and manufacturing method therefor

Abstract

This method for manufacturing a MEMS device includes: preparing a first silicon substrate and a second silicon substrate; forming protrusions and recesses on the second silicon substrate; providing a silicon oxide layer on the second silicon substrate along the protrusions and recesses; providing a silicon layer on the silicon oxide layer along the protrusions and recesses; bonding the silicon layer and the first silicon substrate by means of a bonding layer; removing the second silicon substrate bonded to the first silicon substrate; and removing the silicon oxide layer bonded to the first silicon substrate.

Description

MEMS device and method for manufacturing the same

[0001] The present invention relates to a MEMS device and a method for manufacturing the same.

[0002] MEMS devices manufactured using MEMS (Micro Electro Mechanical Systems) technology have been widely spread. MEMS devices are applied, for example, to inertial sensors that detect acceleration and angular velocity based on changes in capacitance. Efforts are being made to improve the performance of MEMS devices through higher density, multi-layer structuring, and other approaches.

[0003] For example, Patent Document 1 discloses a MEMS device in which three polysilicon layers are provided on a supporting substrate.

[0004] U.S. Pat. No. 10,294,095

[0005] However, in the manufacturing of the MEMS device described in Patent Document 1, the three polysilicon layers are provided by being alternately laminated with silicon oxide layers, so that there are constraints on the shape and arrangement of the polysilicon layers. Such low design freedom of polysilicon layers sometimes hinders the performance improvement of MEMS devices.

[0006] The present invention has been made in view of such circumstances, and an object of the present invention is to provide a MEMS device capable of improving design freedom and a method for manufacturing the same.

[0007] A method for manufacturing a MEMS device according to one aspect of the present invention includes: preparing a first silicon substrate and a second silicon substrate; forming irregularities on the second silicon substrate; providing a silicon oxide layer on the second silicon substrate along the irregularities; providing a silicon layer on the silicon oxide layer along the irregularities; bonding the silicon layer and the first silicon substrate via a bonding layer; removing the second silicon substrate bonded to the first silicon substrate; and removing the silicon oxide layer bonded to the first silicon substrate.

[0008] Another embodiment of the present invention provides a MEMS device comprising a first silicon substrate made of single-crystal silicon, a second silicon substrate made of single-crystal silicon, a silicon layer made of polycrystalline silicon or amorphous silicon, a silicon oxide layer provided between the second silicon substrate and the silicon layer, and a bonding layer that joins the first silicon substrate and the silicon layer, wherein the second silicon substrate has irregularities formed on the side facing the first silicon substrate, and the silicon layer is provided along the irregularities of the second silicon substrate.

[0009] According to the present invention, it is possible to provide a MEMS device and a method for manufacturing the same that can improve the degree of design freedom.

[0010] This is a cross-sectional view of a MEMS device according to the first embodiment. This is an enlarged cross-sectional view of a MEMS device according to the first embodiment. This is a flowchart showing a method for manufacturing a MEMS device according to the first embodiment. This is a cross-sectional view showing the manufacturing process of a MEMS device according to the first embodiment. This is a cross-sectional view showing the manufacturing process of a MEMS device according to the first embodiment. This is a cross-sectional view showing the manufacturing process of a MEMS device according to the first embodiment. This is an enlarged cross-sectional view of a MEMS device according to the second embodiment. This is a cross-sectional view showing the manufacturing process third embodiment. This is a cross-sectional view of a MEMS device according to the fourth embodiment. This is a cross-sectional view of a MEMS device according to the fifth embodiment.

[0011] Embodiments of the present invention will be described below with reference to the drawings. The drawings of this embodiment are illustrative, and the dimensions and shapes of each part are schematic; the technical scope of the present invention should not be limited to this embodiment.

[0012] <First Embodiment> First, the configuration of the MEMS device 1 according to the first embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view of the MEMS device according to the first embodiment. Figure 1 is an enlarged cross-sectional view of the MEMS device according to the first embodiment.

[0013] The following describes the various components of the MEMS device 1. Each drawing may, for convenience, include a Cartesian coordinate system consisting of the X, Y, and Z axes to clarify the relationships between the drawings and to help understand the positional relationships of each component. The directions parallel to the X, Y, and Z axes are referred to as the X-axis direction, Y-axis direction, and Z-axis direction, respectively. The plane defined by the X and Y axes is referred to as the XY plane. For convenience, the positive Z-axis direction (direction of the arrow) is described as up or upward, and the negative Z-axis direction (opposite direction of the arrow) is described as down or downward; however, the orientation of the MEMS device 1 is not limited to these. In the following description, the Z-axis direction is referred to as the height direction, depth direction, and thickness direction.

[0014] MEMS device 1 is a device manufactured using MEMS technology. MEMS device 1 comprises a device substrate 10, a device layer 20, a first cover substrate 30, a second cover substrate 40, a first bonding layer 50, and a second bonding layer 60. MEMS device 1 is a capacitive inertial sensor that detects inertial forces (e.g., acceleration and angular velocity) in the X-axis, Y-axis, and Z-axis directions by detecting the capacitance formed by the device substrate 10. The first cover substrate 30, the first bonding layer 50, the device layer 20, the device substrate 10, the second bonding layer 60, and the second cover substrate 40 are stacked in this order in the Z-axis direction. The first cover substrate 30, the first bonding layer 50, the second bonding layer 60, and the second cover substrate 40 constitute a package structure that forms a movable space inside which the device substrate 10 moves.

[0015] The device substrate 10 comprises a silicon substrate F10 and a silicon oxide layer F11. The silicon substrate F10 is formed from a silicon single crystal. The silicon substrate F10 is formed from, for example, a p-type silicon (Si) semiconductor. The silicon substrate F10 may contain boron (B) as a p-type dopant. The resistance of the silicon (Si) used in the silicon substrate F10 is, for example, about 10 mΩ·cm. The silicon substrate F10 is an example of a second silicon substrate.

[0016] The silicon oxide layer F11 is provided on the second lid substrate 40 side of the silicon substrate F10. The silicon oxide layer F11 is formed of silicon oxide mainly composed of SiO2. The silicon oxide layer F11 is provided, for example, by thermal oxidation of the silicon substrate F10, but may also be provided by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0017] As shown in Figure 1, the silicon substrate F10 of the device substrate 10 has movable parts 12A, 12B, support parts 17A, 17B, column part 18, and peripheral part 19. The movable parts 12A, 12B, support parts 17A, 17B, column part 18, and peripheral part 19 are provided by removing the silicon substrate F10. The removal of the silicon substrate F10 is carried out by dry etching, such as deep reactive ion etching (DRIE), but is not limited to this. The removal of the silicon substrate F10 may also be carried out by other methods such as wet etching or laser etching. The movable parts 12A and 12B are examples of first movable parts, the support parts 17A and 17B are examples of first support parts, the column part 18 is an example of a first column part, and the peripheral part 19 is an example of a first peripheral part.

[0018] The movable parts 12A and 12B are configured to move away from the device layer 20 and the second lid substrate 40. For example, movable part 12A is configured to move in the Z-axis direction, and movable part 12B is configured to move in the X-axis direction. The movable parts 12A and 12B are separated from the polysilicon layer K10 (described later) by the thickness of the silicon oxide layer K11 (described later), and separated from the silicon substrate Q10 (described later) by the thickness of the second bonding layer 60 (described later). That is, a movable space is formed between the movable parts 12A and 12B and the polysilicon layer K10 by the silicon oxide layer K11, and a movable space is formed between the movable parts 12A and 12B and the silicon substrate Q10 by the second bonding layer 60. The movable parts 12A and 12B are partially separated from the surrounding silicon substrate F10 by a slit that penetrates the silicon substrate F10 in the Z-axis direction. As a result, the movable parts 12A and 12B are configured to move.

[0019] The movable part 12A is an electrode and weight for detecting inertial force and pressure in the Z-axis direction. As shown in Figure 2, the movable part 12A faces the capacitance forming part 22A of the polysilicon layer K10 (described later) with a gap in the Z-axis direction, and forms a capacitance between the movable part 12A and the capacitance forming part 22A. When the MEMS device 1 is subjected to inertial force and pressure in the Z-axis direction, the movable part 12A is displaced in the Z-axis direction, the gap between the movable part 12A and the capacitance forming part 22A changes, and the capacitance formed by the movable part 12A changes. By detecting this change in capacitance, the inertial force in the Z-axis direction that the MEMS device 1 is subjected to can be detected. Multiple movable parts 12A may be provided on the silicon substrate F10 of the device substrate 10.

[0020] The distance in the Z-axis direction between the movable part 12A and the silicon substrate P10 is greater than the distance in the Z-axis direction between the support part 17A and the silicon substrate P10, and the distance in the Z-axis direction between the column part 18 and the silicon substrate P10. This is because, as shown in Figure 1, a cavity C12A is formed on the silicon substrate P10 side of the silicon substrate F10 in the movable part 12A. The cavity C12A is formed, for example, by providing a patterned mask on the silicon substrate F10, locally thermally oxidizing the silicon substrate F10 through the opening of the mask (LOCOS: Local Oxidation of Silicon), and removing the thermally oxidized region. The method of forming the cavity C12A is not limited to the above, and may be formed, for example, by perpendicular anisotropic reactive ion etching. The cavity C12A is an example of the unevenness of the silicon substrate P10.

[0021] As shown in Figure 2, the movable part 12A is further away from the silicon substrate P10 than the support part 17A and the column part 18, which increases the range of motion of the movable part 12A in the -Z axis direction. This is because the displacement of the movable part 12A in the -Z axis direction is limited by collision with the silicon substrate P10. The increased range of motion of the movable part 12A improves the detection accuracy of the change in capacitance formed by the movable part 12A.

[0022] The movable part 12B is an electrode and weight for detecting inertial force and pressure in the X-axis direction. Multiple movable parts 12B are provided on the silicon substrate F10 of the device substrate 10. As shown in Figure 2, the movable parts 12B are arranged alternately with spacing in the X-axis direction with respect to the capacitance forming part 22B of the polysilicon layer K10, which will be described later, and a capacitance is formed between them and the capacitance forming part 22B. The movable part 12B and the capacitance forming part 22B are so-called comb-tooth electrodes. When the MEMS device 1 is subjected to inertial force and pressure in the Z-axis direction, the movable part 12B is displaced in the Z-axis direction, and the capacitance between the movable part 12B and the capacitance forming part 22B changes. By detecting this change in capacitance, the inertial force in the Z-axis direction that the MEMS device 1 is subjected to can be detected.

[0023] As shown in Figure 1, cavities C12B are formed on the silicon substrate P10 side of the silicon substrate F10 in two adjacent movable parts 12B in the X-axis direction. The cavities C12B are formed on parts of the opposing sides of the two adjacent movable parts 12B. As a result, the gap at the -Z-axis side end of the adjacent movable part 12B is larger than the gap at the +Z-axis side end of the adjacent movable part 12B. The cavities C12B may be formed in the same process as the cavities C12A, and the process for forming the cavities C12B may be different from the process for forming the cavities C12A. The cavities C12B are an example of the irregularities of the silicon substrate P10.

[0024] As shown in Figure 2, a capacitance forming section 22B, described later, is provided inside the gap at the -Z-axis end of the adjacent movable section 12B, i.e., the cavity C12B. In other words, the movable section 12B and the capacitance forming section 22B constitute a comb-tooth electrode that is alternately arranged with a gap in the X-axis direction. Because the movable section 12B and the capacitance forming section 22B constitute a comb-tooth electrode, the opposing area between the movable section 12B and the capacitance forming section 22B is increased, thereby improving the detection accuracy of the change in capacitance formed by the movable section 12B.

[0025] Although not shown in the diagram, the MEMS device 1 may further include a movable part for detecting inertial force and pressure in the Y-axis direction. Such a movable part is, for example, a comb-shaped electrode composed of multiple movable parts arranged in the Y-axis direction. Similar to the movable part 12B, the inertial force and pressure in the Y-axis direction acting on the MEMS device 1 are detected by detecting the change in capacitance formed between the movable part and the capacitance-forming part of the polysilicon layer K10.

[0026] Support portion 17A supports the movable portion 12A. Support portion 17B supports the movable portion 12B. Support portions 17A and 17B are bonded to the device layer 20. This maintains the position of the movable portions 12A and 12B relative to the device layer 20 and the second lid substrate 40. Support portions 17A and 17B are spaced apart from the second lid substrate 40. This suppresses the propagation of stress from the second lid substrate 40 to the movable portions 12A and 12B.

[0027] The column portion 18 supports the entire device substrate 10. The column portion 18 is bonded to the device layer 20 and the second lid substrate 40. This maintains the gap between the device substrate 10 and the device layer 20, and the gap between the device substrate 10 and the second lid substrate 40. A silicon oxide layer F11 is provided on the second lid substrate 40 side of the column portion 18. This silicon oxide layer F11 provided on the second lid substrate 40 side of the column portion 18 has through holes that penetrate in the Z-axis direction. The silicon substrate F10 of the column portion 18 is electrically connected to the second bonding layer 60 through these through holes.

[0028] The peripheral portion 19 is a frame-shaped end along the outer edge of the device substrate 10 when viewed in plan in the Z-axis direction (hereinafter simply referred to as "plan view"). In the plan view, the peripheral portion 19 surrounds the movable portions 12A, 12B, the support portions 17A, 17B, and the column portion 18. The peripheral portion 19 is bonded to the device layer 20 and the second lid substrate 40. This maintains the gap between the device substrate 10 and the device layer 20, and the gap between the device substrate 10 and the second lid substrate 40. A silicon oxide layer F11 is provided on the second lid substrate 40 side of the peripheral portion 19, and this silicon oxide layer F11 electrically insulates the peripheral portion 19 from the second bonding layer 60.

[0029] The device layer 20 includes a polysilicon layer K10 and a silicon oxide layer K11. The polysilicon layer K10 and the silicon oxide layer K11 are provided between the device substrate 10 and the first lid substrate 30.

[0030] The polysilicon layer K10 is provided between the silicon substrate P10 and the silicon substrate F10, along the irregularities of the silicon substrate F10 formed by the cavities C12A and C12B. The polysilicon layer K10 has a portion in contact with the silicon oxide layer K11, a portion facing the silicon oxide layer K11 with a gap between them, and a portion in contact with the silicon substrate F10. The polysilicon layer K10 is made of polycrystalline silicon (polysilicon). The polysilicon layer K10 is an example of a silicon layer, and the silicon layer may be made of amorphous silicon. The polysilicon layer K10 is formed, for example, by chemical vapor deposition. The method for forming the polysilicon layer K10 is not limited to the above, and it may also be formed by modifying amorphous silicon to polysilicon by a method such as excimer laser annealing (ELA).

[0031] The silicon oxide layer K11 is provided between the polysilicon layer K10 and the silicon substrate F10. The silicon oxide layer K11 is formed of silicon oxide mainly composed of silicon dioxide (SiO2). The silicon oxide layer K11 is formed by, for example, thermal oxidation, but the method of forming the silicon oxide layer K11 is not limited to the above and may be formed by chemical vapor deposition or physical vapor deposition, etc.

[0032] As shown in Figure 1, the polysilicon layer K10 of the device layer 20 has capacitance forming portions 22A, 22B, support portions 27A, 27B, column portions 28, and peripheral portions 29. The capacitance forming portions 22A, 22B, support portions 27A, 27B, column portions 28, and peripheral portions 29 are provided by removing the polysilicon layer K10. The removal of the polysilicon layer K10 is carried out by, for example, dry etching, but is not limited to this. The removal of the polysilicon layer K10 may also be carried out by wet etching, laser etching, etc. The capacitance forming portions 22A, 22B are examples of second movable portions, the support portions 27A, 27B are examples of second support portions, the column portions 28 are examples of second column portions, and the peripheral portions 29 are examples of second peripheral portions.

[0033] The capacitance forming sections 22A and 22B are configured to be movable, separated from the device substrate 10 and the first lid substrate 30. The capacitance forming sections 22A and 22B are separated from the silicon substrate F10 by the thickness of the silicon oxide layer K11 and from the silicon substrate P10 by the thickness of the silicon oxide layer H10. That is, a space is formed between the capacitance forming sections 22A and 22B and the silicon substrate F10 by the silicon oxide layer K11, and a space is formed between the capacitance forming sections 22A and 22B and the silicon substrate P10 by the silicon oxide layer H10. As a result, the propagation of stress from the device substrate 10 and the first lid substrate 30 to the capacitance forming sections 22A and 22B is suppressed, and the detection accuracy of the change in capacitance formed by the capacitance forming sections 22A and 22B is improved. The capacitance forming sections 22A and 22B are partially separated from the surrounding polysilicon layer K10 by a slit that penetrates the polysilicon layer K10 in the Z-axis direction. As a result, the volume-forming sections 22A and 22B are configured to be movable.

[0034] The capacitance forming section 22A is an electrode for detecting inertial force and pressure in the Z-axis direction, and forms capacitance with the movable section 12A. The capacitance forming section 22A is provided between the movable section 12A and the silicon substrate P10, and is provided with a gap between it and both the movable section 12A and the silicon substrate P10.

[0035] The capacitance forming section 22B is an electrode for detecting inertial force and pressure in the Z-axis direction, and forms capacitance with the movable section 12B. The capacitance forming section 22B extends from the -Z-axis side of the movable section 12B into the interior of the cavity C12B. As a result, the -Z-axis side end of the movable section 12B and the +Z-axis side end of the capacitance forming section 22B are alternately aligned in the X-axis direction.

[0036] Support portion 27A supports the capacitance forming portion 22A. Support portion 27B supports the capacitance forming portion 22B. Support portions 27A and 27B are bonded to the silicon substrate F10. This maintains the positions of the capacitance forming portions 22A and 22B relative to the device substrate 10 and the first lid substrate 30. Support portion 27A is spaced apart from the first lid substrate 30. This suppresses the propagation of stress from the first lid substrate 30 to the capacitance forming portion 22A.

[0037] The column portion 28 supports the entire device layer 20. The column portion 28 is bonded to the device layer 20 and the first lid substrate 30. A silicon oxide layer K11 is provided between the column portion 28 and the column portion 18, and a silicon oxide layer H10 is provided between the column portion 28 and the silicon substrate P10. This maintains the gap between the device substrate 10 and the device layer 20, and the gap between the device layer 20 and the first lid substrate 30. The column portion 28 is electrically connected to the column portion 18.

[0038] The peripheral portion 29 is a frame-shaped end along the outer edge of the device layer 20 when viewed from above. In a plan view, the peripheral portion 29 surrounds the capacitance forming portions 22A, 22B, the support portions 27A, 27B, and the column portion 28. The peripheral portion 29 is bonded to the device substrate 10 and the first lid substrate 30. A silicon oxide layer K11 is provided between the peripheral portion 29 and the peripheral portion 19, and a silicon oxide layer H10 is provided between the peripheral portion 29 and the silicon substrate P10. This maintains the gap between the device substrate 10 and the device layer 20, and the gap between the device layer 20 and the first lid substrate 30. The peripheral portion 29 is electrically connected to the peripheral portion 19.

[0039] The first lid substrate 30 has a silicon substrate P10, a silicon oxide layer P11, and terminals TM1, TM2, and TM3. The silicon substrate P10 is provided in a flat plate shape, and the side of the silicon substrate P10 facing the device layer 20 is provided in a planar shape. The silicon substrate P10 is formed from a single crystal of silicon. The resistance value of the silicon (Si) used in the silicon substrate P10 is, for example, about 10 mΩ·cm. The silicon substrate P10 is a so-called handle substrate. The silicon substrate P10 is an example of a first silicon substrate. The silicon oxide layer P11 is formed from silicon oxide mainly composed of silicon dioxide (SiO2). The silicon oxide layer P11 is provided on the side of the silicon substrate P10 opposite to the side facing the device layer 20, and on the inner walls of through holes HL1, HL2, and HL3 that penetrate the silicon substrate P10 in the Z-axis direction. The silicon oxide layer P11 electrically insulates terminals TM1, TM2, and TM3 from each other. Terminal TM1 is electrically connected to the column portion 28 through the through hole HL1. Terminal TM1 is, for example, a grounding terminal that electrically grounds the silicon substrate Q10 via the column portion 28, column portion 18, and the second bonding layer 60. Terminals TM2 and TM3 are detection electrodes that are electrically connected to either the capacitance forming portion 22A or 22B through the through holes HL2 or HL3.

[0040] The first bonding layer 50 bonds the device layer 20 and the first lid substrate 30. The first bonding layer 50 has a silicon oxide layer H10. The silicon oxide layer H10 is formed by CVD, for example, which is easier to form in a thicker thickness than by thermal oxidation, but the method of forming the silicon oxide layer H10 is not limited to this. The silicon oxide layer H10 is bonded to the silicon substrate P10 and the polysilicon layer K10. The silicon oxide layer H10 is, for example, formed on the silicon substrate P10 and hydrophilically bonded to the polysilicon layer K10. Alternatively, for example, the silicon oxide layer H10 may be formed on the polysilicon layer K10 and hydrophilically bonded to the silicon substrate P10.

[0041] The first bonding layer 50 has an anchor portion AK and a peripheral bonding portion FL. The anchor portion AK bonds the capacitance forming portions 22A, 22B and the support portions 27A, 27B to the silicon substrate P10. The anchor portion AK supports the polysilicon layer K10 which is spaced apart from the silicon substrate F10. The peripheral bonding portion FL bonds the peripheral portion 29 to the frame-shaped peripheral portion of the silicon substrate P10. The peripheral bonding portion FL is provided in a frame shape in plan view and seals the internal space of the MEMS device 1.

[0042] In this embodiment, a single-layer structure of silicon oxide was used as an example for the first bonding layer, but the first bonding layer is not limited to the above as long as it includes an insulating layer. For example, the first bonding layer may have a layer made of silicon nitride, aluminum nitride, aluminum oxide, or silicon carbide as the insulating layer. The first bonding layer may also have a multilayer structure including an insulating layer. Furthermore, the structure of the first bonding layer may change depending on the location. A change in structure here refers to a change such as switching between a multilayer structure and a single-layer structure depending on the location, or a change in the constituent materials depending on the location. For example, the layer structure of the anchor portion may differ from the layer structure of the peripheral joint portion, and the layer structure of the anchor portion joined to the movable portion may differ from the layer structure of the anchor portion joined to the column portion. Furthermore, the layer structure may change inside the peripheral joint portion or inside the anchor portion.

[0043] The second lid substrate 40 includes a silicon substrate Q10, a silicon oxide layer Q11, an internal wiring WR, and a protruding portion PR. The silicon substrate Q10 is formed in a flat plate shape, and the side of the silicon substrate Q10 facing the device substrate 10 is formed in a planar shape. The silicon substrate Q10 is formed of, for example, a single crystal of silicon. The resistance value of silicon (Si) used for the silicon substrate Q10 is, for example, about 10 mΩ·cm. The silicon oxide layer Q11 is provided on the side of the silicon substrate Q10 facing the device substrate 10. The silicon oxide layer Q11 is formed of silicon oxide containing SiO₂ as a main component. The thickness of the silicon oxide layer Q11 is, for example, larger than the thickness of the silicon oxide layer F11. The silicon oxide layer Q11 is formed by, for example, plasma CVD, which allows easier formation of a thicker layer than thermal oxidation, but the method for forming the silicon oxide layer Q11 is not limited thereto. The internal wiring WR and the protruding portion PR are provided on the device substrate 10 side of the silicon oxide layer Q11. The internal wiring WR is, for example, a wiring that electrically connects each part of the device substrate 10. The internal wiring WR is provided of a metal material, for example, aluminum copper alloy (AlCu). The protruding portion PR is a so-called sticking-preventing protrusion that prevents the movable portion 12A from sticking to the silicon oxide layer Q11. The protruding portion PR is provided by forming an insulating film on the internal wiring WR in a region overlapping with the movable portion 12A in plan view.

[0044] Note that the configuration of the second lid substrate is not limited to the above. The second lid substrate may have, for example, a glass substrate or a ceramic substrate. The second lid substrate may have a composite substrate in which silicon for establishing electrical connection and glass for electrically insulating the silicon from each other are intricately provided.

[0045] The second bonding layer 60 bonds the device substrate 10 and the second lid substrate 40. The second bonding layer 60 is, for example, a eutectic alloy (AlGeTi) of aluminum (Al), germanium (Ge), and titanium (Ti). That is, the device substrate 10 and the second lid substrate 40 are bonded by eutectic bonding. The second bonding layer 60 electrically connects the silicon substrate Q10 and the pillar portion 18.

[0046] Note that the configuration of the second bonding layer is not limited to the above. The second bonding layer may be, for example, a eutectic alloy such as gold-tin eutectic alloy (AuSn) or gold-silicon eutectic alloy (AuSi). The second bonding layer may be provided by, for example, an organic adhesive containing epoxy-based, vinyl-based, acrylic-based, urethane-based or silicone-based resin, or may be provided by a silicon-based adhesive containing water glass or the like. The second bonding layer may be low-melting-point glass (for example, lead borate-based, tin phosphate-based, etc.). However, in order to electrically connect the silicon substrate of the device substrate and the silicon substrate of the second lid substrate, it is preferable that the second bonding layer is formed of a conductive material.

[0047] Next, with reference to FIGS. 3 to 6, a method for manufacturing the MEMS device 1 according to the first embodiment will be described. FIG. 3 is a flowchart showing the method for manufacturing the MEMS device 1 according to the first embodiment. FIGS. 4 to 6 are cross-sectional views showing the manufacturing steps of the MEMS device 1 according to the first embodiment.

[0048] First, a first silicon substrate and a second silicon substrate are prepared (S10). A flat silicon substrate P10 corresponding to the first silicon substrate and a flat silicon substrate F10 corresponding to the second silicon substrate are cut out from a single-crystal silicon ingot. Each main surface of the silicon substrates F10 and P10 is polished to improve flatness.

[0049] Next, irregularities are formed on the second silicon substrate (S20). As shown in Figure 4, cavities C12A and C12B are formed on the silicon substrate F10. Cavities C12A and C12B are formed, for example, by DRIE. In this embodiment, the irregularities are formed by forming cavities, but the method of forming the irregularities is not limited to the above. For example, irregularities may be formed on a flat silicon substrate by forming protrusions with single-crystal silicon, polycrystalline silicon, or amorphous silicon.

[0050] Next, a silicon oxide layer is formed on the second silicon substrate along the irregularities (S30), and a polysilicon layer is formed on the silicon oxide layer along the irregularities (S40). As shown in Figure 5, the silicon oxide layer K11 and the polysilicon layer K10 are formed in this order so as to cover the side of the silicon substrate F10 where cavities C12A and C12B are formed. The thickness T11 of the silicon oxide layer K11 may be smaller or larger than the depth D12A of the cavity C12A. The thickness T11 may be approximately equal to the depth D12A. The thickness T10 of the polysilicon layer K10 may be smaller or larger than the depth D12A of the cavity C12A. The thickness T10 may be approximately equal to the depth D12A. Also, the depth D12B of the cavity C12B may be smaller or larger than the thickness T11 of the silicon oxide layer K11. The thickness T11 may be approximately equal to the depth D12B. Furthermore, the depth D12B of the cavity C12B may be smaller or larger than the thickness T10 of the polysilicon layer K10. The thickness T10 may be approximately equal to the depth D12B. For example, the relationship T10 ≤ D12A ≤ T11 ≤ D12B holds, but the relative sizes of thicknesses T10, T11 and depths D12A, D12B are not limited to this.

[0051] The depth D12A of the cavity C12A is not particularly limited, but increasing the depth D12A allows the movable part 12A to be displaced more significantly in the Z-axis direction. Therefore, the larger the depth D12A, the greater the dynamic range of acceleration and angular velocity that the MEMS device 1 can detect. Accordingly, the depth D12A is preferably 5 μm or more, more preferably 7.5 μm or more, and even more preferably 10 μm or more. On the other hand, decreasing the depth D12A increases the thickness of the movable part 12A and the weight of the movable part 12A. Therefore, the smaller the depth D12A, the greater the sensitivity of the MEMS device 1 to acceleration and angular velocity. Accordingly, the depth D12A is preferably 50 μm or less, more preferably 20 μm or less, and even more preferably 10 μm or less.

[0052] The depth D12B of the cavity C12B is not particularly limited, but increasing the depth D12B increases the area where the movable parts 12B and 22B face each other in the X-axis direction. Therefore, the larger the depth D12B, the larger the capacitance formed between the movable part 12B and the capacitance forming part 22B. In addition, increasing the depth D12B allows the movable part 12B to be displaced more in the Z-axis direction. Therefore, the larger the depth D12B, the larger the dynamic range of acceleration and angular velocity that the MEMS device 1 can detect. For this reason, the depth D12B is preferably 10 μm or more, more preferably 20 μm or more, and even more preferably 30 μm or more. On the other hand, decreasing the depth D12B increases the thickness of the movable part 12B and the weight of the movable part 12B. Therefore, the smaller the depth D12B, the greater the sensitivity of the MEMS device 1 to acceleration and angular velocity. Therefore, the depth D12B is preferably 90 μm or less, more preferably 60 μm or less, and even more preferably 30 μm or less.

[0053] Furthermore, the height T12B of the portion of the polysilicon layer K10 that extends into the cavity C12B and faces the silicon substrate F10 in the X-axis direction is not particularly limited, but increasing the height T12B increases the capacitance formed between the movable part 12B and the capacitance forming part 22B. For this reason, the larger the height T12B, the more the detection noise of the MEMS device 1 can be reduced and the sensitivity can be increased. Therefore, the height T12B is preferably 1 μm or more, more preferably 2.5 μm or more, and even more preferably 5 μm or more. On the other hand, if the depth D12B is the same, reducing the height T12B allows the movable part 12B to be displaced more in the Z-axis direction. For this reason, the smaller the height T12B, the greater the dynamic range of acceleration and angular velocity that the MEMS device 1 can detect. For this reason, the height T12B is preferably 20 μm or less, more preferably 15 μm or less, and even more preferably 10 μm or less.

[0054] Next, the polysilicon layer is removed (S50). The polysilicon layer K10 is removed by etching to form the volume-forming parts 22A, 22B, support parts 27A, 27B, column parts 28, and peripheral parts 29, etc.

[0055] Next, the polysilicon layer and the first silicon substrate are joined (S60). First, a silicon oxide layer H10 is formed on the silicon substrate P10. This silicon oxide layer H10 is removed by etching to form an anchor portion AK and a peripheral joint portion FL. This anchor portion AK and peripheral joint portion FL are joined to the polysilicon layer K10 by hydrophilic bonding. Note that the silicon oxide layer H10 may not be removed in this step S60, but may be removed simultaneously with the silicon oxide layer F11 in step S80, which will be described later, when removing the silicon oxide layer F11.

[0056] After this, the silicon substrate F10 may be thinned by performing back grinding (BG) on the side of the silicon substrate F10 opposite to the side facing the silicon substrate P10. Alternatively, the flatness may be improved by performing chemical mechanical polishing (CMP) on the back-ground surface of the silicon substrate F10. During BG and CMP processing, pressure is applied to the silicon substrate F10 in the direction of the silicon substrate P10. At this time, the anchor portion AK supports the silicon substrate F10, the polysilicon layer K10, and the silicon oxide layer K11, suppressing deformation. Therefore, fluctuations in the thickness of the silicon substrate F10 due to BG and CMP processing are suppressed.

[0057] Next, the second silicon substrate is removed (S70). The silicon oxide layer F11 is provided on the side of the silicon substrate F10 opposite to the side facing the silicon substrate P10. The silicon oxide layer F11 is patterned by etching. Using the patterned silicon oxide layer F11 as a mask, the silicon substrate F10 is removed by DRIE as shown in Figure 6. This removal process forms the movable parts 12A, 12B, support parts 17A, 18B, column parts 18 and peripheral parts 19 of the silicon substrate F10.

[0058] Next, the silicon oxide layer is removed (S80). The silicon oxide layer F11 is etched. At this time, the etchant used to etch the silicon oxide layer F11 is also supplied to the silicon oxide layer K11 through the gaps formed between the movable parts 12A, 12B, the support parts 17A, 18B, the column part 18, and the peripheral part 19. As a result, as shown in Figure 6, both the silicon oxide layer F11 and the silicon oxide layer K11 are etched.

[0059] Next, the second lid substrate is bonded to the device substrate (S90). The second lid substrate 40 is bonded to the device substrate 10 via the second bonding layer 60. The second bonding layer 60 bonds the silicon oxide layer F11 of the device substrate 10 to the silicon oxide layer Q11 of the second lid substrate 40. The second bonding layer 60 is electrically connected to the silicon substrate F10 through through holes formed in the silicon oxide layer F11, and is also electrically connected to the silicon substrate Q10 through through holes formed in the silicon oxide layer Q11. The second bonding layer 60 is formed by sandwiching aluminum (Al), germanium (Ge), and titanium (Ti) between the device substrate 10 and the second lid substrate 40, and heating and pressurizing them to form a eutectic alloy. The silicon substrate Q10 of the second lid substrate 40 bonded to the device substrate 10 may be subjected to BG processing or CMP processing.

[0060] As described above, the method for manufacturing the MEMS device 1 includes preparing silicon substrates P10 and F10, forming irregularities on the silicon substrate F10, providing a silicon oxide layer K11 on the silicon substrate F10 along the irregularities, providing a polysilicon layer K10 on the silicon oxide layer K11 along the irregularities, bonding the polysilicon layer K10 and the silicon substrate P10 with a first bonding layer 50, removing the silicon substrate F10 bonded to the silicon substrate P10, and removing the silicon oxide layer K11 bonded to the silicon substrate P10.

[0061] Furthermore, the MEMS device 1 comprises a silicon substrate P10 made of single-crystal silicon, a silicon substrate F10 made of single-crystal silicon, a polysilicon layer K10, and a silicon oxide layer K11 provided between the silicon substrate F10 and the polysilicon layer K10. The silicon substrate F10 has irregularities formed on the silicon substrate P10 side by cavities C12A and C12B, and the polysilicon layer K10 is provided along the irregularities of the silicon substrate F10.

[0062] According to this, the polysilicon layer K10 can be provided three-dimensionally, rather than in a planar shape along the XY plane. Therefore, the design freedom of the MEMS device 1 can be improved with respect to the relative positions and shapes of the silicon substrate P10, the polysilicon layer K10, and the silicon substrate F10.

[0063] In one embodiment described above, the depth D12A of the cavity C12A of the silicon substrate F10 is greater than the thickness T10 of the polysilicon layer K10.

[0064] In one embodiment described above, the depth D12B of the cavity C12B of the silicon substrate F10 is greater than the thickness T11 of the silicon oxide layer K11.

[0065] In one embodiment described above, the depth D12B of the cavity C12B of the silicon substrate F10 is greater than the sum T10 + T11 of the thickness T10 of the polysilicon layer K10 and the thickness T11 of the silicon oxide layer K11.

[0066] In one embodiment described above, the depth D12A of the cavity C12A of the silicon substrate F10 is smaller than the thickness T11 of the silicon oxide layer K11.

[0067] In one embodiment of the above manufacturing method, the silicon substrate F10 is removed by providing movable parts 12A and 12B that are configured to move away from the polysilicon layer K10, and support parts 17A and 17B that support the movable parts 12A and 12B.

[0068] One embodiment of the above manufacturing method further includes removing the first bonding layer 50 and removing the polysilicon layer K10 bonded to the silicon substrate P10. Removing the polysilicon layer K10 involves providing volume forming portions 22A and 22B that are movable and spaced apart from the silicon substrate P10 and silicon substrate F10, and support portions 27A and 27B that support the volume forming portions 22A and 22B. Removing the first bonding layer 50 involves providing anchor portions AK that bond the support portions 27A and 27B to the silicon substrate P10.

[0069] In one embodiment described above, the irregularities are cavities C12A that increase the distance between the silicon substrate P10 and the silicon substrate F10.

[0070] According to this, the range of motion of the movable part 12A can be increased. By increasing the range of motion of the movable part 12A, the accuracy of detecting changes in capacitance formed by the movable part 12A is improved.

[0071] In one embodiment described above, the depth D12A of the cavity C12A is 5 μm or more.

[0072] According to this, the range of motion of the movable part 12A can be further expanded.

[0073] In one embodiment described above, a capacitance-forming portion 22B, which is part of the polysilicon layer K10, is inserted into the inside of the irregularities, forming a comb-tooth electrode in which the silicon substrate F10 and the polysilicon layer K10 are arranged alternately.

[0074] According to this, the contact area between the silicon substrate F10 and the polysilicon layer K10 becomes larger, thus improving the accuracy of detecting changes in capacitance.

[0075] In one embodiment described above, the height T12B of the polysilicon layer K10 embedded in the uneven surface is 1 μm or more and 20 μm or less.

[0076] According to this method, it is possible to increase the contact area between the silicon substrate F10 and the polysilicon layer K10 while suppressing the decrease in the mechanical strength of the silicon substrate P10 caused by the creation of irregularities.

[0077] In one embodiment described above, the height T12B of the polysilicon layer K10 embedded in the uneven surface is 5 μm or more and 10 μm or less.

[0078] According to this method, it is possible to increase the contact area between the silicon substrate F10 and the polysilicon layer K10 while suppressing the decrease in the mechanical strength of the silicon substrate P10 caused by the creation of irregularities.

[0079] In one embodiment of the above manufacturing method, the silicon substrate P10 and silicon substrate F10 are made of single-crystal silicon.

[0080] In one embodiment described above, the first bonding layer 50 is made of silicon oxide.

[0081] Other embodiments are described below. Components identical or similar to those shown in the first embodiment are denoted by the same or similar reference numerals, and their descriptions are omitted as appropriate. Furthermore, similar effects and benefits from similar components are not mentioned sequentially.

[0082] <Second Embodiment> Next, the configuration of the MEMS device 2 according to the second embodiment of the present invention and its manufacturing method will be described with reference to Figures 7 to 10. Figure 7 is an enlarged cross-sectional view of the MEMS device according to the second embodiment. Figures 8 to 10 are cross-sectional views showing the manufacturing process of the MEMS device according to the second embodiment.

[0083] The MEMS device 2 is a capacitive force sensor that detects forces (pressures) in the X, Y, and Z directions, for example. As shown in Figure 7, the MEMS device 2 comprises a first device substrate 270, a device layer 280, and a second device substrate 290. The first device substrate 270, the device layer 280, and the second device substrate 290 are stacked in this order in the Z-axis direction.

[0084] The first device substrate 270 has a silicon substrate V20. The silicon substrate V20 is formed from a single crystal of silicon. The silicon substrate V20 is, for example, silicon containing boron (B) as a p-type dopant and is formed from silicon with a resistance of about 10 mΩ·cm. The silicon substrate V20 is an example of the first silicon substrate.

[0085] The silicon substrate V20 of the first device substrate 270 is provided with a force receiving portion 278, a peripheral portion 279, and a capacitance forming portion 272. The force receiving portion 278 receives a "force" input from the outside and is displaced in the X-axis direction according to that "force". The peripheral portion 279 is provided in a frame shape so as to surround the force receiving portion 278 and the capacitance forming portion 272 in a plan view. The capacitance forming portion 272 is configured to be movable, separated from the device layer 280. The capacitance forming portion 272 forms a capacitance that changes according to the displacement of the force receiving portion 278 in the X-axis direction. The magnitude of the "force" input from the outside is detected by detecting the change in the capacitance of the capacitance forming portion 272.

[0086] The device layer 280 includes a polysilicon layer K20 and a silicon oxide layer K21. The polysilicon layer K20 and the silicon oxide layer K21 are bonded to each other; the polysilicon layer K20 is bonded to the silicon substrate V20, and the silicon oxide layer K21 is bonded to the silicon substrate W20, which will be described later. The polysilicon layer K20 is made of polycrystalline silicon (polysilicon). The polysilicon layer K20 is an example of a silicon layer, and the silicon layer may be made of amorphous silicon. The silicon oxide layer K21 is formed of silicon oxide mainly composed of silicon dioxide (SiO2).

[0087] A diaphragm portion DP is provided in the polysilicon layer K20 of the device layer 280. The diaphragm portion DP is provided to be movable, spaced apart from the first device substrate 270 and the second device substrate 290. In a plan view, the diaphragm portion DP overlaps with the capacitance forming portion 272 and connects the force receiving portion 298 and the peripheral portion 299, which will be described later. The silicon oxide layer K21 is removed in the diaphragm portion DP.

[0088] The second device substrate 290 has a silicon substrate W20. The silicon substrate W20 is formed from a single crystal of silicon. The silicon substrate W20 is, for example, silicon containing boron (B) as a p-type dopant, and is formed from silicon with a resistance of about 10 mΩ·cm. The silicon substrate W20 is an example of a second silicon substrate.

[0089] The silicon substrate W20 of the second device substrate 290 is provided with a force-receiving portion 298 and a peripheral portion 299. The force-receiving portion 298 of the second device substrate 290 is bonded to the force-receiving portion 278 of the first device substrate 270 via the polysilicon layer K20 and silicon oxide layer K21 of the device layer 280. The peripheral portion 299 of the second device substrate 290 is bonded to the peripheral portion 279 of the first device substrate 270 via the polysilicon layer K20 and silicon oxide layer K21 of the device layer 280. The force-receiving portion 298 receives a "force" input from the outside and is displaced in the X-axis direction according to that "force". The "force" input to the force-receiving portion 298 is transmitted to the force-receiving portion 278. The peripheral portion 299 is provided in a frame shape so as to surround the force-receiving portion 298 in a plan view.

[0090] Next, the manufacturing of the MEMS device 2 will be described. First, as shown in Figure 8, a cavity C20 is formed in the silicon substrate W20. Next, as shown in Figure 9, a silicon oxide layer K21 is provided on the silicon substrate W20 along the cavity C20, and a polysilicon layer K10 is provided on the silicon oxide layer K21 along the cavity C20. The silicon oxide layer K21 and the polysilicon layer K10 cover the entire side of the silicon substrate W20 where the cavity C20 is formed.

[0091] The depth D20 of cavity C20 is preferably greater than the thickness T21 of the silicon oxide layer K21, but may be smaller. The depth D20 of cavity C20 is preferably greater than the thickness T20 of the polysilicon layer K20, but may be smaller. Furthermore, the depth D20 of cavity C20 is preferably greater than the sum of the thickness T21 of the silicon oxide layer K21 and the thickness T20 of the polysilicon layer K20, but may be smaller.

[0092] Next, the polysilicon layer K20 and the silicon substrate V20 are hydrophilically bonded. Then, the silicon substrate V20 is removed by etching to form the force receiving portion 278, the peripheral portion 279, and the capacitance forming portion 272. The silicon substrate W20 is also removed by etching to form the force receiving portion 298 and the peripheral portion 299. Then, the portion of the silicon oxide layer K21 exposed on the silicon substrate W20 side is removed by etching to form the diaphragm portion DP.

[0093] As described above, in the MEMS device 2 according to this embodiment, the polysilicon layer K20 constitutes a diaphragm portion DP that connects the separated portions of the silicon substrate W20.

[0094] In this way, by forming the polysilicon layer K20 three-dimensionally along the cavity C20 of the silicon substrate W20, the diaphragm portion DP, which is separated from the silicon substrate V20, can be constructed from the polysilicon layer K20.

[0095] In one embodiment described above, the depth D20 of the cavity C20 of the silicon substrate W20 is greater than the thickness T21 of the silicon oxide layer K21.

[0096] According to this, the diaphragm portion DP can be sufficiently separated from the capacitance forming portion 272. Therefore, when the diaphragm portion DP is deformed and when the capacitance forming portion 272 is displaced in the Z-axis direction, contact between the diaphragm portion DP and the capacitance forming portion 272 can be suppressed.

[0097] In one embodiment described above, the depth D20 of the cavity C20 of the silicon substrate W20 is greater than the thickness T20 of the polysilicon layer K20. Also, the depth D20 of the cavity C20 of the silicon substrate W20 is greater than the sum of the thickness T20 of the polysilicon layer K20 and the thickness T21 of the silicon oxide layer K21.

[0098] According to this, the diaphragm portion DP can be further separated from the capacitance forming portion 272.

[0099] Furthermore, the silicon substrate V20 of the first device substrate 270 may further have a capacitance forming portion that forms a capacitance that changes according to the displacement of the force receiving portion 278 in the Y-axis direction, and may further have a capacitance forming portion that forms a capacitance that changes according to the displacement of the force receiving portion 278 in the Z-axis direction.

[0100] <Third Embodiment> Next, the configuration of the MEMS device 3 according to the third embodiment of the present invention will be described with reference to Figure 11.

[0101] As shown in Figure 11, the MEMS device 3 differs from the MEMS device 2 according to the second embodiment in that the first bonding layer 50 is provided by a polysilicon layer H11 and a silicon nitride layer H12.

[0102] The polysilicon layer H11 and the silicon nitride layer H12 are bonded to each other. The polysilicon layer H11 is bonded to the silicon substrate P10, and the silicon nitride layer H12 is bonded to the polysilicon layer K10. The polysilicon layer H11 is made of polycrystalline silicon (polysilicon). The polysilicon layer H11 is an example of a silicon layer, and the silicon layer may be made of amorphous silicon. The silicon nitride layer H12 is made of silicon nitride. Regarding etching resistance to vapor hydrofluoric acid (Vapor HF) and aqueous hydrofluoric acid (HF) solutions, which are etchants for etching silicon oxide, the polysilicon layer H11 and the silicon nitride layer H12 have higher etching resistance than silicon oxide.

[0103] According to this embodiment, when etching silicon oxide, aid etching of the polysilicon layer H11 and silicon nitride layer H12 can be suppressed. Therefore, the anchor portion AK can be designed to be narrow, and the volume forming portions 22A, 22B and support portions 27A, 27B supported by the anchor portion AK can also be designed to be narrow. Therefore, the MEMS device 3 can be miniaturized and made denser.

[0104] <Fourth Embodiment> Next, the configuration of the MEMS device 4 according to the fourth embodiment of the present invention will be described with reference to Figure 12.

[0105] As shown in Figure 12, the MEMS device 4 differs from the MEMS device 1 according to the first embodiment in that protrusions P1A and P1B are provided on the second lid substrate 40 side of the silicon substrate F10.

[0106] The protrusions P1A and P1B are part of the silicon substrate F10 and protrude toward the second lid substrate 40. Protrusion P1A is provided, for example, on the support portion 17A. The tip of protrusion P1A abuts against the internal wiring WR or silicon oxide layer Q11 of the second lid substrate 40, and protrusion P1A maintains the gap between the silicon substrate F10 of the device substrate 410 and the silicon oxide layer Q11 of the second lid substrate 40. Protrusion P1B is provided, for example, on the movable portion 12A. Protrusion P1B is spaced apart from the second lid substrate 40 and prevents the movable portion 12A from sticking to the silicon oxide layer Q11. Protrusions P1A and P1B are formed, for example, by removing the thermal oxidation region with LOCOS. Protrusion P1A is an example of the first protrusion.

[0107] As described above, the manufacturing method of the MEMS device 4 according to this embodiment further includes joining the second lid substrate 40 and the silicon substrate F10, thereby forming a gap between the second lid substrate 40 and the silicon substrate F10.

[0108] In one embodiment described above, a protrusion P1A for maintaining a gap is provided on the second lid substrate 40 side of the silicon substrate F10, and the tip of the protrusion P1A is in contact with the second lid substrate 40. The tip of the protrusion P1A may also be joined to the second lid substrate 40.

[0109] According to this, contact between the movable parts 12A and 12B of the device substrate 410 and the second cover substrate 40 can be suppressed. This makes it possible to suppress damage caused by contact between the silicon substrate F10 and the silicon oxide layer Q11.

[0110] <Fifth Embodiment> Next, the configuration of the MEMS device 5 according to the fifth embodiment of the present invention will be described with reference to Figure 13.

[0111] As shown in Figure 13, the MEMS device 5 differs from the MEMS device 1 according to the first embodiment in that the second lid substrate 540 has protrusions P4A and P4B on the device substrate 10 side.

[0112] The protrusions P4A and P4B are provided by forming protrusions on the silicon substrate Q10 and protrude toward the device substrate 10. Protrusion P4A is provided, for example, in a region that becomes the support portion 17A in a plan view. The tip of protrusion P4A abuts against the support portion 17A on the silicon substrate F10 of the device substrate 10, and protrusion P4A maintains the gap between the silicon substrate F10 of the device substrate 10 and the silicon oxide layer Q11 of the second lid substrate 540. Protrusion P4B is provided, for example, in a region that overlaps with the movable portion 12A in a plan view. Protrusion P4B is spaced apart from the silicon substrate F10 of the device substrate 10 and prevents the movable portion 12A from sticking to the silicon oxide layer Q11. Protrusions P4A and P4B are formed, for example, by removing the thermal oxidation region with LOCOS. Protrusion P4A is an example of a second protrusion.

[0113] As described above, a protrusion P4A for maintaining a gap is provided on the silicon substrate F10 side of the second lid substrate 540, and the tip of the protrusion P4A is in contact with the silicon substrate F10. The tip of the protrusion P4A may also be bonded to the silicon substrate F10 of the device substrate 10.

[0114] This makes it possible to suppress contact between the movable parts 12A and 12B of the device substrate 10 and the second cover substrate 540. As a result, it is possible to suppress damage caused by contact between the silicon substrate F10 and the silicon oxide layer Q11.

[0115] The embodiments of the present invention are not particularly limited and can be appropriately applied to any sensor that detects changes in capacitance, such as an inertial sensor like an acceleration sensor or a gyroscope, or a pressure sensor.

[0116] As described above, according to one aspect of the present invention, a MEMS device and a method for manufacturing the same can be provided that can improve the degree of design freedom.

[0117] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. The present invention can be modified or improved without departing from its spirit, and equivalents thereof are also included. That is, any design modifications made to each embodiment by those skilled in the art are also included within the scope of the present invention, as long as they retain the features of the present invention. For example, the elements of each embodiment, their arrangement, materials, conditions, shapes, sizes, etc., are not limited to those exemplified and can be modified as appropriate. Furthermore, the elements of each embodiment can be combined to the extent that it is technically possible, and any combination thereof is also included within the scope of the present invention, as long as it retains the features of the present invention.

[0118] 1…MEMS device 10…Device substrate 12A, 12B…Movable part 17B, 17C…Support part 18…Column part 19…Peripheral part F10…Silicon substrate F11…Silicon oxide layer 20…Device layer 22A, 22B…Capacitance forming part 27A, 27B…Support part 28…Column part 29…Peripheral part K10…Polysilicon layer K21…Silicon oxide layer 30…First lid substrate P10…Silicon substrate P11…Silicon oxide layer 40…Second lid substrate Q10…Silicon substrate Q11…Silicon oxide layer 50…First bonding layer AK…Anchor part FL…Peripheral bonding part H10…Silicon oxide layer 60…Second bonding layer

Claims

1. A method for manufacturing a MEMS device, comprising: preparing a first silicon substrate and a second silicon substrate; forming irregularities on the second silicon substrate; providing a silicon oxide layer on the second silicon substrate along the irregularities; providing a silicon layer on the silicon oxide layer along the irregularities; bonding the silicon layer and the first silicon substrate with a bonding layer; removing the second silicon substrate bonded to the first silicon substrate; and removing the silicon oxide layer bonded to the first silicon substrate.

2. The method for manufacturing a MEMS device according to claim 1, wherein the depth of the irregularities on the second silicon substrate is greater than the thickness of the silicon layer.

3. The method for manufacturing a MEMS device according to claim 1 or 2, wherein the depth of the irregularities on the second silicon substrate is greater than the thickness of the silicon oxide layer.

4. The method for manufacturing a MEMS device according to any one of claims 1 to 3, wherein the depth of the irregularities on the second silicon substrate is greater than the sum of the thickness of the silicon layer and the thickness of the silicon oxide layer.

5. The method for manufacturing a MEMS device according to claim 1 or 2, wherein the depth of the irregularities on the second silicon substrate is less than the thickness of the silicon oxide layer.

6. The method for manufacturing a MEMS device according to any one of claims 1 to 5, wherein the removal process of the second silicon substrate involves providing a first movable part that is configured to be movable away from the silicon layer and a first support part that supports the first movable part.

7. A method for manufacturing a MEMS device according to any one of claims 1 to 6, further comprising: removing the bonding layer; and removing the silicon layer bonded to the first silicon substrate, wherein the removal of the silicon layer involves providing a second movable part configured to be movable away from the first silicon substrate and the second silicon substrate, and a second support part that supports the second movable part; and the removal of the bonding layer involves providing an anchor part that bonds the second support part to the first silicon substrate.

8. The method for manufacturing a MEMS device according to any one of claims 1 to 7, wherein the irregularities are cavities that increase the distance between the first silicon substrate and the second silicon substrate.

9. The method for manufacturing a MEMS device according to claim 8, wherein the depth of the irregularities is 5 μm or more.

10. The method for manufacturing a MEMS device according to any one of claims 1 to 7, wherein the silicon layer constitutes a diaphragm portion connecting the separated portions of the second silicon substrate.

11. A method for manufacturing a MEMS device according to any one of claims 1 to 7, wherein a portion of the silicon layer is embedded inside the irregularities, and the second silicon substrate and the silicon layer are arranged alternately to form a comb-tooth electrode.

12. The method for manufacturing a MEMS device according to claim 11, wherein the height of the silicon layer embedded in the irregularities is 1 μm or more and 20 μm or less.

13. The method for manufacturing a MEMS device according to claim 11, wherein the height of the silicon layer embedded in the irregularities is 5 μm or more and 10 μm or less.

14. A method for manufacturing a MEMS device according to any one of claims 1 to 13, wherein the first silicon substrate and the second silicon substrate are made of single-crystal silicon.

15. The method for manufacturing a MEMS device according to any one of claims 1 to 14, wherein the bonding layer is made of silicon oxide.

16. The method for manufacturing a MEMS device according to any one of claims 1 to 14, wherein the bonding layer comprises a silicon nitride layer and a second silicon layer made of polycrystalline silicon or amorphous silicon.

17. A method for manufacturing a MEMS device according to any one of claims 1 to 16, further comprising joining a lid substrate and the second silicon substrate, wherein a gap is formed between the lid substrate and the second silicon substrate.

18. A first protrusion for holding the gap is provided on the lid substrate side of the second silicon substrate, and the tip of the first protrusion abuts against or connects to the lid substrate, the method for manufacturing a MEMS device according to claim 17.

19. A second protrusion for holding the gap is provided on the second silicon substrate side of the lid substrate, and the tip of the second protrusion abuts against or connects to the second silicon substrate, the method for manufacturing a MEMS device according to claim 17 or 18.

20. A MEMS device comprising: a first silicon substrate made of single-crystal silicon; a second silicon substrate made of single-crystal silicon; a silicon layer made of polycrystalline silicon or amorphous silicon; a silicon oxide layer provided between the second silicon substrate and the silicon layer; and a bonding layer that joins the first silicon substrate and the silicon layer, wherein the second silicon substrate has irregularities formed on the side facing the first silicon substrate, and the silicon layer is provided along the irregularities of the second silicon substrate.

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