Imaging device

Abstract

[Problem] To provide an imaging device capable of improving image quality by suppressing capacitive coupling between adjacent pixels. [Solution] An imaging device according to the present embodiment comprises: a plurality of pixels each including a photoelectric conversion section that photoelectrically converts incident light into a pixel signal, a holding section including first and second capacitive elements that hold the pixel signal from the photoelectric conversion section, and an amplification section that amplifies and outputs the pixel signal held by the holding section; and a shielding section that is provided between the plurality of adjacent pixels and is maintained at a predetermined fixed voltage or the voltage of the pixel signal.

Description

Image pickup apparatus

[0001] The present disclosure relates to an image pickup apparatus.

[0002] A CMOS (Complementary Metal Oxide Semiconductor) image sensor (hereinafter also referred to as CIS) may employ a global shutter system (hereinafter also referred to as GS system) that performs an exposure operation collectively for all effective pixels.

[0003] Japanese Unexamined Patent Application Publication No. 2022-45912 US Patent Publication No. 2020 / 0058688

[0004] In a GS-type CIS, in order to hold signals of all effective pixels, each pixel is provided with a sample-and-hold circuit (hereinafter also referred to as an SH circuit). The SH circuit includes a capacitor for holding a signal of a corresponding pixel. However, between adjacent pixels, there has been a problem that capacitive coupling between the capacitors degrades image quality.

[0005] The present technology has been made in view of such problems, and provides an image pickup apparatus capable of suppressing capacitive coupling between adjacent pixels and improving image quality.

[0006] An image pickup apparatus according to one aspect of the present disclosure includes: a plurality of pixels each including a photoelectric conversion unit that photoelectrically converts incident light into a pixel signal, a holding unit including first and second capacitive elements that hold the pixel signal from the photoelectric conversion unit, and an amplification unit that amplifies and outputs the pixel signal held by the holding unit; and a shielding unit provided between a plurality of adjacent pixels, the shielding unit being maintained at a predetermined fixed voltage or a voltage of a pixel signal.

[0007] The shielding unit has the same configuration as the first and second capacitive elements.

[0008] The first capacitive element, the second capacitive element, and the shielding unit have a stacked structure of a first metal film, a first insulating film, and a second metal film.

[0009] The first capacitive element, the second capacitive element, and the shielding unit are configured by arranging a plurality of columnar bodies each having a stacked structure.

[0010] The first capacitance element, the second capacitance element, and one end of the shielding section are electrically connected in common to the photoelectric conversion section.

[0011] The other end of the shielding section is connected to a fixed voltage source, or to one end of the shielding section.

[0012] The holding section includes a first switching element provided between the amplification section and the other end of the first capacitance element, and a second switching element provided between the amplification section and the other end of the second capacitance element.

[0013] The imaging device further comprises an AD (Analogue-to-Digital) conversion unit that converts pixel signals into digital signals, a first drive unit that reads pixel signals from multiple pixels in a row selected by address to the AD conversion unit, and a signal processing circuit that generates image data using the digital signals from the AD conversion unit.

[0014] The first capacitance element holds the pixel signal, which does not contain charge due to incident light, as a reset signal, and the second capacitance element holds the pixel signal, which contains charge due to incident light, as a data signal. The shielding portion is arranged adjacent to each of the second capacitance elements of multiple pixels.

[0015] The shielding portion of the first pixel among the multiple pixels is positioned between the second capacitive element of the first pixel and the second pixel adjacent to the first pixel.

[0016] In a planar layout of multiple pixels, the pixels are arranged in a translationally symmetric manner, and the shielding portion is positioned between the pixels, between the second capacitance element of the first pixel and the first capacitance element of the second pixel adjacent to the first pixel.

[0017] In a planar layout of multiple pixels, the pixels are arranged in a mirror-image symmetrical manner, and the shielding portion is positioned between the multiple pixels, between the second capacitive element of the first pixel and the second capacitive element of the second pixel adjacent to the first pixel.

[0018] In a planar layout of multiple pixels, the occlusion portion is positioned along two sides of the outer edge of the pixel.

[0019] In a planar layout of multiple pixels, the occlusion portion is located along the entire outer edge of the pixel.

[0020] In a planar layout of multiple pixels, the shielding portion is positioned between the first and second capacitance elements of each of the multiple pixels.

[0021] In a planar layout of multiple pixels, the shielding portion is arranged along one side of the outer edge of the second capacitance element, extending over a region longer than that side.

[0022] Each of the multiple pixel holding sections further includes third and fourth capacitive elements that hold pixel signals different in conversion efficiency from the pixel signals held by the first and second capacitive elements in the photoelectric conversion section, the third capacitive element holds a pixel signal that does not contain charge due to incident light as a reset signal, the fourth capacitive element holds a pixel signal that contains charge due to incident light as a data signal, and shielding sections are provided between the first and third capacitive elements and between the second and fourth capacitive elements.

[0023] Each of the multiple pixel holding sections further includes fifth and sixth capacitive elements that hold pixel signals different in conversion efficiency from the pixel signals held by the first to fourth capacitive elements in the photoelectric conversion section, the fifth capacitive element holds a pixel signal that does not contain charge due to incident light as a reset signal, and the sixth capacitive element holds a pixel signal that contains charge due to incident light as a data signal, and the shielding sections are provided between the first and third capacitive elements, between the second and fourth capacitive elements, between the third and fifth capacitive elements, and between the fourth and sixth capacitive elements.

[0024] A block diagram showing an example configuration of an imaging device according to the first embodiment. A conceptual diagram showing an example of an imaging device in which semiconductor chips for the pixel section and semiconductor chips for the processing circuit are stacked. A circuit diagram showing an example of the internal configuration of a pixel according to the first embodiment. A plan view showing an example configuration of the first and second capacitance elements and shielding section of the SH circuit according to the first embodiment. A cross-sectional view showing an example configuration of the first capacitance element, second capacitance element and shielding section of the SH circuit according to the first embodiment. A cross-sectional view showing a more detailed example configuration of the columnar bodies of the first capacitance element, second capacitance element and shielding section. A plan view showing an example configuration of the first capacitance element, second capacitance element and shielding section of the SH circuit according to the second embodiment. A plan view showing an example configuration of the first capacitance element, second capacitance element and shielding section of the SH circuit according to the third embodiment. A plan view showing an example configuration of the first capacitance element, second capacitance element and shielding section of the SH circuit according to the fourth embodiment. A plan view showing an example configuration of the first capacitance element, second capacitance element and shielding section of the SH circuit according to the fifth embodiment. A plan view showing an example configuration of the first capacitance element, second capacitance element, and shielding section of the SH circuit according to the sixth embodiment. A plan view showing an example configuration of the first capacitance element, second capacitance element, and shielding section of the SH circuit according to the seventh embodiment. A plan view showing an example configuration of the first capacitance element, second capacitance element, and shielding section of the SH circuit according to the eighth embodiment. A circuit diagram showing an example configuration of the photoelectric conversion section according to the ninth embodiment. A plan view showing an example configuration of the first capacitance element, second capacitance element, and shielding section of the SH circuit according to the ninth embodiment. A circuit diagram showing an example configuration of the SH circuit according to the tenth embodiment. A plan view showing an example configuration of the first capacitance element, second capacitance element, and shielding section of the SH circuit according to the tenth embodiment. A plan view showing an example configuration of the first to fourth capacitance elements and shielding section of the SH circuit according to the eleventh embodiment. A circuit diagram showing an example configuration of the photoelectric conversion section and SH circuit according to the twelfth embodiment. A plan view showing an example configuration of the first capacitance element, second capacitance element, and shielding section of the SH circuit according to the twelfth embodiment. A plan view showing an example configuration of the first to fourth capacitance elements and the shielding section of the SH circuit 20 according to the 13th embodiment.

[0025] The following describes specific embodiments of this technology with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0026] (First Embodiment) Figure 1 is a block diagram showing an example configuration of an imaging device 100 according to the first embodiment. The imaging device 100 is a VDGS (Voltage Domain GS) type CIS used, for example, in industrial machinery. The VDGS type CIS is a GS type CIS that holds the voltage of the pixel signal and performs AD conversion for readout based on the held voltage.

[0027] The imaging device 100 includes a pixel unit 101, a controller 102, a vertical scanning circuit 103, a DAC (digital-to-analog converter) 104, an ADC (analog-to-digital converter) group 105, a horizontal transfer scanning circuit 106, and a signal processing circuit 108.

[0028] The pixel section 101 has a matrix arrangement of unit pixels (hereinafter simply referred to as pixels) which include a photoelectric conversion unit that photoelectrically converts incident light into an amount of charge (pixel signal) corresponding to the amount of light. The specific circuit configuration of the pixels will be described later with reference to Figure 2. In addition, for each row of the matrix-like pixel array in the pixel section 101, pixel drive lines 109 are wired along the left-right direction in the figure (the pixel array direction of the pixel row / horizontal direction), and vertical signal lines 110 are wired along the up-down direction in the figure (the pixel array direction of the pixel column / vertical direction). One end of each pixel drive line 109 is connected to the output terminal corresponding to each row of the vertical scanning circuit 103. The pixel drive lines 109 can be selected by address. In Figure 1, one pixel drive line 109 is shown for each pixel row, but two or more pixel drive lines 109 may be provided for each pixel row.

[0029] The controller 102 generates various control signals at predetermined timings. Based on the CTL signal provided from an external source, the controller 102 generates various control signals and performs drive control of the vertical scanning circuit 103, DAC 104, ADC group 105, and horizontal transfer scanning circuit 106, etc.

[0030] The vertical scanning circuit 103 is composed of a shift register, an address decoder, and the like. The vertical scanning circuit 103 selectively drives one or more pixel drive lines 109 based on an address from the controller 102. As a result, the vertical scanning circuit 103 reads pixel signals from a row of pixels specified by the address among the multiple pixels of the pixel unit 101 to the AD conversion unit. The specific configuration is not shown in the diagram, but the vertical scanning circuit 103 includes a read scanning system and a sweep scanning system.

[0031] The readout scanning system performs sequential selective scanning row by row for each unit of signal readout. Meanwhile, the sweep system sweeps out (resets) unwanted charges from the photoelectric conversion units of all effective pixels in the pixel unit 101 all at once. By controlling the sweeping out (reset) of unwanted charges by this sweep system, a so-called simultaneous electronic shutter operation for all effective pixels is performed. Here, electronic shutter operation refers to the operation of stopping the discharge of photoelectric charge from a state in which photoelectric charge is continuously discharged and starting new exposure (accumulation of photodiode PD). The readout scanning starts after raising the readout operation trigger signal and transferring the reset signal and data signal of the pixel signals of all effective pixels in the pixel unit 101 all at once to the sample-and-hold circuit (20 in Figure 3). After transferring the pixel signals to the sample-and-hold circuit 20, the readout scanning reads the pixel signals to the ADC group 105 by scanning pixel row by pixel. The signals read out by the readout operation of the readout scanning system correspond to the amount of light incident after the electronic shutter operation. The period from the end of the simultaneous sweep operation by the preceding electronic shutter operation to the end of the simultaneous transfer of pixel signals from all effective pixels to the sample-and-hold circuit (20 in Figure 3) becomes the photocharge accumulation time (exposure time) for a single pixel.

[0032] The pixel signal SIG (analog signal) output from each unit pixel of a pixel row selected and scanned by the vertical scanning circuit 103 using row addresses is read out to the ADC group 105 via a plurality of vertical signal lines 110 corresponding to each column.

[0033] The DAC 104 generates a linearly changing ramp waveform reference signal RAMP and supplies it to the ADC group 105. The DAC 104 is commonly connected to multiple comparators 121 via a reference signal line 114 and supplies the same reference signal RAMP to multiple comparators 121.

[0034] The ADC group 105 comprises a plurality of comparators 121, a plurality of counters 122, and a plurality of latch circuits 123. The ADC group 105 converts the pixel signal (analog signal) from the pixel unit 101 into a digital signal.

[0035] The comparator 121, counter 122, and latch circuit 123 are each provided corresponding to the pixel rows of the pixel section 101, and constitute an ADC.

[0036] The comparator 121 compares the pixel signal SIG output from each pixel with the reference signal RAMP and supplies an output signal indicating the comparison result to the counter 122. The comparator 121 inverts the output signal based on the relative magnitudes of the voltages of the pixel signal SIG and the reference signal RAMP.

[0037] Counter 122 is provided in correspondence with comparator 121. Counter 122 receives the output signal of comparator 121 and counts the time from the start of driving the reference signal RAMP until the output signal of comparator 121 inverts, generating a count value. This converts the analog pixel signal SIG into a digital signal represented by the count value. Counter 122 supplies the count value to latch circuit 123. Counter 122 counts the count value of the reset signal corresponding to the pixel signal at the reset level, which does not contain charge due to incident light, and counts the data signal corresponding to the signal level pixel signal, subtracting this count value of the reset signal. The reset signal is the pixel signal of the reset state, which does not contain charge due to incident light. The data signal is the pixel signal which contains charge due to incident light. As a result, counter 122 performs CDS (Correlated Double Sampling) between the reset signal and the data signal. Counter 122 may count the reset signal and the data signal separately and perform CDS processing in latch circuit 123.

[0038] The latch circuit 123 holds the count value obtained by the CDS process, which is supplied from the counter 122. Alternatively, the latch circuit 123 may hold the count value of the data signal corresponding to the signal level of the pixel signal from the counter 122, and the count value of the reset signal corresponding to the reset level of the pixel signal from the counter 122, and perform CDS by taking the difference between the two.

[0039] The horizontal transfer scanning circuit 106 is composed of a shift register, an address decoder, and the like, and sequentially selects and scans the circuit portion corresponding to the pixel sequence of the ADC group 105 according to the address. Through this selective scanning by the horizontal transfer scanning circuit 106, the digital signals held in the latch circuit 123 are sequentially transferred to the signal processing circuit 108 via the horizontal transfer line 111.

[0040] The signal processing circuit 108 performs predetermined signal processing on the digital signal supplied from the ADC group 105 to generate two-dimensional image data. For example, the signal processing circuit 108 performs correction of vertical line defects and point defects, clamps signals, and performs digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation.

[0041] Furthermore, the imaging device 100 shown in FIG. 1 may be configured as one semiconductor chip as a whole, or may be configured with a plurality of semiconductor chips. When the imaging device 100 is configured as a plurality of semiconductor chips, the pixel unit 101 and other processing circuits may be formed as separate semiconductor chips 511 and 512 respectively, and the semiconductor chip 511 and the semiconductor chip 512 may be stacked.

[0042] For example, FIG. 2 is a conceptual diagram showing an example of the imaging device 100 in which the semiconductor chip 511 of the pixel unit 101 and the semiconductor chip 512 of the processing circuit are stacked. As shown in FIG. 2, the imaging device 100 is configured of two stacked semiconductor chips 511 and 512. Note that the number of stacked semiconductor chips may be three or more.

[0043] The semiconductor chip 511 includes the pixel unit 101 formed on a semiconductor substrate. The semiconductor chip 512 includes the ADC group 105, a logic circuit 516, and a peripheral circuit 517 formed on another semiconductor substrate. The logic circuit 516 includes the controller 102, the vertical scanning circuit 103, the DAC 104, the horizontal transfer scanning circuit 106, and the like. The peripheral circuit 517 includes the signal processing circuit 108 and the like.

[0044] Elements of each pixel in the pixel portion 101 of the semiconductor chip 511 and elements of the processing circuits (105, 516, 517) of the semiconductor chip 512 may be electrically connected using, for example, through electrodes such as TSVs (Through Silicon Vias) provided in the via regions 513 and 514. The ADC group 105 can transmit and receive signals to and from the pixel portion 101 via TSVs. Alternatively, the two semiconductor chips may be bonded together such that the wiring of the semiconductor chip 511 and the wiring of the semiconductor chip 512 are brought into contact (Cu-Cu bonding). Furthermore, although not shown in the figure, the pixel portion 101 and a part of the processing circuits (105, 516, 517) may be configured as one semiconductor chip 511, and the other components may be configured as another semiconductor chip 512.

[0045] FIG. 3 is a circuit diagram showing an example of an internal configuration of a pixel according to the first embodiment. A pixel PX includes a photoelectric conversion unit 10, a sample-and-hold circuit (SH circuit) 20 serving as a holding unit, and an amplifier circuit 30.

[0046] The photoelectric conversion unit 10 photoelectrically converts incident light into a pixel signal having a charge amount corresponding to the light amount of the incident light. The photoelectric conversion unit 10 includes a photodiode PD, a transfer transistor Ttrg, an FD transistor Tfdg, a capacitor Cfdg, a reset transistor Trst, an amplification transistor Tamp1, and a load current source LD1.

[0047] The photodiode PD generates a charge corresponding to the light amount of incident light and holds the generated charge. An anode of the photodiode PD is connected to a reference voltage source, and a cathode thereof is connected to a drain of the transfer transistor Ttrg.

[0048] The transfer transistor Ttrg is connected between the photodiode PD and a gate (floating diffusion FD) of the amplification transistor Tamp1. A gate of the transfer transistor Ttrg receives a control signal TRG. The transfer transistor Ttrg transfers the charge accumulated in the photodiode PD to the gate of the amplification transistor Tamp1 when the control signal TRG is activated.

[0049] The reset transistor Trst is connected between the voltage source VDD and the FD transistor Tfdg. The gate of the reset transistor Trst receives the control signal RST. When the control signal RST is activated, the reset transistor Trst resets the gate voltage by removing the charge from the gate of the amplification transistor Tamp1 via the FD transistor Tfdg.

[0050] The FD transistor Tfdg is connected between the reset transistor Trst and the gate (floating diffusion FD) of the amplification transistor Tamp1. The gate of the FD transistor Tfdg receives the control signal FDG. When the control signal FDG is activated, the FD transistor Tfdg electrically connects the capacitor Cfdg to the floating diffusion FD, changing the capacitance of the floating diffusion FD. This allows the photoelectric conversion efficiency of the photoelectric conversion unit 10 to be changed. For example, by adding the capacitor Cfdg to the floating diffusion FD, the photoelectric conversion efficiency of the photoelectric conversion unit 10 decreases. By electrically isolating the capacitor Cfdg from the floating diffusion FD, the photoelectric conversion efficiency increases. This widens the range of the photoelectric conversion efficiency of the photoelectric conversion unit 10.

[0051] One end of capacitor Cfdg is connected to the node between the reset transistor Trst and the FD transistor Tfdg, and the other end is connected to a reference voltage source (e.g., ground). Capacitor Cfdg is used to control the capacitance of the floating diffusion FD.

[0052] The amplification transistor Tamp1 is connected between the voltage source VDD and the switching transistor Tsw. The gate of the amplification transistor Tamp1 is connected to the floating diffusion FD and to one end of the transfer transistor Ttrg and the reset transistor Trst, respectively. The amplification transistor Tamp1 becomes conductive in accordance with the voltage of the floating diffusion FD, and the constant current from the load current source LD1 sets the voltage V1 at node N1 to a voltage corresponding to the voltage of the floating diffusion FD.

[0053] The switching transistor Tsw is connected between the amplification transistor Tamp1 and node N1. The gate of the switching transistor Tsw receives the control signal SW. When the control signal SW is activated, the switching transistor Tsw connects the amplification transistor Tamp1 and node N1 with low resistance. As a result, the switching transistor Tsw supplies a constant current from the load current source LD1 to the amplification transistor Tamp1 and node N1, initiating the amplification operation of the amplification transistor Tamp1. The amplified pixel signal is output to the SH circuit 20 as a voltage V1 at node N1. Furthermore, when the control signal SW is deactivated, the switching transistor Tsw electrically isolates the amplification transistor Tamp1 and node N1. As a result, the switching transistor Tsw electrically isolates the load current source LD1 from the amplification transistor Tamp1 and node N1, stopping the amplification operation of the amplification transistor Tamp1.

[0054] The load current source LD1 is connected between node N1 and the reference voltage source. The load current source LD1 supplies a predetermined constant current to the amplification transistor Temp1 and node N1. During amplification, the load current source LD1 functions as a constant current source, thereby setting the voltage at node N1 to a voltage corresponding to the conduction state of the amplification transistor Temp1. The load current source LD1 may be composed of, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0055] The SH circuit 20 is provided between the photoelectric conversion unit 10 and the gate of the amplification transistor Temp2. ​​The SH circuit 20 temporarily holds the voltage of the pixel signal transferred from the photoelectric conversion unit 10. The SH circuit 20 comprises a first capacitance element CR, a second capacitance element CD, a transistor Tsr, and a transistor Tsd.

[0056] One end of the first capacitance element CR is connected to the photoelectric conversion unit 10. The first capacitance element CR receives a pixel signal transferred from the photoelectric conversion unit 10 and is capable of holding the voltage of the pixel signal. The other end of the first capacitance element CR is connected to one end of the transistor Tsr.

[0057] One end of the second capacitance element CD is connected to the photoelectric conversion unit 10 in common with one end of the first capacitance element CR. The second capacitance element CD receives a pixel signal transferred from the photoelectric conversion unit 10 and is capable of holding the voltage of the pixel signal. The other end of the second capacitance element CD is connected to one end of the transistor Tsd.

[0058] The transistor Tsr, acting as the first switching element, is connected between the other end of the first capacitance element CR and the gate (node ​​N2) of the amplification transistor Tamp2. The gate of transistor Tsr receives the control signal SR.

[0059] The transistor Tsd, acting as the second switching element, is connected between the other end of the second capacitance element CD and the gate of the amplification transistor Tamp2. The gate of transistor Tsd receives the control signal SD.

[0060] Thus, the first capacitance element CR and transistor Tsr are connected in series between node N1 and node N2. The second capacitance element CD and transistor Tsd are connected in series between node N1 and node N2. The first capacitance element CR and transistor Tsr are connected in parallel to the second capacitance element CD and transistor Tsd.

[0061] When the SH circuit 20 receives a pixel signal from node N1 or outputs a pixel signal to node N2, both control signals SR and SD are not activated simultaneously. When one of the control signals SR or SD is activated, the other is inactive. That is, when one of the transistors Tsr or Tsd is in the ON state (conducting state), the other is in the OFF state (non-conducting state).

[0062] For example, when transferring a reset signal to the first capacitance element CR, the reset signal is transmitted to node N1, then transistor Tsr is turned on, and the reset signal is read to node N1. In this state, when transistor Tsr is turned off from on, the first capacitance element C1 retains the reset signal. At this time, transistor Ts2 remains off. When transferring a data signal to the second capacitance element C2, the data signal is transmitted to node N1, then transistor Tsd is turned on, and the data signal is read to node N1. In this state, when transistor Ts2 is turned off from on, the second capacitance element C2 retains the data signal. At this time, transistor Ts1 remains off.

[0063] Furthermore, when reading the reset signal held in the first capacitance element CR, transistor Tsr turns ON. At this time, transistor Tsd remains OFF. When reading the data signal held in the second capacitance element CD, transistor Tsd turns ON. At this time, transistor Tsr remains OFF.

[0064] The amplification circuit 30 further comprises a reset transistor Trstb, an amplification transistor Tamp2, a selection transistor Tsel, and a load current source LD2.

[0065] The reset transistor Trstb is connected between the voltage source VREG and node N2. The gate of the reset transistor Trstb receives the control signal RSTB. The reset transistor Trstb is provided to reset the gate voltage of the amplification transistor Temp to the voltage of the voltage source VREG.

[0066] The amplification transistor Tamp2 is connected between the voltage source VDD and the selection transistor Tsel. The gate of the amplification transistor Tamp2 is connected to the SH circuit 20 as node N2. The amplification transistor Tamp2 amplifies and outputs the pixel signal held in the first capacitance element CR or the second capacitance element CD of the SH circuit 20.

[0067] The selection transistor Tsel is connected between the amplification transistor Tamp2 and the vertical signal line 110. The gate of the selection transistor Tsel is connected to the vertical scanning circuit 103 and receives the control signal SEL. The control signal SEL is activated by being specified by an address by the vertical scanning circuit 103. When the control signal SEL is activated, the selection transistor Tsel turns on, and the load current source LD2 supplies a constant current to the amplification transistor Tamp2. As a result, the voltage across the vertical signal line 110 becomes a voltage corresponding to the gate voltage of the amplification transistor Tamp2 (voltage at node N2). That is, the vertical signal line 110 transmits a voltage corresponding to the pixel signal to the ADC group 105.

[0068] The load current source LD2 is connected between the vertical signal line 110 and the reference voltage source. The load current source LD2 is configured to supply a constant current to the amplification transistor Temp2. ​​The load current source LD may be composed of, for example, a MOSFET.

[0069] The transistors Ttrg, Trst, Tamp1, Tpc, Tvb, Tsr, Tsd, Trstb, Tamp2, and Tsel may be composed of, for example, N-type MOSFETs. The first and second capacitance elements CR and CD may be capacitors such as MIM (Metal-Insulator-Metal).

[0070] Figure 4 is a plan view showing an example configuration of the first and second capacitance elements CR, CD and shielding section SLD of the SH circuit 20 according to the first embodiment. Figure 4 shows a plan view of the pixel section 101 as seen from the direction of light incidence, and shows the first and second capacitance elements CR, CD and shielding section SLD corresponding to the four pixels PX.

[0071] Figure 5 is a cross-sectional view showing an example of the configuration of the first capacitance element CR, the second capacitance element CD, and the shielding section SLD of the SH circuit 20 according to the first embodiment. Figure 5 shows a cross-section along the line 5-5 in Figure 4.

[0072] As shown in Figure 4, the first and second capacitance elements CR and CD are provided one at a time within each pixel PX, forming a pair. Each of the first and second capacitance elements CR and CD is composed of multiple columnar bodies CL, for example, nine columnar bodies CL arranged in a 3x3 grid. Multiple pixels PX each have the same planar layout and are arranged in a translationally symmetrical manner.

[0073] The shielding section SLD is provided on one side of the outer edge of each pixel PX and is positioned adjacent to the second capacitance element CD. For example, if the pixel PX has a substantially rectangular shape, the shielding section SLD is provided along one of its four sides that extends in the Y direction. The shielding section SLD is provided between multiple adjacent pixel PXs. The shielding section SLD is composed of multiple columnar bodies CL, for example, three columnar bodies CL arranged in a 3x1 grid. In this embodiment, one shielding section SLD is composed of three columnar bodies CL arranged in the Y direction between a first pixel PX1 and a second pixel PX2 that are adjacent in the X direction.

[0074] Since multiple pixels PX are arranged in translational symmetry, the three columnar bodies CL of the shielding portion SLD within the first pixel PX1 are positioned in the Y direction between the second capacitance element CD of the first pixel PX1 and the first capacitance element CR of the second pixel PX2 adjacent to the first pixel PX1. The three columnar bodies CL of the shielding portion SLD within the second pixel PX2 are arranged in the Y direction between the second capacitance element CD of the second pixel PX2 and the first capacitance element CR of another pixel (not shown) adjacent to it in the -X direction.

[0075] Within the pixel PX, each columnar body CL of the shielding section SLD is arranged adjacent to the columnar bodies of the second capacitance element CD in the -X direction. When three rows of columnar bodies are arranged in the Y direction in the second capacitance element CD, the three columnar bodies CL of the shielding section SLD are arranged adjacent to the three rows of columnar bodies of the second capacitance element CD, respectively.

[0076] The shielding section SLD is maintained at a predetermined fixed voltage (e.g., ground voltage) or the pixel signal voltage V1. This allows the shielding section SLD to suppress coupling capacitance between adjacent first pixels PX1 and second pixels PX2, thereby improving image quality.

[0077] As described above, the first and second capacitance elements CR and CD are each composed of a total of nine columnar bodies CL arranged in a 3x3 grid. To increase the capacitance of the first and second capacitance elements CR and CD, the number of columnar bodies CL in each of the first and second capacitance elements CR and CD may be increased. To decrease the capacitance of the first and second capacitance elements CR and CD, the number of columnar bodies CL in each of the first and second capacitance elements CR and CD may be decreased.

[0078] The shielding section SLD is constructed by arranging three columnar bodies CL in the Y direction. However, the number of columnar bodies CL in the first and second capacitance elements CR and CD, and the shielding section SLD is not limited to this. To improve the shielding effect of the capacitive coupling, it is preferable to arrange the columnar bodies CL of the shielding section SLD in a manner corresponding to the rows of columnar bodies CL of the first or second capacitance elements CR and CD.

[0079] Furthermore, the first capacitance element CR, the second capacitance element CD, and the shielding section SLD refer to elements composed of the columnar body CL contained within each.

[0080] As shown in Figure 5, the first capacitance element CR, the second capacitance element CD, and the shielding portion SLD are provided between the upper wiring MU and the lower wiring ML, extending in the Z direction within the interlayer insulating film ILD. The upper wiring MU is electrically connected in common to the electrodes on the upper end (one end on the +Z side) of the first capacitance element CR, the second capacitance element CD, and the shielding portion SLD of each pixel PX. The lower wiring ML is individually connected to the electrodes on the lower end (the other end on the -Z side) of the first capacitance element CR, the second capacitance element CD, and the shielding portion SLD of each pixel PX. That is, one end of the first capacitance element CR, the second capacitance element CD, and the shielding portion SLD are electrically connected in common to the upper wiring MU, and the other end is connected to the individual lower wiring ML. One end of the first capacitance element CR, the second capacitance element CD, and the shielding portion SLD are commonly connected to node N1 of the photoelectric conversion unit 10 via the upper wiring MU. As a result, even with the addition of the shielding SLD, the layout area of ​​the pixel PX does not increase significantly.

[0081] Figure 6 is a cross-sectional view showing a more detailed configuration example of the columnar body CL of the first capacitance element CR, the second capacitance element CD, and the shielding part SLD. The columnar body CL of the first capacitance element CR, the second capacitance element CD, and the shielding part SLD each have the same configuration.

[0082] A metal pillar MP is provided on the lower wiring ML. The lower wiring ML is made of a conductive material such as copper. The metal pillar MP is made of a conductive material such as tungsten.

[0083] A hole H extending in the Z direction is formed within the interlayer insulating film ILD on a metal pillar MP. A lower electrode EL, an insulating film IN, and an upper electrode EU are provided within the hole H. The lower electrode EL is provided on the inner wall of the hole H and is electrically connected to the lower wiring ML via the metal pillar MP. The lower electrode EL is made of a conductive material such as TiN. The insulating film IN is formed on the lower electrode EL on the inner wall of the hole H. The insulating film IN is made of, for example, ZAZ(ZrO ２ Al ２ O ３ , ZrO ２It is made of insulating material such as ). The upper electrode EU is embedded inside the insulating film IN of hole H and is electrically connected to the upper wiring MU. The upper electrode EU is made of a conductive material such as TiN.

[0084] Thus, each columnar body CL of the first and second capacitance elements CR and CD, and the shielding section SLD, is composed of a laminated structure of a lower electrode EL, an insulating film IN, and an upper electrode EU. The lower electrode EL and the upper electrode EU are electrically isolated by the insulating film IN, and the first and second capacitance elements CR and CD function as capacitance elements. The shielding section SLD is not used as a capacitance element, but is composed of a columnar body CL having the same configuration as the first and second capacitance elements CR and CD. Therefore, the shielding section SLD can be manufactured in the same process as the first and second capacitance elements CR and CD. Thus, no additional manufacturing process is required for the formation of the shielding section SLD.

[0085] The common upper wiring MU of the first capacitance element CR, the second capacitance element CD, and the shielding section SLD is electrically connected to a portion of the lower wiring ML via a contact plug CP that extends the interlayer insulating film ILD in the Z direction. The lower wiring ML connected to the upper wiring MU is connected to node N1 in Figure 3 and transmits voltage V1 to the upper electrodes EU of the first capacitance element CR, the second capacitance element CD, and the shielding section SLD.

[0086] The lower wiring ML, connected to the lower electrodes EL of the first and second capacitance elements CR and CD, is connected to transistors Tsr and Tsd in Figure 3, respectively, and transmits the voltage V2 to node N2 via transistors Tsr and Tsd.

[0087] The lower wiring ML connected to the lower electrode EL of the shielding section SLD is electrically connected to a fixed voltage source (e.g., ground) or node N1. As a result, the voltage of the lower electrode EL of the shielding section SLD is maintained at a predetermined fixed voltage or at the same voltage V1 as the upper electrode EU.

[0088] If a shielding section SLD is not provided, the capacitive coupling between pixel PX1 and pixel PX2 will cause a disturbance due to the voltage difference ΔV between the second capacitive element CD of adjacent pixel PX1 and the first capacitive element CR of pixel PX2, leading to image degradation.

[0089] In contrast, according to this embodiment, a shielding section SLD is provided between adjacent pixels PX1 and PX2. The shielding section SLD suppresses capacitive coupling between the second capacitive element CD of pixel PX1 and the first capacitive element CR of pixel PX2, thereby suppressing disturbance between pixels due to the voltage difference ΔV. This makes it possible to suppress image degradation.

[0090] Furthermore, one end of the columnar body of the shielding section SLD is connected to node N1, and the other end is grounded to a reference voltage source (for example, ground). However, both ends of the columnar body of the shielding section SLD may also be connected to node N1.

[0091] (Second Embodiment) Figure 7 is a plan view showing an example of the configuration of the first capacitance element CR, the second capacitance element CD, and the shielding portion SLD of the SH circuit 20 according to the second embodiment. In the second embodiment, in the planar layout of the pixel portion 101 viewed from the Z direction, the multiple pixels PX are arranged to be mirror-symmetric in the X and Y directions. In adjacent pixels PX1 and PX2, two rows of shielding portions SLD of pixels PX1 and PX2 are arranged between the second capacitance element CD of pixel PX1 and the second capacitance element CD of pixel PX2.

[0092] Thus, in the second embodiment, multiple rows of shielding units SLD are arranged between adjacent pixels PX1 and PX2, between the second capacitive elements CD that hold the data signal. The data signal fluctuates greatly depending on the intensity of the incident light. Therefore, by arranging multiple shielding units SLD between the second capacitive elements CD, the disturbance between pixels due to the voltage difference ΔV can be effectively suppressed.

[0093] The other components of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0094] (Third Embodiment) Figure 8 is a plan view showing an example configuration of the first capacitance element CR, the second capacitance element CD, and the shielding part SLD of the SH circuit 20 according to the third embodiment. Although only one pixel PX is shown in Figure 8, multiple pixels PX may be arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0095] In the third embodiment, in a planar layout of the pixel section 101 viewed from the Z direction, the shielding section SLD is arranged along two sides of the outer edge of each pixel PX. Between two adjacent pixels PX in the X direction, the shielding section SLD is configured by arranging columnar bodies CL so as to be adjacent in the -X direction to each row of columnar bodies CL of the second capacitance element CD. Between two adjacent pixels PX in the Y direction, the shielding section SLD is configured by arranging columnar bodies CL so as to be adjacent in the -Y direction to each row of columnar bodies of the first and second capacitance elements CR and CD.

[0096] Each pixel PX's shielding section SLD shares an upper wiring MU with each other, and also shares an upper wiring MU with the first and second capacitive elements CR and CD. Each pixel PX's shielding section SLD shares a lower wiring ML with each other, but does not share a lower wiring ML with the first and second capacitive elements CR and CD.

[0097] Thus, in the third embodiment, the shielding SLDs are arranged along two sides of the outer edge of each pixel PX. This not only suppresses capacitive coupling between adjacent pixels PX in the X direction, but also between adjacent pixels PX in the Y direction. As a result, disturbance of the pixel signal between pixels PX can be effectively suppressed.

[0098] Other components of the third embodiment may be the same as those of the first or second embodiment. Therefore, the third embodiment can achieve the same effects as the first or second embodiment.

[0099] (Fourth Embodiment) Figure 9 is a plan view showing an example of the configuration of the first capacitance element CR, the second capacitance element CD, and the shielding part SLD of the SH circuit 20 according to the fourth embodiment. Although only one pixel PX is shown in Figure 9, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0100] In the fourth embodiment, in a planar layout of the pixel section 101 viewed from the Z direction, the shielding section SLD is arranged to surround the entire outer edge (four sides) of each pixel PX. Between two adjacent pixel PX in the ±X direction, the shielding section SLD is configured by arranging columnar bodies CL so as to be adjacent in the ±X direction to each row of columnar bodies CL of the first or second capacitive elements CR and CD. Between two adjacent pixel PX in the ±Y direction, the shielding section SLD is configured by arranging columnar bodies so as to be adjacent in the ±Y direction to each row of columnar bodies of the first and second capacitive elements CR and CD.

[0101] Each pixel PX's shielding section SLD shares an upper wiring MU with each other, and also shares an upper wiring MU with the first and second capacitive elements CR and CD. Each pixel PX's shielding section SLD shares a lower wiring ML with each other, but does not share a lower wiring ML with the first and second capacitive elements CR and CD.

[0102] Thus, in the fourth embodiment, the multiple shielding units SLD are arranged to surround the entire outer edge of each pixel PX. This not only suppresses capacitive coupling between adjacent pixels PX in the X direction, but also suppresses capacitive coupling between adjacent pixels PX in the Y direction.

[0103] Furthermore, since multiple pixels PX have a similar configuration, multiple columns or rows of shielding sections (SLDs) are provided between adjacent pixels PX in the X and Y directions. Therefore, capacitive coupling between adjacent pixels PX in the X and Y directions can be suppressed even more effectively. As a result, disturbance of the pixel signal between pixels PX can be suppressed even more effectively.

[0104] Other configurations of the fourth embodiment may be the same as those of the first or second embodiment. Therefore, the fourth embodiment can obtain the same effects as the first or second embodiment.

[0105] (Fifth Embodiment) Figure 10 is a plan view showing an example configuration of the first capacitance element CR, the second capacitance element CD, and the shielding part SLD of the SH circuit 20 according to the fifth embodiment. Although only one pixel PX is shown in Figure 10, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0106] In the fifth embodiment, in a planar layout of the pixel section 101 viewed from the Z direction, the shielding section SLD is arranged to surround the entire outer edge (all four sides) of each pixel PX. In this respect, the fifth embodiment is the same as the fourth embodiment.

[0107] In the fifth embodiment, a shielding portion SLD is further arranged between a first capacitive element CR and a second capacitive element CD within each pixel PX. Within each pixel PX, the shielding portion SLD is arranged between a first capacitive element CR and a second capacitive element CD adjacent in the X direction. The shielding portion SLD between the first capacitive element CR and the second capacitive element CD is constructed by arranging a plurality of columnar bodies CL between the columnar bodies CL of the first and second capacitive elements CR and CD.

[0108] Each pixel PX's shielding section SLD shares an upper wiring MU with each other, and also shares an upper wiring MU with the first and second capacitive elements CR and CD. Each pixel PX's shielding section SLD shares a lower wiring ML with each other, but does not share a lower wiring ML with the first and second capacitive elements CR and CD.

[0109] Thus, in the fifth embodiment, a shielding section SLD is arranged between the first capacitive element CR and the second capacitive element CD within the pixel PX. This not only suppresses capacitive coupling between adjacent pixels PX, but also suppresses capacitive coupling between the first capacitive element CR and the second capacitive element CD within the pixel PX. As a result, disturbance of pixel signals between pixels PX and disturbance of pixel signals within pixels PX can be suppressed even more effectively.

[0110] The other configurations of the fifth embodiment may be the same as those of the first, second, or fourth embodiment. Therefore, the fifth embodiment can obtain the same effects as the first, second, or fourth embodiment.

[0111] (Sixth Embodiment) Figure 11 is a plan view showing an example of the configuration of the first capacitance element CR, the second capacitance element CD, and the shielding part SLD of the SH circuit 20 according to the sixth embodiment. Although only one pixel PX is shown in Figure 11, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0112] In the sixth embodiment, in a planar layout of the pixel section 101 viewed from the Z direction, the shielding section SLD is arranged along one side of the outer edge of the second capacitance element CD, in a region that is longer in the Y direction than that side. The shielding section SLD is configured by arranging columnar bodies CL adjacent to the row of columnar bodies CL of the second capacitance element CD in the -X direction, and further arranging columnar bodies CL in the ±Y directions of the columnar bodies CL. As a result, the multiple columnar bodies CL of the shielding section SLD are arranged over a region longer than one side of the outer edge of the second capacitance element CD. Consequently, capacitive coupling between adjacent pixels PX can be effectively suppressed.

[0113] The other configurations of the sixth embodiment may be the same as those of the first or second embodiment. Therefore, the sixth embodiment can obtain the same effects as the first or second embodiment.

[0114] (Seventh Embodiment) Figure 12 is a plan view showing an example configuration of the first capacitance element CR, the second capacitance element CD, and the shielding part SLD of the SH circuit 20 according to the seventh embodiment. Although only one pixel PX is shown in Figure 12, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0115] In the seventh embodiment, in a planar layout of the pixel section 101 viewed from the Z direction, the lower wiring ML connected to the shielding section SLD is connected to node N1 and receives the voltage V1. The lower wiring ML of the shielding section SLD is routed and connected to the lower wiring ML connected to node N1.

[0116] Other configurations of the seventh embodiment may be the same as those of the first or second embodiment. Therefore, the seventh embodiment can obtain the same effects as the first or second embodiment.

[0117] (Eighth Embodiment) Figure 13 is a plan view showing an example configuration of the first capacitance element CR, the second capacitance element CD, and the shielding part SLD of the SH circuit 20 according to the eighth embodiment. Although only one pixel PX is shown in Figure 13, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0118] In the eighth embodiment, in a planar layout of the pixel section 101 viewed from the Z direction, the lower wiring ML connected to the shielding section SLD is connected to a reference voltage source (e.g., ground) and receives the output voltage. The lower wiring ML of the shielding section SLD is routed to the reference voltage source.

[0119] Other configurations of the eighth embodiment may be the same as those of the first or second embodiment. Therefore, the eighth embodiment can obtain the same effects as the first or second embodiment.

[0120] (Ninth Embodiment) Figure 14 is a circuit diagram showing an example of the configuration of the photoelectric conversion unit 10 according to the ninth embodiment. Figure 15 is a plan view showing an example of the configuration of the first capacitance element CR, the second capacitance element CD, and the shielding unit SLD of the SH circuit 20 according to the ninth embodiment. Although only one pixel PX is shown in Figure 15, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0121] As shown in Figure 14, in the ninth embodiment, the photoelectric conversion unit 10 has a capacitive element C3 provided between node N1 and the voltage source instead of the load current source LD1. The capacitive element C3 generates a voltage at node N1 corresponding to the pixel signal by flowing the charged charge to node N1. Such a CCS (Capacitor Current Source) method may be used in the photoelectric conversion unit 10.

[0122] In this case, as shown in Figure 15, the capacitive element C3 is provided within each pixel PX, separately from the first capacitive element CR, the second capacitive element CD, and the shielding part SLD. The capacitive element C3 is composed of a plurality of columnar bodies CL arranged in a row. The columnar bodies CL of the capacitive element C3 may have the same configuration as the columnar bodies CL of the first capacitive element CR, the second capacitive element CD, and the shielding part SLD.

[0123] One end of the capacitive element C3 is connected to the upper wiring MU, which is common to the first capacitive element CR, the second capacitive element CD, and the shielding section SLD. The other end of the capacitive element C3 is connected to the lower wiring ML, which is provided separately from the lower wiring ML of the first capacitive element CR, the second capacitive element CD, and the shielding section SLD, and receives a predetermined fixed voltage.

[0124] Other configurations of the ninth embodiment may be the same as those of the first or second embodiment. Therefore, the ninth embodiment can obtain the same effects as the first or second embodiment. As with the ninth embodiment, this technology is also applicable to CCS-type CIS.

[0125] (Tenth Embodiment) Figure 16 is a circuit diagram showing an example configuration of the SH circuit 20 according to the tenth embodiment. Figure 17 is a plan view showing an example configuration of the first capacitance element CR, the second capacitance element CD, and the shielding part SLD of the SH circuit 20 according to the tenth embodiment. Although only one pixel PX is shown in Figure 17, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0126] As shown in Figure 16, in the tenth embodiment, the SH circuit 20 of each pixel PX has first to fourth capacitive elements CR_H, CD_H, CR_L, and CD_L. In other words, the SH circuit 20 of each pixel PX has two pairs of capacitive elements CR and CD. Accordingly, switching transistors Tsr_H, Tsd_H, Tsr_L, and Tsd_L are provided corresponding to each of the first to fourth capacitive elements CR_H, CD_H, CR_L, and CD_L. The first to fourth capacitive elements CR_H, CD_H, CR_L, and CD_L are commonly connected to node N1 at one end and connected to node N2 at the other end via switching transistors Tsr_H, Tsd_H, Tsr_L, and Tsd_L, respectively.

[0127] As shown in Figure 17, the first to fourth capacitance elements CR_H, CD_H, CR_L, and CD_L are each composed of the same columnar body CL and have the same configuration.

[0128] When the FD transistor Tfdg in Figure 3 is turned off, the capacitance of the floating diffusion FD becomes relatively small, and the photoelectric conversion efficiency of the photoelectric conversion unit 10 increases. The reset signal and data signal at this high conversion efficiency are held by the first and second capacitance element pairs CR_H and CD_H, respectively.

[0129] On the other hand, when the FD transistor Tfdg is turned on, the capacitance of the floating diffusion FD becomes relatively large, and the photoelectric conversion efficiency of the photoelectric conversion unit 10 decreases. The reset signal and data signal at such low conversion efficiency are held by the third and fourth capacitance element pairs CR_L and CD_L, respectively. In this way, the first and second capacitance element pairs CR_H and CD_H and the third and fourth capacitance element pairs CR_L and CD_L hold pixel signals generated at different photoelectric conversion efficiencies. As a result, the SH circuit 20 can hold pixel signals generated at a wide range of photoelectric conversion efficiencies.

[0130] As shown in Figure 17, the shielding section SLD is provided between the first capacitance element CR_H and the third capacitance element CR_L, and between the second capacitance element CD_H and the fourth capacitance element CD_L. The shielding section SLD is constructed by arranging columnar bodies CL between the first capacitance element CR_H and the third capacitance element CR_L, and between the second capacitance element CD_H and the fourth capacitance element CD_L, so as to correspond to the rows of columnar bodies CL of the first to fourth capacitance elements CR_H, CD_H, CR_L, and CD_L. The columnar bodies CL of the shielding section SLD may have the same configuration as the columnar bodies CL of the first to fourth capacitance elements CR_H, CD_H, CR_L, and CD_L.

[0131] The upper wiring MU is commonly connected to one end of the first to fourth capacitance elements CR_H, CD_H, CR_L, CD_L and the shielding section SLD. The lower wiring ML is individually connected to the other end of the first to fourth capacitance elements CR_H, CD_H, CR_L, CD_L and the shielding section SLD. The lower wiring ML of the shielding section SLD is connected to node N1 or a reference voltage source (e.g., ground).

[0132] In this way, by providing the shielding SLD between the first capacitance element CR_H and the third capacitance element CR_L, and between the second capacitance element CD_H and the fourth capacitance element CD_L, capacitive coupling between the first capacitance element CR_H and the third capacitance element CR_L, and between the second capacitance element CD_H and the fourth capacitance element CD_L is suppressed. As a result, disturbance of the pixel signal between the first capacitance element CR_H and the third capacitance element CR_L, and between the second capacitance element CD_H and the fourth capacitance element CD_L can be suppressed.

[0133] Furthermore, in the tenth embodiment, the SH circuit 20 has multiple pairs of capacitive elements. This makes it possible to widen the dynamic range of the photoelectric conversion efficiency of the imaging device 100.

[0134] Other configurations of the tenth embodiment may be the same as those of the first or second embodiment. Therefore, the tenth embodiment can obtain the same effects as the first or second embodiment.

[0135] (Eleventh Embodiment) Figure 18 is a plan view showing an example configuration of the first to fourth capacitance elements CR_H, CD_H, CR_L, CD_L, and shielding part SLD of the SH circuit 20 according to the eleventh embodiment. Although only one pixel PX is shown in Figure 18, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0136] In the 11th embodiment, in the planar layout of the pixel section 101 viewed from the Z direction, the shielding section SLD is provided not only between the first capacitive element CR_H and the third capacitive element CR_L, and between the second capacitive element CD_H and the fourth capacitive element CD_L, but also between the first capacitive element CR_H and the second capacitive element CD_H, and between the third capacitive element CR_L and the fourth capacitive element CD_L.

[0137] The shielding section SLD is constructed by arranging columnar bodies CL so as to correspond to the rows or columns of columnar bodies CL of the first to fourth capacitive elements CR_H, CD_H, CR_L, and CD_L. The columnar bodies CL of the shielding section SLD may have the same configuration as the columnar bodies CL of the first to fourth capacitive elements CR_H, CD_H, CR_L, and CD_L. In each pixel PX, the upper wiring MU and lower wiring ML of the shielding section SLD are common.

[0138] In this way, by providing the shielding SLD between the first to fourth capacitive elements CR_H, CD_H, CR_L, and CD_L, capacitive coupling between the first to fourth capacitive elements CR_H, CD_H, CR_L, and CD_L is suppressed. As a result, disturbance of the pixel signal can be suppressed not only between the first capacitive element CR_H and the third capacitive element CR_L, and between the second capacitive element CD_H and the fourth capacitive element CD_L, but also between the first capacitive element CR_H and the second capacitive element CD_H, and between the third capacitive element CR_L and the fourth capacitive element CD_L.

[0139] The other configurations of the 11th embodiment may be the same as those of the 10th embodiment. Therefore, the 11th embodiment can obtain the same effects as the 10th embodiment.

[0140] (Twelfth Embodiment) Figure 19 is a circuit diagram showing an example configuration of the photoelectric conversion unit 10 and SH circuit 20 according to the twelfth embodiment. Figure 20 is a plan view showing an example configuration of the first capacitance element CR, the second capacitance element CD, and the shielding unit SLD of the SH circuit 20 according to the twelfth embodiment. Although only one pixel PX is shown in Figure 20, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0141] The twelfth embodiment is an imaging device having a so-called LOFIC (Lateral Overflow Integration Capacitor) configuration.

[0142] As shown in Figure 19, in the twelfth embodiment, the photoelectric conversion unit 10 of each pixel PX has a reset transistor Trst and an overflow transistor Tofg directly connected between the voltage source VDD and the photodiode PD. The reset transistor Trst is controlled by the control signal RST. The overflow transistor Tofg is controlled by the control signal OFG.

[0143] Furthermore, transistors Tfdg and Tfcg are connected in series between the floating diffusion element FD and the capacitor Cfdg. Transistor Tfdg is controlled to be on or off by the control signal FDG. Transistor Tfcg is controlled to be on or off by the control signal FCG.

[0144] Transistors Tfdg and Tfcg are used to change the capacitance of the floating diffusion FD. For example, when both transistors Tfdg and Tfcg are in the off state, the capacitance of the floating diffusion FD is relatively small. In this case, the photoelectric conversion efficiency of the photoelectric conversion unit 10 is high. When transistor Tfdg is in the on state and transistor Tfcg is in the off state, the capacitance from the floating diffusion FD to transistor Tfcg is added to the floating diffusion FD, and the capacitance of the floating diffusion FD becomes about average. In this case, the photoelectric conversion efficiency of the photoelectric conversion unit 10 is about average. When both transistors Tfdg and Tfcg are in the on state, capacitor Cfdg is connected to the floating diffusion FD, so the capacitance of the floating diffusion FD becomes relatively large. In this case, the photoelectric conversion efficiency of the photoelectric conversion unit 10 is low. In this way, the capacitance of the floating diffusion FD can be changed by switching the transistors Tfdg and Tfcg on and off, and the photoelectric conversion efficiency of the photoelectric conversion unit 10 can be changed in, for example, three stages.

[0145] Accordingly, the SH circuit 20 of each pixel PX has three pairs each of capacitive elements CR and CD. Switching transistors Tsr_H, Tsd_H, Tsr_M, Tsd_M, Tsr_L, and Tsd_L are provided corresponding to the first to sixth capacitive elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L, respectively. The first to sixth capacitive elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L are connected between node N1 and node N2 via switching transistors Tsr_H, Tsd_H, Tsr_M, Tsd_M, Tsr_L, and Tsd_L, respectively.

[0146] As shown in Figure 20, the first to sixth capacitance elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L are each composed of the same columnar body CL and have the same configuration.

[0147] When both transistors Tfdg and Tfcg are turned off, the capacitance of the floating diffusion FD becomes relatively small, and the photoelectric conversion efficiency of the photoelectric conversion unit 10 increases. The reset signal and data signal at such high conversion efficiency are held by the first and second capacitance element pairs CR_H and CD_H, respectively.

[0148] When transistor Tfdg is turned ON and transistor Tfcg is turned OFF, the capacitance of the floating diffusion FD becomes approximately intermediate, and the photoelectric conversion efficiency of the photoelectric conversion unit 10 becomes approximately intermediate. The reset signal and data signal at this intermediate conversion efficiency are held by the third and fourth capacitance elements CR_M and CD_M, respectively.

[0149] Furthermore, when both transistors Tfdg and Tfcg are turned on, the capacitance of the floating diffusion FD becomes relatively large, and the photoelectric conversion efficiency of the photoelectric conversion unit 10 decreases. The reset signal and data signal at such low conversion efficiency are held by the fifth and sixth capacitance elements CR_L and CD_L pairs, respectively. In this way, the first and second capacitance element pairs CR_H and CD_H, the third and fourth capacitance element pairs CR_M and CD_M, and the fifth and sixth capacitance element pairs CR_L and CD_L each hold pixel signals generated at different photoelectric conversion efficiencies. As a result, the SH circuit 20 can hold pixel signals generated at a wide range of photoelectric conversion efficiencies.

[0150] As shown in Figure 20, the shielding section SLD is provided between the first capacitance element CR_H and the third capacitance element CR_M, between the second capacitance element CD_H and the fourth capacitance element CD_M, between the third capacitance element CR_M and the fifth capacitance element CR_L, and between the fourth capacitance element CD_M and the sixth capacitance element CD_L. The shielding section SLD is constructed by arranging columnar bodies CL to correspond to the rows of columnar bodies CL of the first to sixth capacitance elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L. The columnar bodies CL of the shielding section SLD may have the same configuration as the columnar bodies CL of the first to sixth capacitance elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L.

[0151] The upper wiring MU is commonly connected to one end of the first to sixth capacitance elements CR_H, CD_H, CR_M, CD_M, CR_L, CD_L and the shielding section SLD. The lower wiring ML is individually connected to the other end of the first to sixth capacitance elements CR_H, CD_H, CR_M, CD_M, CR_L, CD_L and the shielding section SLD. The lower wiring ML of the shielding section SLD is connected to node N1 or a reference voltage source (e.g., ground).

[0152] In this way, by providing the shielding SLD between the first capacitance element CR_H and the third capacitance element CR_M, between the second capacitance element CD_H and the fourth capacitance element CD_M, between the third capacitance element CR_M and the fifth capacitance element CR_L, and between the fourth capacitance element CD_M and the sixth capacitance element CD_L, capacitive coupling between these elements is suppressed. As a result, disturbance of the pixel signal between the first capacitance element CR_H and the third capacitance element CR_M, between the second capacitance element CD_H and the fourth capacitance element CD_M, between the third capacitance element CR_M and the fifth capacitance element CR_L, and between the fourth capacitance element CD_M and the sixth capacitance element CD_L can be suppressed.

[0153] Furthermore, in the twelfth embodiment, the SH circuit 20 has multiple pairs of capacitive elements. This makes it possible to widen the dynamic range of the photoelectric conversion efficiency of the imaging device 100.

[0154] Other configurations of the twelfth embodiment may be the same as those of the first or second embodiment. Therefore, the twelfth embodiment can obtain the same effects as the first or second embodiment.

[0155] (Third Embodiment) Figure 21 is a plan view showing an example configuration of the first to fourth capacitance elements CR_H, CD_H, CR_L, CD_L, and shielding part SLD of the SH circuit 20 according to the thirteenth embodiment. Although only one pixel PX is shown in Figure 21, multiple pixels PX are arranged in the X-Y plane. The multiple pixels PX may be arranged in translational symmetry as in the first embodiment, or they may be arranged in mirror symmetry as in the second embodiment.

[0156] In the 13th embodiment, similar to the 12th embodiment, the SH circuit 20 has first to sixth capacitance elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L. In the planar layout of the pixel section 101 viewed from the Z direction, the shielding section SLD is provided not only between the first capacitance element CR_H and the third capacitance element CR_M, between the second capacitance element CD_H and the fourth capacitance element CD_M, between the third capacitance element CR_M and the fifth capacitance element CR_L, and between the fourth capacitance element CD_M and the sixth capacitance element CD_L, but also between the first capacitance element CR_H and the second capacitance element CD_H, between the third capacitance element CR_M and the fourth capacitance element CD_M, and between the fifth capacitance element CR_L and the sixth capacitance element CD_L.

[0157] The shielding section SLD is constructed by arranging columnar bodies CL so as to correspond to the rows or columns of columnar bodies CL of the first to sixth capacitive elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L. The columnar bodies CL of the shielding section SLD may have the same configuration as the columnar bodies CL of the first to sixth capacitive elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L. In each pixel PX, the upper wiring MU and lower wiring ML of the shielding section SLD are common.

[0158] In this way, by providing the shielding SLD between the first to sixth capacitive elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L, capacitive coupling between the first to sixth capacitive elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L is suppressed. As a result, disturbance of the pixel signals between the first to sixth capacitive elements CR_H, CD_H, CR_M, CD_M, CR_L, and CD_L can be suppressed.

[0159] The other configurations of the 13th embodiment may be the same as those of the 12th embodiment. Therefore, the 13th embodiment can obtain the same effects as the 12th embodiment.

[0160] Furthermore, this technology can be configured as follows:

[0161] (1) An imaging device comprising: a photoelectric conversion unit that photoelectrically converts incident light into a pixel signal; a holding unit including first and second capacitive elements that hold the pixel signal from the photoelectric conversion unit; and a plurality of pixels including an amplification unit that amplifies and outputs the pixel signal held by the holding unit; and a shielding unit provided between a plurality of adjacent pixels and maintained at a predetermined fixed voltage or the voltage of the pixel signal.

[0162] (2) The imaging apparatus according to (1), wherein the shielding portion has the same configuration as the first and second capacitive elements.

[0163] (3) The imaging apparatus according to (2), wherein the first capacitive element, the second capacitive element, and the shielding portion have a laminated structure of a first metal film, a first insulating film, and a second metal film.

[0164] (4) The imaging apparatus according to (3), wherein the first capacitive element, the second capacitive element, and the shielding portion are arranged by arranging a plurality of columnar bodies having the stacked structure.

[0165] (5) The imaging apparatus according to any one of (1) to (4), wherein one end of the first capacitive element, the second capacitive element, and the shielding portion is electrically connected in common to the photoelectric conversion portion.

[0166] (6) The imaging device according to (5), wherein the other end of the shielding portion is connected to a fixed voltage source or to one end of the shielding portion.

[0167] (7) The imaging apparatus according to (5) or (6), wherein the holding portion includes a first switching element provided between the amplification portion and the other end of the first capacitive element, and a second switching element provided between the amplification portion and the other end of the second capacitive element.

[0168] (8) The imaging apparatus according to any one of (1) to (7), further comprising: an AD conversion unit that AD converts the pixel signal into a digital signal; a first drive unit that reads the pixel signal from a plurality of pixels in a row selected by address to the AD conversion unit; and a signal processing circuit that generates image data using the digital signal from the AD conversion unit.

[0169] (9) The imaging apparatus according to any one of (1) to (8), wherein the first capacitive element holds the pixel signal, which does not contain the charge due to the incident light, as a reset signal, the second capacitive element holds the pixel signal, which contains the charge due to the incident light, as a data signal, and the shielding portion is arranged adjacent to each of the second capacitive elements of the plurality of pixels.

[0170] (10) The imaging apparatus according to (9), wherein the shielding portion of the first pixel among the plurality of pixels is arranged between the second capacitive element of the first pixel and the second pixel adjacent to the first pixel.

[0171] (11) The imaging apparatus according to (9) or (10), wherein in the planar layout of the plurality of pixels, the plurality of pixels are arranged to be translationally symmetric, and the shielding portion is positioned between the plurality of pixels, between the second capacitive element of a first pixel and the first capacitive element of a second pixel adjacent to the first pixel.

[0172] (12) The imaging apparatus according to (9) or (10), wherein in the planar layout of the plurality of pixels, the plurality of pixels are arranged in a mirror-image symmetric manner, and the shielding portion is positioned between the plurality of pixels, between the second capacitive element of a first pixel and the second capacitive element of a second pixel adjacent to the first pixel.

[0173] (13) The imaging apparatus according to any one of (9) to (12), wherein in the planar layout of the plurality of pixels, the shielding portion is arranged along two sides of the outer edge of the pixel.

[0174] (14) The imaging apparatus according to any one of (9) to (12), wherein in the planar layout of the plurality of pixels, the shielding portion is arranged around the entire outer edge of the pixels.

[0175] (15) The imaging apparatus according to any one of (9) to (14), wherein in the planar layout of the plurality of pixels, the shielding portion is arranged between the first capacitive element and the second capacitive element of each of the plurality of pixels.

[0176] (16) The imaging apparatus according to any one of (9) to (12), wherein in the planar layout of the plurality of pixels, the shielding portion is arranged along one side of the outer edge of the second capacitive element over a region longer than that side.

[0177] (17) The imaging apparatus according to any one of (1) to (16), wherein each of the plurality of pixels' holding portions further includes third and fourth capacitive elements that hold pixel signals different in conversion efficiency of the photoelectric conversion unit from the pixel signals held by the first and second capacitive elements, the third capacitive element holds the pixel signal that does not include the charge due to the incident light as a reset signal, the fourth capacitive element holds the pixel signal that includes the charge due to the incident light as a data signal, and the shielding portion is provided between the first capacitive element and the third capacitive element, and between the second capacitive element and the fourth capacitive element.

[0178] (18) The imaging apparatus according to (17), wherein each of the plurality of pixels' holding portions further includes fifth and sixth capacitive elements that hold pixel signals different in conversion efficiency of the photoelectric conversion unit from the pixel signals held by the first to fourth capacitive elements, the fifth capacitive element holds the pixel signal that does not include the charge due to the incident light as a reset signal, the sixth capacitive element holds the pixel signal that includes the charge due to the incident light as a data signal, and the shielding portions are provided between the first capacitive element and the third capacitive element, between the second capacitive element and the fourth capacitive element, between the third capacitive element and the fifth capacitive element, and between the fourth capacitive element and the sixth capacitive element.

[0179] Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the gist of this disclosure. Also, the effects described herein are merely illustrative and not limiting, and other effects may exist.

[0180] PX Pixel 10 Photoelectric conversion section 20 Sample and hold circuit 30 Amplifier circuit PD Photodiode Ttrg Transfer transistor Tfdg FD transistor Cfdg Capacitor Trst Reset transistor Tamp1 Amplifier transistor LD1 Load current source CR First capacitance element CD Second capacitance element Tsr Transistor Tsd Transistor Trstb Reset transistor Tamp2 Amplifier transistor Tsel Selection transistor LD2 Load current source SLD Shielding section

Claims

1. An imaging device comprising: a photoelectric conversion unit that photoelectrically converts incident light into a pixel signal; a holding unit including first and second capacitive elements that hold the pixel signal from the photoelectric conversion unit; and a plurality of pixels including an amplification unit that amplifies and outputs the pixel signal held by the holding unit; and a shielding unit provided between a plurality of adjacent pixels and maintained at a predetermined fixed voltage or the voltage of the pixel signal.

2. The imaging apparatus according to claim 1, wherein the shielding portion has the same configuration as the first and second capacitance elements.

3. The imaging apparatus according to claim 2, wherein the first capacitance element, the second capacitance element, and the shielding portion have a laminated structure of a first metal film, a first insulating film, and a second metal film.

4. The imaging apparatus according to claim 3, wherein the first capacitive element, the second capacitive element, and the shielding portion are arranged by arranging a plurality of columnar bodies having the stacked structure.

5. The imaging apparatus according to claim 1, wherein one end of the first capacitive element, the second capacitive element, and the shielding portion are electrically connected in common to the photoelectric conversion portion.

6. The imaging device according to claim 5, wherein the other end of the shielding portion is connected to a fixed voltage source or to one end of the shielding portion.

7. The imaging apparatus according to claim 5, wherein the holding portion includes a first switching element provided between the amplification portion and the other end of the first capacitive element, and a second switching element provided between the amplification portion and the other end of the second capacitive element.

8. The imaging apparatus according to claim 1, further comprising: an AD conversion unit that performs AD (Analogue-to-Digital) conversion of the pixel signals to digital signals; a first drive unit that reads the pixel signals from a plurality of pixels in a row selected by address to the AD conversion unit; and a signal processing circuit that generates image data using the digital signals from the AD conversion unit.

9. The imaging apparatus according to claim 1, wherein the first capacitive element holds the pixel signal, which does not include the charge due to the incident light, as a reset signal; the second capacitive element holds the pixel signal, which includes the charge due to the incident light, as a data signal; and the shielding portion is arranged adjacent to each of the second capacitive elements of the plurality of pixels.

10. The imaging apparatus according to claim 9, wherein the shielding portion of the first pixel among the plurality of pixels is arranged between the second capacitive element of the first pixel and the second pixel adjacent to the first pixel.

11. The imaging apparatus according to claim 9, wherein in the planar layout of the plurality of pixels, the plurality of pixels are arranged to be translationally symmetric, and the shielding portion is positioned between the plurality of pixels, between the second capacitive element of a first pixel and the first capacitive element of a second pixel adjacent to the first pixel.

12. The imaging apparatus according to claim 9, wherein in the planar layout of the plurality of pixels, the plurality of pixels are arranged in a mirror-image symmetric manner, and the shielding portion is positioned between the plurality of pixels, between the second capacitive element of a first pixel and the second capacitive element of a second pixel adjacent to the first pixel.

13. The imaging apparatus according to claim 9, wherein in the planar layout of the plurality of pixels, the shielding portion is arranged along two sides of the outer edge of the pixel.

14. The imaging apparatus according to claim 9, wherein in the planar layout of the plurality of pixels, the shielding portion is arranged around the entire outer edge of the pixels.

15. The imaging apparatus according to claim 9, wherein in the planar layout of the plurality of pixels, the shielding portion is arranged between the first capacitive element and the second capacitive element of each of the plurality of pixels.

16. The imaging apparatus according to claim 9, wherein in the planar layout of the plurality of pixels, the shielding portion is arranged along one side of the outer edge of the second capacitive element, extending over a region longer than that side.

17. The imaging apparatus according to claim 1, wherein each of the plurality of pixels' holding portions further includes third and fourth capacitive elements that hold pixel signals different in conversion efficiency of the photoelectric conversion unit from the pixel signals held by the first and second capacitive elements, the third capacitive element holds the pixel signal that does not include the charge due to the incident light as a reset signal, the fourth capacitive element holds the pixel signal that includes the charge due to the incident light as a data signal, and the shielding portion is provided between the first capacitive element and the third capacitive element, and between the second capacitive element and the fourth capacitive element.

18. The imaging apparatus according to claim 17, wherein each of the plurality of pixels' holding portions further includes fifth and sixth capacitive elements that hold pixel signals different in conversion efficiency of the photoelectric conversion unit from the pixel signals held by the first to fourth capacitive elements, the fifth capacitive element holds the pixel signal that does not include the charge due to the incident light as a reset signal, the sixth capacitive element holds the pixel signal that includes the charge due to the incident light as a data signal, and the shielding portions are provided between the first capacitive element and the third capacitive element, between the second capacitive element and the fourth capacitive element, between the third capacitive element and the fifth capacitive element, and between the fourth capacitive element and the sixth capacitive element.

Images