Semiconductor device

Abstract

[Problem] To provide a semiconductor device capable of expanding a circuit arrangement region by suppressing diffusion of moisture from a junction surface. [Solution] A semiconductor device according to an embodiment of the present disclosure comprises: a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; a protective film; a first seal ring provided on the first semiconductor substrate; a second seal ring provided on the second semiconductor substrate; at least one protective film provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate or on at least one of the upper side and the lower side of the bonding surface; and a third seal ring provided on the bonding surface and connected to the protective film.

Description

Semiconductor device

[0001] The present disclosure relates to a semiconductor device.

[0002] Along with the three-dimensional integration of LSIs, Wafer on Wafer bonding and Chip on Wafer bonding have been increasingly utilized. Conventionally, in MEMS (Micro Electro Mechanical Systems), a hermetic seal ring is used to maintain a vacuum state.

[0003] International Publication No. WO 2022 / 265059

[0004] In LSI applications such as image sensors, the seal ring positions or chip sizes may vary, so the bonded portion is not necessarily hermetically sealed by the seal ring. Therefore, a moisture diffusion path may exist. In this case, considering water diffusion, the circuit arrangement region is limited.

[0005] The present disclosure provides a semiconductor device capable of expanding a circuit arrangement region by suppressing moisture diffusion from a bonding surface.

[0006] A semiconductor device according to an embodiment of the present disclosure includes: a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; at least one protective film provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate, or on at least one of an upper side and a lower side of the bonding surface; a first seal ring provided on the first semiconductor substrate; a second seal ring provided on the second semiconductor substrate; and a third seal ring provided on the bonding surface and connected to the protective film.

[0007] Further, the third seal ring may include a metal layer and a contact via connected to the metal layer.

[0008] Further, the third seal ring may be arranged at a position different from that of the first seal ring and the second seal ring, or may be arranged at a position connected to at least one of the first seal ring and the second seal ring.

[0009] Furthermore, the third seal ring may have a cross-section that connects to the second seal ring, and a cross-section that connects to the first seal ring and the second seal ring.

[0010] Furthermore, the protective film may include an insulating two-dimensional material.

[0011] Furthermore, the first semiconductor substrate and the second semiconductor substrate may include a circuit layer in the first seal ring or the second seal ring, and the circuit layer may include a low-k layer.

[0012] The semiconductor device may further include a third semiconductor substrate bonded between the first semiconductor substrate and the second semiconductor substrate, a fourth seal ring connected to the protective film on the upper side of the first bonding surface between the first semiconductor substrate and the third semiconductor substrate, and a fifth seal ring connected to the protective film on the lower side of the second bonding surface between the third semiconductor substrate and the second semiconductor substrate.

[0013] Furthermore, the fifth seal ring may include a TSV that penetrates the semiconductor layer of the third semiconductor substrate.

[0014] Furthermore, the planar area of ​​the first semiconductor substrate may differ from the planar area of ​​the second semiconductor substrate.

[0015] Furthermore, the planar area of ​​the first semiconductor substrate may be larger than the planar area of ​​the second semiconductor substrate, a plurality of second semiconductor substrates may be bonded to the first semiconductor substrate, and the third seal ring may have a frame-shaped portion surrounding the plurality of second semiconductor substrates.

[0016] The third seal ring may have a portion that penetrates the protective film.

[0017] The second seal ring may be positioned outside the first seal ring, and the third seal ring may be positioned outside the second seal ring.

[0018] The protective film may be provided in the middle of the second seal ring.

[0019] The structure of the first seal ring may differ from the structure of the second seal ring.

[0020] The first seal ring may include a plurality of metal layers arranged in layers, and the uppermost metal layer may have the largest planar area among the plurality of metal layers.

[0021] This is a plan view of a semiconductor device according to the first embodiment. This is a cross-sectional view along the cutting line A-A shown in Figure 1. This is a diagram showing the schematic cross-sectional structure of a semiconductor device according to a comparative example. This is a diagram showing the schematic cross-sectional structure of a semiconductor device according to the first embodiment. This is a cross-sectional view of a semiconductor device according to the second embodiment. This is a cross-sectional view of a semiconductor device according to the third embodiment. This is a cross-sectional view of a semiconductor device according to a modified example of the third embodiment. This is a cross-sectional view of a semiconductor device according to the fourth embodiment. This is a cross-sectional view of a semiconductor device according to the fifth embodiment. This is a cross-sectional view of a semiconductor device according to the sixth embodiment. This is a cross-sectional view of a semiconductor device according to the seventh embodiment. This is a cross-sectional view of a semiconductor device according to a modified example of the seventh embodiment. This is a plan view of a semiconductor device according to the eighth embodiment. This is a cross-sectional view along the cutting line B-B shown in Figure 13. This is a plan view of a semiconductor device according to the ninth embodiment. This is a cross-sectional view along the cutting line C-C shown in Figure 15. This is a cross-sectional view along the cutting line D-D shown in Figure 15. This is a cross-sectional view of a semiconductor device according to the first modified example of the ninth embodiment. This is a cross-sectional view of a semiconductor device according to the second modified example of the ninth embodiment. This is a cross-sectional view of a semiconductor device according to the tenth embodiment. This is a cross-sectional view of a semiconductor device according to the eleventh embodiment. This is a cross-sectional view of a semiconductor device according to the twelfth embodiment. This is a plan view of a semiconductor device according to a modified example of the twelfth embodiment. This is a plan view of a semiconductor device according to the thirteenth embodiment. This is a cross-sectional view of a semiconductor device according to the thirteenth embodiment. This is a cross-sectional view of a semiconductor device according to a modified example of the thirteen This is a cross-sectional view of a semiconductor device according to the 14th embodiment. This is a block diagram showing an example of a schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation positions of the external information detection unit and the imaging unit.

[0022] Preferred embodiments of this disclosure will be described in detail below with reference to the attached drawings. In this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant explanations will be omitted. In the following description, two mutually orthogonal directions in the in-plane direction parallel to the semiconductor substrate may be referred to as the X direction and the Y direction, respectively. In addition, the out-of-plane direction perpendicular to the semiconductor substrate may be referred to as the Z direction, which is orthogonal to the X direction and the Y direction.

[0023] (First Embodiment) Figure 1 is a plan view of a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view taken along the cutting line A-A shown in Figure 1. The semiconductor device 1 according to this embodiment has a first semiconductor substrate 101 and a second semiconductor substrate 102. The second semiconductor substrate 102 is joined to the first semiconductor substrate 101 in the Z direction in an inverted state. The structure of the first semiconductor substrate 101 will now be described. Note that the structure of the second semiconductor substrate 102 is the same as that of the first semiconductor substrate 101, so its description will be omitted.

[0024] The first semiconductor substrate 101 includes a semiconductor layer 111, a circuit layer 112, and a junction layer 113. The semiconductor layer 111 is, for example, a silicon layer. A semiconductor element, such as an image sensor, is formed on the semiconductor layer 111.

[0025] The circuit layer 112 is stacked on the semiconductor layer 111. Internal circuits are formed in the circuit layer 112. These internal circuits include drive circuits for driving semiconductor elements formed on the semiconductor layer 111.

[0026] Furthermore, the circuit layer 112 has a first insulating layer 121, a second insulating layer 122, and a third insulating layer 123 laminated on it. The first insulating layer 121 and the third insulating layer 123 are made of, for example, silicon oxide (SiO2). ２ The second insulating layer 122 is a low-k layer. Examples of low-k materials include silicon oxide and silicon hydride carbon oxide (SiCOH).

[0027] Furthermore, in the first semiconductor substrate 101, the first seal ring 131 surrounds the outer periphery of the circuit layer 112. Similarly, in the second semiconductor substrate 102, the second seal ring 132 surrounds the outer periphery of the circuit layer 112.

[0028] The first seal ring 131 is a conductive member for suppressing the diffusion of moisture from the bonding surface S between the first semiconductor substrate 101 and the second semiconductor substrate 102 to the circuit layer 112 of the first semiconductor substrate 101. On the other hand, the second seal ring 132 is a conductive member for suppressing the diffusion of moisture from the bonding surface S to the circuit layer 112 of the second semiconductor substrate 102. The first seal ring 131 and the second seal ring 132 are positioned offset from each other in the X direction. In this embodiment, the second seal ring 132 is positioned outside the first seal ring 131.

[0029] Each of the first seal ring 131 and the second seal ring 132 has a first metal layer 141, a second metal layer 142, a third metal layer 143, a fourth metal layer 144, and contact vias 145. Each metal layer and contact via 145 can be formed using, for example, copper.

[0030] The first metal layer 141 is placed within the first insulating layer 121. The second metal layer 142 is placed on the first metal layer 141 via the second insulating layer 122. The third metal layer 143 is placed on the second metal layer 142 via the second insulating layer 122. The fourth metal layer 144 is placed on the third metal layer 143 via the third insulating layer 123. The contact vias 145 extend in the Z direction and are connected to each of the first to fourth metal layers 141 to 144.

[0031] A protective film 124 is formed between the circuit layer 112 and the bonding layer 113. The protective film 124 of the first semiconductor substrate 101 is an insulating member for suppressing the diffusion of moisture from the first semiconductor substrate 101 to the circuit layer 112. On the other hand, the protective film 124 of the second semiconductor substrate 102 is an insulating member for suppressing the diffusion of moisture from the second semiconductor substrate 102 to the circuit layer 112. For the protective film 124, an insulating film made of an insulating two-dimensional material such as silicon nitride (SiN) film, silicon carbonitride (SiCN) film, silicon oxynitride (SiON) film, silicon carbonitride (SiCO) film, silicon carbonate nitride (SiCON) film, silicon carbide (SiC), or boron nitride (BN) film can be applied.

[0032] A fourth insulating layer 125 is provided in the bonding layer 113. The fourth insulating layer 125 is, for example, a silicon oxide layer. A third seal ring 133 is provided in both the circuit layer 112 and the bonding layer 113. The third seal ring 133 is a conductive member for suppressing the diffusion of moisture from the bonding surface S between the first semiconductor substrate 101 and the second semiconductor substrate 102 to the circuit layer 112 of each semiconductor substrate.

[0033] The third seal ring 133 has a fifth metal layer 151 and contact vias 152. The fifth metal layer 151 and contact vias 152 can be formed from the same material as the first seal ring 131 and the second seal ring 132, for example, copper.

[0034] The fifth metal layer 151 is located in the same layer as the fourth metal layer 144. The contact vias 152 extend in the Z direction within the fourth insulating layer 125 and are connected to the fifth metal layer 151. In the third seal ring 133, the contact vias 152 are joined together in the Z direction. The fifth metal layers 15 face each other in the Z direction via the contact vias 152.

[0035] Here, with reference to Figures 3 and 4, a comparative example will be described that is in comparison with the semiconductor device 1 according to the first embodiment described above. Figure 3 is a diagram showing a schematic cross-sectional structure of a semiconductor device according to the comparative example. Figure 4 is a diagram showing a schematic cross-sectional structure of the semiconductor device according to the first embodiment.

[0036] In the semiconductor device 100 according to this comparative example, when the first semiconductor substrate 101 and the second semiconductor substrate 102 are joined, the first seal ring 131 and the second seal ring 132 are positioned offset in the X direction. Therefore, a moisture diffusion path exists from the joining surface S toward the circuit layer 112. In order to reduce the influence of moisture, it is necessary to ensure a sufficient distance L0 from the end of each semiconductor substrate to form the circuit arrangement region R0 of the circuit layer 112. As a result, the size of the circuit arrangement region R0 is limited.

[0037] In contrast, in the semiconductor device 1 according to this embodiment, the third seal rings 133 are joined together at the bonding surface S, as shown in Figure 4. A protective film 124 is provided between the circuit layer 112 and the bonding surface S. The protective film 124 is connected to the third seal rings 133. Therefore, the moisture diffusion path from the bonding surface S to the circuit layer 112 is blocked by the third seal rings 133 and the protective film 124. As a result, the distance L1 from the end of each semiconductor substrate can be made shorter than the distance L0 in the comparative example described above. As a result, a circuit arrangement area R1 larger than the circuit arrangement area R0 can be secured.

[0038] Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement area.

[0039] (Second Embodiment) Figure 5 is a cross-sectional view of a semiconductor device according to the second embodiment. Here, the differences from the semiconductor device 1 according to the first embodiment described above will be explained in detail. The semiconductor device 2 according to this embodiment differs from the first embodiment in the structure of the third seal ring 133. In the first embodiment, the fifth metal layer 151 is arranged in the same layer as the fourth metal layer 144.

[0040] In contrast, in the present embodiment, the fifth metal layer 151 is arranged at a position different from that of the fourth metal layer 144. Specifically, the fifth metal layer 151 is formed in the bonding layer 113. That is, the fifth metal layer 151 is arranged in a layer opposite to the fourth metal layer 144 in the Z direction with the protective film 124 interposed therebetween. Even when the fifth metal layer 151 is arranged in the bonding layer 113 as described above, moisture that has intruded from the bonding surface S is blocked from diffusing into the circuit layer 112 by the third seal ring 133 and the protective film 124.

[0041] Therefore, even in the present embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement region.

[0042] (Third Embodiment) FIG. 6 is a cross-sectional view of a semiconductor device according to the third embodiment. Here, description will be given focusing on points different from the semiconductor device 2 according to the second embodiment described above. The semiconductor device 3 according to the present embodiment differs from the second embodiment in the structure of the third seal ring 133. The third seal ring 133 according to the second embodiment includes the fifth metal layer 151 and a contact via 152.

[0043] In contrast, the third seal ring 133 according to the present embodiment does not include the fifth metal layer 151, and is configured only by the contact via 152. One end of this contact via 152 is in contact with the protective film 124. Even when the third seal ring 133 is configured only by the contact via 152 as described above, moisture that has intruded from the bonding surface S is blocked from diffusing into the circuit layer 112 by the third seal ring 133 and the protective film 124.

[0044] Therefore, even in the present embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement region. Furthermore, in the present embodiment, the step of forming the fifth metal layer 151 is not required, so that the manufacturing time can be shortened.

[0045] Fig. 7 is a cross-sectional view of a semiconductor device according to a modification of the third embodiment. As in the third embodiment described above, forming the contact via 152 so as to terminate within the bonding layer 113 requires an advanced manufacturing process. In contrast, in the semiconductor device 3a according to the present modification, the contact via 152 terminates within the circuit layer 112. In this case, since the contact via 152 may penetrate the protective film 124, an advanced manufacturing process is not required.

[0046] Even if the contact via 152 penetrates the protective film 124, moisture that has entered from the bonding surface S can be prevented from diffusing into the circuit layer 112 by the third seal ring 133 and the protective film 124.

[0047] Therefore, even in the present modification, it is possible to suppress diffusion of moisture from the bonding surface S and expand the circuit arrangement region. Furthermore, in the present modification, an advanced manufacturing process is not required compared to the third embodiment, so the manufacturing process can be simplified.

[0048] (Fourth Embodiment) Fig. 8 is a cross-sectional view of a semiconductor device according to the fourth embodiment. Here, description will be focused on points that differ from the semiconductor device 1 according to the first embodiment described above.

[0049] In the semiconductor device 4 according to the present embodiment, the protective film 124 is not provided on the first semiconductor substrate 101. In other words, the protective film 124 is not provided below the bonding surface S. Further, the third seal ring 133 is connected to the first seal ring 131. In the third seal ring 133, the contact via 152 of the first semiconductor substrate 101 is connected to the fourth metal layer 144.

[0050] In the semiconductor device 4 according to the present embodiment configured as described above, diffusion of moisture that has entered from the bonding surface S into the circuit layer 112 of the second semiconductor substrate 102 is blocked by the protective film 124. Further, this moisture is blocked by the third seal ring 133 connected to the first seal ring 131 from diffusing into a region inner than the first seal ring 131 in the circuit layer 112 of the first semiconductor substrate 101, that is, the circuit arrangement region.

[0051] Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement area. Furthermore, in this embodiment, the steps of forming a protective film 124 on the first semiconductor substrate 101 and forming the fifth metal layer 151 of the third seal ring 133 are unnecessary, thus shortening the manufacturing time.

[0052] (Fifth Embodiment) Figure 9 is a cross-sectional view of the semiconductor device according to the fifth embodiment. Here, the differences from the semiconductor device 1 according to the first embodiment described above will be explained in detail.

[0053] In the semiconductor device 5 according to this embodiment, the second semiconductor substrate 102 is not provided with a protective film 124. In other words, the upper side of the bonding surface S is not provided with a protective film 124. Also, the third seal ring 133 is connected to the second seal ring 132. In the third seal ring 133, the contact vias 152 of the second semiconductor substrate 102 are connected to the fourth metal layer 144.

[0054] In the semiconductor device 5 configured as described above according to this embodiment, moisture that enters from the bonding surface S is prevented from diffusing into the circuit layer 112 of the first semiconductor substrate 101 by the protective film 124. Furthermore, this moisture is prevented from diffusing into the region inside the second seal ring 132 in the circuit layer 112 of the second semiconductor substrate 102, i.e., the circuit arrangement region, by the third seal ring 133 connected to the second seal ring 132.

[0055] Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement area. Furthermore, in this embodiment, the steps of forming a protective film 124 on the second semiconductor substrate 102 and forming the fifth metal layer 151 of the third seal ring 133 are unnecessary, thus shortening the manufacturing time.

[0056] (Sixth Embodiment) Figure 10 is a cross-sectional view of the semiconductor device according to the sixth embodiment. Here, the differences from the semiconductor device 1 according to the first embodiment described above will be explained in detail.

[0057] In the semiconductor device 6 according to this embodiment, the protective film 124 is provided in the middle of the second seal ring 132. Specifically, the protective film 124 is provided between the third metal layer 143 and the fourth metal layer 144 in the second seal ring 132.

[0058] Furthermore, the third seal ring 133 has a sixth metal layer 153 and a contact via 154 in addition to the fifth metal layer 151 and contact via 152. The sixth metal layer 153 is provided in the same layer as the third metal layer 143. The contact via 154 extends in the Z direction and connects the fifth metal layer 151 and the sixth metal layer 153.

[0059] In the semiconductor device 6 configured as described above according to this embodiment, moisture that enters from the bonding surface S is prevented from diffusing into the region inside the first seal ring 131 in the circuit layer 112 of the first semiconductor substrate 101 and into the region inside the second seal ring 132 in the circuit layer 112 of the second semiconductor substrate 102 by the protective film 124 and the third seal ring 133. Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement area.

[0060] (Seventh Embodiment) Figure 11 is a cross-sectional view of the semiconductor device according to the seventh embodiment. Here, the differences from the semiconductor device 1 according to the first embodiment described above will be explained in detail.

[0061] In the semiconductor device 7 according to this embodiment, a protective film 124 is provided on the bonding surface S. That is, the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded together by the protective films 124. In addition, in this semiconductor device 7, a third seal ring 133 is connected to the first seal ring 131 and the second seal ring 132, respectively. Specifically, the third seal ring 133 has a fifth metal layer 151 and contact vias 152, as well as contact vias 155.

[0062] The contact via 155 provided on the first semiconductor substrate 101 is positioned between the fourth metal layer 144 of the first seal ring 131 and the contact via 152 provided on the second semiconductor substrate 102. The contact via 155 provided on the second semiconductor substrate 102 is positioned between the fourth metal layer 144 of the second seal ring 132 and the contact via 152 provided on the first semiconductor substrate 101.

[0063] In the semiconductor device 7 configured as described above according to this embodiment, moisture that enters from the bonding surface S is prevented from diffusing into the region inside the first seal ring 131 in the circuit layer 112 of the first semiconductor substrate 101 and into the region inside the second seal ring 132 in the circuit layer 112 of the second semiconductor substrate 102 by the protective film 124 and the third seal ring 133. Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement area.

[0064] In this embodiment, the protective film 124 is provided on the bonding surface S, but it may also be provided near the bonding surface S. Specifically, the protective film 124 may be placed in the region R between the fifth metal layer 151 on the first semiconductor substrate 101 side and the fifth metal layer 151 on the second semiconductor substrate 102 side. In this case as well, the protective film 124 and the third seal ring 133 can suppress the diffusion of moisture into the circuit layer 112.

[0065] Figure 12 is a cross-sectional view of a semiconductor device according to a modification of the seventh embodiment. In the semiconductor device 7a according to this modification, the structure of the third seal ring 133 differs from that of the semiconductor device 7 according to the seventh embodiment described above. Specifically, the third seal ring 133 according to this modification does not have a fifth metal layer 151.

[0066] Even without the fifth metal layer 151, moisture that enters from the bonding surface S can be prevented from diffusing into the circuit layer 112 by the third seal ring 133 and the protective film 124. Therefore, in this modified example as well, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit placement area. Furthermore, in this modified example, the manufacturing process for the fifth metal layer 151 is unnecessary, making it possible to shorten the manufacturing time.

[0067] (Eighth Embodiment) Figure 13 is a plan view of the semiconductor device according to the eighth embodiment. Figure 14 is a cross-sectional view along the cutting line B-B shown in Figure 13. Here, we will mainly explain the differences from the semiconductor device 1 according to the first embodiment described above. In the semiconductor device 1 according to the first embodiment described above, the third seal ring 133 is arranged between the first seal ring 131 and the second seal ring 132.

[0068] On the other hand, in the semiconductor device 8 according to this embodiment, the third seal ring 133 is positioned outside the second seal ring 132. That is, the third seal ring 133 is positioned furthest out among the seal rings.

[0069] Even with the third seal ring 133 positioned as described above, the protective film 124 and the third seal ring 133 prevent diffusion to the region of the circuit layer 112 of the first semiconductor substrate 101 that is inside the first seal ring 131, and to the region of the circuit layer 112 of the second semiconductor substrate 102 that is inside the second seal ring 132. Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement area. Furthermore, in this embodiment, since the third seal ring 133 is positioned on the outermost side, it is possible to further expand the circuit arrangement area R compared to the first embodiment.

[0070] (Ninth Embodiment) Figure 15 is a plan view of the semiconductor device according to the ninth embodiment. Figure 16 is a cross-sectional view along the cutting line C-C shown in Figure 15. Furthermore, Figure 17 is a cross-sectional view along the cutting line D-D shown in Figure 15. Here, we will mainly explain the differences from the semiconductor device 1 according to the first embodiment described above. In the semiconductor device 1 according to the first embodiment, the positions of each seal ring do not overlap in the Z direction. That is, each seal ring does not overlap with each other in the Z direction.

[0071] On the other hand, the semiconductor device 16 according to this embodiment has an overlapping portion in which the second seal ring 132 overlaps with the third seal ring 133 in the Z direction, as shown in Figure 16, and an overlapping portion in which the first seal ring 131, the second seal ring 132, and the third seal ring 133 all overlap in the Z direction, as shown in Figure 17.

[0072] In the overlapping portion shown in Figure 16, the two contact vias 152 of the third seal ring 133 are connected vertically at the joint surface S. The upper contact via 152 is also connected to the fourth metal layer 144 of the second seal ring 132. The lower contact via 152 is also connected to the fifth metal layer 151 of the first seal ring 131, which is arranged in the same layer as the fourth metal layer 144.

[0073] In the overlapping portion shown in Figure 17, the third seal ring 133 has two contact vias 152 connected vertically at the joint surface S. The upper contact via 152 is also connected to the fourth metal layer 144 of the second seal ring 132. The lower contact via 152 is also connected to the fourth metal layer 144 of the first seal ring 131.

[0074] In the semiconductor device 9 configured as described above according to this embodiment, moisture that enters from the bonding surface S is prevented from diffusing into the region inside the first seal ring 131 in the circuit layer 112 of the first semiconductor substrate 101 and into the region inside the second seal ring 132 in the circuit layer 112 of the second semiconductor substrate 102 by the protective film 124 and the third seal ring 133. Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement area. Furthermore, in the third seal ring 133 according to this embodiment, since the position of a part of the seal ring overlaps in the Z direction, the area occupied by the seal ring relative to the substrate size (chip size) is reduced, making it possible to increase the area of ​​the circuit arrangement area.

[0075] Figure 18 is a cross-sectional view of a semiconductor device according to the first modified example of the ninth embodiment. This cross-sectional view corresponds to a cross-sectional view along the cutting line D-D shown in Figure 15. In the semiconductor device 9A according to this modified example, the structure of the first seal ring 131 differs from the structure of the second seal ring 132. Specifically, the planar area (area in the XY plane) of the first metal layers 141 to the fourth metal layers 144 and the number of contact vias 152 are different. For example, the planar area of ​​each metal layer of the first seal ring 131 is larger than the planar area of ​​each metal layer of the second seal ring 132. Also, the first seal ring 131 has three contact vias 145, while the second seal ring 132 has two contact vias 145.

[0076] Even though the upper and lower seal rings have different structures, as in this modified example, the diffusion of moisture that enters from the joint surface S is prevented by the protective film 124 and the third seal ring 133. Therefore, it is possible to suppress the diffusion of moisture from the joint surface S and expand the circuit placement area. In addition, in this modified example, the first seal ring 131 to the third seal ring 133 overlap in the Z direction, so the area occupied by the seal rings is reduced. Thus, it is possible to increase the area of ​​the circuit placement area.

[0077] Figure 19 is a cross-sectional view of a semiconductor device according to a second modification of the ninth embodiment. This cross-sectional view corresponds to a cross-sectional view along the cutting line D-D shown in Figure 15. In the semiconductor device 9B according to this modification, the structure of the first seal ring 131 differs from the structure of the second seal ring 132. Specifically, the structure of the metal layers differs between the first seal ring 131 and the second seal ring 132. In the second seal ring 132, the planar areas of all four metal layers are equal, whereas in the first seal ring 131, the planar area of ​​the uppermost fourth metal layer 144 is larger than the planar areas of the remaining metal layers (first metal layer 141 to third metal layer 143). Therefore, the remaining metal layers and each metal layer of the first metal layer 141 are connected via the third seal ring 133, while being offset from each other in the X direction.

[0078] Even though the upper and lower seal rings have different structures as in this modified example, the diffusion of moisture that enters from the joint surface S is prevented by the protective film 124 and the third seal ring 133, thus suppressing the diffusion of moisture from the joint surface S and expanding the circuit placement area. In addition, in this modified example, a part of the first seal ring 131 overlaps with the second seal ring 132 and the third seal ring 133 in the Z direction, so the area occupied by the seal rings is reduced. Therefore, it is possible to increase the area of ​​the circuit placement area.

[0079] (Tenth Embodiment) Figure 20 is a cross-sectional view of a semiconductor device according to the tenth embodiment. Here, the differences from the first embodiment described above will be explained in detail. In the semiconductor device 1 according to the first embodiment, the first semiconductor substrate 101 and the second semiconductor substrate 102 are joined together, whereas in the semiconductor device 10 according to this embodiment, the third semiconductor substrate 103 is joined between the first semiconductor substrate 101 and the second semiconductor substrate 102.

[0080] The third semiconductor substrate 103 has a semiconductor layer 111, a first circuit layer 112A, a second circuit layer 112B, a first junction layer 113A, and a second junction layer 113B. The first circuit layer 112A is laminated on the back surface (bottom surface) of the semiconductor layer 111. The first junction layer 113A is laminated on the bottom surface of the first circuit layer 112A. The second circuit layer 112B is laminated on the front surface (top surface) of the semiconductor layer 111. The second junction layer 113B is laminated on the top surface of the second circuit layer 112B. The first circuit layer 112A and the second circuit layer 112B are provided with circuits for processing signals output from semiconductor elements mounted on the second semiconductor substrate 102, and memory circuits for storing various information.

[0081] A fourth seal ring 134 is provided on the outer periphery of the first circuit layer 112A. A fifth seal ring 135 is provided on the outer periphery of the second circuit layer 112B. In this embodiment, the fifth seal ring 135 is positioned outside the fourth seal ring 134. The structures of the fourth seal ring 134 and the fifth seal ring 135 are the same as those of the first seal ring 131 described in the first embodiment, so their description is omitted.

[0082] The bonding layer 113 of the first semiconductor substrate 101 and the first bonding layer 113A of the third semiconductor substrate 103 are bonded together by a third seal ring 133A. In this embodiment, the third seal ring 133A surrounds the first bonding surface S1 between the first semiconductor substrate 101 and the third semiconductor substrate 103 between the first seal ring 131 and the fourth seal ring 134.

[0083] The bonding layer 113 of the second semiconductor substrate 102 and the second bonding layer 113B of the third semiconductor substrate 103 are bonded by a third seal ring 133B. In this embodiment, the third seal ring 133B surrounds the second bonding surface S2 between the second semiconductor substrate 102 and the third semiconductor substrate 103 between the second seal ring 132 and the fifth seal ring 135. The structures of the third seal ring 133A and the third seal ring 133B are the same as those of the third seal ring 133 described in the first embodiment, so their description is omitted.

[0084] In the semiconductor device 10 configured as described above according to this embodiment, moisture that enters from the first bonding surface S1 is prevented from diffusing into the region inside the first seal ring 131 in the circuit layer 112 of the first semiconductor substrate 101 and into the region inside the fourth seal ring 134 in the first circuit layer 112A of the third semiconductor substrate 103 by the protective film 124 and the third seal ring 133A.

[0085] Furthermore, moisture that enters from the second bonding surface S2 is prevented from diffusing into the region of the circuit layer 112 of the second semiconductor substrate 102 inside the second seal ring 132 and into the region of the second circuit layer 112B of the third semiconductor substrate 103 inside the fifth seal ring 135 by the protective film 124 and the third seal ring 133B.

[0086] Therefore, according to this embodiment, it is possible to expand the circuit layout area by suppressing the diffusion of moisture from the first bonding surface S1 and the second bonding surface S2. Furthermore, in the semiconductor device 10 according to this embodiment, it is possible to further increase the area of ​​the circuit layout area by increasing the number of semiconductor substrate layers.

[0087] (Eleventh Embodiment) Figure 21 is a cross-sectional view of the semiconductor device according to the eleventh embodiment. Here, the differences from the tenth embodiment described above will be explained in detail. In this embodiment, the structure of the fifth seal ring 135 differs from that of the tenth embodiment.

[0088] The fifth seal ring 135 according to this embodiment further includes a contact via 146 and a seventh metal layer 147 in addition to the components of the fifth seal ring 135 according to the tenth embodiment. The contact via 146 is a TSV (Through-Silicon Via) that penetrates the semiconductor layer 111 of the third semiconductor substrate 103 in the Z direction. The upper end of the contact via 146 is connected to the first metal layer 141. The lower end of the contact via 146 is connected to the seventh metal layer 147. The seventh metal layer 147 is arranged on the second insulating layer 122 of the first circuit layer 112A.

[0089] In the semiconductor device 11 configured as described above according to this embodiment, similar to the tenth embodiment, moisture that enters from the first bonding surface S1 is prevented from diffusing into the region inside the first seal ring 131 in the circuit layer 112 of the first semiconductor substrate 101 and into the region inside the fourth seal ring 134 in the first circuit layer 112A of the third semiconductor substrate 103 by the protective film 124 and the third seal ring 133A.

[0090] Furthermore, moisture that enters from the second bonding surface S2 is prevented from diffusing into the region of the circuit layer 112 of the second semiconductor substrate 102 inside the second seal ring 132 and into the region of the second circuit layer 112B of the third semiconductor substrate 103 inside the fifth seal ring 135 by the protective film 124 and the third seal ring 133B.

[0091] Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the first bonding surface S1 and the second bonding surface S2 and expand the circuit arrangement area. Furthermore, in the semiconductor device 11 according to this embodiment, since the fifth seal ring 135 has contact vias 146 and a seventh metal layer 147, the fifth seal ring 135 penetrates the semiconductor layer 111 and extends to the first circuit layer 112A. As a result, it is possible to stabilize the support of the fifth seal ring 135.

[0092] (Twelfth Embodiment) Figure 22 is a cross-sectional view of a semiconductor device according to the twelfth embodiment. Here, the differences from the first embodiment described above will be explained in detail. In the semiconductor device 12 according to this embodiment, a second semiconductor substrate 102A and a second semiconductor substrate 102B are bonded to a first semiconductor substrate 101. The second semiconductor substrate 102A and the second semiconductor substrate 102B are arranged side by side in the X direction. The planar area of ​​each second semiconductor substrate is smaller than the planar area of ​​the first semiconductor substrate 101. In this embodiment, the first semiconductor substrate 101 is a semiconductor wafer, and each second semiconductor substrate is a semiconductor chip.

[0093] Furthermore, in the semiconductor device 12 according to this embodiment, the first portion 133a of the third seal ring 133 is connected to the second seal ring 132 of the second semiconductor substrate 102A. In addition, the second portion 133b of the third seal ring 133 is provided between the first seal ring 131 and the second seal ring 132 of the second semiconductor substrate 102B. In order to accommodate the second portion 133b, the protective film 124 on the second semiconductor substrate side extends to the outside of the second semiconductor substrate 102B.

[0094] In the semiconductor device 12 configured as described above according to this embodiment, the protective film 124 and the first portion 133a and the second portion 133b prevent moisture that has entered from the bonding surface S from diffusing into the region inside the first seal ring 131 in the circuit layer 112 of the first semiconductor substrate 101 and into the region inside the second seal ring 132 in the circuit layer 112 of each second semiconductor substrate.

[0095] Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit arrangement area. Furthermore, in the semiconductor device 12 according to this embodiment, since the second portion 133b is provided, the first portion 133a can be made unnecessary between the second semiconductor substrate 102B and the first semiconductor substrate 101.

[0096] Figure 23 is a plan view of a semiconductor device according to a modified example of the twelfth embodiment. In the semiconductor device 12A according to this modified example, the planar shape of the second portion 133b of the third seal ring 133 is frame-shaped, enclosing both the second semiconductor substrate 102A and the second semiconductor substrate 102B.

[0097] Even if the second portion 133b is formed in a frame shape, the diffusion of moisture from the joint surface S is suppressed, making it possible to expand the circuit arrangement area. Furthermore, in this modified example, the first portion 133a is unnecessary, making it possible to increase the area of ​​the joint surface S.

[0098] (13th Embodiment) Figure 24 is a plan view of the semiconductor device according to the 13th embodiment. Figure 25 is a cross-sectional view of the semiconductor device according to the 13th embodiment. Here, we will mainly explain the differences from the 12th embodiment described above. In the semiconductor device 13 according to this embodiment, a second semiconductor substrate 102 is bonded to a first semiconductor substrate 101. The second semiconductor substrates 102 are arranged in a two-dimensional array along the X and Y directions.

[0099] Furthermore, in the semiconductor device 13 according to this embodiment, the third seal ring 133 is connected to the second seal ring 132 of the second semiconductor substrate 102. In addition, the inter-chip wiring that electrically connects the second semiconductor substrates 102 is formed in the scrub region R2. The scrub region R2 is a region formed between the second semiconductor substrates 102, as shown in Figure 25.

[0100] In the semiconductor device 13 configured as described above according to this embodiment, the protective film 124 and the third seal ring 133 prevent moisture that has entered from the bonding surface S from diffusing into the region of the circuit layer 112 of the first semiconductor substrate 101 that is inside the first seal ring 131 and into the region of the circuit layer 112 of each second semiconductor substrate 102 that is inside the second seal ring 132.

[0101] Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit layout area. Furthermore, in the semiconductor device 13 according to this embodiment, since the third seal ring 133 overlaps with the second seal ring 132 in the Z direction, the area of ​​the seal rings on the substrate is reduced. This makes it possible to further expand the circuit layout area.

[0102] Figure 26 is a cross-sectional view of a semiconductor device according to a modified example of the 13th embodiment. In the semiconductor device 13A according to this modified example, a circuit layer 112C and a bonding layer 113 are laminated on the surface (upper surface) of a semiconductor layer 111, and a circuit layer 112D and a bonding layer 113 are laminated on the back surface (lower surface) of the semiconductor layer 111. A protective film 124 is provided between the circuit layer 112D and the bonding layer 113. Furthermore, a support layer 114 is provided below the bonding layer 113. The support layer 114 is, for example, a silicon substrate.

[0103] Furthermore, in the semiconductor device 13A according to this modified example, the first seal ring 131, the second seal ring 132, and the third seal ring 133 are connected in an overlapping manner in the Z direction. In addition, the circuit arrangement region R3 of the circuit layer 112D is surrounded by the sixth seal ring 136. Inter-chip wiring and the like are formed in the circuit arrangement region R3.

[0104] In the semiconductor device 13A according to this modified configuration as described above, the protective film 124 and the third seal ring 133 prevent moisture that has entered from the bonding surface S from diffusing into the region inside the first seal ring 131 in the circuit layer 112C of the first semiconductor substrate 101 and into the region inside the second seal ring 132 in the circuit layer 112 of each second semiconductor substrate 102. Furthermore, the protective film 124 and the sixth seal ring 136 provided between the circuit layer 112D and the bonding layer 113 prevent the diffusion of moisture into the circuit arrangement region R.

[0105] Therefore, according to this modified example, it is possible to suppress the diffusion of moisture from the bonding surface S and expand the circuit layout area. Furthermore, in the semiconductor device 13A according to this modified example, since the first seal ring 131 to the third seal ring 133 overlap in the Z direction, the area of ​​the seal rings on the substrate is reduced. This makes it possible to further expand the circuit layout area.

[0106] (14th Embodiment) Figure 26 is a cross-sectional view of the semiconductor device according to the 14th embodiment. Here, the differences from the 10th embodiment described above will be explained in detail.

[0107] In this embodiment, the semiconductor device 14 is not provided with a third seal ring 133A. In this case, there is a concern about the diffusion of moisture from the first bonding surface S1 between the first semiconductor substrate 101 and the third semiconductor substrate 103.

[0108] Therefore, in this embodiment, the bonding layer 113 and the circuit arrangement region R15 in the first bonding layer 113A, which are bonded at the first bonding surface S1, are arranged such that the distance L2 from the end of the third semiconductor substrate 103 is longer than the diffusion distance of moisture. Furthermore, the circuit arrangement region R14, which is placed on top of the circuit arrangement region R15, is surrounded by a fourth seal ring 134 positioned at a distance L3 (< L2) from the end of the third semiconductor substrate 103.

[0109] In the semiconductor device 14 configured as described above according to this embodiment, moisture that enters from the first bonding surface S1 is prevented from diffusing into the circuit layout region R14 and circuit layout region R16 by the protective film 124. Furthermore, since the circuit layout region R15 is positioned sufficiently inward from the moisture diffusion distance as described above, moisture can be prevented from entering.

[0110] Furthermore, moisture that enters from the second bonding surface S2 is prevented from diffusing into the circuit arrangement region R13, circuit arrangement region R12, and circuit arrangement region R11 by the protective film 124 and the third seal ring 133B.

[0111] Therefore, according to this embodiment, it is possible to suppress the diffusion of moisture from the first bonding surface S1 and the second bonding surface S2 and expand the circuit arrangement area. Furthermore, in the semiconductor device 14 according to this embodiment, the process of forming the third seal ring 133A is unnecessary, so the manufacturing time can be shortened compared to the semiconductor device 10 according to the tenth embodiment.

[0112] <Examples of application to mobile devices> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0113] Figure 28 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0114] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 28, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0115] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0116] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0117] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0118] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0119] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0120] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0121] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0122] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0123] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 28, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0124] Figure 29 shows an example of the installation position of the imaging unit 12031.

[0125] In Figure 29, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0126] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by imaging units 12101 and 12105 are mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0127] Figure 29 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0128] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0129] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0130] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0131] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0132] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, any of the semiconductor devices of the embodiments described above can be mounted on the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, the optical characteristics are improved. As a result, it becomes possible to improve the performance of the vehicle 12100.

[0133] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0134] Furthermore, this technology can take the following configuration.

[0135] (1) A semiconductor device comprising: a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; a protective film; a first seal ring provided on the first semiconductor substrate; a second seal ring provided on the second semiconductor substrate; at least one protective film provided on the bonding surface between the first semiconductor substrate and the second semiconductor substrate, or on at least one of the upper and lower sides of the bonding surface; and a third seal ring provided on the bonding surface and connected to the protective film.

[0136] (2) The semiconductor device according to (1), wherein the third seal ring has a metal layer and contact vias connected to the metal layer.

[0137] (3) The semiconductor device according to (1) or (2), wherein the third seal ring is positioned differently from the first seal ring and the second seal ring, or is positioned to connect with at least one of the first seal ring and the second seal ring.

[0138] (4) The semiconductor device according to any one of (1) to (3), wherein the third seal ring has a cross section connected to the second seal ring and a cross section connected to the first seal ring and the second seal ring.

[0139] (5) The semiconductor device according to any one of (1) to (4), wherein the protective film comprises an insulating two-dimensional material.

[0140] (6) The semiconductor device according to any one of (1) to (5), wherein the first semiconductor substrate and the second semiconductor substrate include a circuit layer in the first seal ring or the second seal ring, and the circuit layer includes a low-k layer.

[0141] (7) The semiconductor device according to any one of (1) to (6), further comprising: a third semiconductor substrate bonded between the first semiconductor substrate and the second semiconductor substrate; a fourth seal ring connected to the protective film on the upper side of the first bonding surface between the first semiconductor substrate and the third semiconductor substrate; and a fifth seal ring connected to the protective film on the lower side of the second bonding surface between the third semiconductor substrate and the second semiconductor substrate.

[0142] (8) The semiconductor device according to (7), wherein the fifth seal ring includes a TSV that penetrates the semiconductor layer of the third semiconductor substrate.

[0143] (9) The semiconductor device according to any one of (1) to (8), wherein the planar area of ​​the first semiconductor substrate is different from the planar area of ​​the second semiconductor substrate.

[0144] (10) The semiconductor device according to any one of (1) to (9), wherein the planar area of ​​the first semiconductor substrate is larger than the planar area of ​​the second semiconductor substrate, a plurality of second semiconductor substrates are bonded to the first semiconductor substrate, and the third seal ring has a frame-shaped portion surrounding the plurality of second semiconductor substrates.

[0145] (11) The semiconductor device according to any one of (1) to (10), wherein the third seal ring has a portion that penetrates the protective film.

[0146] (12) The semiconductor device according to (3), wherein the second seal ring is positioned outside the first seal ring, and the third seal ring is positioned outside the second seal ring.

[0147] (13) The semiconductor device according to any one of (1) to (12), wherein the protective film is provided in the middle of the second seal ring.

[0148] (14) The semiconductor device according to any one of (1) to (13), wherein the structure of the first seal ring is different from the structure of the second seal ring.

[0149] (15) The semiconductor device according to (1) to (14), wherein the first seal ring includes a plurality of metal layers arranged in layers, and the uppermost metal layer has the largest planar area among the plurality of metal layers.

[0150] 1-14: Semiconductor device 101: First semiconductor substrate 102: Second semiconductor substrate 103: Third semiconductor substrate 124: Protective film 131: First seal ring 132: Second seal ring 133: Third seal ring 134: Fourth seal ring 135: Fifth seal ring 141: First metal layer 142: Second metal layer 143: Third metal layer 144: Fourth metal layer 145: Contact via

Claims

1. A semiconductor device comprising: a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; a protective film; a first seal ring provided on the first semiconductor substrate; a second seal ring provided on the second semiconductor substrate; at least one protective film provided on the bonding surface between the first semiconductor substrate and the second semiconductor substrate, or on at least one of the upper and lower sides of the bonding surface; and a third seal ring provided on the bonding surface and connected to the protective film.

2. The semiconductor device according to claim 1, wherein the third seal ring comprises a metal layer and contact vias connected to the metal layer.

3. The semiconductor device according to claim 1, wherein the third seal ring is positioned differently from the first seal ring and the second seal ring, or is positioned to connect with at least one of the first seal ring and the second seal ring.

4. The semiconductor device according to claim 1, wherein the third seal ring has a cross section connected to the second seal ring and a cross section connected to the first seal ring and the second seal ring.

5. The semiconductor device according to claim 1, wherein the protective film comprises an insulating two-dimensional material.

6. The semiconductor device according to claim 1, wherein the first semiconductor substrate and the second semiconductor substrate include a circuit layer in the first seal ring or the second seal ring, and the circuit layer includes a low-k layer.

7. The semiconductor device according to claim 1, further comprising: a third semiconductor substrate bonded between the first semiconductor substrate and the second semiconductor substrate; a fourth seal ring connected to the protective film on the upper side of the first bonding surface between the first semiconductor substrate and the third semiconductor substrate; and a fifth seal ring connected to the protective film on the lower side of the second bonding surface between the third semiconductor substrate and the second semiconductor substrate.

8. The semiconductor device according to claim 7, wherein the fifth seal ring includes a TSV that penetrates the semiconductor layer of the third semiconductor substrate.

9. The semiconductor device according to claim 1, wherein the planar area of ​​the first semiconductor substrate is different from the planar area of ​​the second semiconductor substrate.

10. The semiconductor device according to claim 1, wherein the planar area of ​​the first semiconductor substrate is larger than the planar area of ​​the second semiconductor substrate, a plurality of second semiconductor substrates are bonded to the first semiconductor substrate, and the third seal ring has a frame-shaped portion surrounding the plurality of second semiconductor substrates.

11. The semiconductor device according to claim 1, wherein the third seal ring has a portion that penetrates the protective film.

12. The semiconductor device according to claim 3, wherein the second seal ring is positioned outside the first seal ring, and the third seal ring is positioned outside the second seal ring.

13. The semiconductor device according to claim 1, wherein the protective film is provided in the middle of the second seal ring.

14. The semiconductor device according to claim 1, wherein the structure of the first seal ring is different from the structure of the second seal ring.

15. The semiconductor device according to claim 14, wherein the first seal ring includes a plurality of metal layers arranged in layers, and the uppermost metal layer has the largest planar area among the plurality of metal layers.

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