Photodetection device and electronic apparatus

Abstract

A photodetection device according to one embodiment of the present disclosure comprises a first pixel, a first signal line, a reading circuit, and a control circuit. The reading circuit includes: a first holding circuit that includes a first capacitive element and can hold signals that are inputted via the first signal line; and a first AD conversion circuit. The control circuit can execute control that causes a pixel signal that is inputted to the first capacitive element to be held by the first capacitive element for a first time period and causes an AD conversion to be performed on the pixel signal by the first AD conversion circuit. The control circuit can also execute control that causes a first signal that has a first voltage and is inputted to the first capacitive element to be held by the first capacitive element for a second time period that is longer than the first time period.

Description

Photodetection Device and Electronic Apparatus

[0001] The present disclosure relates to a photodetection device and an electronic apparatus.

[0002] An imaging apparatus including a signal processing unit having a function of performing diagnostic processing and outputting a diagnostic result has been proposed (Patent Document 1).

[0003] International Publication No. 2018 / 150790

[0004] In a device that detects light, it is desirable to be compatible with failure detection.

[0005] It is desirable to provide a photodetection device that is advantageous for failure detection.

[0006] A photodetection device according to an embodiment of the present disclosure includes: a first pixel having a first photoelectric conversion element; a first signal line electrically connected to the first pixel; a readout circuit including a first holding circuit that includes a first capacitive element and is capable of holding a signal input via the first signal line, and a first AD conversion circuit; and a control circuit capable of controlling the readout circuit. The control circuit is capable of executing control to hold a pixel signal input to the first capacitive element by the first capacitive element for a first time, and perform AD conversion on the pixel signal by the first AD conversion circuit. The control circuit is capable of executing control to hold a first signal having a first voltage input to the first capacitive element by the first capacitive element for a second time longer than the first time. An electronic apparatus according to an embodiment of the present disclosure includes: an optical system; and the photodetection device that receives light transmitted through the optical system. The photodetection device includes: a first pixel having a first photoelectric conversion element; a first signal line electrically connected to the first pixel; a readout circuit including a first holding circuit that includes a first capacitive element and is capable of holding a signal input via the first signal line, and a first AD conversion circuit; and a control circuit capable of controlling the readout circuit. The control circuit is capable of executing control to hold a pixel signal input to the first capacitive element by the first capacitive element for a first time, and perform AD conversion on the pixel signal by the first AD conversion circuit. The control circuit is capable of executing control to hold a first signal having a first voltage input to the first capacitive element by the first capacitive element for a second time longer than the first time.

[0007] Figure 1 is a block diagram showing an example of the schematic configuration of an imaging device, which is an example of a photodetector according to an embodiment of the present disclosure. Figure 2 is a diagram showing an example of the planar configuration of an imaging device according to an embodiment of the present disclosure. Figure 3 is a diagram showing an example of the pixel circuit configuration of an imaging device according to an embodiment of the present disclosure. Figure 4 is a diagram for explaining an example of the configuration of an imaging device according to an embodiment of the present disclosure. Figure 5 is a diagram for explaining an example of the configuration of the readout circuit of an imaging device according to an embodiment of the present disclosure. Figure 6 is a timing chart showing an example of the operation of an imaging device according to an embodiment of the present disclosure. Figure 7 is a timing chart showing an example of the operation of an imaging device according to an embodiment of the present disclosure. Figure 8 is a diagram for explaining an example of the fault determination process in an imaging device according to an embodiment of the present disclosure. Figure 9 is a flowchart showing an example of the operation of an imaging device according to an embodiment of the present disclosure. Figure 10 is a diagram for explaining another example of the configuration of an imaging device according to an embodiment of the present disclosure. Figure 11 is a diagram for explaining another example of the configuration of the readout circuit of an imaging device according to an embodiment of the present disclosure. Figure 12 is a flowchart showing another example of the operation of an imaging device according to an embodiment of the present disclosure. Figure 13 is a diagram for explaining an example of the processing sequence of an imaging device according to an embodiment of the present disclosure. Figure 14 is a diagram illustrating an example configuration of a photodetection system according to an embodiment of the present disclosure. Figure 15 is a diagram illustrating an example configuration of data generated by an imaging device according to an embodiment of the present disclosure. Figure 16 is a diagram illustrating an example configuration of an imaging device according to a modified example of the present disclosure. Figure 17 is a block diagram showing an example configuration of an electronic device having an imaging device. Figure 18 is a block diagram illustrating an example of a schematic configuration of a vehicle control system. Figure 19 is an explanatory diagram showing an example of the installation positions of an external information detection unit and an imaging unit. Figure 20 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. Figure 21 is a block diagram illustrating an example of the functional configuration of a camera head and a CCU.

[0008] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order: 1. Embodiments 2. Modifications 3. Application Examples 4. Application Examples

[0009] <1. Embodiments> Figure 1 is a block diagram showing an example of the schematic configuration of an imaging device, which is an example of a light detection device according to an embodiment of the present disclosure. A light detection device is a device capable of detecting incident light. An imaging device 1, which is an example of a light detection device, has a plurality of pixels P including a photoelectric conversion unit, and is configured to generate a signal by photoelectric conversion of incident light.

[0010] The imaging device 1 is configured using, for example, a substrate (such as a silicon (Si) substrate or a silicon on insulator (SOI) substrate) on which a photoelectric conversion unit for each pixel P is provided. The imaging device 1 receives light transmitted through an optical system (not shown) and generates a signal. The imaging device 1 may have a structure (i.e., a laminated structure) composed of multiple substrates (or semiconductor layers) stacked on top of each other.

[0011] The imaging device 1 has a region (pixel section 100) where multiple pixels P are provided, as shown in the example in Figure 1. The imaging device 1 has, for example, a pixel section 100 in which multiple pixels P are arranged in a matrix in two dimensions as an imaging area. The photoelectric conversion section of each pixel P is a photoelectric conversion element, and can also be called a photoelectric conversion region. The photoelectric conversion section of the pixel P is, for example, a photodiode (PD), and is configured to convert light into photoelectric energy.

[0012] The imaging device 1 captures incident light (image light) from the subject to be measured, for example, through an optical system including an optical lens and an aperture (diaphragm). The imaging device 1 captures an image of the subject formed by the optical system. The imaging device 1 generates a pixel signal by photoelectric conversion of the received light (e.g., visible light, infrared light, etc.). The imaging device 1, being a light detection device, is a device capable of receiving light and generating a signal, and can also be called a light receiving device.

[0013] The imaging device 1 (light detection device) is configured as an image sensor, a distance measuring sensor, etc. For example, the imaging device 1 is a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a CCD (Charge Coupled Device) image sensor, etc. The imaging device 1 can be used in various electronic devices such as digital still cameras, video cameras, and mobile phones.

[0014] [Outline Configuration of the Imaging Device] The imaging device 1, as shown in the example in Figure 1, includes a pixel unit 100, a pixel control circuit 111, a readout circuit 112, a processing circuit 113, and a control circuit 114. The imaging device 1 is also provided with a plurality of control lines Lc and a plurality of signal lines VSL. The pixel unit 100 is a pixel array in which a plurality of pixels P are arranged. The number and arrangement of pixels P provided in the pixel unit 100 can be changed as appropriate.

[0015] The control line Lc is a signal line capable of transmitting signals to control the pixel P, and is connected to the pixel control circuit 111 and the pixel P of the pixel unit 100. The control line Lc is configured to transmit, for example, a control signal for reading signals from the pixel P. In the example shown in Figure 1, multiple control lines Lc are wired to each pixel row of the pixel unit 100, which is composed of multiple pixels P arranged horizontally (in the row direction).

[0016] The multiple control lines Lc for each pixel row of the imaging device 1 include, for example, wiring that transmits signals to control the transfer transistor, wiring that transmits signals to control the selection transistor, wiring that transmits signals to control the reset transistor, etc. The control lines Lc can also be called drive lines (or pixel drive lines) that transmit signals to drive the pixels P.

[0017] The signal line VSL is a signal line capable of transmitting signals from pixels P, and is connected to the pixels P of the pixel unit 100 and the readout circuit 112. The signal line VSL is a vertical signal line and is configured to transmit signals output from pixels P. For example, in the pixel unit 100, a signal line VSL is wired for each pixel column, which is composed of multiple pixels P arranged vertically (in the column direction).

[0018] The pixel control circuit 111 is configured to control each pixel P of the pixel unit 100. The pixel control circuit 111 (pixel control unit) is composed of multiple circuits, including, for example, a buffer, a shift register, an address decoder, etc. The pixel control circuit 111 generates a signal for controlling the pixels P and outputs it to each pixel P of the pixel unit 100 via a control line Lc. The pixel control circuit 111 is controlled by the control circuit 114 and controls the pixels P of the pixel unit 100.

[0019] The pixel control circuit 111 generates signals to control the pixels P, such as signals to control the transfer transistor of the pixel P, signals to control the selection transistor, and signals to control the reset transistor, and supplies these signals to each pixel P via the control line Lc. The pixel control circuit 111 can perform control to read out pixel signals from each pixel P. The pixel control circuit 111 can also be described as a pixel driving circuit (pixel driving unit) configured to drive each pixel P.

[0020] The control circuit 114 is configured to control various parts of the imaging device 1. The control circuit 114 includes, for example, a PLL (Phase Locked Loop), a timing generator, a DAC (Digital to Analog Converter), etc. As an example, the control circuit 114 can receive a clock and data commanding the operating mode from an external source, and can also output data such as internal information of the imaging device 1.

[0021] The control circuit 114 includes, for example, a timing generator configured to generate various timing signals. Based on the various timing signals (pulse signals, clock signals, etc.) generated by the timing generator, the control circuit 114 controls the operation of the pixel control circuit 111, the readout circuit 112, and the processing circuit 113, etc. Note that the control circuit 114 and the processing circuit 113 may be configured as an integrated unit.

[0022] The readout circuit 112 is configured to perform signal processing on the input signal. The readout circuit 112 includes a load circuit, a holding circuit, an AD (Analog Digital) conversion circuit, etc., as will be described later. The load circuit is, for example, composed of a current source capable of supplying current to the amplification transistor of the pixel P, and together with the amplification transistor of the pixel P, it forms a source follower circuit.

[0023] The load circuit, holding circuit, and A / D conversion circuit of the readout circuit 112 are provided, for example, for each of the multiple signal lines VSL. The readout circuit 112 may also have an amplification circuit configured to amplify the signals input via the signal lines VSL. As an example, a load circuit, amplification circuit, holding circuit, and A / D conversion circuit are provided for each pixel row of the pixel section 100.

[0024] The signals output from each pixel P selected and scanned by the pixel control circuit 111 are input to the readout circuit 112 via the signal line VSL. The readout circuit 112 performs signal processing such as AD conversion and CDS (Correlated Double Sampling). The signals from each pixel P transmitted via each signal line VSL are processed by the readout circuit 112 and output to the processing circuit 113.

[0025] The processing circuit 113 is configured to perform signal processing. The processing circuit 113 includes a plurality of logic circuits, and for example, it includes circuits that perform various signal processing on the input pixel signals. The processing circuit 113 may include, as an example, an arithmetic circuit, a memory circuit, etc. The processing circuit 113 may also include an I / F (interface) circuit.

[0026] The processing circuit 113 performs signal processing on the input pixel signal and outputs the processed pixel signal. Furthermore, as will be described later, the processing circuit 113 is configured to perform fault detection. The processing circuit 113 may include a processor and memory. The processing circuit 113 may also include a readout circuit 112.

[0027] The pixel unit 100, pixel control circuit 111, readout circuit 112, processing circuit 113, control circuit 114, etc., described above may be provided on a single substrate or on multiple substrates. The imaging device 1 may have a laminated structure formed by stacking multiple substrates (for example, two or more semiconductor substrates).

[0028] The pixel control circuit 111, readout circuit 112, processing circuit 113, control circuit 114, etc. of the imaging device 1 may be provided, for example, as peripheral circuits around the pixel section 100 (i.e., the pixel array). Furthermore, some or all of the pixel control circuit 111, readout circuit 112, processing circuit 113, and control circuit 114 may be configured integrally.

[0029] Figure 2 shows an example of a planar configuration of an imaging device according to an embodiment. The pixel section 100 of the imaging device 1 has, for example, a region 101 on which pixels P are provided and a region 102 located around region 101. Region 101 is a pixel region in which a plurality of pixels P are arranged in two dimensions, and can also be called an effective pixel region.

[0030] As shown in Figure 2, the direction of incidence of light from the subject being measured is defined as the Z-axis direction, the left-right direction perpendicular to the Z-axis direction is defined as the X-axis direction, and the up-down direction perpendicular to both the Z-axis and X-axis directions is defined as the Y-axis direction. In subsequent figures, directions may also be indicated based on the direction of the arrows in Figure 2.

[0031] In region 101, for example, multiple pixels P are provided arranged horizontally (X-axis direction) and vertically (Y-axis direction). In region 102, multiple cells PX are provided. Cell PX has, for example, the same circuit elements (transistors, capacitors, etc.) as pixels P. Cell PX can be used, for example, for fault detection, correction of pixel signals, etc.

[0032] Region 102 has, for example, a cell PX provided for each pixel row of the pixel section 100. The cell PX is provided for the signal line VSL and is electrically connected to the signal line VSL. The cell PX can also be called a dummy pixel or dummy pattern. Region 102 can also be called a dummy pattern region.

[0033] A light-shielding pixel may be provided in the region 102 of the pixel section 100. The light-shielding pixel has, for example, a light-shielding member (light-shielding film) and is in a state of being light-shielded by the light-shielding member. In the imaging device 1, for example, the light-shielding member is provided so as to cover all or part of the region 102. At least a part of the region 102 may be configured as an OPB (Optical Black) region or a light-shielding pixel region.

[0034] [Pixel Configuration] Figure 3 shows an example of the circuit configuration of a pixel in an imaging device according to an embodiment. A pixel P includes, for example, a photoelectric conversion unit 11, a transistor TG, a floating diffusion FD, and a pixel circuit 15. The photoelectric conversion unit 11 (photoelectric conversion element) is configured to receive light and generate a signal. The pixel circuit 15 is configured to output a signal based on the photoelectrically converted charge.

[0035] The photoelectric conversion unit 11 is configured to generate electric charge through photoelectric conversion. In the example shown in Figure 3, the photoelectric conversion unit 11 is a photodiode (PD) that converts incident light into electric charge. The photoelectric conversion unit 11 performs photoelectric conversion to generate an electric charge corresponding to the amount of light received. The photoelectric conversion unit 11 is a photoelectric conversion element and can also be called a light receiving element.

[0036] The transistor TG is configured to transfer the charge photoelectrically converted in the photoelectric conversion unit 11 to the floating diffusion FD. The transistor TG is a transfer transistor. The transistor TG is controlled by the signal STG to electrically connect or disconnect the photoelectric conversion unit 11 and the floating diffusion FD. The transistor TG (i.e., the transfer transistor) can transfer the charge converted and stored in the photoelectric conversion unit 11 to the floating diffusion FD.

[0037] The floating diffusion FD is configured to store transferred charge. The floating diffusion FD can store the charge photoelectrically converted by the photoelectric conversion unit 11. The floating diffusion FD stores the transferred charge and converts it into a voltage corresponding to the capacitance of the floating diffusion FD. The floating diffusion FD can also be described as a charge-holding unit.

[0038] The pixel circuit 15 is configured to read out a pixel signal based on the charge photoelectrically converted by the photoelectric conversion unit 11. The pixel circuit 15 includes, as an example, a transistor AMP, a transistor SEL, and a transistor RST. The pixel circuit 15 may also include a floating diffusion FD. The pixel circuit 15 may also include a transistor TG. The pixel circuit 15 is also referred to as a readout circuit or pixel readout circuit, etc.

[0039] The transistor AMP is configured to generate and output a signal based on the charge stored in the floating diffusion FD. The transistor AMP is an amplifying transistor. The transistor AMP (i.e., the amplifying transistor) can generate and output a signal based on the charge converted by the photoelectric conversion unit 11.

[0040] The gate of the transistor AMP is electrically connected to the floating diffusion diode (FD), and the voltage converted by the floating diffusion diode is input to it. The drain of the transistor AMP is connected to a power line that supplies, for example, the power supply voltage (the power supply voltage VDD in the example shown in Figure 3).

[0041] The source of the transistor AMP is connected to the signal line VSL, for example, via the transistor SEL. The transistor AMP is configured to generate a signal based on the charge stored in the floating diffusion FD, i.e., a signal based on the voltage of the floating diffusion FD, and output it to the signal line VSL.

[0042] The transistor SEL is configured to control the output of the pixel signal. The transistor SEL is a selection transistor. The transistor SEL is electrically connected in series with the transistor AMP. The transistor SEL is controlled by the signal SSEL and is configured to output the signal from the transistor AMP to the signal line VSL. The transistor SEL (i.e., the selection transistor) can control the timing of the pixel signal output.

[0043] The transistor SEL is configured to be capable of outputting a signal based on the charge converted by the photoelectric conversion unit 11. The transistor SEL can output the pixel signal of the pixel P to the signal line VSL. Note that the transistor SEL may be electrically connected in series between a power supply line supplied with a power supply voltage (the power supply voltage VDD in FIG. 3) and the transistor AMP. The transistor SEL may be omitted if necessary.

[0044] The transistor RST is configured to be capable of resetting the voltage of the floating diffusion FD. The transistor RST is a reset transistor. The transistor RST (i.e., the reset transistor) is, for example, electrically connected to a power supply line to which a power supply voltage (the power supply voltage VDD in the example shown in FIG. 3) is supplied, and is configured to be capable of resetting the charge of the pixel P.

[0045] The transistor RST is controlled by a signal SRST, can reset the charge accumulated in the floating diffusion FD, and can reset the voltage of the floating diffusion FD. The transistor RST electrically connects the power supply line and the floating diffusion FD, and discharges the charge accumulated in the floating diffusion FD. Note that the transistor RST can reset the charge accumulated in the photoelectric conversion unit 11 via the transistor TG.

[0046] It should be noted that the pixel circuit 15 may be configured to be capable of changing the conversion gain (i.e., conversion efficiency) when converting charge to voltage. For example, the pixel circuit 15 includes a transistor (switching transistor) used for setting the conversion gain. As an example, the switching transistor is electrically connected between the floating diffusion FD and the transistor RST.

[0047] In the pixel circuit 15, when the switching transistor is turned on, the capacitance added to the floating diffusion FD of the pixel P increases, and the conversion gain for converting electric charge into voltage is switched. The switching transistor can switch the capacitance connected to the gate of the transistor AMP, thereby changing the conversion gain (conversion efficiency). The switching transistor may be electrically connected in series to the transistor RST, or may be electrically connected in parallel to the transistor RST.

[0048] The aforementioned transistor TG (transfer transistor), transistor AMP (amplification transistor), transistor SEL (selection transistor), transistor RST (reset transistor), and switching transistor are each, for example, a MOS transistor (MOSFET) having gate, source, and drain terminals.

[0049] In the example shown in Figure 3, the transistor TG, the transistor AMP, the transistor SEL, and the transistor RST are each formed of an NMOS transistor. Note that the transistors of the pixel P may alternatively be formed of PMOS transistors as needed.

[0050] The pixel control circuit 111 (see FIG. 1) of the imaging device 1 supplies control signals to the gates of the transistor TG, transistor SEL, transistor RST, switching transistor and other components of each pixel P via the above-described control line Lc, to set the transistors to an on state (conducting state) or an off state (non-conducting state).

[0051] The plurality of control lines Lc for each pixel row of the imaging device 1 include, by way of example, a wiring for transmitting a signal STG that controls the transistor TG, a wiring for transmitting a signal SSEL that controls the transistor SEL, a wiring for transmitting a signal SRST that controls the transistor RST, a wiring for transmitting a signal that controls the switching transistor, and the like.

[0052] Transistors TG, SEL, RST, and switching transistors are controlled on and off by the pixel control circuit 111. The pixel control circuit 111 controls the pixel circuit 15 of each pixel P, causing each pixel P to output a pixel signal to the signal line VSL. The pixel control circuit 111 can also control the reading of the pixel signal from each pixel P to the signal line VSL.

[0053] Although the above describes an example of the configuration of pixel P, this is merely an example, and the configuration of pixel P is not limited to the example described above. For example, pixel P may have a region (i.e., a MEM region) that temporarily holds charge before charge transfer from the photoelectric conversion unit 11 to the floating diffusion FD. The MEM region may be composed of capacitive elements such as MOS capacitors and MIM (Metal-Insulator-Metal) capacitors.

[0054] The imaging device 1 may have a configuration in which multiple pixels P share one pixel circuit 15 (i.e., a pixel readout circuit). The pixel circuit 15 is provided for multiple pixels P, for example. In the imaging device 1, a pixel circuit 15 may be arranged for each of the multiple pixels P, and one pixel circuit 15 may be shared by multiple pixels P. As an example, a 2x2 pixel array, composed of four adjacent pixels P, may share one pixel circuit 15.

[0055] [Configuration of the Imaging Device] Figure 4 is a diagram illustrating an example of the configuration of an imaging device according to an embodiment. The imaging device 1 has a readout circuit 112 and a processing circuit 113, as shown in the example in Figure 4. The readout circuit 112 has, for example, a load circuit 20, an amplification circuit 30, a holding circuit 40, and an AD conversion circuit 60. The imaging device 1 also has an interface circuit 120.

[0056] The load circuit 20, amplification circuit 30, holding circuit 40, and AD conversion circuit 60 are provided for each of the multiple signal lines VSL (i.e., vertical signal lines). For example, the load circuit 20, amplification circuit 30, holding circuit 40, and AD conversion circuit 60 are provided for each pixel row of the pixel unit 100 (pixel array). The readout circuit 112 can also be called a column readout circuit.

[0057] The load circuit 20 is composed of, for example, a current source 25. The current source 25 is electrically connected to the signal line VSL and configured to supply current. The current source 25 is electrically connected to the transistor SEL and transistor AMP of each pixel P via the signal line VSL. The current source 25, together with the transistor AMP of the pixel P, constitutes a source follower circuit.

[0058] The amplification circuit 30 is configured to amplify the input signal. The amplification circuit 30 is connected to the signal line VSL and is configured to amplify the signal input via the signal line VSL and output it. The amplification circuit 30 is connected between the signal line VSL and the holding circuit 40 and outputs, for example, an amplified signal of the pixel signal from pixel P to the holding circuit 40.

[0059] The holding circuit 40 includes, for example, a plurality of capacitive elements C (in the example shown in Figure 4, capacitive elements Cp and Cd) and a plurality of switches, and is configured to hold the input signal. The holding circuit 40 is configured as a sample-and-hold circuit. The capacitive elements C have a predetermined capacitance value and are configured to hold a voltage. The capacitive elements C can hold the signal voltage of the signal input via the signal line VSL.

[0060] In the example shown in Figure 4, the capacitive element Cp holds the voltage of the signal from pixel P, which is input via the signal line VSL and the amplification circuit 30. The capacitive element Cd can also hold the voltage of the signal from pixel P, which is input via the signal line VSL and the amplification circuit 30. The capacitive elements Cp and Cd are each composed of MOS capacitance, MIM (Metal-Insulator-Metal) capacitance, etc. The holding circuit 40 may have three or more capacitive elements C.

[0061] The AD conversion circuit 60 is configured to perform AD conversion and converts the input analog signal into a digital signal. The AD conversion circuit 60 (AD conversion unit) performs AD conversion processing on, for example, the pixel signal, which is an analog signal input from the holding circuit 40. The AD conversion circuit 60 outputs the pixel signal that has been AD converted after being held by the holding circuit 40.

[0062] The AD conversion circuit 60 includes, for example, a comparator circuit 50 and a counter 55. The AD conversion circuit 60 is an ADC (Analog to Digital Converter). The AD conversion circuit 60 is configured to convert an input signal into a digital signal of a predetermined number of bits. As an example, the AD conversion circuit 60 is a single-slope ADC.

[0063] The comparison circuit 50 of the AD conversion circuit 60 is configured, for example, by a comparator circuit, and is configured to compare the input signal to be converted with a reference signal (reference signal). The comparison circuit 50 (comparison unit) compares, for example, the pixel signal, which is an analog signal to be converted, with the reference signal to be compared.

[0064] The comparison circuit 50, as an example, compares the pixel signal of the pixel P held by the capacitive element C of the holding circuit 40 with a reference signal whose voltage (potential) changes (for example, a ramp signal whose signal level changes over time), and outputs an output signal which is the result of the comparison. The output signal of the comparison circuit 50 is a signal that shows the magnitude relationship between the pixel signal and the reference signal.

[0065] The counter 55 of the AD conversion circuit 60 is configured to count (count) in response to the input signal. For example, the counter 55 (counter circuit) measures the time until the comparison result in the comparison circuit 50 is inverted, based on the input clock signal and the output signal from the comparison circuit 50, and generates a signal indicating the count value.

[0066] The counter 55 holds a digital signal indicating a count value corresponding to the period from the start of comparison by the comparison circuit 50 until the comparison result is reversed (changed), as the pixel signal after AD conversion. The pixel signals output sequentially from each pixel P are held by the holding circuit 40 and converted into digital signals by AD conversion in the AD conversion circuit 60.

[0067] The AD conversion circuit 60 converts the input signal into a digital signal and outputs the converted digital signal. The readout circuit 112 can, for example, perform AD conversion on the pixel signal from the pixel P and output the pixel signal, which is a digital signal based on the charge converted by the photoelectric conversion unit 11 of the pixel P, to the processing circuit 113.

[0068] As shown in Figure 4, the processing circuit 113 has a signal processing unit 80. The signal processing unit 80 is configured to acquire the signal of each pixel P and perform signal processing. The signal processing unit 80 is a signal processing circuit and is composed of, for example, circuits that perform various signal processing on the input pixel signals. The signal processing unit 80 is composed of logic circuits and memory, etc.

[0069] The signal processing unit 80 is configured to perform various signal processing operations, such as noise reduction, interpolation, and gradation correction. For example, the signal processing unit 80 (signal processing circuit) performs signal processing on the pixel signals input from the readout circuit 112 and outputs the processed pixel signals.

[0070] The signal processing unit 80 is configured to generate image data (image signals) based on the pixel signals of each pixel P. The signal processing unit 80 is configured to generate image data that includes the pixel signals (i.e., pixel values) of each pixel P. For example, the signal processing unit 80 can generate image data showing an image of a subject and output it to the outside via the interface circuit 120.

[0071] The interface circuit 120 is configured to transmit input signals. The interface circuit 120 (I / F circuit) is configured, for example, as an interface circuit that corresponds to a predetermined communication standard. The interface circuit 120 can output image data generated by the signal processing unit 80 to an external device (for example, an image processing device).

[0072] The imaging device 1 is configured to supply an inspection signal having a predetermined voltage (potential) to the capacitive element C of the holding circuit 40. The imaging device 1 is configured to supply an inspection signal Sdet having a voltage Vdmy to the capacitive element C (e.g., capacitive element Cp or capacitive element Cd) of the holding circuit 40 via the signal line VSL and the amplification circuit 30, for example, by using cell PX.

[0073] Cell PX is configured as a supply circuit that is electrically connected to the signal line VSL and capable of supplying a predetermined voltage. In the example shown in Figure 4, cell PX has transistors AMP and SEL, similar to those of pixel P. As an example, a constant voltage Va is applied to the gate of transistor AMP in cell PX.

[0074] Cell PX is controlled by a signal input to the gate of transistor SEL and can output a voltage signal corresponding to the voltage Va to the signal line VSL. Cell PX can also be called a voltage supply circuit or a voltage output circuit. Cell PX is controlled by a signal input from a control circuit that controls Cell PX (for example, a pixel control circuit 111).

[0075] For example, the control circuit 114 controls the value (level) of the voltage Va supplied to the gate of the transistor AMP of cell PX, the on / off timing of the transistor SEL of cell PX, etc., by controlling the pixel control circuit 111. The imaging device 1 may be configured to output a signal Sdet having voltage Vdmy to the capacitive element C via a separate supply circuit (e.g., an amplifier circuit) from cell PX.

[0076] The imaging device 1 is configured to hold the inspection signal Sdet using a capacitive element C for a predetermined time and to perform fault determination based on the voltage of the signal Sdet after the predetermined time has elapsed. The control circuit 114 of the imaging device 1 is configured to control the readout circuit 112 and to hold the signal Sdet in the capacitive element C for a relatively long hold time Tdet.

[0077] The hold time Tdet is set to be longer than the hold time Tsig used when reading the pixel signal from the pixel P to the holding circuit 40 and performing AD conversion. During the test hold time Tdet, the signal level of the signal Sdet held in the capacitive element C, i.e., the voltage of the signal Sdet, changes depending on whether or not there is a fault in the capacitive element C.

[0078] The voltage of the signal Sdet held by the capacitive element C decreases due to deterioration or failure (e.g., dielectric breakdown) of the capacitive element C. Due to leakage current caused by TDDB (Time-Dependent Dielectric Breakdown), the voltage of the signal Sdet held by the capacitive element C tends to decrease over time. The amount of voltage drop of the signal Sdet changes (increases or decreases) depending on the magnitude of the leakage current.

[0079] The control circuit 114, for example, holds the signal Sdet for a hold time Tdet using a capacitive element C, and performs AD conversion of the signal Sdet held for the hold time Tdet using the AD conversion circuit 60. The readout circuit 112 generates a digital signal SdetA, corresponding to the signal Sdet after the hold time Tdet, using the AD conversion circuit 60, and outputs it to the processing circuit 113.

[0080] As shown in Figure 4, the processing circuit 113 has a determination circuit 81. The determination circuit 81 is configured to perform fault determination based on the signal SdetA output from the readout circuit 112. The determination circuit 81 (determination unit) uses the signal SdetA, for example, to determine whether the voltage of the signal Sdet after the hold time Tdet has elapsed is within an acceptable range, and performs fault determination of the capacitive element C.

[0081] The readout circuit 112 outputs a signal SdetA as a signal indicating the voltage value that has decreased in accordance with the leakage current in the capacitive element C during the hold time Tdet. The readout circuit 112 can generate and output a signal SdetA for each column using, for example, the AD conversion circuit 60 for each column. The determination circuit 81 can use the signal SdetA obtained for each column to estimate whether or not there is a fault in the capacitive element C for each column.

[0082] Furthermore, the processing circuit 113 may have a calculation circuit 82. The calculation circuit 82 is configured to calculate the deviation of signal SdetA. The calculation circuit 82 is configured to calculate the deviation of the value of signal SdetA using signal SdetA generated for each row of pixel section 100. The calculation circuit 82 calculates the deviation between the value of one signal SdetA and the average value of multiple signals SdetA for each signal SdetA.

[0083] The processing circuit 113 acquires the signal SdetA for each column (i.e., each holding circuit 40) from the read circuit 112, and the calculation circuit 82 calculates the deviation between, for example, the value of each signal SdetA in multiple columns and the average value of the signals SdetA in multiple columns. The determination circuit 81 determines whether or not there is a failure (abnormality) in the capacitive element C of each column based on the deviation calculated by the calculation circuit 82.

[0084] The calculation circuit 82 may calculate the deviation between the average value of signal SdeA for all columns and one signal SdeA for each column, or it may calculate the deviation between the average value of signal SdeA for some of the columns and one signal SdeA for each column. The determination circuit 81 may also include the calculation circuit 82.

[0085] The imaging device 1 may, for example, perform the process of acquiring an inspection signal SdetA and the process of determining the deviation of signal SdetA multiple times for each column to determine whether or not there is a fault in the capacitive element C for each column. As an example, if the processing circuit 113 determines that the deviation of signal SdetA is an abnormal value in any of the multiple attempts, it may determine that the capacitive element C in the column where the deviation is an abnormal value is "faulty".

[0086] Figure 5 is a diagram illustrating an example of the configuration of a readout circuit of an imaging device according to an embodiment. The readout circuit 112 includes a load circuit 20, an amplification circuit 30, a holding circuit 40, and an AD conversion circuit 60. The holding circuit 40 and the AD conversion circuit 60, etc., are provided for each signal line VSL. In Figure 5, only the AD conversion circuit 60, etc., provided for one row are shown. The readout circuit 112 may have the same circuit configuration as shown in Figure 5 for other rows as well.

[0087] The amplification circuit 30 is configured using an amplifier circuit capable of amplifying a signal, for example, having an input section 31a, an input section 31b, and an output section 32. The input sections 31a and 31b are input terminals of the amplification circuit 30, respectively. The output section 32 is the output terminal of the amplification circuit 30. The input section 31a of the amplification circuit 30 is electrically connected to the signal line VSL. In addition, a reference voltage VREF is input to the input section 31b from an external circuit.

[0088] The amplification circuit 30 is configured to output an output signal based on a signal input via the signal line VSL and a reference voltage. In the example shown in Figure 5, the amplification circuit 30 outputs an output signal from the output unit 32 that has a signal voltage corresponding to the voltage of the output signal of the pixel P (or cell PX) and the reference voltage VREF.

[0089] The holding circuit 40 (i.e., sample-and-hold circuit) includes switches SW_Wp, SW_Wd, SW_Rp, SW_Rd, capacitive element Cp, and capacitive element Cd. The readout circuit 112 also includes switches SW1 and SW2, as shown in Figure 5.

[0090] Switches SW_Wp, SW_Wd, SW_Rp, SW_Rd, SW1, and SW2 are each constructed using transistors, for example. Each of switches SW_Wp, SW_Wd, SW_Rp, SW_Rd, SW1, and SW2 is controlled on or off by signals input from the pixel control circuit 111, for example.

[0091] Switch SW_Wp is connected between the amplification circuit 30 and the capacitive element Cp. Switch SW_Wp is electrically connected, for example, between node N1, which connects the amplification circuit 30 and the holding circuit 40, and the capacitive element Cp. Switch SW_Wp is controlled on / off by signal SH_Wp, electrically connecting or disconnecting node N1 and the capacitive element Cp.

[0092] Switch SW_Wd is connected between the amplification circuit 30 and the capacitive element Cd. Switch SW_Wd is electrically connected, for example, between node N1 and the capacitive element Cd. Switch SW_Wd is controlled on / off by signal SH_Wd. Switch SW_Wd electrically connects or disconnects node N1 and the capacitive element Cd.

[0093] Switch SW_Rp is connected between the capacitive element Cp and the AD conversion circuit 60. Switch SW_Rp is electrically connected between the capacitive element Cp and node N2, which connects the holding circuit 40 and the AD conversion circuit 60. Switch SW_Rp is controlled on / off by signal SH_Rp, electrically connecting or disconnecting the capacitive element Cp and node N2.

[0094] Switch SW_Rd is connected between the capacitive element Cd and the AD conversion circuit 60. Switch SW_Rd is electrically connected between the capacitive element Cd and node N2. Switch SW_Rd is controlled on / off by signal SH_Rd to electrically connect or disconnect the capacitive element Cd and node N2.

[0095] One electrode (terminal) of the capacitive element Cp is electrically connected to switches SW_Wp and SW_Rp. The other electrode of the capacitive element Cp is electrically connected to the reference potential line. Similarly, one electrode of the capacitive element Cd is electrically connected to switches SW_Wd and SW_Rd. The other electrode of the capacitive element Cd is electrically connected to the reference potential line. In the example shown in Figure 5, the reference potential line is the wiring to which a voltage VSS (e.g., 0V) is applied, i.e., the ground line (earth wire).

[0096] Switch SW1 is electrically connected between the signal line VSL, which is connected to the input section 31a of the amplification circuit 30, and node N1. Switch SW1 is controlled on / off by the signal RST_SHIN. Switch SW2 is electrically connected between the input section 31b, to which the reference voltage VREF is supplied, and node N2. Switch SW2 is controlled on / off by the signal RST_SHOUT.

[0097] The AD conversion circuit 60 includes a comparator circuit 50 and a counter 55. The comparator circuit 50 has, for example, an input section 51a, an input section 51b, and an output section 52, and is configured using a differential amplifier capable of amplifying signals. The input sections 51a and 51b are the input terminals of the comparator circuit 50. The output section 52 is the output terminal of the comparator circuit 50.

[0098] The input section 51a of the comparison circuit 50 is electrically connected to the holding circuit 40. The holding circuit 40 inputs, for example, a signal voltage held by a capacitive element Cp or a signal voltage held by a capacitive element Cd to the input section 51a. The input section 51b receives a ramp signal RAMP from an external circuit (for example, a signal generation circuit commonly connected to multiple AD conversion circuits 60).

[0099] The comparison circuit 50 compares, for example, the signal input from the holding circuit 40 with the ramp signal RAMP, whose voltage changes, and outputs an output signal from the output unit 52 indicating the comparison result. The signal output from the comparison circuit 50 is a signal that indicates the magnitude relationship between the input signal from the holding circuit 40 and the ramp signal RAMP.

[0100] The counter 55 is configured to count in accordance with the signal input from the output section 52 of the comparison circuit 50. The signals transmitted from each pixel P (or cell PX) and held by the capacitive element Cp or capacitive element Cd of the holding circuit 40 are sequentially converted into digital signals by the comparison circuit 50 and the counter 55.

[0101] Figure 6 is a timing chart showing an example of operation of the imaging device according to the embodiment. Figure 6 shows an example of reading a signal from pixel P and performing AD conversion. In Figure 6, the signal output to the signal line VSL, signal RST_SHIN, signal RST_SHOUT, signal SH_Wp, signal SH_Rp, the signal held in the capacitive element Cp, signal SH_Wd, signal SH_Rd, and the signal held in the capacitive element Cd are shown on the same time axis.

[0102] During the period from time t1 to time t2, the signal RST_SHIN becomes high level. When the signal RST_SHIN becomes high level, the switch SW1 of the readout circuit 112 is turned ON. As a result, the input section 31a connected to the signal line VSL and node N1 are electrically connected, and the voltage of node N1 is reset.

[0103] On the signal line VSL, a signal Sp is output from the pixel P selected by the pixel control circuit 111, having a voltage Vp corresponding to the voltage of the floating diffusion FD after reset. Signal Sp is a signal read from the pixel P during the P-phase (Pre-charge phase) period after reset, and is a signal indicating the reset level (reference level).

[0104] During the period from time t2 to time t3, the signal SH_Wp ​​becomes high level, causing the switch SW_Wp to turn on, and the amplification circuit 30 and the capacitive element Cp are electrically connected. The P-phase signal Sp is input to and held in the capacitive element Cp by the amplification circuit 30 as a signal Sig_Cp having a voltage corresponding to the voltage Vp (voltage Vp_Cp).

[0105] During the period from time t4 to time t5, the signal RST_SHOUT becomes high level. When the signal RST_SHOUT becomes high level, the switch SW2 of the readout circuit 112 is turned ON. As a result, the input section 31b to which the reference voltage VREF is supplied is electrically connected to node N2, and the voltage of node N2 is reset.

[0106] During the period from time t5 to time t6, the signal SH_Rp becomes high level. This turns on the switch SW_Rp, electrically connecting the capacitive element Cp and the A / D conversion circuit 60. The signal Sig_Cp, held in the capacitive element Cp for a hold time Tsig_Cp, is read out to the A / D conversion circuit 60. The A / D conversion circuit 60 performs A / D conversion processing on the signal Sig_Cp.

[0107] The hold time Tsig_Cp is, for example, the time from the falling edge timing of signal SH_Wp ​​to the rising edge timing of signal SH_Rp, as shown in the example in Figure 6. The hold time Tsig_Cp corresponds to the period from when signal Ssig_Cp is held in the capacitive element Cp until the AD conversion of signal Ssig_Cp begins.

[0108] A signal Sd having a voltage Vd corresponding to the voltage of the floating diffusion FD after charge transfer is output from pixel P to the signal line VSL. Signal Sd is a signal read out from pixel P during the D phase (Data phase) period after charge has been transferred from the photoelectric conversion unit 11 to the floating diffusion FD.

[0109] During the period from time t5 to time t6, the signal SH_Wd becomes high level. When the signal SH_Wd becomes high level, the switch SW_Wd turns on, and the amplification circuit 30 and the capacitive element Cd are electrically connected. The D-phase signal Sd is input to the capacitive element Cd and held by the amplification circuit 30 as a signal Ssig_Cd having a voltage (voltage Vd_Cd) corresponding to the voltage Vd.

[0110] During the period from time t7 to time t8, the signal SH_Rd becomes high level, which turns on the switch SW_Rd, electrically connecting the capacitive element Cd and the A / D conversion circuit 60. The signal Ssig_Cd, held in the capacitive element Cd for a hold time Tsig_Cd, is read out to the A / D conversion circuit 60. The A / D conversion circuit 60 performs A / D conversion processing on the signal Ssig_Cd.

[0111] The hold time Tsig_Cd is, for example, the time from the falling edge timing of signal SH_Wd to the rising edge timing of signal SH_Rd, as shown in the example in Figure 6. The hold time Tsig_Cd corresponds to the period from when signal Ssig_Cd is held by the capacitive element Cd until the AD conversion of signal Ssig_Cd begins. The length of the hold time Tsig_Cd may be equal to the length of the hold time Tsig_Cp.

[0112] The AD conversion circuit 60 sets the aforementioned signal Ssig_Cp as the initial value for counting (down counting or up counting) and performs AD conversion processing on the signal Ssig_Cd. The AD conversion circuit 60 generates a digital signal indicating the difference between the signal Ssig_Cd and the signal Ssig_Cp and outputs it to the processing circuit 113 as the pixel signal SsigA.

[0113] The processing circuit 113 acquires the pixel signal SsigA of each pixel P from the readout circuit 112. The processing circuit 113 performs signal processing on the pixel signal SsigA of each pixel P to generate image data. The processing circuit 113 generates image data including the pixel signal SsigA of each pixel P and can output (transmit) it to the outside via the interface circuit 120.

[0114] Figure 7 is a timing chart showing an example of operation of the imaging device according to the embodiment. Figure 7 shows an example where the inspection signal is held in the capacitive element C and then AD converted. An example of operation of the imaging device 1 during inspection will be explained with reference to the timing chart in Figure 7, as well as Figures 4 and 5, etc.

[0115] Figure 7 shows an example where the signal voltage held by the capacitive element Cp decreases over time due to leakage current in the capacitive element Cp, etc. The signal voltage of the capacitive element Cp shown by the dotted line L1 represents the case where the leakage current in the capacitive element Cp is small and the voltage drop of the capacitive element Cp is small.

[0116] During the period from time t11 to time t12 as shown in Figure 7, the signal RST_SHIN becomes high level. When the signal RST_SHIN becomes high level, switch SW1 of the readout circuit 112 shown in Figure 5 is turned ON. In this case, the input section 31a connected to the signal line VSL and node N1 are electrically connected, and the voltage of node N1 is reset.

[0117] A test signal Sdet is output to the signal line VSL. For example, the pixel control circuit 111 controls the cell PX (see Figure 4) to output a signal Sdet with voltage Vdmy to the signal line VSL and the amplification circuit 30. A voltage Vdmy that is a constant voltage is supplied to the signal line VSL, for example, as shown in the example in Figure 7.

[0118] During the period from time t12 to time t13, the signal SH_Wp ​​becomes high level. As a result, the switch SW_Wp is turned on, and the amplification circuit 30 and the capacitive element Cp are electrically connected. The signal Sdet is input to the capacitive element Cp and held by the amplification circuit 30 as the signal Sdet_Cp, which has a voltage corresponding to the voltage Vdmy (voltage Vdmy_Cp).

[0119] Furthermore, during the period from time t12 to time t13, the signal SH_Wd also becomes high level. Switch SW_Wd is turned ON, and the amplification circuit 30 and the capacitive element Cd are electrically connected. The signal Sdet is input to the capacitive element Cd and held by the amplification circuit 30 as a signal Sdet_Cd having a voltage corresponding to the voltage Vdmy (voltage Vdmy_Cd).

[0120] Between time t14 and time t15, the signal RST_SHOUT becomes high. When the signal RST_SHOUT becomes high, switch SW2 is turned ON. As a result, the input section 31b, to which the reference voltage VREF is supplied, and node N2 are electrically connected, and the voltage at node N2 is reset.

[0121] During the period from time t15 to time t16, the signal SH_Rp becomes high level. As a result, the switch SW_Rp is turned ON, and the capacitive element Cp and the AD conversion circuit 60 are electrically connected. The signal Sdet_Cp, which is held in the capacitive element Cp for a hold time Tdet_Cp, is read out to the AD conversion circuit 60. The AD conversion circuit 60 performs AD conversion processing on the signal Sdet_Cp.

[0122] The hold time Tdet_Cp is, for example, the time from the falling edge timing of signal SH_Wp ​​to the rising edge timing of signal SH_Rp, as shown in the example in Figure 7. The hold time Tdet_Cp corresponds to the period from when the signal Sdet_Cp, which has voltage Vdmy_Cp, is held in the capacitive element Cp until the AD conversion of signal Sdet_Cp is started.

[0123] During the period from time t17 to time t18, the signal SH_Rd becomes high level, causing the switch SW_Rd to turn on, and the capacitive element Cd and the A / D conversion circuit 60 are electrically connected. The signal Sdet_Cd, which is held in the capacitive element Cd for a hold time Tdet_Cd, is read out to the A / D conversion circuit 60. The A / D conversion circuit 60 performs A / D conversion processing on the signal Sdet_Cd.

[0124] The hold time Tdet_Cd is, for example, the time from the falling edge timing of signal SH_Wd to the rising edge timing of signal SH_Rd. The hold time Tdet_Cd corresponds to the period from when the signal Sdet_Cd, which has voltage Vdmy_Cd, is held in the capacitive element Cd until the AD conversion of signal Sdet_Cd begins.

[0125] The test hold times Tdet_Cp and Tdet_Cd are set to be longer than the hold times when reading signals from pixel P and performing AD conversion (i.e., during normal operation) (for example, the hold times Tsig_Cp or Tsig_Cd mentioned above).

[0126] In the imaging device 1, for example, as shown in the example in Figure 7, by setting the inspection hold time Tdet_Cd to a long time, it becomes possible to acquire a signal Sdet_Cp corresponding to the voltage drop due to the leakage current in the capacitive element Cp, and to appropriately determine whether or not there is a fault.

[0127] The hold times Tdet_Cp and Tdet_Cd may each be several times longer than the normal hold time during operation. For example, the hold time Tdet_Cp may be at least 10 times longer than the hold time Tsig_Cp. Also, the hold time Tdet_Cd may be at least 10 times longer than the hold time Tsig_Cd.

[0128] The hold times Tdet_Cp and Tdet_Cd may each be set to be 8 times or more, or 12 times or more, the length of the hold time Tsig_Cp (or Tsig_Cd). The length of the hold time Tdet_Cd may also be equal to the length of the hold time Tdet_Cp.

[0129] The AD conversion circuit 60 sets the aforementioned signal Sdet_Cp as the initial value for counting (down counting or up counting) and performs AD conversion processing on the signal Sdet_Cd. The AD conversion circuit 60 generates a digital signal that represents the difference between the signal Sdet_Cd and the signal Sdet_Cp and outputs it to the processing circuit 113 as the signal SdetA.

[0130] The calculation circuit 82 of the processing circuit 113 obtains, for example, the signal SdetA for each column from the readout circuit 112. The calculation circuit 82 is configured to calculate the deviation of the value of signal SdetA, i.e., (signal Sdet_Cd - signal Sdet_Cp). As shown in the example in Figure 8, the calculation circuit 82 calculates the deviation between the average value of signal SdetA for multiple columns and the value of each signal SdetA for multiple columns.

[0131] The determination circuit 81 uses the column-specific deviations calculated by the calculation circuit 82 to determine whether each deviation is within an acceptable range. For example, the determination circuit 81 checks whether each deviation is greater than the threshold Th_H and whether each deviation is less than the threshold Th_L to determine whether there is a fault in the capacitive element of each column.

[0132] The judgment circuit 81 determines, for example, that a capacitive element in a column whose deviation is an abnormal value greater than the threshold Th_H ("+3" in Figure 8) is "faulty". The judgment circuit 81 determines that a capacitive element in a column whose deviation is an abnormal value less than the threshold Th_L ("-3" in Figure 8) is "faulty". The judgment circuit 81 also determines that a capacitive element in a column whose deviation is within the range of threshold Th_L or greater and threshold Th_H or less is "normal".

[0133] As an example, the determination circuit 81 determines that the capacitive element Cd is abnormal (failed) if the deviation of the value of signal SdetA (signal Sdet_Cd - signal Sdet_Cp) is greater than the threshold Th_H, that is, if the polarity of the deviation is positive. The determination circuit 81 may also determine that the capacitive element Cp is abnormal if the deviation of the value of signal SdetA (signal Sdet_Cd - signal Sdet_Cp) is less than the threshold Th_L, that is, if the polarity of the deviation is negative.

[0134] Figure 9 is a flowchart showing an example of the operation of an imaging device according to an embodiment. An example of the fault detection process in the imaging device 1 will be explained with reference to the flowchart in Figure 9.

[0135] In step S10, the control circuit 114 controls the pixel control circuit 111 and the readout circuit 112, and provides a test signal Sdet having a predetermined voltage to the capacitive elements Cd and Cp of the holding circuit 40, causing the same voltage to be sampled by the capacitive elements Cd and Cp.

[0136] The holding circuit 40 holds the signal Sdet, which is input to both the capacitive element Cd and the capacitive element Cp, as the signal Sdet_Cd by the capacitive element Cd, and also holds it as the signal Sdet_Cp by the capacitive element Cp. In step S11, the holding circuit 40 holds the signals Sdet_Cd and Sdet_Cp for a certain period of time.

[0137] In step S12, the readout circuit 112 reads the signal Sdet_Cd from the capacitive element Cd and performs AD conversion, and reads the signal Sdet_Cp from the capacitive element Cp and performs AD conversion. The readout circuit 112 generates a digital signal SdetA, which represents the difference between the signal Sdet_Cd and the signal Sdet_Cp, and outputs it to the processing circuit 113.

[0138] The processing circuit 113 calculates the deviation of the value of signal SdetA (signal Sdet_Cd - signal Sdet_Cp). In step S13, the processing circuit 113 determines whether the deviation of signal SdetA exceeds a threshold. If the determination result in step S13 is positive ("Yes" in step S13), the process proceeds to step S14.

[0139] In step S14, the processing circuit 113 determines whether the polarity of the deviation of signal SdetA is positive or negative. If the determination result in step S14 is positive ("Yes" in step S14), that is, if the deviation is greater than the threshold Th_H, the process proceeds to step S15. In step S15, the processing circuit 113 determines that the capacitive element Cp is "abnormal".

[0140] If the result of the judgment in step S14 is negative ("No" in step S14), that is, if the deviation is smaller than the threshold Th_L, the process proceeds to step S16. In step S16, the processing circuit 113 determines that the capacitive element Cd is "abnormal".

[0141] If the determination result in step S13 is negative ("No" in step S13), the process proceeds to step S17. In step S17, the processing circuit 113 determines that there is "no abnormality". After that, the process shown in the flowchart of Figure 9 is terminated. In this way, the optical detection device (imaging device 1) according to the present disclosure makes it possible to realize an optical detection device that enables suitable fault detection.

[0142] Figure 10 is a diagram illustrating another configuration example of the imaging device according to the embodiment. Figure 11 is a diagram illustrating another configuration example of the readout circuit of the imaging device. In the examples shown in Figures 10 and 11, the readout circuit 112 has a switch SW3. The switch SW3 is configured using, for example, a transistor and is controlled on / off by a signal input from the pixel control circuit 111.

[0143] Switch SW3 is electrically connected, for example, between node N1, which is connected to the output section 32 of the amplification circuit 30, and node N2, which is connected to the input section 51a of the AD conversion circuit 60. Switch SW3 is controlled by a signal input from the pixel control circuit 111 to electrically connect or disconnect nodes N1 and N2.

[0144] The control circuit 114 is configured to enable control of inputting the test signal Sdet to the AD conversion circuit 60 without going through the holding circuit 40, by controlling the switch SW3 of the readout circuit 112. For example, the control circuit 114 controls the AD conversion of the signal Sdet, which is input from the amplification circuit 30 to the AD conversion circuit 60 via the switch SW3, by the AD conversion circuit 60.

[0145] The processing circuit 113 is configured to perform fault determination based on the signal Sdet_Cp (or signal Sdet_Cd) from the capacitive element C of the holding circuit 40 and the signal Sdet from the switch SW3. The processing circuit 113 determines whether the difference between the signal Sdet_Cp (or signal Sdet_Cd) and the signal Sdet is within an acceptable range and performs fault determination of the capacitive element C.

[0146] The AD conversion circuit 60 sets, for example, the signal Sdet_Cp from the capacitive element Cp (or the signal Sdet_Cd from the capacitive element Cd) as the initial value for the count, and performs AD conversion processing on the signal Sdet input from the amplification circuit 30 via the switch SW3. The AD conversion circuit 60 generates a digital signal that represents the difference between the signal Sdet_Cp (or the signal Sdet_Cd) and the signal Sdet, and outputs it to the processing circuit 113 as the signal SdetB.

[0147] The calculation circuit 82 of the processing circuit 113 obtains, for example, the signal SdetB for each column from the readout circuit 112. The calculation circuit 82 is configured to calculate the deviation of the value of the signal SdetB, for example, (signal Sdet - signal Sdet_Cp) or (signal Sdet - signal Sdet_Cd). The calculation circuit 82 calculates the deviation between the average value of the signal SdetB of multiple columns and the value of each signal SdetB of the multiple columns.

[0148] The determination circuit 81 uses the column-specific deviations calculated by the calculation circuit 82 to determine whether each deviation is within an acceptable range. For example, the determination circuit 81 checks whether each deviation is greater than the threshold Th_H' and whether each deviation is less than the threshold Th_L' to determine whether there is a fault in the capacitive element of each column.

[0149] Figure 12 is a flowchart showing another example of operation of the imaging device according to the embodiment. An example of the fault detection process in the imaging device 1 will be explained with reference to the flowchart in Figure 12.

[0150] In step S20, the control circuit 114 controls the pixel control circuit 111 and the readout circuit 112, supplying a test signal Sdet having a predetermined voltage to the holding circuit 40, causing the capacitive element C (capacitive element Cp or capacitive element Cd) to be tested to sample the voltage of the signal Sdet.

[0151] The holding circuit 40, for example, holds the input signal Sdet as the signal Sdet_Cp using the capacitive element Cp. In step S21, the holding circuit 40 holds the signal Sdet_Cp in the capacitive element Cp for a certain period of time.

[0152] In step S22, the readout circuit 112 reads the signal Sdet_Cp from the capacitive element Cp and performs AD conversion, and reads the signal Sdet from the amplification circuit 30 via switch SW3 and performs AD conversion. The readout circuit 112 generates a digital signal SdetB, which represents the difference between the signal Sdet_Cp and the signal Sdet, and outputs it to the processing circuit 113.

[0153] The processing circuit 113 calculates the deviation of the value of signal SdetB (signal Sdet - signal Sdet_Cp). In step S23, the processing circuit 113 determines whether the deviation of signal SdetB exceeds a threshold. If the determination result in step S23 is positive ("Yes" in step S23), the process proceeds to step S24.

[0154] In step S24, the processing circuit 113 determines that the capacitive element Cp is "abnormal". If the result of the determination in step S23 is negative ("No" in step S23), the process proceeds to step S25. In step S25, the processing circuit 113 determines that there is "no abnormality". After that, the process shown in the flowchart of Figure 12 is terminated.

[0155] Figure 13 is a diagram illustrating an example of the processing sequence of an imaging device according to an embodiment. In Figure 13, the V-synchronization signal and the status of the imaging device 1 (Startup, Streaming, VBLANK) are schematically shown on the same time axis. The V-synchronization signal (vertical synchronization signal) is a signal generated, for example, based on the frame rate of imaging, and indicates the time interval of one frame.

[0156] The imaging device 1 may, for example, use a readout circuit 112 and a processing circuit 113 to perform fault detection processing as shown in Figure 9 or Figure 12 during the VBLANK period T3 (vertical blank period). Alternatively, the imaging device 1 may perform fault detection processing during the Startup period T1, in which each circuit block is started and configured.

[0157] The imaging device 1 is configured to perform fault detection processing during at least one of the VBLANK period T3 and the Startup period T1. The imaging device 1 can, for example, perform fault detection processing during the period T3 for each frame, i.e., the period after the Streaming period T2 in which signals are read out from each pixel.

[0158] Figure 14 is a diagram illustrating an example configuration of a photodetection system according to an embodiment. The photodetection system 10 includes an imaging device 1, which is an example of a photodetection device, and an external device 2. The external device 2 may be, for example, a semiconductor chip or an AP (Application Processor). The imaging device 1 communicates with the external device 2 via, for example, an interface circuit 120.

[0159] External device 2, for example, includes a processor and memory (ROM, RAM, etc.) and is configured to perform various signal processing tasks. External device 2 is composed of, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and memory (ROM, RAM, etc.). Note that the light detection system 10 may be configured to include multiple external devices 2.

[0160] The imaging device 1 includes, for example, an interface circuit 120, which consists of an interface circuit 120a and an interface circuit 120b. Interface circuit 120a includes a transmission circuit and is configured to transmit input signals. Interface circuit 120a is composed of an interface circuit that supports, for example, MIPI (Mobile Industry Processor Interface), SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock), etc.

[0161] The interface circuit 120a transmits, for example, image data generated by the processing circuit 113 to the external device 2 at high speed. The image data (image signal) transmitted from the interface circuit 120a is input to the interface circuit and processor of the external device 2 via the transmission line. The external device 2 has, for example, an interface circuit similar to the interface circuit 120 of the imaging device 1, and performs signal transmission and reception.

[0162] The processing circuit 113 is configured to generate information related to the failure determination results described above (referred to as failure information). The failure information includes, for example, information indicating whether or not each capacitive element C (capacitive element Cp, capacitive element Cd, etc.) of the holding circuit 40 is faulty, information indicating the column that has been determined to be faulty, and information indicating the value of the deviation described above.

[0163] The processing circuit 113 is configured to, for example, add fault information (fault data) to image data and output it to the external device 2 via the interface circuit 120a. The processing circuit 113 and the interface circuit 120a can output fault information as embedded data (EBD), as shown in the example in Figure 15.

[0164] The interface circuit 120b is configured to perform serial communication. The interface circuit 120b is configured as a communication circuit that supports, for example, SPI (Serial Peripheral Interface), I2C (Inter Integrated Circuit), etc. The processing circuit 113 may be configured to output fault information to the external device 2 via the interface circuit 120b.

[0165] The interface circuit 120 may have a terminal 122 used for notifying fault information. Terminal 122 may be, for example, a terminal (pad) used for transmitting signals to the outside, and may be provided as a dedicated terminal for notifying fault determination results. The processing circuit 113 may output a signal to the external device 2 via terminal 122 indicating whether or not the capacitive element C is faulty.

[0166] [Function and Effects] The light detection device according to this embodiment includes a first pixel (pixel P) having a first photoelectric conversion element (photoelectric conversion unit 11), a first signal line (signal line VSL) electrically connected to the first pixel, a first holding circuit (holding circuit 40) including a first capacitive element (e.g., capacitive element Cd) and capable of holding a signal input via the first signal line, a readout circuit (readout circuit 112) having a first AD conversion circuit (AD conversion circuit 60), and a control circuit (e.g., control circuit 114) capable of controlling the readout circuit. The control circuit is capable of performing control to hold the pixel signal input to the first capacitive element for a first time by the first capacitive element and to perform AD conversion of the pixel signal by the first AD conversion circuit. The control circuit is capable of performing control to hold a first signal having a first voltage input to the first capacitive element for a second time longer than the first time by the first capacitive element.

[0167] In the optical detection device (imaging device 1) according to this embodiment, the control circuit 114 can perform control to hold the pixel signal input to the capacitive element Cd for a hold time Tsig by the capacitive element Cd, and to perform AD conversion of the pixel signal by the AD conversion circuit 60. The control circuit 114 can perform control to hold the signal Sdet_Cd, which has a voltage Vdmy_Cd input to the capacitive element Cd, for a hold time Tdet that is longer than the hold time Tsig by the capacitive element Cd. Therefore, it is possible to realize an optical detection device that is advantageous for fault detection.

[0168] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0169] <2. Modified Examples> In the embodiments described above, an example of the configuration of the imaging device was explained, but the configuration of the imaging device is not limited to the example described above. Figure 16 is a diagram illustrating an example of the configuration of an imaging device according to a modified example of the present disclosure. The imaging device 1 may be configured to correct the pixel signal based on the fault determination result.

[0170] The processing circuit 113 may have a correction circuit 83, as shown in the example in Figure 16. The correction circuit 83 is configured to correct the pixel signal SsigA based on a test signal SdetA. For example, the correction circuit 83 is configured to estimate the voltage drop amount associated with the leakage current in the capacitive element Cd (or capacitive element Cp) using the signal SdetA, and to correct (adjust) the value of the signal SdetA.

[0171] The correction circuit 83 (correction unit) may use the above-described signal SdetB to grasp the voltage drop amount associated with the leakage current in the capacitive element Cd (or capacitive element Cp) and correct the value of signal SdetA. For example, the correction circuit 83 performs a process to correct the signal value (i.e., pixel value) of signal SdetA for each pixel based on the above-described difference value or deviation.

[0172] The processing circuit 113 may also output information regarding the correction amount of the pixel signal calculated by the correction circuit 83 to an external device via the interface circuit 120. For example, the processing circuit 113 may generate information regarding the correction amount of the signal for each pixel using the correction circuit 83, add it to the image data, and output it to the external device 2.

[0173] <3. Examples of Application> The above-described imaging device 1 can be applied to any type of electronic device equipped with an imaging function, such as camera systems like digital still cameras and video cameras, or mobile phones with imaging capabilities. Figure 17 shows a schematic configuration of the electronic device 1000.

[0174] The electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0175] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0176] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

[0177] The display unit 1004 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records the video or still image data captured by the imaging device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0178] The operation unit 1006 outputs operation signals for various functions possessed by the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0179] <4. Application Examples> (Application Examples to Mobile Devices) The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0180] Figure 18 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0181] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 18, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0182] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0183] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0184] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0185] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0186] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0187] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0188] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0189] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0190] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 18, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0191] Figure 19 shows an example of the installation position of the imaging unit 12031.

[0192] In Figure 19, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0193] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0194] Figure 19 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0195] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0196] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0197] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0198] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0199] The above describes an example of a mobile control system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, for example, the imaging device 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, it becomes possible to perform fault detection appropriately.

[0200] (Examples of application to endoscopic surgical systems) The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be applied to endoscopic surgical systems.

[0201] Figure 20 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0202] Figure 20 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0203] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0204] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0205] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0206] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display the image based on that image signal.

[0207] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0208] The light source device 11203 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0209] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0210] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0211] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0212] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0213] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0214] Figure 21 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 20.

[0215] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0216] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0217] The imaging unit 11402 is composed of image sensors. The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is composed of multiple chips, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is composed of multiple chips, multiple lens units 11401 may also be provided corresponding to each image sensor.

[0218] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0219] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0220] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0221] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0222] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0223] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0224] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0225] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0226] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0227] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0228] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0229] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0230] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0231] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be suitably applied, for example, to the imaging unit 11402 provided on the camera head 11102 of the endoscope 11100. By applying the technology described herein to the imaging unit 11402, it becomes possible to provide a high-definition endoscope 11100.

[0232] Although the present disclosure has been described above with reference to embodiments, modifications, application examples, and application examples, the present technology is not limited to the above embodiments, and various modifications are possible. For example, although the above modifications were described as modifications of the above embodiments, the configurations of each modification can be combined as appropriate.

[0233] In the embodiments described above, an imaging device was used as an example; however, the light detection device of this disclosure may be any device that receives incident light and converts the light into an electric charge. The output signal may be an image information signal or a distance measurement information signal. The light detection device (imaging device) can be applied to an image sensor, a distance measurement sensor, etc. Furthermore, this disclosure is not limited to back-illuminated image sensors, but is also applicable to front-illuminated image sensors.

[0234] The light detection device relating to this disclosure can also be used as a distance measuring sensor capable of measuring distance using the Time of Flight (TOF) method. The light detection device (imaging device) can also be used as a sensor capable of detecting events, for example, an event-driven sensor (also known as an EVS (Event Vision Sensor), EDS (Event Driven Sensor), DVS (Dynamic Vision Sensor), etc.).

[0235] An optical detection device according to one embodiment of the present disclosure comprises a first pixel having a first photoelectric conversion element, a first signal line electrically connected to the first pixel, a first holding circuit including a first capacitive element and capable of holding a signal input via the first signal line, a readout circuit having a first AD conversion circuit, and a control circuit capable of controlling the readout circuit. The control circuit is capable of performing control to hold the pixel signal input to the first capacitive element for a first time by the first capacitive element and to perform AD conversion of the pixel signal by the first AD conversion circuit. The control circuit is capable of performing control to hold a first signal having a first voltage input to the first capacitive element for a second time longer than the first time by the first capacitive element. Therefore, it is possible to realize an optical detection device advantageous for fault detection.

[0236] Furthermore, the effects described herein are merely illustrative and not limited to those described herein, and other effects may also exist. In addition, the present disclosure may take the following configurations: (1) A photodetector comprising: a first pixel having a first photoelectric conversion element; a first signal line electrically connected to the first pixel; a readout circuit having a first holding circuit including a first capacitive element and capable of holding a signal input via the first signal line; and a control circuit capable of controlling the readout circuit, wherein the control circuit is capable of performing control to hold a pixel signal input to the first capacitive element by the first capacitive element for a first time and to perform AD conversion of the pixel signal by the first AD conversion circuit; and the control circuit is capable of performing control to hold a first signal having a first voltage input to the first capacitive element by the first capacitive element for a second time longer than the first time. (2) The photodetector according to (1), further comprising a determination circuit capable of performing fault determination based on the first signal held for the second time. (3) The photodetector according to (1) or (2), wherein the first pixel is capable of outputting a pixel signal based on the charge converted by the first photoelectric conversion element to the first signal line. (4) The photodetector according to any one of (1) to (3), further comprising a cell electrically connected to the first signal line and capable of outputting the first signal to the first signal line. (5) The photodetector according to any one of (1) to (4), comprising a determination circuit capable of performing fault determination, wherein the control circuit is capable of performing control to hold the first signal input to the first capacitive element for a second time by the first capacitive element and to perform AD conversion of the first signal by the first AD conversion circuit, and the determination circuit is capable of performing fault determination based on a digital signal corresponding to the first signal. (6) The photodetector according to (5), wherein the first holding circuit includes a second capacitive element, and the control circuit is capable of performing control to hold the second signal having the first voltage input to the second capacitive element for a third time longer than the first time by the second capacitive element.(7) The optical detection device according to (6), wherein the control circuit is capable of performing control to hold the second signal input to the second capacitive element for the third time by the second capacitive element and to perform AD conversion of the second signal by the first AD conversion circuit, and the determination circuit is capable of performing fault determination based on a digital signal corresponding to the second signal. (8) The optical detection device according to (7), wherein the determination circuit is capable of performing fault determination based on a digital signal corresponding to the difference between the first signal and the second signal. (9) The optical detection device according to any one of (1) to (8), further comprising a second pixel having a second photoelectric conversion element and a second signal line electrically connected to the second pixel, wherein the readout circuit has a second holding circuit capable of holding a signal input via the second signal line and a second AD conversion circuit, and the first holding circuit and the second holding circuit each include the first capacitive element. (10) The photodetector according to (9), further comprising a determination circuit capable of performing fault determination, wherein the determination circuit is capable of performing fault determination based on a first signal that is held by the first capacitive element of the first holding circuit and then AD-converted by the first AD conversion circuit, and a first signal that is held by the first capacitive element of the second holding circuit and then AD-converted by the second AD conversion circuit. (11) The photodetector according to (9) or (10), wherein the first holding circuit and the second holding circuit each include a first capacitive element and a second capacitive element, and the control circuit is capable of performing control to hold a second signal having a first voltage input to the second capacitive element by the second capacitive element for a third time longer than the first time, and to perform AD conversion of the second signal. (12) The photodetector according to any one of (9) to (11), further comprising a calculation circuit capable of calculating a deviation of the value of a digital signal corresponding to the first signal. (13) The photodetector according to (12), further comprising a determination circuit capable of performing fault determination based on the deviation. (14) The photodetector according to claim 1, wherein the second time is 10 times or more the first time. (15) The photodetector according to any one of (1) to (14), further comprising a determination circuit capable of performing fault determination and an interface circuit capable of outputting a signal to the outside regarding the presence or absence of a fault.(16) The photodetector according to (15), wherein the interface circuit is capable of outputting a signal to the outside regarding the presence or absence of a fault in the first capacitive element. (17) The photodetector according to any one of (1) to (16), wherein the readout circuit has a first amplification circuit connected between the first signal line and the first holding circuit, and the first holding circuit is capable of holding a signal input via the first amplification circuit. (18) The photodetector according to (17), wherein the first holding circuit has a first switch connected between the first amplification circuit and the first capacitive element, and a second switch connected between the first capacitive element and the first AD conversion circuit, and the control circuit is capable of controlling the first switch and the second switch. (19) Electronic device comprising an optical system and a light detection device for receiving light transmitted through the optical system, wherein the light detection device comprises a first pixel having a first photoelectric conversion element, a first signal line electrically connected to the first pixel, a readout circuit having a first holding circuit including a first capacitive element and capable of holding a signal input via the first signal line, and a first AD conversion circuit, and a control circuit capable of controlling the readout circuit, wherein the control circuit is capable of performing control to hold a pixel signal input to the first capacitive element by the first capacitive element for a first time and to perform AD conversion of the pixel signal by the first AD conversion circuit, and the control circuit is capable of performing control to hold a first signal having a first voltage input to the first capacitive element by the first capacitive element for a second time longer than the first time.

[0237] This application claims priority based on Japanese Patent Application No. 2025-049627, filed with the Japan Patent Office on 25 March 2025, and all contents of that application are incorporated herein by reference.

[0238] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A photodetector comprising: a first pixel having a first photoelectric conversion element; a first signal line electrically connected to the first pixel; a first holding circuit including a first capacitive element and capable of holding a signal input via the first signal line; a readout circuit having a first AD conversion circuit; and a control circuit capable of controlling the readout circuit, wherein the control circuit is capable of performing control to hold a pixel signal input to the first capacitive element by the first capacitive element for a first time and to perform AD conversion of the pixel signal by the first AD conversion circuit; and the control circuit is capable of performing control to hold a first signal having a first voltage input to the first capacitive element by the first capacitive element for a second time longer than the first time.

2. The photodetector according to claim 1, further comprising a determination circuit capable of performing fault determination based on the first signal held for the second time.

3. The photodetector according to claim 1, wherein the first pixel is capable of outputting a pixel signal based on the charge converted by the first photoelectric conversion element to the first signal line.

4. The photodetector according to claim 1, further comprising a cell electrically connected to the first signal line and capable of outputting the first signal to the first signal line.

5. The optical detection device according to claim 1, comprising a determination circuit capable of performing fault determination, wherein the control circuit is capable of performing control to hold the first signal input to the first capacitive element for a second time by the first capacitive element and to perform AD conversion of the first signal by the first AD conversion circuit, and the determination circuit is capable of performing fault determination based on a digital signal corresponding to the first signal.

6. The photodetector according to claim 5, wherein the first holding circuit includes a second capacitive element, and the control circuit is capable of performing control to hold a second signal having the first voltage input to the second capacitive element for a third time longer than the first time by the second capacitive element.

7. The optical detection device according to claim 6, wherein the control circuit is capable of holding the second signal input to the second capacitive element for the third time by the second capacitive element and performing AD conversion of the second signal by the first AD conversion circuit, and the determination circuit is capable of performing fault determination based on a digital signal corresponding to the second signal.

8. The optical detection device according to claim 7, wherein the determination circuit is capable of performing fault determination based on a digital signal corresponding to the difference between the first signal and the second signal.

9. The photodetector according to claim 1, further comprising a second pixel having a second photoelectric conversion element, and a second signal line electrically connected to the second pixel, wherein the readout circuit comprises a second holding circuit capable of holding a signal input via the second signal line, and a second AD conversion circuit, and the first holding circuit and the second holding circuit each include the first capacitive element.

10. The optical detection device according to claim 9, comprising a determination circuit capable of performing fault determination, wherein the determination circuit is capable of performing fault determination based on a first signal that is held by the first capacitive element of the first holding circuit and then AD-converted by the first AD conversion circuit, and a first signal that is held by the first capacitive element of the second holding circuit and then AD-converted by the second AD conversion circuit.

11. The photodetector according to claim 9, wherein the first holding circuit and the second holding circuit each include the first capacitive element and the second capacitive element, and the control circuit is capable of performing control to hold the second signal having the first voltage input to the second capacitive element for a third time longer than the first time, and to perform AD conversion of the second signal.

12. The photodetector according to claim 9, further comprising a calculation circuit capable of calculating the deviation of the value of a digital signal corresponding to the first signal.

13. The optical detection device according to claim 12, further comprising a determination circuit capable of performing fault determination based on the aforementioned deviation.

14. The photodetector according to claim 1, wherein the second time is 10 times or more the first time.

15. The optical detection device according to claim 1, further comprising a determination circuit capable of performing fault determination and an interface circuit capable of outputting a signal to the outside regarding the presence or absence of a fault.

16. The photodetector according to claim 15, wherein the interface circuit is capable of outputting a signal to the outside regarding the presence or absence of a failure of the first capacitive element.

17. The photodetector according to claim 1, wherein the readout circuit has a first amplification circuit connected between the first signal line and the first holding circuit, and the first holding circuit is capable of holding the signal input via the first amplification circuit.

18. The photodetector according to claim 17, wherein the first holding circuit has a first switch connected between the first amplification circuit and the first capacitive element, and a second switch connected between the first capacitive element and the first AD conversion circuit, and the control circuit is capable of controlling the first switch and the second switch.

19. An electronic device comprising an optical system and a light detection device for receiving light transmitted through the optical system, wherein the light detection device comprises a first pixel having a first photoelectric conversion element, a first signal line electrically connected to the first pixel, a first holding circuit including a first capacitive element and capable of holding a signal input via the first signal line, a readout circuit having a first AD conversion circuit, and a control circuit capable of controlling the readout circuit, wherein the control circuit is capable of performing control to hold a pixel signal input to the first capacitive element by the first capacitive element for a first time and to perform AD conversion of the pixel signal by the first AD conversion circuit, and the control circuit is capable of performing control to hold a first signal having a first voltage input to the first capacitive element by the first capacitive element for a second time longer than the first time.

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