Light detection device

Abstract

A light detection device according to an embodiment of the present disclosure comprises: a pixel having a semiconductor layer, a photoelectric conversion element, and a first transistor provided on a first surface side of the semiconductor layer; a semiconductor region of a first conductivity type provided in the semiconductor layer; an isolation region provided in the semiconductor layer; and wiring. At least a part of the wiring is provided in the isolation region, is electrically connected to the semiconductor region, and is given a predetermined potential.

Description

Photodetector

[0001] The present disclosure relates to a photodetector.

[0002] An imaging device including a plurality of pixels and deep trenches for separating adjacent pixels from each other has been proposed (Patent Document 1).

[0003] Japanese Unexamined Patent Publication No. 2016-92178

[0004] In a device that detects light, it is desirable to be able to suppress a decrease in signal quality.

[0005] It is desirable to provide a photodetector capable of suppressing a decrease in signal quality.

[0006] A photodetector according to one embodiment of the present disclosure comprises a semiconductor layer, a photoelectric conversion element, a pixel having a first transistor provided on the first surface side of the semiconductor layer, a semiconductor region of a first conductivity type provided on the semiconductor layer, an isolation region provided on the semiconductor layer, and wiring. At least a portion of the wiring is provided within the isolation region and is electrically connected to the semiconductor region and is given a predetermined potential. A photodetector according to one embodiment of the present disclosure comprises a semiconductor layer, a photoelectric conversion element, a first floating diffusion, a pixel having a first transistor provided on the first surface side of the semiconductor layer and electrically connected to the first floating diffusion, a second transistor provided on the first surface side of the semiconductor layer and capable of resetting the voltage of the first floating diffusion, an isolation region provided on the semiconductor layer, and first wiring. The first transistor has a first semiconductor region provided on the semiconductor layer and electrically connected to the first floating diffusion, and a second semiconductor region provided on the semiconductor layer. At least a portion of the first wiring is provided within the isolation region and is electrically connected to the second semiconductor region. A photodetector according to one embodiment of the present disclosure comprises a semiconductor layer, a photoelectric conversion element, a floating diffusion element, a pixel having a first transistor provided on the first surface side of the semiconductor layer and capable of outputting a first signal based on the charge accumulated in the floating diffusion element, an isolation region provided in the semiconductor layer, and a first wiring. The first transistor has a first gate electrode. At least a portion of the first wiring is provided around the first gate electrode within the isolation region.

[0007] Figure 1 is a block diagram showing an example of the schematic configuration of an imaging device, which is an example of a photodetector according to the first embodiment of this disclosure. Figure 2 is a diagram showing an example of the pixel section of an imaging device according to the first embodiment of this disclosure. Figure 3 is a diagram showing an example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 4 is a diagram showing another example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 5 is a diagram showing another example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 6 is a diagram showing another example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 7 is a diagram showing another example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 8 is a diagram illustrating an example of the planar configuration of an imaging device according to the first embodiment of this disclosure. Figure 9A is a diagram illustrating an example of the cross-sectional configuration of an imaging device according to the first embodiment of this disclosure. Figure 9B is a diagram illustrating an example of the cross-sectional configuration of an imaging device according to the first embodiment of this disclosure. Figure 10 is a diagram illustrating an example of the configuration of an imaging device according to Modification 1 of this disclosure. Figure 11 is a diagram illustrating another configuration example of the imaging device according to Modification 1 of the present disclosure. Figure 12A is a diagram illustrating another configuration example of the imaging device according to Modification 1 of the present disclosure. Figure 12B is a diagram illustrating another configuration example of the imaging device according to Modification 1 of the present disclosure. Figure 13A is a diagram illustrating another configuration example of the imaging device according to Modification 1 of the present disclosure. Figure 13B is a diagram illustrating another configuration example of the imaging device according to Modification 1 of the present disclosure. Figure 14 is a diagram illustrating an example of the imaging device according to Modification 2 of the present disclosure. Figure 15 is a diagram illustrating an example of the imaging device according to Modification 3 of the present disclosure. Figure 16A is a diagram illustrating an example of the imaging device according to Modification 3 of the present disclosure. Figure 16B is a diagram illustrating an example of the imaging device according to Modification 3 of the present disclosure. Figure 17 is a diagram illustrating an example of the imaging device according to the second embodiment of the present disclosure. Figure 18 is a diagram illustrating an example of the imaging device according to the second embodiment of the present disclosure. Figure 19 is a diagram illustrating an example of the imaging device according to the second embodiment of the present disclosure. Figure 20A shows an example of a method for manufacturing an imaging device according to a second embodiment of the present disclosure.Figure 20B is a diagram showing an example of a method for manufacturing an imaging device according to a second embodiment of the present disclosure. Figure 20C is a diagram showing an example of a method for manufacturing an imaging device according to a second embodiment of the present disclosure. Figure 20D is a diagram showing an example of a method for manufacturing an imaging device according to a second embodiment of the present disclosure. Figure 20E is a diagram showing an example of a method for manufacturing an imaging device according to a second embodiment of the present disclosure. Figure 20F is a diagram showing an example of a method for manufacturing an imaging device according to a second embodiment of the present disclosure. Figure 20G is a diagram showing an example of a method for manufacturing an imaging device according to a second embodiment of the present disclosure. Figure 20H is a diagram showing an example of a method for manufacturing an imaging device according to a second embodiment of the present disclosure. Figure 21 is a diagram illustrating an example of the configuration of an imaging device according to Modification 4 of the present disclosure. Figure 22 is a diagram illustrating an example of the configuration of an imaging device according to Modification 4 of the present disclosure. Figure 23 is a diagram illustrating an example of the configuration of an imaging device according to Modification 4 of the present disclosure. Figure 24 is a diagram illustrating an example of the configuration of an imaging device according to Modification 5 of the present disclosure. Figure 25 is a diagram illustrating an example of the configuration of an imaging device according to Modification 5 of the present disclosure. Figure 26 is a diagram illustrating an example configuration of an imaging device according to Modification 5 of the present disclosure. Figure 27 is a diagram illustrating an example configuration of an imaging device according to Modification 6 of the present disclosure. Figure 28 is a diagram illustrating an example configuration of an imaging device according to Modification 6 of the present disclosure. Figure 29 is a diagram illustrating an example configuration of an imaging device according to Modification 6 of the present disclosure. Figure 30 is a diagram illustrating an example configuration of an imaging device according to Modification 6 of the present disclosure. Figure 31 is a diagram illustrating an example configuration of an imaging device according to Modification 6 of the present disclosure. Figure 32 is a diagram illustrating an example configuration of an imaging device according to Modification 7 of the present disclosure. Figure 33 is a diagram illustrating an example configuration of an imaging device according to Modification 7 of the present disclosure. Figure 34 is a diagram illustrating another example configuration of an imaging device according to Modification 7 of the present disclosure. Figure 35 is a diagram illustrating another example configuration of an imaging device according to Modification 7 of the present disclosure. Figure 36 is a diagram illustrating an example configuration of an imaging device according to Modification 8 of the present disclosure. Figure 37A is a diagram illustrating an example configuration of an imaging device according to Modification 8 of the present disclosure. Figure 37B is a diagram illustrating an example of the configuration of an imaging device according to Modification 8 of the present disclosure. Figure 38 is a diagram illustrating an example of the configuration of an imaging device according to the third embodiment of the present disclosure.Figure 39 is a diagram illustrating an example configuration of an imaging device according to a third embodiment of the present disclosure. Figure 40A is a diagram illustrating an example configuration of an imaging device according to a third embodiment of the present disclosure. Figure 40B is a diagram illustrating an example configuration of an imaging device according to a third embodiment of the present disclosure. Figure 41 is a diagram illustrating an example configuration of an imaging device according to modification 9 of the present disclosure. Figure 42 is a diagram illustrating an example configuration of an imaging device according to modification 10 of the present disclosure. Figure 43 is a diagram illustrating an example configuration of an imaging device according to modification 10 of the present disclosure. Figure 44 is a diagram illustrating an example configuration of an imaging device according to modification 11 of the present disclosure. Figure 45 is a diagram illustrating an example configuration of an imaging device according to modification 11 of the present disclosure. Figure 46 is a diagram illustrating an example configuration of an imaging device according to modification 12 of the present disclosure. Figure 47 is a diagram illustrating an example configuration of an imaging device according to modification 12 of the present disclosure. Figure 48 is a diagram illustrating an example configuration of an imaging device according to modification 13 of the present disclosure. Figure 49 is a diagram illustrating an example configuration of an imaging device according to modification 13 of the present disclosure. Figure 50 is a diagram illustrating an example configuration of an imaging device according to Modification 14 of the present disclosure. Figure 51 is a diagram illustrating an example configuration of an imaging device according to the fourth embodiment of the present disclosure. Figure 52A is a diagram illustrating an example configuration of an imaging device according to the fourth embodiment of the present disclosure. Figure 52B is a diagram illustrating an example configuration of an imaging device according to the fourth embodiment of the present disclosure. Figure 53 is a diagram illustrating an example configuration of an imaging device according to Modification 15 of the present disclosure. Figure 54 is a diagram illustrating an example configuration of an imaging device according to Modification 15 of the present disclosure. Figure 55 is a diagram illustrating an example configuration of an imaging device according to Modification 16 of the present disclosure. Figure 56 is a diagram illustrating an example configuration of an imaging device according to Modification 16 of the present disclosure. Figure 57 is a diagram illustrating an example configuration of an imaging device according to Modification 16 of the present disclosure. Figure 58 is a diagram illustrating an example configuration of an imaging device according to Modification 17 of the present disclosure. Figure 59 is a diagram illustrating an example configuration of an imaging device according to Modification 17 of the present disclosure. Figure 60 is a diagram illustrating an example configuration of an imaging device according to the fifth embodiment of the present disclosure. Figure 61 is a diagram illustrating an example of the configuration of an imaging device according to a fifth embodiment of the present disclosure.Figure 62A is a diagram illustrating an example of the configuration of an imaging device according to the fifth embodiment of this disclosure. Figure 62B is a diagram illustrating an example of the configuration of an imaging device according to the fifth embodiment of this disclosure. Figure 63 is a diagram illustrating an example of the operation of an imaging device according to the fifth embodiment of this disclosure. Figure 64 is a diagram illustrating an example of the configuration of an imaging device according to modification 18 of this disclosure. Figure 65A is a diagram illustrating an example of the configuration of an imaging device according to modification 18 of this disclosure. Figure 65B is a diagram illustrating an example of the configuration of an imaging device according to modification 18 of this disclosure. Figure 66 is a diagram illustrating an example of the configuration of an imaging device according to modification 19 of this disclosure. Figure 67A is a diagram illustrating an example of the configuration of an imaging device according to modification 19 of this disclosure. Figure 67B is a diagram illustrating an example of the configuration of an imaging device according to modification 19 of this disclosure. Figure 67C is a diagram illustrating an example of the configuration of an imaging device according to modification 19 of this disclosure. Figure 68 is a diagram illustrating an example of the configuration of an imaging device according to modification 20 of this disclosure. Figure 69A is a diagram illustrating an example configuration of an imaging device according to Modification 20 of the present disclosure. Figure 69B is a diagram illustrating an example configuration of an imaging device according to Modification 20 of the present disclosure. Figure 69C is a diagram illustrating an example configuration of an imaging device according to Modification 20 of the present disclosure. Figure 69D is a diagram illustrating an example configuration of an imaging device according to Modification 20 of the present disclosure. Figure 70 is a diagram illustrating an example configuration of an imaging device according to Modification 21 of the present disclosure. Figure 71A is a diagram illustrating an example configuration of an imaging device according to Modification 21 of the present disclosure. Figure 71B is a diagram illustrating an example configuration of an imaging device according to Modification 21 of the present disclosure. Figure 71C is a diagram illustrating an example configuration of an imaging device according to Modification 21 of the present disclosure. Figure 72 is a diagram illustrating an example configuration of an imaging device according to the sixth embodiment of the present disclosure. Figure 73 is a diagram illustrating an example configuration of an imaging device according to the sixth embodiment of the present disclosure. Figure 74 is a diagram illustrating an example configuration of an imaging device according to the sixth embodiment of the present disclosure. Figure 75 is a diagram illustrating an example configuration of an imaging device according to Modification 22 of the present disclosure. Figure 76 is a diagram illustrating an example configuration of an imaging device according to Modification 22 of the present disclosure. Figure 77 is a diagram illustrating an example configuration of an imaging device according to Modification 22 of the present disclosure.Figure 78 is a diagram illustrating an example configuration of an imaging device according to Modification 23 of the present disclosure. Figure 79 is a diagram illustrating another example configuration of an imaging device according to Modification 23 of the present disclosure. Figure 80 is a diagram illustrating another example configuration of an imaging device according to Modification 23 of the present disclosure. Figure 81 is a diagram illustrating another example configuration of an imaging device according to Modification 23 of the present disclosure. Figure 82 is a diagram illustrating another example configuration of an imaging device according to Modification 23 of the present disclosure. Figure 83 is a block diagram showing an example configuration of an electronic device having an imaging device. Figure 84 is a block diagram illustrating an example of a schematic configuration of a vehicle control system. Figure 85 is an explanatory diagram showing an example of the installation positions of an external information detection unit and an imaging unit. Figure 86 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. Figure 87 is a block diagram illustrating an example of the functional configuration of a camera head and a CCU.

[0008] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order: 1. First Embodiment 2. Second Embodiment 3. Third Embodiment 4. Fourth Embodiment 5. Fifth Embodiment 6. Sixth Embodiment 7. Application Examples 8. Application Examples

[0009] <1. First Embodiment> Figure 1 is a block diagram showing an example of the schematic configuration of an imaging device, which is an example of a photodetector according to the first embodiment of the present disclosure. Figure 2 is a diagram showing an example of the pixel section of an imaging device according to the first embodiment. A photodetector is a device capable of detecting incident light. An imaging device 1, which is an example of a photodetector, has a plurality of pixels P including a photoelectric conversion unit, and is configured to generate a signal by photoelectric conversion of incident light.

[0010] The imaging device 1 is configured using, for example, a substrate (such as a silicon (Si) substrate or a silicon on insulator (SOI) substrate) on which the photoelectric conversion unit for each pixel P is provided. The imaging device 1 may also have a structure (i.e., a laminated structure) formed by stacking multiple substrates (or semiconductor layers). As an example, the imaging device 1 receives light transmitted through an optical system (not shown) and generates a signal.

[0011] The imaging device 1 has a region (pixel section 100) where a plurality of pixels P are provided, as shown in the example in Figure 1 or Figure 2. The imaging device 1 has, for example, a pixel section 100 in which a plurality of pixels P are arranged in a matrix in two dimensions as an imaging area. The photoelectric conversion section of the pixel P is, for example, a photodiode (PD) and is configured to convert light into photoelectric energy. The photoelectric conversion section of each pixel P is a photoelectric conversion element and can also be called a photoelectric conversion region.

[0012] The imaging device 1 captures incident light (image light) from the subject to be measured, for example, through an optical system including an optical lens and an aperture (diaphragm). The imaging device 1 captures an image of the subject formed by the optical system. The imaging device 1 generates a pixel signal by photoelectric conversion of the received light (e.g., visible light, infrared light, etc.). The imaging device 1, being a light detection device, is a device capable of receiving light and generating a signal, and can also be called a light receiving device.

[0013] The imaging device 1 (light detection device) is configured, for example, as an image sensor. The imaging device 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a CCD (Charge Coupled Device) image sensor, etc. The imaging device 1 can be used in various electronic devices such as digital still cameras, video cameras, and mobile phones.

[0014] As shown in Figure 2, the direction of incidence of light from the subject being measured is defined as the Z-axis direction, the left-right direction perpendicular to the Z-axis direction is defined as the X-axis direction, and the up-down direction perpendicular to both the Z-axis and X-axis directions is defined as the Y-axis direction. In subsequent figures, directions may also be indicated based on the direction of the arrows in Figure 2.

[0015] [Outline Configuration of the Imaging Device] The imaging device 1, as an example, has a pixel section 100, a pixel control unit 111, a signal processing unit 112, a control unit 113, and a processing unit 114, as shown in Figure 1. The imaging device 1 also has, for example, a plurality of control lines Lc and a plurality of signal lines VSL. The pixel section 100 is a pixel array in which a plurality of pixels P are arranged. The number and arrangement of pixels P provided in the pixel section 100 (i.e., the pixel array) can be changed as appropriate.

[0016] The control line Lc is a signal line capable of transmitting signals to control the pixel P, and is connected to the pixel control unit 111 and the pixel P of the pixel unit 100. The control line Lc is configured to transmit, for example, a control signal for reading signals from the pixel P. In the example shown in Figure 1, multiple control lines Lc are wired to each pixel row of the pixel unit 100, which is composed of multiple pixels P arranged horizontally (in the row direction).

[0017] The multiple control lines Lc for each pixel row of the imaging device 1 include, for example, wiring that transmits signals to control the transfer transistor, wiring that transmits signals to control the selection transistor, wiring that transmits signals to control the reset transistor, wiring that transmits signals to control the switching transistor, etc. The control lines Lc can also be called drive lines (or pixel drive lines) that transmit signals to drive the pixels P.

[0018] The signal line VSL is a signal line capable of transmitting signals from pixels P, and is connected to the pixels P of the pixel unit 100 and the signal processing unit 112. The signal line VSL is electrically connected to the pixels P and is configured to transmit signals output from the pixels P. For example, the signal line VSL is wired to each pixel row of the pixel unit 100, which is composed of multiple pixels P arranged vertically (in the column direction).

[0019] In the pixel section 100 of the imaging device 1, multiple signal lines VSL may be provided for a single pixel row. For example, the imaging device 1 has multiple signal lines VSL for each pixel row containing multiple pixels P. The number and arrangement of control lines Lc and signal lines VSL provided in the imaging device 1 are not limited to the illustrated example and can be changed as appropriate.

[0020] The pixel control unit 111 is configured to control each pixel P. The pixel control unit 111 is a control circuit (pixel control circuit) and is composed of multiple circuits, such as a buffer, a shift register, and an address decoder. The pixel control unit 111 generates a signal for controlling the pixels P and outputs it to each pixel P of the pixel unit 100 via a control line Lc. The pixel control unit 111 is controlled, for example, by the control unit 113, and controls each pixel P of the pixel unit 100.

[0021] The pixel control unit 111 generates signals for controlling pixels P (signals to control the transfer transistor of pixel P, signals to control the selection transistor, signals to control the reset transistor, signals to control the switching transistor, etc.) and supplies them to each pixel P via the control line Lc. The pixel control unit 111 can perform control to read out pixel signals from each pixel P. The pixel control unit 111 can also be described as a pixel drive unit (pixel drive circuit) configured to drive each pixel P.

[0022] The signal processing unit 112 is configured to perform signal processing on the input pixel signal. The signal processing unit 112 is a signal processing circuit and includes, for example, a load circuit, an AD (Analog Digital) conversion circuit, a horizontal selection switch, etc. The load circuit is, for example, composed of a current source capable of supplying current to the amplification transistor of the pixel P, and together with the amplification transistor of the pixel P, it forms a source follower circuit.

[0023] The load circuit and AD conversion circuit of the signal processing unit 112 are provided, for example, for each of the multiple signal lines VSL. The signal processing unit 112 may also have an amplification circuit configured to amplify the signal read from the pixel P via the signal line VSL. As an example, a load circuit, an amplification circuit, and an AD conversion circuit are provided for each pixel row of the pixel unit 100.

[0024] The signals output from each pixel P selected and scanned by the pixel control unit 111 are input to the signal processing unit 112 via the signal line VSL. The signal processing unit 112 performs signal processing such as AD conversion and CDS (Correlated Double Sampling) of the pixel P signals. The signals from each pixel P transmitted via each signal line VSL are processed by the signal processing unit 112 and output to the processing unit 114.

[0025] The processing unit 114 is configured to acquire signals from each pixel P and perform signal processing. The processing unit 114 is a processing circuit and is composed of, for example, circuits that perform various signal processing on the input pixel signals. The processing unit 114 (processing circuit) is composed of, for example, an arithmetic circuit, a memory circuit, an I / F (interface) circuit, etc.

[0026] The processing unit 114 is configured to perform various signal processing operations, such as noise reduction, interpolation, and gradation correction. For example, the processing unit 114 can perform signal processing on the pixel signal input from the signal processing unit 112 and output the processed pixel signal. The processing unit 114 may also include a processor and memory.

[0027] The control unit 113 is configured to control each part of the imaging device 1. The control unit 113 is a control circuit and includes, for example, a PLL (Phase Locked Loop), a timing generator, a DAC (Digital to Analog Converter), etc. As an example, the control unit 113 can receive a clock and data commanding the operating mode from an external source, and can also output data such as internal information of the imaging device 1.

[0028] The control unit 113 includes, for example, a timing generator configured to generate various timing signals. Based on the various timing signals (pulse signals, clock signals, etc.) generated by the timing generator, the control unit 113 performs drive control for the pixel control unit 111 and the signal processing unit 112, etc. Note that the control unit 113 and the processing unit 114 may be configured as an integrated unit.

[0029] The pixel unit 100, pixel control unit 111, signal processing unit 112, control unit 113, processing unit 114, etc., described above may be provided on a single substrate or on multiple substrates. The imaging device 1 may have a laminated structure formed by stacking multiple substrates (for example, two or more semiconductor substrates).

[0030] The pixel control unit 111, signal processing unit 112, control unit 113, processing unit 114, etc. of the imaging device 1 may be provided, for example, as peripheral circuits in the peripheral area of ​​the pixel unit 100 (pixel array). Note that some or all of the signal processing unit 112, control unit 113, and processing unit 114 may be configured as a single unit.

[0031] [Pixel Configuration] Figure 3 shows an example of the circuit configuration of a pixel in an imaging device according to the first embodiment. As an example, a pixel P has a photoelectric conversion unit 11, a transistor TRG, a floating diffusion FD1, and a readout circuit 15, as shown in Figure 3. Each photoelectric conversion unit 11 (photoelectric conversion element) of each pixel P is configured to receive light and generate a signal.

[0032] The photoelectric conversion unit 11 is configured to generate electric charge through photoelectric conversion. In the example shown in Figure 3, the photoelectric conversion unit 11 is a photodiode (PD) that converts incident light into electric charge. The photoelectric conversion unit 11 performs photoelectric conversion to generate an electric charge corresponding to the amount of light received. The photoelectric conversion unit 11 is a photoelectric conversion element and can also be called a light receiving element.

[0033] The transistor TRG is configured to transfer the charge photoelectrically converted in the photoelectric conversion unit 11 to the floating diffusion FD1. The transistor TRG is controlled by the signal STRG to electrically connect or disconnect the photoelectric conversion unit 11 and the floating diffusion FD1. The transistor TRG (i.e., the transfer transistor) can transfer the charge converted and stored in the photoelectric conversion unit 11 to the floating diffusion FD1.

[0034] The floating diffusion FD1 is configured to store transferred charge. The floating diffusion FD1 can store charge photoelectrically converted by the photoelectric conversion unit 11. The floating diffusion FD1 stores the transferred charge and converts it into a voltage corresponding to the capacitance of the floating diffusion FD1. The floating diffusion FD1 can also be described as a charge storage unit or a charge holding unit.

[0035] The readout circuit 15 is configured to output a signal based on the photoelectrically converted charge. The readout circuit 15 may include, for example, a transistor AMP, a transistor SEL, and a transistor RST. The readout circuit 15 may also include a floating diffusion FD1. The readout circuit 15 may also include a transistor TRG.

[0036] The readout circuit 15 has multiple transistors (also called pixel transistors), such as transistors AMP and transistors SEL, and is provided for each pixel P or for multiple pixels P. The readout circuit 15 is configured to read out pixel signals based on the charge photoelectrically converted by the photoelectric conversion unit 11. The readout circuit 15 can also be called a pixel readout circuit.

[0037] The transistor AMP is configured to generate and output a signal based on the charge stored in the floating diffusion FD1. The transistor AMP (i.e., the amplifying transistor) can generate and output a signal based on the charge converted by the photoelectric conversion unit 11. The gate of the transistor AMP is electrically connected to the floating diffusion FD1, and the voltage converted by the floating diffusion FD1 is input to it.

[0038] The drain of the transistor AMP is connected to a power line to which, for example, the power supply voltage (power supply voltage VDD in the example shown in Figure 3) is supplied. The source of the transistor AMP is connected to the signal line VSL via transistor SEL. The transistor AMP is configured to generate a signal based on the charge accumulated in the floating diffusion FD1, i.e., a signal based on the voltage of the floating diffusion FD1, and output it to the signal line VSL.

[0039] The transistor SEL is configured to control the output of the pixel signal. The transistor SEL is electrically connected in series with the transistor AMP, as shown in the example in Figure 3. The transistor SEL is controlled by the signal SSEL and is configured to output the signal from the transistor AMP to the signal line VSL. The transistor SEL (i.e., the selection transistor) can control the output timing of the pixel signal.

[0040] The transistor SEL is configured to be capable of outputting a signal based on the charge converted by the photoelectric conversion unit 11. The transistor SEL can output the pixel signal of the pixel P to the signal line VSL. Note that the transistor SEL may be electrically connected in series between a power supply line to which a power supply voltage (the power supply voltage VDD in FIG. 3) is supplied and the transistor AMP. The transistor SEL may be omitted if necessary.

[0041] The readout circuit 15 may include a floating diffusion FD2 and a transistor FDG, as in the examples shown in FIG. 4 or FIG. 5. The floating diffusion FD2 is a floating diffusion different from the floating diffusion FD1, and can also be referred to as a sub-floating diffusion (Sub-FD).

[0042] The floating diffusion FD2 is configured to be capable of accumulating transferred charges. The floating diffusion FD2 accumulates the transferred charges and converts the charges into a voltage corresponding to the capacitance C1 of the floating diffusion FD2. The capacitance C1 can be referred to as a Sub-FD capacitance. Note that the floating diffusion FD2 can also be referred to as an accumulation unit capable of accumulating charges or a holding unit capable of holding charges.

[0043] The transistor FDG is a transistor used for setting conversion gain (i.e., conversion efficiency) when converting charges into a voltage. The readout circuit 15 of the pixel P includes the transistor FDG and is configured to be capable of changing the conversion gain. The transistor FDG is a switching transistor, and can also be referred to as a gain switching transistor or a capacitance switching transistor.

[0044] The transistor FDG is configured to be capable of electrically connecting the floating diffusion FD1 and the floating diffusion FD2 (i.e., Sub-FD). The transistor FDG is controlled by, for example, a signal SFDG to electrically connect or disconnect the floating diffusion FD1 and the floating diffusion FD2.

[0045] In the readout circuit 15, when the transistor FDG is turned on, the floating diffusion FD1 and the floating diffusion FD2 are electrically connected. The capacitance added to the floating diffusion FD1 increases, and the conversion gain (conversion efficiency) when converting charge into voltage is switched.

[0046] When the transistor FDG is in the on state, in addition to the capacitance of the floating diffusion FD1 (i.e., the FD capacitance), the capacitance C1 of the floating diffusion FD2 (i.e., the Sub-FD capacitance) is added to the gate of the transistor AMP. The transistor FDG can switch the capacitance connected to the gate of the transistor AMP, thereby changing the conversion gain.

[0047] In the image pickup apparatus 1, by performing on-off control on the transistor FDG, the capacitance added to the floating diffusion FD1 can be changed, and the conversion gain (i.e., conversion efficiency) can be switched. By controlling the transistor FDG, the capacitance for accumulating charge can be switched stepwise, which makes it possible to expand the dynamic range.

[0048] As an example, the transistor FDG is electrically connected to the floating diffusion FD1 and the transistor RST. Note that the transistor FDG may be electrically connected in series to the transistor RST, or may be electrically connected in parallel to the transistor RST, as in the examples shown in FIG. 4 or FIG. 5.

[0049] In the example shown in FIG. 4 or FIG. 5, when the transistor FDG is in the off state, the floating diffusion FD1 and the floating diffusion FD2 are electrically disconnected. In this case, the conversion gain when converting charge into voltage increases, and the pixel P and the readout circuit 15 enter a state where the conversion gain is "high".

[0050] When the transistor FDG is in the off state, i.e., when the high conversion gain setting (HCG setting) is enabled, the charge transferred from the photoelectric conversion unit 11 is stored in the floating diffusion FD1. The imaging device 1 has an operating mode in which the transistor FDG is in the off state, i.e., a high conversion gain mode (i.e., a high conversion efficiency mode) which is the HCG setting.

[0051] Furthermore, in the example shown in Figure 4 or Figure 5, when transistor FDG is ON, floating diffusion FD1 and floating diffusion FD2 are electrically connected. In this case, the conversion gain is lower than in the HCG setting, and the pixel P and readout circuit 15 are in a "low" conversion gain state.

[0052] When transistor FDG is ON, i.e., in the low conversion gain setting (LCG setting), the charge transferred from the photoelectric conversion unit 11 is accumulated in floating diffusion FD1 and floating diffusion FD2. The imaging device 1 has an operating mode in which transistor FDG is ON, i.e., a low conversion gain mode (i.e., a low conversion efficiency mode) which is the LCG setting.

[0053] The transistor RST is configured to reset the voltages of floating diffusion FD1 and floating diffusion FD2. The transistor RST (i.e., the reset transistor) is electrically connected to a power line to which a power supply voltage (power supply voltage VDD in the examples shown in Figures 3 and 4, etc.) is supplied, and is configured to perform a reset of the charge of pixel P.

[0054] The transistor RST is controlled by the signal SRST and can reset the charge accumulated in floating diffusion FD1 and floating diffusion FD2, and reset the voltage of floating diffusion FD1 and floating diffusion FD2.

[0055] Transistor RST electrically connects the power line to the floating diffusion FD1 and FD2, and can discharge the charge accumulated in the floating diffusion FD1 and FD2. Transistor RST can also reset the charge accumulated in the photoelectric conversion unit 11 via transistor TRG.

[0056] Figures 6 and 7 show another example of the pixel circuit configuration of the imaging device according to the first embodiment. The imaging device 1 may have a configuration in which a plurality of pixels P share one readout circuit 15. The readout circuit 15 is provided for a plurality of pixels P (i.e., pixel units). For example, in the imaging device 1, a readout circuit 15 is arranged for each of the plurality of pixels P, and one readout circuit 15 is shared by the plurality of pixels P.

[0057] As shown in Figure 6 or Figure 7, for example, a readout circuit 15 is provided for every eight pixels P (referred to as pixels Pa, Pb, Pc, Pd, Pe, Pf, Pg, and Ph). Pixels Pa to Ph share one readout circuit 15. For example, a 2x4 pixel (or 4x2 pixel) array composed of adjacent pixels Pa to Ph shares one readout circuit 15.

[0058] The imaging device 1 can read out the pixel signal of each of the eight pixels by operating the readout circuit 15 in a time-division manner. The imaging device 1 can also read out a pixel signal which is the sum of the individual signals of multiple pixels. For example, the imaging device 1 can read out a pixel signal corresponding to the sum of the charges obtained by photoelectric conversion at each of multiple pixels.

[0059] The photoelectric conversion unit 11 (in the example shown in Figure 6 or Figure 7, the photodiode PD of pixel Pa to the photodiode PD of pixel Ph) performs photoelectric conversion to generate a charge corresponding to the amount of light received. The transistor TRG (in Figure 6 or Figure 7, the transistor TRG of pixel Pa to the transistor TRG of pixel Ph) is configured to transfer the charge converted photoelectrically by the photoelectric conversion unit 11 to the floating diffusion FD1.

[0060] Each transistor TRG in pixels Pa through Ph is controlled on and off by different signals. The transistor TRG of pixel Pa is controlled by signal STRG1, the transistor TRG of pixel Pb is controlled by signal STRG2, the transistor TRG of pixel Pc is controlled by signal STRG3, and the transistor TRG of pixel Pd is controlled by signal STRG4.

[0061] The transistor TRG of pixel Pe is controlled by signal STRG5, and the transistor TRG of pixel Pf is controlled by signal STRG6. Furthermore, the transistor TRG of pixel Pg is controlled by signal STRG7, and the transistor TRG of pixel Ph is controlled by signal STRG8.

[0062] The readout circuit 15 may include a floating diffusion FD1, and may also include transistors TRG from pixel Pa to pixel Ph. The imaging device 1 may have a configuration in which, for example, two or four pixels P share one readout circuit 15, or a configuration in which eight or more pixels P share one readout circuit 15.

[0063] The readout circuit 15 is provided, for example, for a pixel unit PU including multiple pixels P, as described above. The imaging device 1 may have a configuration in which multiple pixels P share one readout circuit 15. This makes it possible to reduce the number of circuit elements (e.g., the number of transistors) per pixel P (or per photoelectric conversion unit 11). The imaging device 1 may have a structure that is advantageous for pixel miniaturization.

[0064] The transistors TRG (transfer transistor), AMP (amplifier transistor), SEL (selection transistor), FDG (switching transistor), and RST (reset transistor) mentioned above are, for example, MOS transistors (MOSFETs) having gate, source, and drain terminals.

[0065] In the example shown in Figure 3, transistors TRG, AMP, SEL, FDG, and RST are each composed of NMOS transistors. The transistors of pixel P may be composed of PMOS transistors as needed. The transistors of pixel P may also be composed of 3D transistors, such as Fin-type transistors (Fin FETs).

[0066] The pixel control unit 111 (see Figure 1) of the imaging device 1 supplies control signals to the gates of transistors TRG, SEL, FDG, or RST of each pixel P via the control line Lc described above, thereby turning the transistors on (conducting) or off (non-conducting).

[0067] The multiple control lines Lc for each pixel row of the imaging device 1 include, as an example, wiring that transmits the signal STRG for controlling transistor TRG, wiring that transmits the signal SSEL for controlling transistor SEL, wiring that transmits the signal SFDG for controlling transistor FDG, wiring that transmits the signal SRST for controlling transistor RST, and so on.

[0068] Transistors TRG, SEL, FDG, and RST are controlled on and off by the pixel control unit 111. The pixel control unit 111 controls the readout circuit 15 for each pixel P, causing each pixel P to output a pixel signal to the signal line VSL. The pixel control unit 111 can control the reading of the pixel signal from each pixel P to the signal line VSL.

[0069] In the imaging device 1, at least some of the pixels P (or pixel units PU) of the pixel section 100 may have a plurality of photoelectric conversion units 11 (for example, two or four or more photoelectric conversion units 11) and be configured as phase-difference pixels (or image plane phase-difference pixels). As an example, two photoelectric conversion units 11 receive light that has passed through different regions of the optical system, and pupil division is performed.

[0070] For example, the processing unit 114 of the imaging device 1 can obtain phase difference data by using the pixel signal based on the charge converted by one of the two photoelectric conversion units 11 of the pixel P (or pixel unit PU) for phase difference detection, and the pixel signal based on the charge converted by the other photoelectric conversion unit 11. By using the phase difference data, phase difference autofocus (AF) can be performed.

[0071] [Configuration of the Imaging Device] Figure 8 is a diagram illustrating an example of the planar configuration of the imaging device according to the first embodiment. Figure 9A shows an example of the cross-sectional configuration in the direction of the line A-A' shown in Figure 8. Figure 9B shows an example of the cross-sectional configuration in the direction of the line B-B' shown in Figure 8. Figures 8 and 9A, etc., show an example in which one readout circuit 15 is provided for a pixel unit PU containing eight pixels P.

[0072] A pixel unit PU has one region when the pixel section 100 is divided into regions for each of several pixels P (i.e., a predetermined number of pixels P, for example, eight pixels). Other multiple pixel units PU in the pixel section 100 (i.e., pixel array) may have a configuration similar to that shown in Figure 8, etc. Note that a pixel unit PU can also be called a pixel block containing multiple pixels P.

[0073] The imaging device 1 is constructed using, for example, a substrate 120 including a semiconductor layer 101. The substrate 120 has a semiconductor layer 101 and a wiring layer 105. The wiring layer 105 is stacked on the semiconductor layer 101 in the Z-axis direction. For example, the semiconductor layer 101 and the wiring layer 105 are provided from the side where light is incident.

[0074] The substrate 120 is constructed using a semiconductor substrate such as a Si substrate or an SOI substrate. The semiconductor layer 101 has opposing surfaces S1 and S2. Surface S2 is the surface opposite to surface S1. The substrate 120 may also be constructed using a SiGe (silicon germanium) substrate, a SiC (silicon carbide) substrate, or other semiconductor materials.

[0075] Surface S2 of the semiconductor layer 101 is, for example, a light-receiving surface (i.e., a light incident surface). Surface S1 of the semiconductor layer 101 is an element-forming surface on which elements such as transistors, capacitive elements, or resistive elements are formed. A gate electrode, a gate insulating film (e.g., a gate oxide film), etc., are provided on surface S1 of the semiconductor layer 101. The element-forming surface of the semiconductor layer 101 is the surface on which various circuit elements are provided, and can also be called a circuit surface.

[0076] Each pixel P is provided in the semiconductor layer 101. The photoelectric conversion unit 11 is provided between surfaces S1 and S2 of the semiconductor layer 101. For example, multiple photoelectric conversion units 11 are embedded in the semiconductor layer 101. The photoelectric conversion unit 11 is a photoelectric conversion element, and can also be called a photoelectric conversion region.

[0077] A wiring layer 105 is provided on the surface S1 side of the semiconductor layer 101. The wiring layer 105 includes, for example, a conductive film and an insulating film, and has a plurality of wirings and a plurality of vias. The wiring layer 105 has a structure in which a plurality of wirings are laminated with an insulating film acting as an interlayer insulating film (interlayer insulating layer). The wiring layer 105 is configured as a multilayer wiring layer and may include two or more or three or more layers of wiring.

[0078] The wiring of the wiring layer 105 may be formed using metallic materials such as aluminum (Al), copper (Cu), and tungsten (W), or it may be made using polysilicon (Poly-Si) or other conductive materials. The interlayer insulating film may be formed using silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or it may be made using other insulating materials.

[0079] The substrate 120, which includes the semiconductor layer 101, is provided with, for example, the transistor TRG, the floating diffusion FD1, and the transistors of the readout circuit 15 as described above. The pixel control unit 111, signal processing unit 112, control unit 113, processing unit 114 (see Figure 1), etc., are provided on the substrate 120 or on a substrate separate from the substrate 120.

[0080] As shown in Figure 9A, the semiconductor layer 101 has a semiconductor region 20 and a semiconductor region 25. Contacts 51 are provided in the wiring layer 105. The semiconductor region 20 is, for example, a p-type semiconductor region and is provided as a p-type well (p-well). The semiconductor layer 101 is provided with a semiconductor region 20 which is a p-type well region. The semiconductor region 20 may be an n-type semiconductor region as an n-type well region if necessary. The semiconductor region 25 is provided on the surface S1 side of the semiconductor layer 101.

[0081] The semiconductor region 25 is a semiconductor region of the same conductivity type as the semiconductor region 20. The semiconductor region 25 is provided, for example, as a well contact region relative to the semiconductor region 20. For example, the semiconductor region 25 has a higher impurity concentration than the semiconductor region 20 and is configured as a p+ type semiconductor region. The semiconductor region 25 can also be called a p+ type diffusion region (diffusion layer) or a p+ type conductive region.

[0082] The contact 51 is provided in relation to the semiconductor region 25. The contact 51 is constructed using a conductive material. The contact 51 is formed, for example, by embedding (filling) a conductive material such as tungsten (W) into the contact hole. The contact 51 may also be constructed from a metallic material such as copper (Cu) or aluminum (Al), or from other materials. The contact 51 can also be called a well contact.

[0083] The semiconductor region 25 is electrically connected to a reference potential line in the wiring layer 105, for example, via a contact 51. A voltage VSS, which serves as the reference potential, is applied to the semiconductor region 25 (well contact region) and the semiconductor region 20 (well) via the contact 51. The voltage VSS may be the GND potential (i.e., ground potential), for example, 0V.

[0084] The imaging device 1 has an isolation region 17, as shown in the example in Figure 8. The isolation region 17 is an isolation region (isolation part) provided in the semiconductor layer 101. The isolation region 17 is constructed using a trench 18 (groove). The isolation region 17, including the trench 18, is provided, for example, around a pixel P (or pixel unit PU).

[0085] The isolation region 17 has an STI (Shallow Trench Isolation) structure and is formed on the S1 side of the semiconductor layer 101. The isolation region 17 is provided, for example, on the side of the semiconductor layer 101 opposite to the light-receiving surface (light incident surface). The isolation region 17 is formed on the element formation surface side where elements such as transistors are formed, and separates the elements as shown in the example in Figure 8.

[0086] The trench 18 of the isolation region 17 is provided, for example, from the surface S1 of the semiconductor layer 101 to the space between the surfaces S1 and S2 of the semiconductor layer 101. An insulating film (insulator) such as an oxide film (e.g., silicon oxide film) or a nitride film (e.g., silicon nitride film) is provided within the trench 18 (groove) of the isolation region 17. The isolation region 17 can also be called an isolation section or an element isolation section.

[0087] The isolation region 17 is provided, for example, around a plurality of pixels P, i.e., a pixel unit PU, that share a readout circuit 15. The isolation region 17 is formed between a plurality of adjacent pixel units PU, separating them from each other. At least a portion of the isolation region 17 is provided at the boundary between adjacent pixel units PU in the semiconductor layer 101. It can also be said that the pixel unit PU (or pixel P) has a structure partitioned by the isolation region 17.

[0088] In the example shown in Figure 8, the isolation region 17, including the trench 18, is provided around four adjacent photoelectric conversion units 11 (four 2x2 photodiodes (PDs)). Part of the isolation region 17 is provided between four adjacent photoelectric conversion units 11 and four other adjacent photoelectric conversion units 11 in the pixel unit PU. Another part of the isolation region 17 is provided around each transistor of the readout circuit 15.

[0089] The isolation region 17 is provided around the multiple photoelectric conversion units 11 in each pixel unit PU, around each transistor in the readout circuit 15 of the pixel unit PU, etc., in a plan view (i.e., when viewed in the XY plane), and separates the elements. As an example, the isolation region 17 is provided so as to surround each photoelectric conversion unit 11 and the readout circuit 15 of the pixel unit PU in a plan view.

[0090] The isolation region 17 may be formed in a grid pattern so as to surround the photoelectric conversion section 11 and the readout circuit 15 of each pixel unit PU. The isolation region 17 may also be provided so as to penetrate the semiconductor layer 101. As an example, the isolation region 17 has an FTI (Full Trench Isolation) structure and is formed to reach the surface S2 of the semiconductor layer 101.

[0091] An insulating film, such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, is provided in the trench 18 of the separation region 17. The trench 18 of the separation region 17 may be filled with an insulating material, such as polysilicon, a metallic material, or another material.

[0092] On the surface S1 side of the semiconductor layer 101, as shown in the example in Figure 8, for example, a transistor TRG, a floating diffusion FD1, a transistor AMP, a transistor SEL, a floating diffusion FD2, a transistor FDG, and a transistor RST are provided. In addition, wiring L1 as floating diffusion wiring (FD wiring) is provided on the wiring layer 105.

[0093] Transistor TRG has a gate electrode 31. Transistor FDG has a gate electrode 32, and transistor RST has a gate electrode 33. Transistor AMP has a gate electrode 34, and transistor SEL has a gate electrode 35. Also, as shown in Figure 9B, transistor AMP has a gate insulating film 38. Each of transistors TRG, SEL, FDG, and RST also has a gate insulating film, for example, the gate insulating film 38.

[0094] The gate electrodes 31 to 35 are each constructed using, for example, polysilicon (Poly-Si). Each of the gate electrodes 31 to 35 may be constructed using a metallic material or a metallic compound. The gate electrodes 31 to 35 may be constructed using tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), etc., or may be formed using other materials.

[0095] The gate insulating film 38 is composed of, for example, a single layer made of one of silicon oxide, silicon oxynitride, hafnium oxide (HfO), or a multilayer film made of two or more of these materials. The gate insulating film 38 may also be formed using a high dielectric constant material having a dielectric constant higher than that of silicon oxide, such as a hafnium-based insulating film.

[0096] The gate electrode 34 of the transistor AMP is provided on the gate insulating film 38. The gate electrodes 31 to 33 and gate electrode 35 are also provided, for example, on the gate insulating film. Sidewalls may be provided on each of the sides of the gate electrodes 31 to 35.

[0097] The transistor TRG may have, for example, a planar gate structure and be configured as a planar transistor. The transistor TRG may also have a vertical gate structure. For example, at least a portion of the gate electrode 31 is provided by carving into the semiconductor layer 101. The transistor TRG is provided such that a portion of the gate electrode 31 is located within the semiconductor layer 101.

[0098] The floating diffusion FD1 is composed of, for example, a semiconductor region 41 provided in the semiconductor layer 101. The semiconductor region 41 is provided in the semiconductor region 20 (well) as a floating diffusion FD1. The semiconductor region 41 is a semiconductor region of a different conductivity type than the semiconductor region 20 and is formed on the surface S1 side of the semiconductor layer 101.

[0099] The semiconductor region 41 is a region formed using impurities, for example, an n-type semiconductor region. The semiconductor region 41 can also be called an n-type diffusion region or an n-type conductive region. The semiconductor region 41 may have an impurity concentration higher than that of the semiconductor region 20, and may be configured as an n+-type semiconductor region. The semiconductor region 41 can also be called a floating diffusion region.

[0100] The semiconductor region 41 stores charge transferred from the photoelectric conversion unit 11 via the region beneath the gate electrode 31 of the transistor TRG. The semiconductor region 41 is, for example, one of the source region and drain region of the transistor TRG. The semiconductor region 41 is electrically connected to the wiring L1 (i.e., FD wiring) provided in the wiring layer 105, and is electrically connected to the gate electrode 34 of the transistor AMP via the wiring L1.

[0101] In the example shown in Figure 8, the semiconductor region 41 is provided for each of the four adjacent photoelectric conversion units 11 (i.e., the four pixels P). Of the eight photoelectric conversion units 11 of the pixel unit PU, the semiconductor region 41 provided for one set of four photoelectric conversion units 11 and the semiconductor region 41 provided for the other set of four photoelectric conversion units 11 are electrically connected to each other via wiring L1. The floating diffusion FD1 may include wiring L1 which is FD wiring.

[0102] The floating diffusion FD2 is composed of, for example, a semiconductor region 42 provided in the semiconductor layer 101. The semiconductor region 42 is provided in the semiconductor region 20 (well) as, for example, a floating diffusion FD2 (i.e., Sub-FD). The semiconductor region 42 is a semiconductor region of a different conductivity type than the semiconductor region 20 and is formed on the surface S1 side of the semiconductor layer 101.

[0103] The semiconductor region 42 is, for example, an n-type semiconductor region, and can also be called an n-type diffusion region or an n-type conductive region. The semiconductor region 42 may have a higher impurity concentration than the semiconductor region 20 and may be configured as an n+-type semiconductor region. The semiconductor region 42 can also be called a subfloating diffusion region.

[0104] The semiconductor region 42 stores the charge transferred from the floating diffusion FD1 via the region beneath the gate electrode 32 of the transistor FDG. In the example shown in Figure 8, the semiconductor region 42 is also one of the source and drain regions of the transistor FDG. The transistor FDG also has a semiconductor region 43 which is the other of the source and drain regions of the transistor FDG, and a gate electrode 32.

[0105] The transistor RST has a gate electrode 33, a semiconductor region 43, and a semiconductor region 44. The semiconductor region 43 is one of the source region and drain region of the transistor RST. The semiconductor region 44 is the other of the source region and drain region of the transistor RST. In the example shown in Figure 8, the semiconductor region 43 is electrically connected to the wiring L1, which is an FD wiring.

[0106] The semiconductor region 43 and the semiconductor region 44 are, for example, semiconductor regions of a different conductivity type than the semiconductor region 20, and are formed on the surface S1 side of the semiconductor layer 101. Each of the semiconductor region 43 and the semiconductor region 44 is, for example, an n-type semiconductor region, and may be configured as an n+-type semiconductor region. The semiconductor region 44 is electrically connected, for example, to a power line (wiring) to which a power supply voltage (for example, power supply voltage VDD) is supplied.

[0107] The transistor AMP has a gate electrode 34, a semiconductor region 44, and a semiconductor region 45. The semiconductor region 44 is one of the source region and drain region of the transistor AMP, for example, the drain region. The semiconductor region 45 is the other of the source region and drain region of the transistor AMP, for example, the source region.

[0108] The transistor SEL has a gate electrode 35, a semiconductor region 45, and a semiconductor region 46. The semiconductor region 45 is either the source region or the drain region of the transistor SEL. The semiconductor region 46 is the other either the source region or the drain region of the transistor SEL. Note that the semiconductor region 45 is also, for example, the source region of the transistor AMP.

[0109] Each of the semiconductor regions 45 and 46 is a semiconductor region of a different conductivity type than semiconductor region 20, and is formed on the surface S1 side of the semiconductor layer 101. The semiconductor regions 45 and 46 are, for example, n-type semiconductor regions, or may be configured as n+-type semiconductor regions. The semiconductor region 46 is electrically connected, for example, to the signal line VSL described above. In the example shown in Figure 8, isolation regions 17 are provided around semiconductor regions 42 to 46.

[0110] The imaging device 1 has wiring L2, as shown in the example in Figure 8, etc. The wiring L2 is configured such that at least a portion of it is provided within the isolation region 17. The wiring L2 is provided within the trench 18 of the isolation region 17, for example, as shown in the example in Figures 9A and 9B. The wiring L2 may be arranged so as to be embedded in the trench 18 of the semiconductor layer 101. As an example, the wiring L2 is made of Poly-Si (polysilicon).

[0111] The wiring L2 is provided, for example, with a predetermined potential (voltage) and is located around the pixel unit PU (or pixel P). The wiring L2 is configured as a conductive member (conductor) to which a predetermined potential is applied and can be arranged to surround the pixel unit PU. At least a portion of the wiring L2 is provided at the boundary between adjacent pixel units PU in the isolation region 17. A constant potential is supplied to the wiring L2, for example, by the wiring and electrodes of the wiring layer 105.

[0112] The wiring L2 is electrically connected, for example, to the semiconductor region 25 (well contact region). A voltage VSS (e.g., 0V) is applied to the wiring L2 via the semiconductor region 25 and the contact 51. The wiring L2 may be provided to be directly connected to the semiconductor region 25, or it may be electrically connected to the semiconductor region 25 via wiring and vias of the wiring layer 105.

[0113] In the pixel section 100 of the imaging device 1, the wiring L2 is formed such that, for example, a portion of the wiring L2 is located near the semiconductor region 25 on the surface S1 side of the semiconductor layer 101. In each pixel unit PU or each pixel P of the pixel section 100, the wiring L2 may be wired so as to be adjacent to the semiconductor region 25. The wiring L2 may also be provided so as to cover a portion of the semiconductor region 25 on the surface S1 side of the semiconductor layer 101.

[0114] The wiring L2 is provided, for example, within the isolation region 17 in contact with the semiconductor region 25. The wiring L2 may be provided within the trench 18 of the isolation region 17 in contact with the semiconductor region 25 in the X-axis direction (or Y-axis direction). In the examples shown in Figures 8 and 9A, the wiring L2 has a side contact structure and is in contact with the side (side surface) of the semiconductor region 25.

[0115] In this disclosure, "in contact" includes cases where there is direct contact and cases where there is contact via a native oxide film or the like. "The wiring L2 and the semiconductor region 25 are in contact" includes cases where a native oxide film is interposed, and includes cases where the wiring L2 is in contact with the semiconductor region 25 via a thin native oxide film.

[0116] The imaging device 1 has wiring L2 provided between multiple adjacent pixel units PU, as shown in the example in Figure 8. For example, the wiring L2 is provided in a trench 18 of the isolation region 17 so as to surround multiple photoelectric conversion units 11 and readout circuits 15 of the pixel unit PU. In the example shown in Figure 8, wiring L2 is also provided between four adjacent photoelectric conversion units 11 and four other adjacent photoelectric conversion units 11 in the pixel unit PU.

[0117] The wiring L2 is made of, for example, a semiconductor material doped with impurities or a metallic material. The wiring L2 may be made of p+ type polysilicon or n+ type polysilicon. The wiring L2 may be made of polysilicon containing B (boron), P (phosphorus), or As (arsenic) as impurities.

[0118] The wiring L2 (conductive member) may be formed using metallic materials such as Al (aluminum), W (tungsten), Cu (copper), Ti (titanium), Ni (nickel), Co (cobalt), and Ru (ruthenium). The wiring L2 may also be composed of titanium nitride (TiN), titanium aluminum (TiAL), tantalum nitride (TaN), etc.

[0119] The wiring L2 may be composed of silicon that has been partially or entirely silicided using Ti (titanium), Co (cobalt), Ni (nickel), Pt (platinum), etc. The wiring L2 may be composed of other conductive materials. The wiring L2 may be composed of multiple films laminated together.

[0120] If the imaging device 1 does not have wiring L2, the parasitic capacitance formed between adjacent pixel units (or pixels) will increase, potentially leading to increased crosstalk. In particular, as pixels become smaller, the distance between the FD (floating diffusion) of a pixel unit and the FD of a surrounding pixel unit, or the distance between the FD and the power line, decreases, making it easier for crosstalk between multiple FDs and deterioration of the PSRR (Power Supply Rejection Ratio) to occur.

[0121] As described above, the imaging device 1 according to this embodiment has wiring L2 provided in the isolation region 17. The wiring L2 is electrically connected to the semiconductor region 21 and a predetermined potential is applied. Therefore, it is possible to reduce unwanted parasitic capacitance between pixel units PU (or between pixels P) (for example, unwanted coupling capacitance added to the floating diffusion FD1 or the gate electrodes of each transistor), and to suppress crosstalk.

[0122] In the imaging device 1, the wiring L2 provided within the isolation region 17 of the semiconductor layer 101 can effectively reduce capacitive coupling within the semiconductor layer 101. In particular, even with fine pixels, it is possible to suppress the deterioration of crosstalk and PSRR. The imaging device 1 can have a structure that is advantageous for pixel miniaturization. It is possible to suppress crosstalk without impairing miniaturization.

[0123] In this embodiment, by providing wiring L2 as shown in the example in Figure 8, unwanted parasitic capacitance formed between pixel units PU (or between pixels P) can be reduced, thereby suppressing crosstalk. This suppresses noise from being mixed into the pixel signal, improving the quality of the pixel signal. It also makes it possible to improve the image quality of the image generated using the pixel signal of each pixel.

[0124] [Function and Effects] The photodetector according to this embodiment comprises a semiconductor layer (for example, a semiconductor layer 101), a photoelectric conversion element (photoelectric conversion unit 11), a pixel (pixel P) having a first transistor (for example, transistor AMP or transistor SEL) provided on the first surface side of the semiconductor layer, a semiconductor region of a first conductivity type (semiconductor region 25) provided on the semiconductor layer, an isolation region (isolation region 17) provided on the semiconductor layer, and wiring (wiring L2). At least a portion of the wiring is provided within the isolation region, is electrically connected to the semiconductor region, and is given a predetermined potential.

[0125] The photodetector (imaging device 1) according to this embodiment has a semiconductor region 25 and an isolation region 17 provided on a semiconductor layer 101, and wiring L2. At least a portion of the wiring L2 is provided within the isolation region 17, is electrically connected to the semiconductor region 25, and is given a predetermined potential. Therefore, it is possible to realize a photodetector that can suppress the degradation of signal quality.

[0126] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0127] (Modification 1) In the embodiments described above, an example of the configuration of the imaging device was explained, but the configuration of the imaging device is not limited to the example described above. Figure 10 is a diagram illustrating an example of the configuration of an imaging device according to Modification 1 of the present disclosure. As shown in the example in Figure 10, the isolation region 17 and the wiring L2 may be provided so as to surround the region of the pixel transistor of the readout circuit 15.

[0128] In the example shown in Figure 10, the wiring L2 is provided in the isolation region 17 so as to surround multiple pixel transistors of the readout circuit 15, such as transistor FDG, transistor RST, transistor AMP, and transistor SEL. By configuring the imaging device 1 in this way, the symmetry of the layout can be improved.

[0129] Figures 11, 12A, and 12B are diagrams illustrating another configuration example of the imaging device according to Modification 1. Figure 11 shows an example of the planar configuration of the imaging device 1. Figure 12A shows an example of the cross-sectional configuration in the direction of line A-A' shown in Figure 11. Figure 12B shows an example of the cross-sectional configuration in the direction of line B-B' shown in Figure 11.

[0130] The imaging device 1 may have a contact 52 connected to the wiring L2. The contact 52 is provided on the surface S1 side of the semiconductor layer 101 and is connected to the wiring L2 provided in the isolation region 17. A predetermined potential is applied to the contact 52 via the wiring L2 or the wiring of the wiring layer 105, etc.

[0131] In the imaging device 1, for example, as shown in the examples in Figures 11 and 12B, wiring L2 and one or more contacts 52 are arranged at the boundary between multiple adjacent pixel units PU (or pixels P). The wiring L2 and contacts 52 can be used as a shielding section (shielding member), making it possible to further reduce crosstalk.

[0132] The contact 52 is constructed using a conductive material such as W (tungsten) or Al (aluminum). The wiring L2 may also be constructed using a metallic material such as Al. As shown in Figures 13A and 13B, the wiring L2 may have, for example, a portion P1 made of a metallic material and a portion P2 made of p+ type polysilicon.

[0133] (Modification 2) Figure 14 is a diagram illustrating an example of the configuration of an imaging device according to Modification 2. In the example shown in Figure 14, one readout circuit 15 is provided for one pixel P. A predetermined potential is applied to the wiring L2, which is provided around the pixel P. The isolation region 17 and the wiring L2 may be formed in a grid pattern in the pixel section 100 so as to surround each element of the pixel P.

[0134] At least a portion of the wiring L2 is provided at the boundary between adjacent pixels P in the isolation region 17. The wiring L2 is electrically connected, for example, to the semiconductor region 25 (well contact region). As an example, the wiring L2 has a side contact structure and is provided in contact with the end face (side surface) of the semiconductor region 25 within the trench 18 of the isolation region 17.

[0135] In the case of the imaging device 1 according to this modified example, the provision of wiring L2 reduces unwanted parasitic capacitance formed between pixels P, thereby suppressing crosstalk between pixels P. This makes it possible to suppress the inclusion of noise in the pixel signal. In this modified example, the same effects as in the above-described embodiment can be obtained.

[0136] (Modification 3) Figures 15, 16A, and 16B are diagrams illustrating an example of the configuration of an imaging device according to Modification 3. The imaging device 1 may have a structure in which a plurality of semiconductor layers 101 (in the example shown in Figure 15, etc., semiconductor layer 101a, semiconductor layer 101b) are stacked. Figure 16A shows an example of a planar configuration in layer 202 including semiconductor layer 101b, and Figure 16B shows an example of a planar configuration in layer 201 including semiconductor layer 101a.

[0137] The imaging device 1 has, for example, layers 201 and 202. The imaging device 1 has a configuration in which layer 201 as a first layer (first layer) and layer 202 as a second layer (second layer) are stacked in the Z-axis direction. Layer 201 has a semiconductor layer 101a and a wiring layer 105a. Layer 202 has a semiconductor layer 101b and a wiring layer 105b.

[0138] The semiconductor layer 101a and semiconductor layer 101b are made of a semiconductor substrate, such as a Si substrate or an SOI substrate. The semiconductor layer 101b may, for example, be made of a silicon layer (i.e., an active layer) on an SOI substrate. From the side where light is incident, the semiconductor layer 101a, the wiring layer 105a, the semiconductor layer 101b, and the wiring layer 105b are provided.

[0139] The semiconductor layer 101a and the wiring layer 105a together can be called the substrate 120a (or circuit layer). The semiconductor layer 101b and the wiring layer 105b together can be called the substrate 120b (or circuit layer). Furthermore, the semiconductor layer 101a and the wiring layer 105a, and the semiconductor layer 101b and the wiring layer 105a together can be called the substrate 120.

[0140] The semiconductor layer 101a has opposing surfaces S1a and S2a. Surface S2a is the surface opposite to surface S1a. Similarly, the semiconductor layer 101b has opposing surfaces S1b and S2b. Surface S2b is the surface opposite to surface S1b. Surface S2a of the semiconductor layer 101a is, for example, a light-receiving surface. Surfaces S1a and S1b are element-forming surfaces on which elements such as transistors and capacitive elements are formed. Gate electrodes, gate insulating films, etc., may be provided on surfaces S1a and S1b.

[0141] Each pixel P is provided with a photoelectric conversion unit 11 in the semiconductor layer 101a. Furthermore, on the surface S1a side of the semiconductor layer 101a, for example, the transistor TRG and floating diffusion FD1 described above are provided. Additionally, a separation region 17a is provided around each pixel P in the semiconductor layer 101a. The separation region 17a may be formed in a grid pattern in the semiconductor layer 101a, for example, surrounding each photoelectric conversion unit 11 of each pixel P.

[0142] At least some of the transistors (pixel transistors such as transistor AMP, transistor SEL, transistor FDG, or transistor RST) of the readout circuit 15 are provided on the surface S1b side of the semiconductor layer 101b. For example, as shown in the examples in Figures 15 and 16A, transistor AMP, transistor SEL, transistor FDG, and transistor RST are provided on the surface S1b side of the semiconductor layer 101b.

[0143] Furthermore, the semiconductor layer 101b is provided with a floating diffusion FD2, a semiconductor region 20, a semiconductor region 25, and an isolation region 17b. The isolation region 17b is provided, for example, around a plurality of pixels P, i.e., pixel units PU, which have an STI structure and share a readout circuit 15. The isolation region 17b may be formed in a grid pattern in the semiconductor layer 101b so as to surround the readout circuit 15 of each pixel unit PU.

[0144] The wiring layer 105a and the wiring layer 105b each include, for example, a conductive film and an insulating film, and have a plurality of wirings and a plurality of vias. Each of the wiring layer 105a and the wiring layer 105b has a configuration in which a plurality of wirings are laminated with an insulating film as an interlayer insulating film in between. The wiring layers 105a and 105b are each configured as multilayer wiring layers and may include two or more or three or more layers of wiring.

[0145] The FD wiring L1 is configured to include, for example, through electrodes 55 used for connecting circuits (elements) located on different layers. The through electrodes 55 are provided so as to penetrate the semiconductor layer 101b. Multiple through electrodes 55 are arranged in a manner corresponding to the number of signals to be transmitted between layers 201 and 202. The gate electrode 34 of the transistor AMP is electrically connected to the floating diffusion FD1 of the semiconductor layer 101a via the through electrodes 55.

[0146] The wiring L2 is provided within the isolation region 17b of the semiconductor layer 101b, for example, around the pixel unit PU. The wiring L2 is provided in contact with the semiconductor region 25, and a voltage VSS is applied to it. In this modified example, the same effects as in the above-described embodiment can be obtained. The imaging device 1 may have a structure in which three or four or more semiconductor layers are stacked.

[0147] <2. Second Embodiment> Next, a second embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0148] Figures 17, 18, and 19 are diagrams illustrating an example configuration of an imaging device according to a second embodiment of the present disclosure. Figure 17 shows an example of the circuit configuration of a pixel unit of the imaging device. The imaging device 1 may have a configuration in which, for example, a plurality of pixels P (a total of eight pixels, from pixels Pa to Ph in Figure 17) share one readout circuit 15.

[0149] Figure 18 shows an example of a planar configuration of an imaging device according to the second embodiment. Figure 19 shows an example of a cross-sectional configuration of an imaging device. Figures 17 and 18 show an example in which one readout circuit 15 is provided for a pixel unit PU containing eight pixels P. In addition, in the imaging device 1, a readout circuit 15 may be provided for each pixel P.

[0150] As described above, transistor FDG is a switching transistor and is electrically connected, for example, between the floating diffusion FD1 and transistor RST. Transistor FDG is electrically connected in series with transistor RST (i.e., the reset transistor), as shown in Figure 17.

[0151] Transistor FDG electrically connects or links floating diffusion FD1 and floating diffusion FD2. Transistor FDG is configured to electrically connect the capacitance C1 (i.e., Sub-FD capacitance) of floating diffusion FD2 to floating diffusion FD1.

[0152] In this embodiment, the imaging device 1 has wiring L2 as part of the floating diffusion FD2. The wiring L2 is configured such that at least a portion of it is located within the isolation region 17, as in the first embodiment. For example, at least a portion of the wiring L2 is located within a trench 18 of the isolation region 17 having an STI structure.

[0153] The wiring L2 is provided so as to be embedded in the trench 18 of the separation region 17. As described above, the wiring L2 is made of Poly-Si, a metal material, etc. For example, the wiring L2 may be made of n+ type Poly-Si. The conductive member wiring L2 may be made of a metal material or of silicide.

[0154] Wiring L2 is provided as sub-floating diffusion wiring (Sub-FD wiring). Wiring L2 is electrically connected to transistor FDG as part of floating diffusion FD2. Wiring L2 may also be electrically connected between transistor FDG and transistor RST.

[0155] One of the source and drain regions of transistor FDG, semiconductor region 42, is connected to wiring L1, which is FD wiring, and is electrically connected to floating diffusion FD1. The other of the source and drain regions of transistor FDG, semiconductor region 43a, is electrically connected to wiring L2, which is Sub-FD wiring.

[0156] The wiring L2 is provided in contact with the semiconductor region 43a within the isolation region 17, for example, as shown in the examples in Figures 18 and 19. The wiring L2 may be provided in contact with the semiconductor region 43a in the Y-axis direction (or X-axis direction) within the trench 18 of the isolation region 17. The wiring L2 has a side contact structure and is in contact with the side (side surface) of the semiconductor region 43a.

[0157] The wiring L2 may be provided in contact with the semiconductor region 43a of transistor FDG and the semiconductor region 43b of transistor RST. In the example shown in Figure 18, a portion of the wiring L2 is provided so as to be located between the semiconductor region 43a and the semiconductor region 43b. The wiring L2 is in contact with the semiconductor regions 43a and 43b within the trench 18 of the isolation region 17.

[0158] One of the source and drain regions of transistor RST, semiconductor region 43b, is electrically connected to wiring L2, which is a Sub-FD wiring. The other of the source and drain regions of transistor RST, semiconductor region 44, is electrically connected, for example, to a power line to which the power supply voltage VDD is supplied.

[0159] In the example shown in Figure 18, the wiring L2 is formed within the isolation region 17 so as to sandwich a part of the semiconductor region 43a of transistor FDG and a part of the semiconductor region 43b of transistor RST, respectively. The wiring L2 may also be provided within the trench 18 of the isolation region 17 so as to sandwich one of the parts of the semiconductor region 43a and the part of the semiconductor region 43b.

[0160] For example, the semiconductor region 43a of transistor FDG may be configured as the drain region of transistor FDG. Also, the semiconductor region 43b of transistor RST may be configured as the source region of transistor RST. Note that the semiconductor regions 43a and 43b connected to wiring L2 are also part of the floating diffusion FD2 and can be called the Sub-FD region.

[0161] The wiring L2 may be provided along at least one of transistor FDG and transistor RST. In each pixel unit PU (or pixel P) of the pixel unit 100, the wiring L2 may be formed to have a predetermined length, for example, between the photoelectric conversion unit 11 and the transistor of the readout circuit 15.

[0162] The wiring L2 is provided, for example, to extend in the Y-axis direction (or X-axis direction) when viewed in a plan view (i.e., in the XY plane). In the example shown in Figure 18, the wiring L2 is formed to follow the transistors FDG, RST, AMP, and SEL of the readout circuit 15 and has a shape that extends in the Y-axis direction. Note that the placement position and size of the wiring L2 are not limited to the illustrated example and can be set arbitrarily.

[0163] As described above, the imaging device 1 according to this embodiment has wiring L2 provided in the isolation region 17. The wiring L2 is electrically connected, for example, to the semiconductor region 43a of the transistor FDG. The wiring L2 can be used as a Sub-FD wiring, and the value of the capacitance C1, which is a Sub-FD capacitance, can be increased.

[0164] In the imaging device 1, the wiring L2, which is a Sub-FD wiring, is provided, which increases the size (capacitance value) of the Sub-FD capacitance added to the floating diffusion FD1 in low conversion gain mode. This ensures a sufficient capacitance value for the Sub-FD capacitance, making it possible to sufficiently reduce the conversion gain in low conversion gain mode.

[0165] By utilizing the wiring L2 provided within the isolation region 17 of the semiconductor layer 101, it is possible to prevent an increase in parasitic capacitance added to the wiring L1, which is the FD wiring of the wiring layer 105. This suppresses a decrease in conversion gain in high conversion gain mode and prevents an increase in random noise mixed into the pixel signal. This also improves the signal-to-noise ratio of the pixel signal.

[0166] According to the imaging device 1 of this embodiment, sufficient Sub-FD capacitance (capacitance C1) can be obtained while avoiding the addition of unnecessary parasitic capacitance to the FD wiring. In high conversion gain mode, the conversion gain can be made sufficiently high, and in low conversion gain mode, the conversion gain can be made sufficiently low. The imaging device 1 can improve FWC (Full Well Capacity) and make it possible to appropriately generate pixel signals according to the amount of light received.

[0167] In the imaging device 1, the wiring length, width, etc. of the wiring L2 can be changed by the layout of the separation region 17 and the wiring L2, and the capacitance C1 (Sub-FD capacitance) of the floating diffusion FD2 can be adjusted. This makes it possible to appropriately determine the conversion gain in low conversion gain mode.

[0168] Figures 20A to 20H show an example of a manufacturing method for an imaging device according to a second embodiment. As shown in Figure 20A, a hard mask 91 is formed on the semiconductor layer 101. Then, a trench 18 is formed by etching, and a member 92 (for example, SiO) is placed inside the trench 18. ２ By embedding (filling) a filling material such as a membrane, a separation region 17 having an STI structure is formed, as shown in Figure 20B.

[0169] Next, as shown in Figure 20C, the member 92 is etched (i.e., etched back) to form a region for the wiring L2 within the trench 18 of the separation region 17. Then, as shown in Figure 20D, a member 93 (for example, a Poly-Si film) is formed as the material for the wiring L2. Furthermore, as shown in Figure 20E, after etching (etching back) the members 92 and 93, the hard mask 91 is removed as shown in Figure 20F.

[0170] Next, as shown in Figure 20G, a gate electrode, a semiconductor region (i.e., a diffusion layer), etc., are formed on the surface S1 side of the semiconductor layer 101. Then, as shown in Figure 20H, a wiring layer 105 having wiring L1 and contacts, etc., is formed. By using the above manufacturing method, the imaging device 1 shown in Figure 19, etc., can be manufactured. Note that the above manufacturing method is merely an example, and other manufacturing methods may be used.

[0171] [Function and Effects] The photodetector according to this embodiment comprises a semiconductor layer (e.g., semiconductor layer 101), a photoelectric conversion element (photoelectric conversion unit 11), a pixel (pixel P) having a first floating diffusion (floating diffusion FD1), a first transistor (e.g., transistor FDG) provided on the first surface side of the semiconductor layer and electrically connected to the first floating diffusion, and a second transistor (transistor RST) provided on the first surface side of the semiconductor layer and capable of resetting the voltage of the first floating diffusion, an isolation region (isolation region 17) provided in the semiconductor layer, and a first wiring (wiring L2). The first transistor has a first semiconductor region (e.g., semiconductor region 42) provided in the semiconductor layer and electrically connected to the first floating diffusion, and a second semiconductor region (e.g., semiconductor region 43a) provided in the semiconductor layer. At least a part of the first wiring is provided in the isolation region and electrically connected to the second semiconductor region.

[0172] The photodetector (imaging device 1) according to this embodiment includes a transistor FDG (i.e., a switching transistor), an isolation region 17 provided in the semiconductor layer 101, and wiring L2. At least a portion of the wiring L2, which is a Sub-FD wiring, is provided within the isolation region 17 and is electrically connected to the semiconductor region 43a of the transistor FDG. This makes it possible to realize a photodetector that can suppress the degradation of signal quality.

[0173] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0174] (Modification 4) Figures 21, 22, and 23 are diagrams illustrating an example of the configuration of an imaging device according to Modification 4 of the present disclosure. Figure 21 shows an example of the circuit configuration of the pixel unit of the imaging device according to Modification 4. Figure 22 shows an example of the planar configuration of the imaging device. Figure 23 shows an example of the cross-sectional configuration of the imaging device.

[0175] The transistor FDG may be electrically connected in parallel with the transistor RST, as shown in the example in Figure 21. The imaging device 1 may have a configuration in which multiple pixels P, for example pixels Pa to Ph, share one readout circuit 15. Alternatively, one readout circuit 15 may be provided for each pixel P.

[0176] One of the source and drain regions of transistor FDG, semiconductor region 42, is electrically connected to wiring L2, which is a Sub-FD wiring. The other of the source and drain regions of transistor FDG, semiconductor region 43, is connected to wiring L1, which is an FD wiring, and is electrically connected to floating diffusion FD1.

[0177] The wiring L2 is provided in contact with the semiconductor region 42 within the isolation region 17, as shown in the examples in Figures 22 and 23. For example, the wiring L2 is provided in contact with the end face (side surface) of the semiconductor region 42 within the trench 18 of the isolation region 17. The imaging device 1 according to this modified example also provides the same effects as the embodiment described above.

[0178] (Modification 5) Figures 24, 25, and 26 are diagrams illustrating an example of the configuration of the imaging device according to Modification 5. Figure 24 shows an example of the circuit configuration of the pixel unit of the imaging device according to Modification 5. Figure 25 shows an example of the planar configuration of the imaging device. Figure 26 shows an example of the cross-sectional configuration of the imaging device.

[0179] The imaging device 1 may be configured such that multiple pixel units PU (or multiple pixels P) share wiring L2. For example, as shown in the examples in Figures 24 and 25, two adjacent pixel units PU are configured to share wiring L2 and capacitance C1. Other pixel units PU of the pixel section 100 may also have the configurations shown in Figures 24 and 25.

[0180] In the example shown in Figure 25, the wiring L2 is provided to extend in the Y-axis direction, corresponding to multiple adjacent pixel units PU in the Y-axis direction. By configuring the imaging device 1 as shown in the example in Figure 25, the capacitance value of the Sub-FD capacitance C1 can be increased. This makes it possible to achieve a lower conversion gain in the low conversion gain mode.

[0181] Furthermore, a common wiring L2 may be provided for two or more pixel units PU. Also, a common wiring L2 may be provided for two or more pixels P. Transistor FDG may be electrically connected in series with transistor RST, or electrically connected in parallel with transistor RST.

[0182] (Modification 6) Figures 27 to 31 are diagrams illustrating an example of the configuration of an imaging device according to Modification 6. The readout circuit 15 may have a plurality of transistors FDG (in the example shown in Figures 27 to 31, transistors FDG1, FDG2) and a plurality of floating diffusion FD2 (in Figures 27 to 31, floating diffusion FD2a, FD2b).

[0183] Transistors FDG1 and FDG2 may be connected in series with transistor RST, or in parallel with transistor RST. Transistor FDG2 may be connected in series with transistor FDG1, or in parallel with transistor FDG1.

[0184] Transistor FDG1 is configured to electrically connect, for example, the capacitance C1a (i.e., Sub-FD capacitance) of floating diffusion FD2a to floating diffusion FD1. Transistor FDG1 is controlled by signal SFDG1 to electrically connect or disconnect floating diffusion FD1 and floating diffusion FD2a.

[0185] The transistor FDG2 is configured to electrically connect, for example, the capacitance C1b (i.e., the Sub-FD capacitance) of floating diffusion FD2b to floating diffusion FD1 (or FD2a). The transistor FDG2 is controlled by the signal SFDG2 to electrically connect or disconnect floating diffusion FD1 (or FD2a) and floating diffusion FD2b.

[0186] In imaging device 1, for example, when transistor FDG1 is in the off state, floating diffusion FD1 and floating diffusion FD2a are electrically disconnected. In this case, the pixel unit PU has a conversion gain of "high". Imaging device 1 has a high conversion gain mode (HCG setting).

[0187] When transistor FDG1 is ON and transistor FDG2 is OFF, floating diffusion FD1 and floating diffusion FD2a are electrically connected. In this case, the conversion gain is lower than in the HCG setting, and the pixel unit PU has a "medium" conversion gain. The imaging device 1 has a medium conversion gain mode which is the medium conversion gain setting (MCG setting).

[0188] When both transistor FDG1 and transistor FDG2 are ON, floating diffusion FD1, floating diffusion FD2a, and floating diffusion FD2b are electrically connected. In this case, the conversion gain is lower than in the MCG setting, and the pixel unit PU is in a "low" conversion gain state. The imaging device 1 has a low conversion gain mode which is a low conversion gain setting (LCG setting).

[0189] As shown in Figure 27 and other figures, the imaging device 1 has wiring L2a for a floating diffusion FD 2a which is a Sub-FD wiring, and wiring L2b for a floating diffusion FD 2b which is a Sub-FD wiring. Wiring L2a may be provided within the isolation region 17, or wiring L2b may be provided within the isolation region 17.

[0190] The readout circuit 15 may have three or more transistors FDG and three or more floating diffusion FD2. In this modified example, it is possible to realize three or more conversion gain modes. In addition, only some of the Sub-FD wirings among the multiple Sub-FD wirings may be provided in the isolation region 17. For example, only one of wiring L2a and wiring L2b may be placed in the isolation region 17. (Modification 7) Figures 32 and 33 are diagrams for illustrating an example of the configuration of an imaging device according to Modification 7. Figure 32 shows an example of the circuit configuration of a pixel in the imaging device according to Modification 7. Figure 33 shows an example of the planar configuration of the imaging device. As shown in the examples in Figures 32 and 33, one readout circuit 15 may be provided for one pixel P.

[0191] Figures 34 and 35 illustrate another configuration example of the imaging device according to Modification 7. Transistor FDG may be electrically connected in parallel with transistor RST. In this modification as well, the same effects as in the above-described embodiment can be obtained. Note that pixel P may have multiple transistors FDG and multiple floating diffusion FD2.

[0192] (Modification 8) Figures 36, 37A, and 37B are diagrams illustrating an example of the configuration of an imaging device according to Modification 8. The imaging device 1 may have a plurality of semiconductor layers 101 (in the example shown in Figure 36, etc., semiconductor layer 101a and semiconductor layer 101b). For example, each circuit element of the pixel P is provided on semiconductor layer 101a and semiconductor layer 101b.

[0193] The wiring L2 is provided as a Sub-FD wiring in the isolation region 17b of the semiconductor layer 101b. For example, the wiring L2 is provided in contact with the semiconductor region 43a of transistor FDG and the semiconductor region 43b of transistor RST. In this modified example, the same effects as in the above-described embodiment can be obtained. The imaging device 1 may have a structure in which three or four or more semiconductor layers are stacked.

[0194] <3. Third Embodiment> Next, a third embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0195] Figures 38, 39, 40A, and 40B are diagrams illustrating an example configuration of an imaging device according to a third embodiment of the present disclosure. Figure 38 shows an example of the circuit configuration of a pixel unit of the imaging device. Figure 39 shows an example of the planar configuration of the imaging device. Figure 40A shows an example of the cross-sectional configuration in the direction of the line A-A' shown in Figure 39. Figure 40B shows an example of the cross-sectional configuration in the direction of the line B-B' shown in Figure 39.

[0196] Figures 38 and 39 show an example where a readout circuit 15 is provided for each pixel unit PU. In the imaging device 1, a readout circuit 15 may be provided for each pixel P. Transistor FDG may be connected in series with transistor RST, or it may be connected in parallel with transistor RST.

[0197] The imaging device 1 has wiring L2 as sub-floating diffusion wiring (Sub-FD wiring), similar to the second embodiment and its modified form described above. For example, the wiring L2 is provided in contact with the semiconductor region 43a of transistor FDG and the semiconductor region 43b of transistor RST. The arrangement of wiring L2 is not limited to the illustrated example and can be changed as appropriate.

[0198] The imaging device 1 according to this embodiment has wiring L3 in addition to wiring L2 (i.e., Sub-FD wiring), as shown in the example in Figure 39, etc. The wiring L3 is configured such that at least a portion of it is provided around the wiring L2. As an example, the wiring L3 is made of Poly-Si (polysilicon). The wiring L3 may be made of a metallic material or other material.

[0199] Wiring L3 is provided, for example, with a predetermined potential (voltage) and is located around wiring L2 as a Sub-FD wiring. Wiring L3 is positioned adjacent to wiring L2 such that a capacitance is formed between wiring L2 and wiring L3. Wiring L3 is provided along wiring L2 via an insulating film 39, as in the example shown in Figure 40B. As an example, a portion of wiring L3 is provided on top of wiring L2 via the insulating film 39.

[0200] The wiring L3 is provided around the wiring L2, facing the wiring L2. For example, the wiring L3 is provided adjacent to the wiring L2 in the thickness direction (i.e., the Z-axis direction) of the wiring layer 105. As shown in the examples in Figures 39 and 40B, at least a portion of the wiring L3 is provided to be laminated with the wiring L2. The wiring L3 may be formed to cover at least a portion of the wiring L2.

[0201] The wiring L3 is provided, for example, on the surface S1 side of the semiconductor layer 101 and is located above the wiring L2. The wiring L3 is provided so as to overlap at least a portion of the wiring L2. In the wiring layer 105, for example, the wiring L3 extends in the Y-axis direction (or X-axis direction) along the wiring L2 and is provided so as to face the wiring L2 in the Z-axis direction. The wiring L3 may also be arranged so as to be adjacent to the wiring L2 in the X-axis direction or the Y-axis direction.

[0202] Sub-FD wiring L2 and wiring L3 may be provided side by side. At least a portion of wiring L3 may be provided within the trench 18 of the separation region 17. Wiring L3 is configured as a conductive member (conductor) to which a predetermined potential is applied. Wiring L3 is supplied with a constant potential by, for example, the wiring and electrodes of the wiring layer 105.

[0203] The wiring L3 is electrically connected to, for example, the semiconductor region 25 (i.e., the well contact region). A voltage VSS (e.g., 0V) is applied to the wiring L3, for example, via the semiconductor region 25 and the contact 51. The wiring L3 may be electrically connected to the semiconductor region 25 via the wiring of the wiring layer 105 and the contact 53, etc., as shown in the example in Figure 40A. Alternatively, the wiring L3 may be provided to be directly connected to the semiconductor region 25.

[0204] The floating diffusion FD2 has a capacitance C1 as a Sub-FD capacitance, which is configured using wiring L2 and wiring L3. Capacitance C1 includes, for example, at least a portion of wiring L2 and at least a portion of wiring L3, and is configured as a wiring capacitance. Capacitance C1 has, for example, an insulating film 39 provided between wiring L3 and wiring L2. In the example shown in Figure 40B, wiring L3 and wiring L2 are stacked with the insulating film 39 in between.

[0205] Wiring L3 is constructed using Poly-Si, a metal material, or the like. Wiring L3 may be constructed using, for example, n+ type Poly-S. Wiring L3 may also be constructed using p+ type Poly-Si. Wiring L3, which is a conductive member (conductor), may be constructed using a metal material such as Al, or it may be constructed using silicide. Wiring L3 and wiring L2 may be constructed using different materials, or they may be constructed using the same type of material.

[0206] The wiring L3 may be constructed using the same material (e.g., polysilicon) as the gate electrode of the transistor of the pixel P, for example, the gate electrode 31 of transistor TRG. The insulating film 39 may be made of, for example, silicon oxide (SiO2). ２ It is constructed using insulating materials such as ). The insulating film 39 may be formed using a high dielectric constant material. The insulating film 39 may be constructed using the same material as the gate insulating film of the transistor of the pixel P, for example, the gate insulating film 38.

[0207] In the imaging device 1 according to this embodiment, a capacitance C1 formed by wiring L2 and wiring L3 is added to the floating diffusion FD2 as a Sub-FD capacitance. Capacitance C1 includes, for example, wiring capacitances having a part of wiring L2 and a part of wiring L3 as electrodes. The value of capacitance C1, which is a Sub-FD capacitance, can be increased, making it possible to obtain a sufficiently low conversion gain (conversion efficiency) in the low conversion gain mode.

[0208] In the imaging device 1, the capacitance C1 (Sub-FD capacitance) of the floating diffusion FD2 can be adjusted by the layout of the wiring L2 and L3 (for example, the length of the wiring, the width of the wiring, the position of the wiring, etc.). This makes it possible to appropriately set the conversion gain in low conversion gain mode. This improves the FWC (Full Well Capacity), making it possible to obtain, for example, high-resolution images.

[0209] [Function and Effects] The photodetector according to this embodiment comprises a photoelectric conversion element, a pixel having a first floating diffusion (floating diffusion FD1) and a first transistor (e.g., transistor FDG), an isolation region (isolation region 17) provided in a semiconductor layer, a first wiring (wiring L2), and a second wiring (wiring L3) to which a predetermined potential is applied. The first transistor has a first semiconductor region (e.g., semiconductor region 42) and a second semiconductor region (e.g., semiconductor region 43a). At least a portion of the first wiring is provided within the isolation region and is electrically connected to the second semiconductor region. At least a portion of the second wiring is provided around the first wiring (wiring L2).

[0210] The photodetector (imaging device 1) according to this embodiment further includes wiring L3 to which a predetermined potential is applied. At least a portion of wiring L3 is provided around wiring L2 as a Sub-FD wiring. Therefore, the Sub-FD capacitance can be increased. This makes it possible to realize a photodetector that can suppress the degradation of signal quality.

[0211] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0212] (Modification 9) Figure 41 is a diagram illustrating an example of the configuration of an imaging device according to Modification 9 of the present disclosure. The imaging device 1 may have a connection region 26, as shown in the example in Figure 41. The connection region 26 is provided, for example, on the surface S1 side of the semiconductor layer 101, adjacent to the semiconductor region 25. At least a part of the connection region 26 is provided so as to be in contact with the semiconductor region 25.

[0213] The connection region 26 is composed of, for example, polysilicon doped with impurities. The connection region 26 is composed of, as an example, p-type or p+-type polysilicon. The connection region 26 contains a high concentration of impurities and can be configured as a conductive region (conductive part). The connection region 26 may also be composed of other conductive materials (e.g., metallic materials).

[0214] The connection region 26 has, for example, a side contact structure and is provided in contact with the side (side) of the semiconductor region 25. In the example shown in Figure 41, a portion of the wiring L3 is located on the connection region 26 provided on the semiconductor layer 101 and is connected to the connection region 26. The wiring L3 is electrically connected to the semiconductor region 25 via the connection region 26.

[0215] (Modification 10) Figures 42 and 43 are diagrams illustrating an example of the configuration of an imaging device according to Modification 10. Figure 42 shows an example of the planar configuration of the imaging device. Figure 43 shows an example of the cross-sectional configuration in the direction of the line C-C' shown in Figure 42. The imaging device 1 may be configured such that the wiring L2 as Sub-FD wiring and the wiring L3 located around wiring L2 have different lengths from each other.

[0216] As shown in the example in Figure 42, for example, the length of wiring L3 in the Y-axis direction may be shorter than the length of wiring L2, which is a Sub-FD wiring, in the Y-axis direction. A voltage VSS (e.g., 0V) is applied to wiring L3 via contact 53 and wiring, as an example, as shown in Figure 43. In the imaging device 1, the capacitance value of capacitance C1, which is a Sub-FD capacitance, can be adjusted by adjusting the lengths of wiring L2 and wiring L3.

[0217] (Modification 11) Figures 44 and 45 are diagrams illustrating an example of the configuration of an imaging device according to Modification 11. Figure 44 shows an example of a planar configuration of the imaging device. Figure 45 shows an example of a cross-sectional configuration in the direction of the line C-C' shown in Figure 44. The imaging device 1 may have contacts 54 connected to the floating diffusion FD2.

[0218] In the example shown in Figure 44, the wiring L2, which is a Sub-FD wiring, is provided in contact with the semiconductor region 43a of transistor FDG and the semiconductor region 43b of transistor RST. The contact 54 may, for example, be provided with respect to the semiconductor region 43b of transistor RST, as shown in Figure 45.

[0219] The contact 54 may be provided on the semiconductor region 43a of the transistor FDG. The contact 54 may also be provided on the region of the wiring L2 located between the semiconductor region 43a and the semiconductor region 43b. The capacitance formed by the contact 54 and the wiring connected to the contact 54 (for example, wiring capacitance) can be added to the floating diffusion FD2 as capacitance C1 (Sub-FD capacitance).

[0220] (Modification 12) Figures 46 and 47 are diagrams illustrating an example of the configuration of an imaging device according to Modification 12. Figure 46 shows an example of a planar configuration of the imaging device. Figure 47 shows an example of a cross-sectional configuration in the direction of the line B-B' shown in Figure 46. Wiring L2 and wiring L3 may be provided so as to partially overlap each other. The imaging device 1 may be configured such that wiring L2 and wiring L3 have different widths from each other.

[0221] The wiring L3 is formed such that, for example, a portion of the wiring L3 faces a portion of the wiring L2 via an insulating film 39. The wiring L3 may be provided so as to cover a portion of the wiring L2 via the insulating film 39. By configuring the imaging device 1 in this way, the capacitance value of the capacitance C1 added to the floating diffusion FD2 can be adjusted.

[0222] (Modification 13) Figures 48 and 49 are diagrams illustrating an example of the configuration of an imaging device according to Modification 13. Figure 48 shows an example of a planar configuration of the imaging device. Figure 49 shows an example of a cross-sectional configuration in the direction of the line B-B' shown in Figure 48. The wiring L3 may be provided such that at least a portion of the wiring L3 is located within the wiring L2. At least a portion of the wiring L3 may be formed within the wiring L2 provided in the trench 18 of the separation region 17.

[0223] In the example shown in Figure 49, a portion of each of the wiring L3 and the insulating film 39 is provided within the wiring L2 of the isolation region 17. A portion of the wiring L3 is arranged to be embedded within the wiring L2. The wiring L2, which is a Sub-FD wiring, is configured to have a concave shape. By configuring the imaging device 1 in this way, the area of ​​the region where the wiring L2 and wiring L3 face each other can be increased, making it possible to increase the Sub-FD capacitance.

[0224] (Modification 14) Figure 50 is a diagram illustrating an example of the configuration of an imaging device according to Modification 14. As shown in the example in Figure 50, wiring L3 and wiring L2 may be provided between the photoelectric conversion unit 11 and the transistor of the readout circuit 15, respectively. For example, wiring L3 may be provided so as to surround the area of ​​the pixel transistor of the readout circuit 15.

[0225] In the example shown in Figure 50, the wiring L3 is provided so as to surround a plurality of pixel transistors of the readout circuit 15, such as transistor FDG, transistor RST, transistor AMP, and transistor SEL. According to the imaging device 1 of this modified example, it is possible to increase the value of the capacitance C1 formed as a Sub-FD capacitance.

[0226] <4. Fourth Embodiment> Next, a fourth embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0227] Figures 51, 52A, and 52B are diagrams illustrating an example configuration of an imaging device according to a fourth embodiment of the present disclosure. Figure 51 shows an example of a planar configuration of the imaging device. Figure 52A shows an example of a cross-sectional configuration in the direction of line A-A' shown in Figure 51. Figure 52B shows an example of a cross-sectional configuration in the direction of line B-B' shown in Figure 51.

[0228] Figures 51 and 52A show an example where a readout circuit 15 is provided for each pixel unit PU containing eight pixels P. Transistor FDG may be electrically connected in parallel with transistor RST, or electrically connected in series with transistor RST. In addition, in the imaging device 1, a readout circuit 15 may be provided for each pixel P.

[0229] The imaging device 1 has wiring L2 as sub-floating diffusion wiring (Sub-FD wiring), similar to the second and third embodiments described above. As an example, wiring L2 is provided in contact with the semiconductor region 43a of transistor FDG and the semiconductor region 43b of transistor RST. The arrangement of wiring L2 is not limited to the illustrated example and can be changed as appropriate.

[0230] Furthermore, the imaging device 1 has wiring L3, similar to the third embodiment. In this embodiment, the wiring L3 is configured such that at least a portion of it is provided within the isolation region 17. For example, at least a portion of the wiring L3 is provided within the trench 18 of the isolation region 17 having an STI structure. The wiring L3 may be provided so as to be embedded within the trench 18 of the isolation region 17.

[0231] The wiring L3 is provided along the wiring L2 via an insulating film 39, for example, as shown in the example in Figure 52B. The wiring L3 is positioned opposite the wiring L2 within the isolation region 17 so that a capacitance is formed between the wiring L2 and the wiring L3. At least a portion of the wiring L3 is provided in the isolation region 17 of the semiconductor layer 101 so as to cover the periphery of the wiring L2 via the insulating film 39.

[0232] For example, a portion of the wiring L3 is provided to extend in the Y-axis direction along the wiring L2 within the trench 18 of the isolation region 17. In the example shown in Figure 52B, at least a portion of the wiring L2 and the insulating film 39 are formed within the wiring L3 provided in the trench 18 of the isolation region 17. A portion of each of the wiring L2 and the insulating film 39 is arranged to be embedded within the wiring L3.

[0233] A predetermined potential is supplied to wiring L3, which is provided around wiring L2, which is a Sub-FD wiring, by, for example, the wiring and electrodes of wiring layer 105. Wiring L3 is electrically connected to one or more contacts 52 provided on wiring layer 105, as an example. Wiring L3 is supplied with a voltage VSS (e.g., 0V) as a reference potential via the contacts 52.

[0234] In the imaging device 1, a capacitance C1 formed by wiring L2 and wiring L3 is added to the floating diffusion FD2 as a Sub-FD capacitance. Capacitance C1 includes, for example, wiring capacitance having a part of wiring L2 and a part of wiring L3. The value of capacitance C1 as a Sub-FD capacitance can be increased, making it possible to obtain a sufficiently low conversion gain in low conversion gain mode.

[0235] In this embodiment, by utilizing the wiring L3 provided within the isolation region 17 of the semiconductor layer 101, it is possible to improve the flexibility of the layout of other wiring. Furthermore, it is possible to obtain sufficient Sub-FD capacitance (capacitance C1) while avoiding the addition of unnecessary parasitic capacitance to the FD wiring L1. It is possible to make the conversion gain sufficiently high in high conversion gain mode and sufficiently low in low conversion gain mode.

[0236] [Function and Effects] The photodetector according to this embodiment comprises a photoelectric conversion element, a pixel having a first floating diffusion (floating diffusion FD1) and a first transistor (e.g., transistor FDG), an isolation region (isolation region 17) provided in a semiconductor layer, a first wiring (wiring L2), and a second wiring (wiring L3) to which a predetermined potential is applied. The first transistor has a first semiconductor region (e.g., semiconductor region 42) and a second semiconductor region (e.g., semiconductor region 43a). At least a portion of the first wiring is provided within the isolation region and is electrically connected to the second semiconductor region. At least a portion of the second wiring is provided around the first wiring (wiring L2) within the isolation region.

[0237] The photodetector (imaging device 1) according to this embodiment includes wiring L3 to which a predetermined potential is applied. At least a portion of wiring L3 is provided around wiring L2 as Sub-FD wiring within the isolation region 17. Therefore, the Sub-FD capacitance can be increased. This makes it possible to realize a photodetector that can suppress the degradation of signal quality.

[0238] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0239] (Modification 15) Figures 53 and 54 are diagrams illustrating an example of the configuration of an imaging device according to Modification 15 of the present disclosure. Figure 53 shows an example of a planar configuration of the imaging device. Figure 54 shows an example of a cross-sectional configuration in the direction of the line B-B' shown in Figure 53. The wiring L3 may be provided in contact with the semiconductor region 25 within the isolation region 17 of the semiconductor layer 101.

[0240] The wiring L3 may be provided within the trench 18 of the isolation region 17, in contact with the semiconductor region 25 in the X-axis direction (or Y-axis direction). In the example shown in Figures 53 and 54, the wiring L3 has a side contact structure and is in contact with the side (surface) of the semiconductor region 25. A voltage VSS (e.g., 0V) is applied to the wiring L3 via the semiconductor region 25 and the contact 51. The wiring L3 may also be provided on the surface S1 side of the semiconductor layer 101 so as to cover a portion of the semiconductor region 25.

[0241] (Modification 16) Figures 55 and 56 are diagrams illustrating an example of the configuration of an imaging device according to Modification 16. Figure 55 shows an example of a planar configuration of the imaging device. Figure 56 shows an example of a cross-sectional configuration in the direction of the line B-B' shown in Figure 55. The imaging device 1 may have a contact 54 connected to the floating diffusion FD2.

[0242] In the imaging device 1, for example, one or more contacts 54 are provided in the wiring layer 105 for the wiring L2 of the floating diffusion FD2. The capacitance formed by the contacts 54 and the wiring connected to the contacts 54 can be added to the floating diffusion FD2 as capacitance C1 (Sub-FD capacitance).

[0243] The imaging device 1 may have one or more contacts 52 connected to the wiring L3, as shown in the example in Figure 57. The contacts 52 are provided on the surface S1 side of the semiconductor layer 101 and are connected to the wiring L3 provided in the isolation region 17. A predetermined potential is applied to the contacts 52 via the wiring of the wiring layer 105 or the like.

[0244] In the imaging device 1, for example, as shown in Figure 57, one or more contacts 52 are arranged at the boundary between multiple adjacent pixel units PU (or pixels P). The contacts 52 can be used as shielding parts (shielding members), which can reduce unnecessary coupling capacitance. This makes it possible to suppress crosstalk.

[0245] (Modification 17) Figures 58 and 59 are diagrams illustrating an example of the configuration of an imaging device according to Modification 17. Figure 58 shows an example of the planar configuration of the imaging device. Figure 59 shows an example of the cross-sectional configuration in the direction of the line B-B' shown in Figure 58. Wiring L2 and wiring L3 may be arranged adjacent to each other in the X-axis direction (or Y-axis direction) in the separation region 17.

[0246] The wiring L3 is provided, for example, as shown in the example in Figure 59, via an insulating film 39, so as to face the wiring L2 in the X-axis direction (or Y-axis direction). The wiring L3 extends along the wiring L2 within the trench 18 of the separation region 17 and is provided so as to sandwich a part of the wiring L2. In this modified example, the same effects as in the embodiment described above can be obtained.

[0247] <5. Fifth Embodiment> Next, a fifth embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0248] Figures 60, 61, 62A, and 62B are diagrams illustrating an example configuration of an imaging device according to a fifth embodiment of the present disclosure. Figure 60 shows an example of the circuit configuration of a pixel unit of the imaging device. Figure 61 shows an example of the planar configuration of the imaging device. Figure 62A shows an example of the cross-sectional configuration in the direction of the line A-A' shown in Figure 61. Figure 62B shows an example of the cross-sectional configuration in the direction of the line B-B' shown in Figure 61.

[0249] Figures 60 and 61, etc., show an example in which a readout circuit 15 is provided for each pixel unit PU containing eight pixels P. Transistor FDG may be electrically connected in parallel with transistor RST, or electrically connected in series with transistor RST. In the imaging device 1, a readout circuit 15 may be arranged for each pixel P.

[0250] In the imaging device 1 according to this embodiment, the wiring L2 is provided as wiring that can be used for potential control of the FD. The wiring L2 is provided around the transistor AMP and transistor SEL, for example, as will be described later, so that a capacitance (i.e., coupling capacitance) is formed between the FD and the transistor SEL. The wiring L2 is made of a conductive material (conductor), such as polysilicon or a metal material, as described above.

[0251] In the imaging device 1, at least a portion of the wiring L2 is provided around the gate electrode 35 of the transistor SEL in the isolation region 17 of the semiconductor layer 101. The wiring L2 is arranged, for example, within a trench 18 of the isolation region 17, adjacent to the gate electrode 35 of the transistor SEL. The wiring L2 may be formed to face a portion of the gate electrode 35 of the transistor SEL.

[0252] The wiring L2 may be provided within the trench 18 of the isolation region 17 such that at least a portion of the wiring L2 runs along the bottom (lower part) of the gate electrode 35 of the transistor SEL. The wiring L2 is configured such that a portion of it faces the end face (bottom face) of the gate electrode 35 of the transistor SEL. The gate electrode 35 of the transistor SEL is provided so as to overlap a portion of the wiring L2.

[0253] Furthermore, in the imaging device 1, at least the remaining portion of the wiring L2 is provided in the isolation region 17 around the gate electrode 34 of the transistor AMP. For example, the wiring L2 is positioned within the trench 18 of the isolation region 17, adjacent to the gate electrode 34 of the transistor AMP. The wiring L2 may be formed to face a portion of the gate electrode 35 of the transistor AMP.

[0254] The wiring L2 may be provided within the trench 18 of the isolation region 17 such that at least a portion of the wiring L2 lies along the bottom of the gate electrode 34 of the transistor AMP. The wiring L2 is configured such that a portion of it faces the end face (bottom face) of the gate electrode 34 of the transistor AMP. The gate electrode 34 of the transistor AMP is provided so as to overlap with the other portion of the wiring L2.

[0255] The wiring L2 may extend from the region below the gate electrode 35 of transistor SEL to the region below the gate electrode 34 of transistor AMP. The wiring L2 may be arranged adjacent to the gate electrode 35 (or gate electrode 34) in the X-axis or Y-axis direction. The wiring L2 is electrically connected to the gate electrode 35 of transistor SEL or the gate electrode 34 of transistor AMP.

[0256] The wiring L2 is electrically connected, for example, to the gate electrode 35 of the transistor SEL. In the example shown in Figures 62A and 62B, a portion of the wiring L2 is provided in contact with the gate electrode 35 of the transistor SEL. A portion of the wiring L2 (for example, one end of the wiring L2) is located below the gate electrode 35 of the transistor SEL and is connected to the gate electrode 35.

[0257] Furthermore, another portion of the wiring L2 (for example, the other end of the wiring L2) is located near the gate electrode 34 of the transistor AMP. The other portion of the wiring L2 is positioned, for example, facing the lower surface (bottom surface) of the gate electrode 34, so that a capacitance is formed between the gate electrode 34 and the wiring L2. The wiring L2 is provided along the gate electrode 34 of the transistor AMP via an insulating film, for example, a gate insulating film 38.

[0258] In the imaging device 1, as described above, the wiring L2 is provided, and a capacitance C2 is added between the gate of transistor AMP and the gate of transistor SEL, as schematically shown by the dashed line in Figure 62B. The capacitance C2 is formed, for example, as a coupling capacitance by the wiring L2 provided around the gate electrodes 34 and 35, an insulating film (for example, gate insulating film 38), etc.

[0259] Each pixel P readout circuit 15 has a capacitance C2 configured using wiring L2, as described above. Capacitor C2 is connected between the gate node of transistor SEL and the gate node of transistor AMP (i.e., floating diffusion FD1). The value of capacitance C2 (capacitance value) can be adjusted by the length and width of wiring L2.

[0260] One end of capacitor C2 is electrically connected to a wiring L1 connected to the gate electrode 34 of transistor AMP, for example, and to a semiconductor region 41 acting as a floating diffusion FD1. The other end of capacitor C2 is electrically connected to a wiring connected to the gate electrode 35 of transistor SEL, that is, to a wiring that transmits the signal SSEL, which is the control signal of transistor SEL.

[0261] The pixel control unit 111 and control unit 113 (see Figure 1) of the imaging device 1 are configured to utilize capacitive coupling between the gate of transistor SEL and floating diffusion FD1, and to supply a voltage corresponding to the voltage (signal level) of signal SSEL to floating diffusion FD1 via capacitor C2.

[0262] When the floating diffusion FD1 is electrically floating, the potential of the floating diffusion FD changes due to capacitive coupling by capacitor C2, depending on the voltage (potential) applied to the gate of transistor SEL. For example, the potential of the floating diffusion FD1 can be changed according to the change in voltage across wiring L2 and the capacitance value of capacitor C2.

[0263] The pixel control unit 111 is configured to perform control (i.e., SEL boost) that increases the voltage of the floating diffusion FD1 in accordance with the signal SSEL supplied to the gate of the transistor SEL, for example, by utilizing the capacitance C2. The FD potential, which is stepped down by the reset feedthrough, can be boosted by the SEL boost. This makes it possible to suppress a decrease in the amount of charge that can be stored.

[0264] Figure 63 is a diagram illustrating an example of operation of an imaging device according to the fifth embodiment. In Figure 63, the signal SSEL input to the gate of transistor SEL, the signal SRST input to the gate of transistor RST, and the signal STRG input to transistor TRG are shown on the same time axis.

[0265] The pixel control unit 111 is configured to perform control that transitions the voltage of the signal SRST from a high level to a low level, and then transitions the voltage of the signal SSEL from a low level to a high level, as shown in the example in Figure 63 (in the example in Figure 63, time t1 to time t2). This makes it possible to boost the voltage of the floating diffusion FD1, which has been stepped down (reduced) by the reset feedthrough, by the SEL boost.

[0266] According to the imaging device 1 of this embodiment, it is possible to suppress the decrease in the amount of charge that can be stored in the floating diffusion FD1 due to reset feedthrough. It is possible to appropriately transfer charge from the photoelectric conversion unit 11 to the floating diffusion FD1 and obtain a pixel signal corresponding to the amount of light received.

[0267] In the imaging device 1, by utilizing the wiring L2 provided within the separation region 17, it is possible to increase the capacitance C2 between the gate of transistor SEL and the floating diffusion FD1 while suppressing an increase in parasitic capacitance between the gate of transistor SEL and the signal line VSL. This makes it possible to suppress characteristic deterioration such as streaking.

[0268] [Function and Effects] The photodetector according to this embodiment comprises a semiconductor layer (e.g., semiconductor layer 101), a photoelectric conversion element (photoelectric conversion unit 11), a pixel (pixel P) having a floating diffusion (floating diffusion FD1), a first transistor (e.g., transistor SEL) provided on the first surface side of the semiconductor layer and capable of outputting a first signal based on the charge accumulated in the floating diffusion, an isolation region (isolation region 17) provided in the semiconductor layer, and a first wiring (wiring L2). The first transistor has a first gate electrode (e.g., gate electrode 35). At least a portion of the first wiring is provided around the first gate electrode within the isolation region.

[0269] The photodetector (imaging device 1) according to this embodiment includes a pixel P having a transistor SEL provided on the surface S1 side of the semiconductor layer 101, an isolation region 17 provided on the semiconductor layer 101, and wiring L2. The transistor SEL has a gate electrode 35. At least a portion of the wiring L2 is provided around the gate electrode 35 within the isolation region 17. Therefore, it is possible to realize a photodetector capable of suppressing a decrease in signal quality.

[0270] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0271] (Modification 18) Figures 64, 65A, and 65B are diagrams illustrating an example of the configuration of an imaging device according to Modification 18 of the present disclosure. Figure 64 shows an example of a planar configuration of the imaging device. Figure 65A shows an example of a cross-sectional configuration in the direction of the line A-A' shown in Figure 64. Figure 65B shows an example of a cross-sectional configuration in the direction of the line B-B' shown in Figure 64.

[0272] As shown in the example in Figure 64, the wiring L2 may be provided on both sides (both ends) of the transistor SEL and transistor AMP. In the example shown in Figure 64, the imaging device 1 has, for each pixel unit PU (or pixel P), wiring L2 (wiring L2a) provided on the left side of the transistor SEL and AMP, and wiring L2 (wiring L2b) provided on the right side of the transistor SEL and AMP.

[0273] (Modification 19) Figures 66 and 67A to 67C are diagrams illustrating an example of the configuration of an imaging device according to Modification 19. Figure 66 shows an example of a planar configuration of the imaging device. Figure 67A shows an example of a cross-sectional configuration in the direction of the line A-A' shown in Figure 66. Figure 67B shows an example of a cross-sectional configuration in the direction of the line B-B' shown in Figure 66. Figure 67C also shows an example of a cross-sectional configuration in the direction of the line C-C' shown in Figure 66.

[0274] The wiring L2 may be electrically connected to the gate electrode 34 of the transistor AMP, which is one of the transistors SEL and AMP. For example, a portion of the wiring L2 is provided in contact with the gate electrode 34 of the transistor AMP. A portion of the wiring L2 (for example, one end of the wiring L2) is located below the gate electrode 34 of the transistor AMP and is connected to the gate electrode 34.

[0275] Furthermore, another portion of the wiring L2 (for example, the other end of the wiring L2) is provided so as to be located near the gate electrode 35 of the transistor SEL. The other portion of the wiring L2 is positioned, for example, opposite the lower surface (bottom surface) of the gate electrode 35 so that a capacitance is formed between the gate electrode 35 and the wiring L2. The wiring L2 is provided along the gate electrode 35 of the transistor SEL via an insulating film, for example, a gate insulating film 38.

[0276] The imaging device 1 may have a wiring L2 (wiring L2a) electrically connected to the gate electrode 34 of the transistor AMP, and a wiring L2 (wiring L2b) electrically connected to the gate electrode 35 of the transistor SEL, as shown in the example in Figure 66, etc. Wirings L2a and L2b are provided, for example, for each pixel unit PU (or pixel P). Wiring L2a may be electrically connected to the gate electrode 35, and wiring L2b may be electrically connected to the gate electrode 34.

[0277] (Modification 20) Figures 68 and 69A to 69D are diagrams illustrating an example of the configuration of an imaging device according to Modification 20. Figure 68 shows an example of a planar configuration of the imaging device. Figure 69A shows an example of a cross-sectional configuration in the direction of line A-A' shown in Figure 68. Figure 69B also shows an example of a cross-sectional configuration in the direction of line B-B' shown in Figure 68.

[0278] Figure 69C shows an example of a cross-sectional configuration in the direction of the line C-C' shown in Figure 68. Figure 69D also shows an example of a cross-sectional configuration in the direction of the line D-D' shown in Figure 68. The imaging device 1 may have a plurality of wirings L2 arranged adjacent to each other within the separation region 17.

[0279] The imaging device 1 may have a plurality of adjacent wirings L2 in the X-axis direction (or Y-axis direction). The imaging device 1 may also have adjacent wirings L2a and L2b, as shown in the example in Figure 68, etc. One of the wirings L2a and L2b may be electrically connected to the gate electrode 35 of the transistor SEL, and the other of the wirings L2a and L2b may be electrically connected to the gate electrode 34 of the transistor AMP.

[0280] The number and arrangement of wiring L2 in each pixel unit PU (or pixel P) are not limited to the illustrated example and can be changed as appropriate. The imaging device 1 may have three or more wiring L2 arranged in a comb-like pattern. Two or three or more wiring L2 may be arranged to the left of the transistors SEL and AMP, and to the right of the transistors SEL and AMP, respectively.

[0281] (Modification 21) Figures 70 and 71A to 71C are diagrams illustrating an example of the configuration of an imaging device according to Modification 21. Figure 70 shows an example of the planar configuration of the imaging device. Figure 71A shows an example of the cross-sectional configuration in the direction of line A-A' shown in Figure 70. Figure 71B shows another example of the cross-sectional configuration in the direction of line A-A' shown in Figure 70. Figure 71C also shows an example of the cross-sectional configuration in the direction of line B-B' shown in Figure 70.

[0282] Each transistor in pixel P may be configured as a planar transistor or as a Fin-type transistor. At least one of the multiple transistors in the readout circuit 15, for example, transistors SEL, AMP, FDG, and RST, may be configured as a Fin-type transistor (Fin FET).

[0283] The transistor SEL may have, for example, the structure shown in Figure 71A or Figure 71B. The transistor SEL has a gate electrode 35 and a gate insulating film 38 that are provided so as to sandwich a part (which can also be called a fin portion) of the semiconductor layer 101 which serves as a channel region, as in the example shown in Figure 71A or Figure 71B.

[0284] The transistor SEL may have a portion of the gate electrode 35, which is formed by carving out the semiconductor layer 101, as a fin portion, as shown in the example in Figure 71B. The transistor SEL may have a carved gate structure. The transistor SEL has a carved fin structure and can also be called a carved fin transistor. The transistor AMP and the like may also have a configuration similar to the one shown in Figure 71A or Figure 71B.

[0285] <6. Sixth Embodiment> Next, a sixth embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0286] Figures 72 to 74 are diagrams illustrating an example of the configuration of an imaging device according to a sixth embodiment of the present disclosure. Figure 72 shows an example of the circuit configuration of a pixel in the imaging device. Figure 73 shows an example of the planar configuration of the imaging device. Figure 74 shows an example of the cross-sectional configuration in the direction of line A-A' shown in Figure 73.

[0287] Figures 72 and 73 show an example where a readout circuit 15 is provided for each pixel P. In the imaging device 1, a readout circuit 15 may be arranged for each pixel unit PU containing multiple pixels P. The imaging device 1 may have a structure in which multiple semiconductor layers 101 are stacked. The transistor FDG may be electrically connected in series with the transistor RST, or electrically connected in parallel with the transistor RST.

[0288] The imaging device 1 according to this embodiment has wiring L2 as a shielding wire. The wiring L2 is given a predetermined potential (voltage) and is provided around the pixel transistors (transistor AMP, transistor SEL, transistor FDG, or transistor RST, etc.) of the pixel P. The wiring L2 is configured as a shielding wire (shielding portion) to which a predetermined potential is applied.

[0289] The wiring L2 is configured such that at least a portion of it is provided around the gate electrode of a pixel transistor. At least a portion of the wiring L2 is provided on the same layer as the gate electrode of the pixel transistor. The wiring L2 is provided, for example, between the transistor of a pixel P and the transistors of surrounding pixels P. At least a portion of the wiring L2 may be located at the boundary between adjacent pixels P (or pixel unit PU).

[0290] The wiring L2 is made of a conductive material (conductor), such as polysilicon, as described above. The wiring L2 may be made of the same material (e.g., polysilicon) as the gate electrode of the transistor of the pixel P. The wiring L2 may be electrically connected to the reference potential line in the wiring layer 105. A voltage VSS (e.g., 0V) is supplied to the wiring L2, for example, through the wiring and contacts (vias) of the wiring layer 105, as schematically shown in Figure 74.

[0291] The wiring L2 is provided, for example, around the gate electrode 34 of the transistor AMP of pixel P. The wiring L2 is provided between the transistor AMP of pixel Pa, which is one of two adjacent pixels P in the X-axis direction (or Y-axis direction), and the transistor AMP of pixel Pb, which is the other pixel.

[0292] At least a portion of the shielded wiring L2 is provided between the gate electrode 34 of the transistor AMP of pixel Pa and the gate electrode 34 of the transistor AMP of pixel Pb. This makes it possible to suppress crosstalk between the wiring L1 (FD wiring) connected to the gate electrode 34 of the transistor AMP of pixel Pa and the wiring L1 (FD wiring) connected to the gate electrode 34 of the transistor AMP of pixel Pb.

[0293] Furthermore, at least another portion of the wiring L2 may be provided between the gate electrode 35 of the transistor SEL of pixel Pa and the gate electrode 35 of the transistor SEL of pixel Pb. By configuring the imaging device 1 as shown in the examples in Figures 73 and 74, it is possible to effectively reduce crosstalk between floating diffusion FD1.

[0294] The wiring L2 may be provided between another transistor (for example, transistor FDG or transistor RST) in the readout circuit 15 for pixel Pa and another transistor in the readout circuit 15 for pixel Pb. The wiring L2 may also be placed between a pixel transistor provided for a pixel unit PU (i.e., a pixel transistor shared by multiple pixels P) and a pixel transistor provided for the surrounding pixel unit PU.

[0295] In the imaging device 1 according to this embodiment, as described above, wiring L2 is provided as a shielding line. Therefore, crosstalk between adjacent pixels P (or between adjacent pixel units PU) can be suppressed. For example, it is possible to suppress the addition of unnecessary coupling capacitance between floating diffusion FD1.

[0296] In the imaging device 1, capacitive coupling can be effectively reduced by wiring L2 provided on the same layer as the gate electrode of the pixel transistor, as shown in the example in Figure 74. This suppresses noise from being mixed into the pixel signal and improves the quality of the pixel signal. This makes it possible to improve the image quality of the image generated using the pixel signal.

[0297] [Function and Effects] The photodetector according to this embodiment includes a semiconductor layer (e.g., semiconductor layer 101), a first pixel (e.g., pixel Pa) including a first photoelectric conversion element and a first transistor (e.g., transistor AMP) having a first gate electrode provided on the first surface side of the semiconductor layer, a second pixel (e.g., pixel Pb) adjacent to the first pixel, and a shield wire (wiring L2) to which a predetermined potential is applied. At least a portion of the shield wire is provided around the first gate electrode.

[0298] The photodetector (imaging device 1) according to this embodiment has wiring L2 as a shielding wire to which a predetermined potential is applied. At least a portion of wiring L2 is provided, for example, around the gate electrode 34 of a transistor AMP. Therefore, it is possible to realize a photodetector that can suppress the degradation of signal quality.

[0299] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0300] (Modification 22) Figures 75 and 76 are diagrams illustrating an example of the configuration of an imaging device according to Modification 22 of the present disclosure. Figure 75 shows an example of the planar configuration of the imaging device. Figure 76 shows an example of the cross-sectional configuration in the direction of line A-A' shown in Figure 75. The imaging device 1 may have, as shown in the example in Figures 75 and 76, a wiring L2a provided on the surface S1 of the semiconductor layer 101 and a wiring L2b provided on the wiring layer 105.

[0301] In the examples shown in Figures 75 and 76, the wiring L2a is provided on the same layer as the gate electrode of the pixel transistor, for example, the gate electrode 34 of the transistor AMP. The wiring L2b is, for example, made up of the first layer of wiring in the wiring layer 105. The imaging device 1 may also have a contact 57 provided between the wiring L2a and the wiring L2b, as in the example shown in Figure 77. The contact 57 (via) is provided in the wiring layer 105 and connects the wiring L2a and the wiring L2b.

[0302] (Modification 23) Figure 78 is a diagram illustrating an example of the configuration of an imaging device according to Modification 23. In the pixel section 100 (pixel array) of the imaging device 1, wiring L2 shared by three or more pixels P may be provided. The wiring L2 is arranged for a plurality of pixels P arranged in the Y-axis direction (or X-axis direction), for example, as shown in the example in Figure 78. In addition, the imaging device 1 may be provided with wiring L2 shared by a plurality of pixel units PU. For example, a common wiring L2 can be provided for two or four pixel units PU.

[0303] Figures 79 and 80 illustrate another configuration example of the imaging device according to Modification 23. The wiring L2 may be provided so as to span a part of each of a plurality of adjacent transistor AMPs, as in the example shown in Figure 79. For example, the wiring L2 is arranged so as to overlap a part of the drain region of the transistor AMP of pixel Pa and a part of the drain region of the transistor AMP of pixel Pb. In addition, as in the example shown in Figure 80, the wiring L2 may be provided that is shared by a plurality of pixels P or a plurality of pixel units PU.

[0304] Figures 81 and 82 are diagrams illustrating another configuration example of the imaging device according to Modification 23. The wiring L2 may be provided for a plurality of adjacent pixels P (or a plurality of pixel units PU) in the X-axis and Y-axis directions. The wiring L2 is provided so as to extend in the X-axis and Y-axis directions along the boundary of a plurality of adjacent pixels P, for example, as shown in the example in Figure 81 or Figure 82. In this modification as well, the same effects as in the embodiment described above can be obtained.

[0305] <7. Examples of Application> The above-described imaging device 1 can be applied to any type of electronic device equipped with an imaging function, such as camera systems like digital still cameras and video cameras, or mobile phones with imaging capabilities. Figure 83 shows a schematic configuration of the electronic device 1000.

[0306] The electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0307] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0308] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

[0309] The display unit 1004 consists of, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records the video or still image data captured by the imaging device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0310] The operation unit 1006 outputs operation signals for various functions possessed by the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0311] <8. Application Examples> (Application Examples to Mobile Devices) The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0312] Figure 84 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0313] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 84, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0314] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0315] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0316] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0317] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0318] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0319] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0320] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0321] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0322] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 84, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0323] Figure 85 shows an example of the installation position of the imaging unit 12031.

[0324] In Figure 85, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0325] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0326] Figure 85 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0327] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0328] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0329] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0330] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0331] The above describes an example of a mobile control system to which the technology described herein can be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, for example, the imaging device 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, it becomes possible to obtain high-definition captured images. This makes it possible to perform high-precision control using captured images in the mobile control system.

[0332] (Examples of application to endoscopic surgical systems) The technology described herein (the technology) can be applied to various products. For example, the technology described herein may be applied to endoscopic surgical systems.

[0333] Figure 86 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0334] Figure 86 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0335] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0336] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0337] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0338] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display the image based on that image signal.

[0339] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0340] The light source device 11203 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0341] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0342] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0343] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0344] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0345] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0346] Figure 87 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 86.

[0347] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0348] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0349] The imaging unit 11402 is composed of image sensors. The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is composed of multiple chips, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is composed of multiple chips, multiple lens units 11401 may also be provided corresponding to each image sensor.

[0350] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0351] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0352] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0353] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0354] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0355] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0356] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0357] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0358] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0359] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0360] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0361] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0362] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0363] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be suitably applied, for example, to the imaging unit 11402 provided on the camera head 11102 of the endoscope 11100. By applying the technology described herein to the imaging unit 11402, it becomes possible to provide a high-definition endoscope 11100.

[0364] Although the present disclosure has been described above with reference to embodiments, modifications, application examples, and application examples, the present technology is not limited to the above embodiments, and various modifications are possible. For example, although the above modifications were described as modifications of the above embodiments, the configurations of each modification can be combined as appropriate.

[0365] In the embodiments described above, an imaging device was used as an example; however, the light detection device of this disclosure may be any device that receives incident light and converts the light into an electric charge. The output signal may be an image information signal or a distance measurement information signal. The light detection device (imaging device) can be applied to an image sensor, a distance measurement sensor, etc. Furthermore, this disclosure is not limited to back-illuminated image sensors, but is also applicable to front-illuminated image sensors.

[0366] The light detection device relating to this disclosure can also be used as a distance measuring sensor capable of measuring distance using the Time of Flight (TOF) method. The light detection device (imaging device) can also be used as a sensor capable of detecting events, for example, an event-driven sensor (also known as an EVS (Event Vision Sensor), EDS (Event Driven Sensor), DVS (Dynamic Vision Sensor), etc.).

[0367] One embodiment of the present disclosure provides a photodetector comprising a pixel having a semiconductor layer, a photoelectric conversion element, and a first transistor provided on the first surface side of the semiconductor layer, a semiconductor region of a first conductivity type provided on the semiconductor layer, an isolation region provided on the semiconductor layer, and wiring. At least a portion of the wiring is provided within the isolation region, electrically connected to the semiconductor region, and given a predetermined potential. This makes it possible to realize a photodetector capable of suppressing a degradation of signal quality.

[0368] An optical detection device according to one embodiment of the present disclosure comprises a semiconductor layer, a photoelectric conversion element, a first floating diffusion, a pixel having a first transistor provided on the first surface side of the semiconductor layer and electrically connected to the first floating diffusion, and a second transistor provided on the first surface side of the semiconductor layer and capable of resetting the voltage of the first floating diffusion, an isolation region provided in the semiconductor layer, and a first wiring. The first transistor has a first semiconductor region provided in the semiconductor layer and electrically connected to the first floating diffusion, and a second semiconductor region provided in the semiconductor layer. At least a portion of the first wiring is provided within the isolation region and electrically connected to the second semiconductor region. This makes it possible to realize an optical detection device that can suppress the degradation of signal quality.

[0369] An optical detection device according to one embodiment of the present disclosure comprises a semiconductor layer, a photoelectric conversion element, a floating diffusion element, a pixel having a first transistor provided on the first surface side of the semiconductor layer and capable of outputting a first signal based on the charge accumulated in the floating diffusion element, an isolation region provided in the semiconductor layer, and a first wiring. The first transistor has a first gate electrode. At least a portion of the first wiring is provided around the first gate electrode within the isolation region. This makes it possible to realize an optical detection device that can suppress a decrease in signal quality.

[0370] Furthermore, the effects described herein are merely examples and are not limited to those described herein, and other effects may also exist. In addition, this disclosure may take the following configurations: (1) A photodetector comprising: a semiconductor layer; a pixel having a photoelectric conversion element and a first transistor provided on the first surface side of the semiconductor layer; a semiconductor region of a first conductivity type provided on the semiconductor layer; an isolation region provided on the semiconductor layer; and wiring, wherein at least a portion of the wiring is provided within the isolation region, electrically connected to the semiconductor region, and given a predetermined potential. (2) The photodetector according to (1), wherein the wiring is provided in contact with the semiconductor region within the isolation region. (3) The photodetector according to (1) or (2), wherein the isolation region is provided around the pixel, and the wiring is provided around the pixel in the isolation region. (4) The photodetector according to any one of (1) to (3), wherein the pixel has a plurality of transistors including the first transistor, the isolation region is provided around the plurality of transistors, and the wiring is provided so as to surround the plurality of transistors. (5) The photodetector according to any one of (1) to (4), further comprising a contact provided on the first surface side of the semiconductor layer and connected to the wiring provided in the isolation region. (6) The photodetector according to any one of (1) to (5), wherein the semiconductor layer has a first surface and a second surface opposite to the first surface, and the isolation region has a trench provided between the first surface and the second surface of the semiconductor layer. (7) The photodetector according to any one of (1) to (6), comprising a well of a first conductivity type provided in the semiconductor layer, the semiconductor region being provided in the well. (8) The photodetector according to any one of (1) to (7), wherein the photoelectric conversion element is provided in the semiconductor layer.(9) A photodetector comprising: a semiconductor layer; a photoelectric conversion element; a first floating diffusion; a first transistor provided on the first surface side of the semiconductor layer and electrically connected to the first floating diffusion; a pixel having a second transistor provided on the first surface side of the semiconductor layer and capable of resetting the voltage of the first floating diffusion; an isolation region provided in the semiconductor layer; and a first wiring, wherein the first transistor has a first semiconductor region provided in the semiconductor layer and electrically connected to the first floating diffusion, and a second semiconductor region provided in the semiconductor layer, and at least a part of the first wiring is provided in the isolation region and electrically connected to the second semiconductor region. (10) The photodetector according to (9), wherein the first semiconductor region is one of the source region and the drain region of the first transistor; the second semiconductor region is the other of the source region and the drain region of the first transistor; and the first wiring is provided in contact with the second semiconductor region within the isolation region. (11) The photodetector according to (9) or (10), wherein the second transistor has a third semiconductor region provided in the semiconductor layer and is electrically connected in series with the first transistor, the third semiconductor region being either the source region or the drain region of the second transistor, and the first wiring is provided in contact with the second semiconductor region and the third semiconductor region within the isolation region. (12) The photodetector according to any one of (9) to (11), wherein the isolation region is provided around the first transistor and the second transistor, a portion of the first wiring is provided in contact with the second semiconductor region within the isolation region, and another portion of the first wiring is provided in the isolation region along at least one of the first transistor and the second transistor. (13) The photodetector according to any one of (9) to (12), wherein the semiconductor layer has a first surface and a second surface opposite to the first surface, and the isolation region has a trench provided between the first surface and the second surface of the semiconductor layer.(14) The photodetector according to any one of (9) to (13), wherein the pixel has a second floating diffusion including the first wiring, and the first transistor is a transistor capable of electrically connecting the first floating diffusion and the second floating diffusion. (15) The photodetector according to any one of (9) to (14), further comprising a second wiring to which a predetermined potential is applied, wherein at least a portion of the second wiring is provided around the first wiring. (16) The photodetector according to (15), wherein at least a portion of the second wiring is provided around the first wiring within the isolation region. (17) The photodetector according to (15) or (16), wherein at least a portion of the second wiring is provided so as to face the first wiring. (18) The photodetector according to any one of (15) to (17), wherein the pixel has a capacitance including at least a portion of the first wiring and at least a portion of the second wiring. (19) The photodetector according to (18), wherein the capacitance includes an insulating film provided between the first wiring and the second wiring in the isolation region, and at least a portion of the second wiring is provided along the first wiring via the insulating film. (20) The photodetector according to any one of (15) to (19), wherein at least a portion of the second wiring is provided to be laminated with the first wiring. (21) The photodetector according to any one of (15) to (20), wherein at least a portion of the first wiring is provided to be laminated with the second wiring within the isolation region. (22) The photodetector according to any one of (15) to (21), further comprising a well of a first conductivity type provided in the semiconductor layer and a fourth semiconductor region of the first conductivity type provided in the well, wherein the second wiring is electrically connected to the fourth semiconductor region. (23) The photodetector according to any one of (15) to (22), wherein the separation region is provided around the pixel, and the second wiring is provided around the pixel in the separation region.(24) A photodetector comprising: a semiconductor layer; a photoelectric conversion element; a floating diffusion; a pixel having a first transistor provided on the first surface side of the semiconductor layer and capable of outputting a first signal based on the charge accumulated in the floating diffusion; an isolation region provided in the semiconductor layer; and a first wiring, wherein the first transistor has a first gate electrode, and at least a portion of the first wiring is provided around the first gate electrode within the isolation region. (25) The photodetector according to (24), wherein at least a portion of the first wiring is provided within the isolation region and electrically connected to the first gate electrode. (26) The photodetector according to (24), comprising a second transistor having a second gate electrode electrically connected to the floating diffusion and capable of generating the first signal, wherein at least another portion of the first wiring is provided around the second gate electrode within the isolation region. (27) The photodetector according to (26), wherein at least another portion of the first wiring is provided within the isolation region and electrically connected to the second gate electrode. (28) The photodetector according to (26) or (27), wherein at least a portion of the first wiring is provided to face the first gate electrode of the first transistor, and at least another portion of the first wiring is provided to face the second gate electrode of the second transistor. (29) The photodetector according to any one of (26) to (28), wherein the semiconductor layer has a first surface and a second surface opposite to the first surface, and the isolation region has a trench provided between the first surface and the second surface of the semiconductor layer. (30) The photodetector comprising a semiconductor layer, a first pixel including a first photoelectric conversion element and a first transistor having a first gate electrode provided on the first surface side of the semiconductor layer, a second pixel adjacent to the first pixel including a second photoelectric conversion element and a second transistor having a second gate electrode provided on the first surface side of the semiconductor layer, and a shield wire to which a predetermined potential is applied, wherein at least a portion of the shield wire is provided around the first gate electrode.(31) The photodetector according to (30), wherein at least a portion of the shield wire is provided in the same layer as the first gate electrode. (32) The photodetector according to (30) or (31), wherein the first pixel has a first floating diffusion, the second pixel has a second floating diffusion, the first gate electrode of the first transistor is electrically connected to the first floating diffusion, and the second gate electrode of the second transistor is electrically connected to the second floating diffusion. (33) The photodetector according to any one of (30) to (32), wherein at least a portion of the shield wire is provided between the first gate electrode and the second gate electrode. (34) An electronic device comprising an optical system and a photodetector that receives light transmitted through the optical system, wherein the photodetector has a semiconductor layer, a pixel having a photoelectric conversion element and a first transistor provided on the first surface side of the semiconductor layer, a semiconductor region of a first conductivity type provided on the semiconductor layer, an isolation region provided on the semiconductor layer, and wiring, wherein at least a portion of the wiring is provided within the isolation region, is electrically connected to the semiconductor region, and is given a predetermined potential. (35) Electronic device comprising an optical system and a photodetector for receiving light transmitted through the optical system, wherein the photodetector comprises a semiconductor layer, a photoelectric conversion element, a first floating diffusion, a pixel having a first transistor provided on the first surface side of the semiconductor layer and electrically connected to the first floating diffusion, and a second transistor provided on the first surface side of the semiconductor layer and capable of resetting the voltage of the first floating diffusion, an isolation region provided in the semiconductor layer, and a first wiring, wherein the first transistor has a first semiconductor region provided in the semiconductor layer and electrically connected to the first floating diffusion, and a second semiconductor region provided in the semiconductor layer, and at least a part of the first wiring is provided in the isolation region and electrically connected to the second semiconductor region.(36) Electronic device comprising an optical system and a photodetector for receiving light transmitted through the optical system, wherein the photodetector comprises a semiconductor layer, a photoelectric conversion element, a floating diffusion, a pixel having a first transistor provided on the first surface side of the semiconductor layer and capable of outputting a first signal based on the charge accumulated in the floating diffusion, an isolation region provided in the semiconductor layer, and a first wiring, wherein the first transistor has a first gate electrode, and at least a portion of the first wiring is provided around the first gate electrode within the isolation region. (37) Electronic device comprising an optical system and a photodetector for receiving light transmitted through the optical system, wherein the photodetector comprises a semiconductor layer, a first pixel including a first photoelectric conversion element and a first transistor having a first gate electrode provided on the first surface side of the semiconductor layer, a second photoelectric conversion element and a second transistor having a second gate electrode provided on the first surface side of the semiconductor layer, a second pixel adjacent to the first pixel, and a shield wire to which a predetermined potential is applied, and at least a portion of the shield wire is provided around the first gate electrode.

[0371] This application claims priority based on Japanese Patent Application No. 2025-049628, filed with the Japan Patent Office on 25 March 2025, and all contents of that application are incorporated herein by reference.

[0372] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

Semiconductor layer, A pixel having a photoelectric conversion element and a first transistor provided on the first surface side of the semiconductor layer, A first conductivity type semiconductor region provided in the semiconductor layer, A separation region provided in the semiconductor layer, Wiring and Equipped with, At least a portion of the wiring is provided within the isolation region, electrically connected to the semiconductor region, and given a predetermined potential. Light detection device. 　 The wiring is provided within the isolation region in contact with the semiconductor region. The light detection device according to claim 1. 　 The separation region is provided around the pixel, The wiring is provided around the pixel in the separation region. The light detection device according to claim 1. 　 The pixel has a plurality of transistors, including the first transistor. The isolation region is provided around the plurality of transistors, The aforementioned wiring is provided so as to surround the plurality of transistors. The light detection device according to claim 1. 　 The semiconductor layer further comprises a contact provided on the first surface side and connected to the wiring provided within the isolation region. The light detection device according to claim 1. 　 The semiconductor layer has a first surface and a second surface opposite to the first surface. The isolation region has a trench provided between the first and second surfaces of the semiconductor layer. The light detection device according to claim 1. 　 The semiconductor layer comprises the first conductive type well, The semiconductor region is provided in the well. The light detection device according to claim 1. 　 The photoelectric conversion element is provided in the semiconductor layer. The light detection device according to claim 1. 　 Semiconductor layer, A pixel comprising a photoelectric conversion element, a first floating diffusion, a first transistor provided on the first surface side of the semiconductor layer and electrically connected to the first floating diffusion, and a second transistor provided on the first surface side of the semiconductor layer and capable of resetting the voltage of the first floating diffusion, A separation region provided in the semiconductor layer, First wiring and Prepare, The first transistor has a first semiconductor region provided in the semiconductor layer and electrically connected to the first floating diffusion, and a second semiconductor region provided in the semiconductor layer. At least a portion of the first wiring is provided within the isolation region and is electrically connected to the second semiconductor region. Light detection device. 　 The first semiconductor region is one of the source region and the drain region of the first transistor. The second semiconductor region is the other of the source region and the drain region of the first transistor. The first wiring is provided within the isolation region in contact with the second semiconductor region. The light detection device according to claim 9. 　 The second transistor has a third semiconductor region provided in the semiconductor layer and is electrically connected in series with the first transistor. The third semiconductor region is one of the source region and the drain region of the second transistor. The first wiring is provided within the isolation region in contact with the second semiconductor region and the third semiconductor region. The light detection device according to claim 10. 　 The isolation region is provided around the first transistor and the second transistor, A portion of the first wiring is provided within the isolation region in contact with the second semiconductor region, The other portion of the first wiring is provided within the isolation region so as to be along at least one of the first transistor and the second transistor. The light detection device according to claim 9. 　 The semiconductor layer has a first surface and a second surface opposite to the first surface. The isolation region has a trench provided between the first and second surfaces of the semiconductor layer. The light detection device according to claim 9. 　 The pixel has a second floating diffusion including the first wiring, The first transistor is a transistor capable of electrically connecting the first floating diffusion and the second floating diffusion. The light detection device according to claim 9. 　 Further comprising a second wiring to which a predetermined potential is applied, At least a portion of the second wiring is provided around the first wiring. The light detection device according to claim 9. 　 At least a portion of the second wiring is provided around the first wiring within the separation region. The light detection device according to claim 15. 　 At least a portion of the second wiring is provided so as to face the first wiring. The light detection device according to claim 15. 　 The pixel has a capacitance that includes at least a portion of the first wiring and at least a portion of the second wiring. The light detection device according to claim 15. 　 The capacitance includes an insulating film provided between the first wiring and the second wiring in the isolation region. At least a portion of the second wiring is provided along the first wiring via the insulating film. The light detection device according to claim 18. 　 At least a portion of the second wiring is provided to be stacked with the first wiring. The light detection device according to claim 15. 　 At least a portion of the first wiring is provided to be stacked with the second wiring within the separation region. The light detection device according to claim 15. 　 A first conductivity type well provided in the semiconductor layer, The fourth semiconductor region of the first conductivity type provided in the well and Furthermore, The second wiring is electrically connected to the fourth semiconductor region. The light detection device according to claim 15. 　 The separation region is provided around the pixel, The second wiring is provided around the pixel in the separation region. The light detection device according to claim 15. 　 Semiconductor layer, A pixel having a photoelectric conversion element, a floating diffusion, and a first transistor provided on the first surface side of the semiconductor layer and capable of outputting a first signal based on the charge accumulated in the floating diffusion, A separation region provided in the semiconductor layer, First wiring and Prepare, The first transistor has a first gate electrode, At least a portion of the first wiring is provided around the first gate electrode within the isolation region. Light detection device. 　 At least a portion of the first wiring is provided within the isolation region and is electrically connected to the first gate electrode. The light detection device according to claim 24. 　 The second transistor has a second gate electrode electrically connected to the floating diffusion and is capable of generating the first signal, At least the other portion of the first wiring is provided around the second gate electrode within the isolation region. The light detection device according to claim 24. 　 At least the other portion of the first wiring is provided within the isolation region and is electrically connected to the second gate electrode. The light detection device according to claim 26. 　 At least a portion of the first wiring is provided so as to face the first gate electrode of the first transistor, At least the other portion of the first wiring is provided to face the second gate electrode of the second transistor. The light detection device according to claim 26. 　 The semiconductor layer has a first surface and a second surface opposite to the first surface. The isolation region has a trench provided between the first and second surfaces of the semiconductor layer. The light detection device according to claim 26.

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