Method for producing multilayer ceramic capacitor and multilayer ceramic capacitor

Abstract

Provided is a method for producing a multilayer ceramic capacitor that makes it possible to easily and reliably detect positional misalignment of an internal electrode caused by printing misalignment, lamination misalignment, and cutting misalignment. A multilayer ceramic capacitor 1 comprises: a laminate 10 including dielectric layers 20 and internal electrode layers 30; a first external electrode 40A on a first end surface LS1; and a second external electrode 40B on a second end surface LS2. Each internal electrode layer 30 has: an opposing portion 30A facing another internal electrode layer 30 adjacent thereto in the lamination direction T with a dielectric layer 20 therebetween; and a lead-out portion 30B extending from the opposing portion 30A toward the first end surface LS1 or the second end surface LS2. The internal electrode layer 30 is provided with an internal electrode cutout portion N. The entire circumference of the internal electrode cutout portion N is surrounded by a metal material in an LW cross-sectional view. The position of the internal electrode cutout portion N in a WT cross section varies according to the position in the length direction L.

Description

Method for manufacturing a multilayer ceramic capacitor and multilayer ceramic capacitor

[0001] This invention relates to a method for manufacturing a multilayer ceramic capacitor and to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors are conventionally known. Generally, multilayer ceramic capacitors comprise a laminate in which dielectric layers and internal electrode layers are alternately stacked (see Patent Document 1). Such multilayer ceramic capacitors are typically manufactured by forming an internal electrode pattern by printing an internal electrode paste, which is a conductive paste in which metal powder, a conductive component, is dispersed on the surface of a ceramic green sheet; stacking ceramic green sheets with this internal electrode paste printed on them, and stacking a predetermined number of ceramic green sheets without the internal electrode paste printed on both the upper and lower sides of the stacked block and pressing it; cutting the resulting stacked block at predetermined positions to divide it into individual stacked chips; firing it; and then forming external electrodes.

[0003] Japanese Patent Application Publication No. 9-180957

[0004] However, in multilayer ceramic capacitors manufactured as described above, when stacking ceramic green sheets on which the internal electrode paste is printed, misalignment of the internal electrode layers due to printing misalignment, stacking misalignment, or cutting misalignment occurs, which reduces the effective area of ​​the internal electrode layers (the overlapping area of ​​opposing internal electrode layers across the dielectric layer), making it impossible to obtain the desired capacitance.

[0005] Therefore, it is necessary to inspect for any misalignment of the internal electrode paste during the manufacturing process of multilayer ceramic capacitors. In this process, the edge face of the multilayer chip after the mother block has been cut is observed, and the widthwise misalignment of the internal electrode layer is inspected by observing whether there is any bias in the internal electrode layer exposed from the edge face of the multilayer chip.

[0006] However, this method does not allow observation of longitudinal misalignment of the internal electrode layer. Therefore, it was necessary for operators to manually cut the laminated chips lengthwise during sampling inspection to check for longitudinal misalignment of the internal electrode layer. In this sampling inspection, since operators cut manually, the cut shape was unstable, which could lead to variations in inspection quality. In addition, the need for a separate cutting process and cutting machine resulted in increased manufacturing costs.

[0007] The present invention aims to provide a method for manufacturing a multilayer ceramic capacitor that can easily and reliably detect misalignment of internal electrodes caused by printing misalignment, lamination misalignment, or cutting misalignment, and a multilayer ceramic capacitor having a structure that enables this.

[0008] The multilayer ceramic capacitor according to the present invention includes a plurality of stacked dielectric layers and a plurality of internal electrode layers, and comprises a laminate including a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, wherein the internal electrode layer has a facing portion that faces another adjacent internal electrode layer in the stacking direction via the dielectric layer, and a leading portion that is drawn out from the facing portion to the first end surface or the second end surface, and the internal electrode layer is provided with an internal electrode notch portion whose entire circumference is surrounded by a metal material in a cross-sectional view parallel to the width direction and the length direction, and the position of the internal electrode notch portion in the cross-section parallel to the stacking direction and the width direction changes according to the position in the length direction.

[0009] The present invention relates to a method for manufacturing a multilayer ceramic capacitor, wherein the multilayer ceramic capacitor comprises a plurality of stacked dielectric layers and a plurality of internal electrode layers, and includes a laminate that includes a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, wherein the internal electrode layer has a facing portion that faces another adjacent internal electrode layer in the stacking direction via the dielectric layer, and a lead portion that is drawn out from the facing portion to the first end surface or the second end surface, and the internal electrode layer has a planar In a cross-sectional view, an internal electrode notch is provided, surrounded by a metal material, and the position of the internal electrode notch in a cross-section parallel to the stacking direction and the width direction changes according to the position in the length direction. The manufacturing method includes a printing step of printing an internal electrode paste onto a ceramic green sheet; a stacking step of stacking the ceramic green sheets on which the internal electrode paste is printed to produce a stacked sheet; a pressing step of pressing the stacked sheet to produce a stacked block; a cutting step of cutting the stacked block to produce a stacked chip; and a detection step of detecting a misalignment of the printed internal electrode paste based on the position of the unprinted portion corresponding to the internal electrode notch in the cut surface of the stacked chip in a direction intersecting the length direction, which changes according to the position in the length direction.

[0010] According to the present invention, it is possible to provide a method for manufacturing a multilayer ceramic capacitor that can easily and reliably detect misalignment of internal electrodes caused by printing misalignment, lamination misalignment, or cutting misalignment, and a multilayer ceramic capacitor having a structure that enables this.

[0011] This is an external perspective view of a multilayer ceramic capacitor according to the first embodiment. This is a cross-sectional view taken along line II-II in Figure 1. This is a cross-sectional view taken along line III-III in Figure 2. This is a cross-sectional view taken along line IVA-IVA in Figure 2. This is a cross-sectional view taken along line IVB-IVB in Figure 2. This is a flowchart for explaining the manufacturing method of a multilayer ceramic capacitor. This is a schematic diagram for explaining the printing process in the manufacturing method of a multilayer ceramic capacitor. This is a schematic diagram for explaining the lamination process, pressurization process, and cutting process in the manufacturing method of a multilayer ceramic capacitor. This is a schematic diagram showing a good product, a multilayer chip that has undergone the lamination process, pressurization process, and cutting process in the manufacturing method of a multilayer ceramic capacitor, in which there is no printing misalignment, lamination misalignment, or cutting misalignment. This is a schematic diagram showing a defective product, a multilayer chip that has undergone the lamination process, pressurization process, and cutting process in the manufacturing method of a multilayer ceramic capacitor, in which there is printing misalignment, lamination misalignment, or cutting misalignment. This is an external perspective view showing a multilayer chip when the multilayer block is cut between the end face LS and the cut line CA0 or between the end face LS and the cut line CB0 by the cutting process according to the first embodiment. This is an external perspective view showing a laminated chip when the laminated block is cut at cut line CA1 or cut line CB1 by the cutting process according to the first embodiment. This is an external perspective view showing a laminated chip when the laminated block is cut at cut line CA2 or cut line CB2 by the cutting process according to the first embodiment. This is an external perspective view showing a laminated chip when the laminated block is cut at cut line CA3 or cut line CB3 by the cutting process according to the first embodiment. This figure corresponds to Figure 4A in the first modified example of the first embodiment. This figure corresponds to Figure 4B in the first modified example of the first embodiment. This figure corresponds to Figure 4A in the second modified example of the first embodiment. This figure corresponds to Figure 4B in the second modified example of the first embodiment. This figure corresponds to Figure 4A in the second embodiment. This figure corresponds to Figure 4B in the second embodiment. This figure corresponds to Figure 4B in the second embodiment. This is an external perspective view showing a laminated chip when the laminated block is cut from end face LS at cut line CA0 or from end face LS at cut line CB0 by the cutting process according to the second embodiment.This is an external perspective view showing a laminated chip when a laminated block is cut from cut line CA0 to cut line CA1 or from cut line CB0 to cut line CB1 by the cutting process according to the second embodiment. This is an external perspective view showing a laminated chip when a laminated block is cut from cut line CA1 to cut line CA2 or from cut line CB1 to cut line CB2 by the cutting process according to the second embodiment. This is an external perspective view showing a laminated chip when a laminated block is cut from cut line CA2 to cut line CA3 or from cut line CB2 to cut line CB3 by the cutting process according to the second embodiment.

[0012] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment of this disclosure will be described with reference to the drawings. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the embodiment. Figure 2 is a cross-sectional view taken along line II-II of Figure 1. Figure 3 is a cross-sectional view taken along line III-III of Figure 2. Figure 4A is a cross-sectional view taken along line IVA-IVA of Figure 2. Figure 4B is a cross-sectional view taken along line IVB-IVB of Figure 2.

[0013] As shown in Figure 1, the multilayer ceramic capacitor 1 according to this embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 comprises a laminate 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 40 arranged spaced apart from each other at both ends of the laminate 10.

[0014] In Figure 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T is also the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In Figure 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the stacking direction T. In Figure 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 are arranged at one end and the other end of the laminate 10 in the length direction L, respectively.

[0015] Figures 1 to 4B, 7A, 7B, and 8A to 10B show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in Figure 2 is also called the LT cross section. The cross section shown in Figure 3 is also called the WT cross section. The cross sections shown in Figures 4A and 4B are also called the LW cross section.

[0016] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the lamination direction T, a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the lamination direction T, and a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the lamination direction T and the length direction L.

[0017] In the following, when it is not necessary to distinguish between the first end face LS1 and the second end face LS2, the first end face LS1 and the second end face LS2 may be collectively referred to as end face LS.

[0018] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0019] The dimensions of the laminate 10 are not particularly limited, but if the length L of the laminate 10 is denoted as dimension L, then dimension L is preferably 0.2 mm or more and 6 mm or less. If the dimension T of the laminate 10 is denoted as dimension T, then dimension T is preferably 0.05 mm or more and 5 mm or less. If the width W of the laminate 10 is denoted as dimension W, then dimension W is preferably 0.1 mm or more and 5 mm or less.

[0020] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12 and a second main surface-side outer layer 13 arranged to sandwich the inner layer 11 in the lamination direction T.

[0021] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers, which are alternately stacked in the stacking direction T. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0022] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as the above. Alternatively, the dielectric material may have minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components. The dielectric material may have BaTiO as its main component. ３ It is particularly preferable that the material contains [a specific substance].

[0023] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The number of dielectric layers 20 to be stacked is preferably 15 or more and 1200 or less. This number of dielectric layers 20 is the sum of the number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0024] The multiple internal electrode layers 30 include a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with a dielectric layer 20 in between them. The first internal electrode layers 31 are drawn out to the first end face LS1. The second internal electrode layers 32 are drawn out to the second end face LS2. In the following, when it is not necessary to explain the first internal electrode layers 31 and the second internal electrode layers 32 separately, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layer 30.

[0025] As shown in Figures 2 and 4A, the first internal electrode layer 31 has a first opposing portion 31A and a first leading portion 31B. The first opposing portion 31A is a region that faces the second internal electrode layer 32 with the dielectric layer 20 in between, and is located inside the laminate 10. The first leading portion 31B is a portion that is drawn out from the first opposing portion 31A to the first end face LS1, and is exposed to the first end face LS1.

[0026] As shown in Figures 2 and 4B, the second internal electrode layer 32 has a second opposing portion 32A and a second leading portion 32B. The second opposing portion 32A is a region that faces the first internal electrode layer 31 with the dielectric layer 20 in between, and is located inside the laminate 10. The second leading portion 32B is a portion that is drawn out from the second opposing portion 32A to the second end face LS2, and is exposed to the second end face LS2.

[0027] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0028] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0029] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0030] The basic configuration of the first opposing portion 31A and the second opposing portion 32A is the same. Furthermore, the first opposing portion 31A and the second opposing portion 32A have a shape that is generally symmetrical with respect to the WT cross section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to explain the first opposing portion 31A and the second opposing portion 32A separately, the first opposing portion 31A and the second opposing portion 32A may be collectively referred to as the opposing portion 30A.

[0031] The basic configuration of the first lead portion 31B and the second lead portion 32B is the same. Furthermore, the first lead portion 31B and the second lead portion 32B have a shape that is generally symmetrical with respect to the WT cross section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to explain the first lead portion 31B and the second lead portion 32B separately, the first lead portion 31B and the second lead portion 32B may be collectively referred to as the lead portion 30B.

[0032] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0033] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 1000 or less.

[0034] As shown in Figures 2 and 3, the first main surface-side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface-side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface-side outer layer 12 and the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0035] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 4A and 4B show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0036] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3, 4A, and 4B show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0037] The laminate 10 has an end-face outer layer LG. The end-face outer layer LG has a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is a portion located between the opposing electrode portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion 31B. That is, the first end-face outer layer LG1 is an assembly of the portions of the dielectric layers 20 on the first end face LS1 side and the portions of the first lead portions 31B. The second end-face outer layer LG2 is a portion located between the opposing electrode portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion 32B. That is, the second end-face outer layer LG2 is an assembly of the portions of the dielectric layers 20 on the second end face LS2 side and the portions of the second lead portions 32B. Figures 2, 4A, and 4B show the longitudinal range L of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer LG is also called the L gap or end gap.

[0038] As shown in Figures 1 and 2, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10, and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0039] It should be noted that the first external electrode 40A and the second external electrode 40B have the same basic configuration. In addition, the first external electrode 40A and the second external electrode 40B have a generally plane-symmetrical shape with respect to the WT cross-section at the center in the length direction L of the multilayer ceramic capacitor 1. Therefore, in the following description, when it is not necessary to separately describe the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0040] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead-out portion 31B of each of the plurality of first internal electrode layers 31 exposed at the first end face LS1. Thereby, the first external electrode 40A is electrically connected to the plurality of first internal electrode layers 31. The first external electrode 40A may also be disposed on a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1 and a part of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed to extend from above the first end face LS1 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1 and a part of the second side surface WS2.

[0041] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead-out portion 32B of each of the plurality of second internal electrode layers 32 exposed at the second end face LS2. Thereby, the second external electrode 40B is electrically connected to the plurality of second internal electrode layers 32. The second external electrode 40B may also be disposed on a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1 and a part of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed to extend from above the second end face LS2 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1 and a part of the second side surface WS2.

[0042] As described above, in the multilayer body 10, a capacitance is formed when the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 oppose each other with the dielectric layer 20 interposed therebetween. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0043] As shown in FIG. 2, FIG. 4A and FIG. 4B, the first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. Further, the second external electrode 40B includes a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0044] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the respective first lead portions 31B of the plurality of first internal electrode layers 31 exposed at the first end face LS1. In the present embodiment, the first base electrode layer 50A is formed to extend from above the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0045] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the respective second lead portions 32B of the plurality of second internal electrode layers 32 exposed at the second end face LS2. In the present embodiment, the second base electrode layer 50B is formed to extend from above the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0046] In the present embodiment, the first base electrode layer 50A and the second base electrode layer 50B are baked layers. It is preferable that the baked layer contains a metal component and either one of a glass component or a ceramic component, or both of them. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc. For the ceramic component, the same type of ceramic material as that of the dielectric layer 20 may be used, or a different type of ceramic material may be used. The ceramic component is, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ and the like, including at least one selected from the above.

[0047] The baked layer is formed, for example, by applying a conductive paste containing glass and metal onto the multilayer body 10 and baking the same. The baked layer can be formed by co-firing an unfired laminated chip, which is the raw material of the multilayer body 10 having a plurality of internal electrodes and dielectric layers, and the conductive paste applied to the laminated chip. Alternatively, after firing the laminated chip to obtain the multilayer body 10, the baked layer may also be formed by applying the conductive paste onto the multilayer body 10 and baking the same. In the case of the above co-firing, it is preferable that the baked layer is formed by baking a material added with a ceramic material instead of a glass component. In that case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the ceramic material to be added. Furthermore, the baked layer may be a plurality of layers.

[0048] The thickness corresponding to the length direction L of the first base electrode layer 50A located on the first end face LS1 is, for example, preferably about 10 μm or more and 200 μm or less at the central portion of the first base electrode layer 50A in the lamination direction T and the width direction W.

[0049] The thickness of the second base electrode layer 50B located on the second end face LS2, corresponding to the length direction L, is preferably, for example, 10 μm to 200 μm in the central part of the stacking direction T and width direction W of the second base electrode layer 50B.

[0050] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided in this portion, corresponding to the lamination direction T, is preferably, for example, 3 μm to 40 μm, at the center of the first base electrode layer 50A in the length direction L and width direction W.

[0051] When the first base electrode layer 50A is also provided on a part of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided in this part, corresponding to the width direction W, is preferably, for example, 3 μm or more and 40 μm or less in the central part of the length direction L and the lamination direction T of the first base electrode layer 50A provided in this part.

[0052] When a second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the lamination direction T, is preferably, for example, 3 μm to 40 μm, at the center of the second base electrode layer 50B in the length direction L and width direction W.

[0053] When a second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the width direction W, is preferably, for example, 3 μm to 40 μm, at the center of the second base electrode layer 50B provided in this portion, in the length direction L and the lamination direction T.

[0054] The first plating layer 60A is positioned to cover the first underlay electrode layer 50A.

[0055] The second plating layer 60B is positioned to cover the second under electrode layer 50B.

[0056] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0057] The first plating layer 60A is arranged to cover the first underlay electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0058] The second plating layer 60B is arranged to cover the second under electrode layer 50B. In this embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0059] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B and the second Sn plating layer 62B is preferably between 2 μm and 10 μm.

[0060] The external electrode 40 in this embodiment may, for example, have a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be arranged to cover the baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is placed between the baking layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baking layer or cover a part of the baking layer.

[0061] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0062] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or alloys containing these. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0063] Furthermore, the conductive particles may be metal powders with an Ag coating on their surface. When using metal powders with an Ag coating on their surface, the metal powders are preferably Cu, Ni, Sn, Bi, or alloys thereof. It is preferable to use Ag-coated metal powders in order to maintain the properties of Ag while making the base metal less expensive.

[0064] Furthermore, the conductive particles may be Cu or Ni that have been treated to prevent oxidation. Alternatively, the conductive particles may be metal powder coated with Sn, Ni, or Cu on the surface of the metal powder. When using metal powder coated with Sn, Ni, or Cu on the surface, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0065] The shape of the conductive particles is not particularly limited. Conductive particles can have shapes such as spherical or flattened, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0066] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive particles forms an electrical pathway within the conductive resin layer.

[0067] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0068] The conductive resin layer may be formed from multiple layers. Preferably, the thickness of the thickest part of the conductive resin layer is 10 μm or more and 150 μm or less.

[0069] The above describes the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminate 10 and the external electrode 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 6 mm. Furthermore, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.05 mm and 5 mm. Also, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 5 mm.

[0070] Here, the inventors of the present invention have found that a method for manufacturing a multilayer ceramic capacitor in which an internal electrode cutout is formed with the entire circumference surrounded by a metal material in a WT cross-sectional view is desirable to include a detection step that detects printing misalignment, stacking misalignment, and cutting misalignment based on the state of the non-printed area corresponding to the internal electrode cutout in the WT cross-section, in order to easily and reliably detect positional misalignment of the internal electrode caused by printing misalignment, stacking misalignment, and cutting misalignment. This point will be explained below with reference to Figures 4A to 4D.

[0071] Figure 5 is a flowchart illustrating the manufacturing method of a multilayer ceramic capacitor. Figure 6A is a schematic diagram illustrating the printing process in the manufacturing method of a multilayer ceramic capacitor. Figure 6B is a schematic diagram illustrating the lamination process, pressurization process, and cutting process in the manufacturing method of a multilayer ceramic capacitor. Figure 6C is a schematic diagram showing a good multilayer chip that has undergone the lamination process, pressurization process, and cutting process in the manufacturing method of a multilayer ceramic capacitor, in which no cutting misalignment has occurred. Figure 6D is a schematic diagram showing a defective multilayer chip that has undergone the lamination process, pressurization process, and cutting process in the manufacturing method of a multilayer ceramic capacitor, in which cutting misalignment has occurred.

[0072] Figure 7A is an external perspective view showing a multilayer chip MLC when the multilayer block is cut at cut line CA0 or cut line CB0 by the cutting process according to the first embodiment. Figure 7B is an external perspective view showing a multilayer chip MLC when the multilayer block is cut at cut line CA1 or cut line CB1 by the cutting process according to the first embodiment.

[0073] Figure 7C is an external perspective view showing a multilayer chip MLC when the multilayer block is cut at cut line CA2 or cut line CB2 by the cutting process according to the first embodiment. Figure 7D is an external perspective view showing a multilayer chip MLC when the multilayer block is cut at cut line CA3 or cut line CB3 by the cutting process according to the first embodiment.

[0074] As shown in Figures 4A and 4B, the internal electrode layer 30 of the multilayer ceramic capacitor 1 according to this embodiment is provided with an internal electrode notch N. The internal electrode notch N is a configuration that makes it easy and reliable to detect misalignments in the printed internal electrode paste P, such as printing misalignment, stacking misalignment, or cutting misalignment, during the manufacturing of the multilayer ceramic capacitor 1. In the following description, printing misalignment, stacking misalignment, and cutting misalignment refer to misalignment of the printed internal electrode paste, and these may be collectively referred to as internal electrode paste misalignment or misalignment of the internal electrode printed portion.

[0075] More specifically, the non-printed portion NP, described later, which is one aspect of the manufacturing of the internal electrode notch portion N, is used to easily and reliably detect printing misalignment, stacking misalignment, and cutting misalignment that occur during the manufacturing of multilayer ceramic capacitors.

[0076] The laminate 10 is completed through the printing process (step S10) and firing process (step S16) described later. In the following explanation, it will be assumed that the non-printed portion NP formed at the time the laminate 10 is completed becomes the internal electrode notch N. Specifically, in the following explanation, it will be assumed that the non-printed portion NP becomes the internal electrode notch N after the firing process (step S16) is completed, which is the time when the laminate 10 is completed.

[0077] The internal electrode notch N is a region in a cross-sectional view (LW cross-section) parallel to the width direction W and length direction L of a good multilayer ceramic capacitor 1 without internal electrode paste displacement, where the entire circumference is surrounded by the internal electrode layer 30 made of metallic material.

[0078] Specifically, the non-printed portion NP corresponding to the internal electrode notch N may have a continuously decreasing length W in the width direction as it approaches the end face LS of the laminate 10. Or, the length W in the width direction may decrease continuously and linearly as it approaches the end face LS. In this case, the non-printed portion NP corresponding to the internal electrode notch N may have a tapered shape as it approaches the end face LS of the laminate 10.

[0079] In this case, the non-printed portion NP corresponding to the internal electrode notch N gradually decreases in length W in the width direction monotonically as it moves toward the end face LS side of the laminate 10.

[0080] For example, as shown in Figures 4A and 4B, the internal electrode cutout N in the first embodiment has a substantially triangular shape such that the distance in the width direction W decreases as you move from the center side in the length direction L of the laminate 10 toward the end face LS side.

[0081] The internal electrode notch N according to the first embodiment is not limited to the shape shown in Figures 4A and 4B. For example, the internal electrode notch N according to the first embodiment may be a substantially trapezoidal shape such that the distance in the width direction W decreases as you move from the center side in the length direction L of the laminate 10 toward the end face LS. Also, each side of the substantially triangular shape of the internal electrode notch N may be a curve instead of a straight line. Such a shape is also included in the substantially triangular shape.

[0082] It is preferable that the entire area of ​​the internal electrode notch N is located within the range of the pull-out portion 30B of the internal electrode layer 30. The maximum length of the internal electrode notch N in the longitudinal direction L is preferably 20 μm or more and 600 μm or less. The maximum length of the internal electrode notch N in the width direction W is preferably 20 μm or more and 1 / 2 or less of the length of the internal electrode layer 30 in the width direction W.

[0083] Furthermore, the internal electrode notch N is positioned at a predetermined distance from the interface with the external electrode 40, i.e., the end face LS which is the cut surface CF. The predetermined distance is set considering the allowable range for printing misalignment, layering misalignment, and cutting misalignment.

[0084] Here, the printing misalignment detected by the internal electrode notch N occurs when the internal electrode paste P is printed on the ceramic green sheet CS during the printing process (step S10) described later, and the edge of the internal electrode paste P in the longitudinal direction L is shifted in the longitudinal direction L from a predetermined position.

[0085] The stacking misalignment detected by the internal electrode notch N occurs when the stacked sheets MLS are stacked in the stacking process (step S11) described later, with the edges of the internal electrode paste P in the longitudinal direction L shifted from a predetermined position in the longitudinal direction L.

[0086] Furthermore, the cut misalignment detected by the internal electrode notch N occurs when the position where the laminated block is cut in the cutting process (step S13) is shifted in the length direction L from a predetermined position.

[0087] Therefore, the predetermined distance is set so that, in the event of internal electrode paste misalignment, the unprinted portion NP corresponding to the internal electrode notch N is exposed on the cut surface CF obtained by cutting the laminated block MLB in the cutting process (step S13) described later. More specifically, the internal electrode notch N is positioned such that the unprinted portion NP is not exposed on the cut surface CF when there is no printing misalignment, lamination misalignment, or cutting misalignment, and is positioned such that the unprinted portion NP is exposed on the cut surface CF when there is internal electrode paste misalignment.

[0088] For example, the predetermined distance may be set as the limit of the allowable displacement of the internal electrode paste. In this case, the non-printed portion NP corresponding to the internal electrode notch N is exposed to the cut surface CF when the displacement from the position set as the edge position of the internal electrode paste P exceeds the limit of the allowable displacement of the internal electrode paste. On the other hand, the non-printed portion NP corresponding to the internal electrode notch N is not exposed to the cut surface CF when the displacement from the position set as the edge position of the internal electrode paste P is less than or equal to the limit of the allowable displacement of the internal electrode paste.

[0089] The predetermined distance may be set taking into consideration the required thickness L in the longitudinal direction of the end face outer layer LG, printing errors in the printing process (step S10) described later, lamination errors in the lamination process (step S11), processing errors in the cutting process (step S13), etc. The predetermined distance is preferably, for example, 20 μm or more and 600 μm or less.

[0090] The internal electrode notch N may be positioned such that, in a cross-sectional view of the LW, its entire circumference is surrounded by the internal electrode layer 30, which is made of metallic material, and the external electrode 40, and its tapered tip is in contact with the external electrode 40. That is, the tapered tip of the non-printed portion NP corresponding to the internal electrode notch N may be positioned such that it is in contact with the end face LS, which is the cut surface CF of the laminate 10. That is, the tapered tip of the non-printed portion NP corresponding to the internal electrode notch N may be positioned so that it is exposed to the end face LS, which is the cut surface CF of the laminate 10.

[0091] If the tapered tip of the internal electrode notch N contacts the end face LS, which is the cut surface CF of the laminate 10, then contact between the internal electrode layer 30 and the external electrode 40 can be ensured. Furthermore, with this configuration, even slight positional displacement L in the length direction of the internal electrode paste P can be detected.

[0092] In the case of a defective multilayer ceramic capacitor 1 according to this embodiment, for example, if there is a misalignment of the internal electrode paste, the end face LS, which is the cut surface CF, will expose the unprinted portion NP corresponding to the internal electrode notch N and the internal electrode paste P laminated on both ends of the width direction W of the unprinted portion NP.

[0093] In other words, in this embodiment, when the non-printed portion NP corresponding to the internal electrode notch N is exposed on the cut surface CF of the laminated chip MLC in a direction intersecting the length direction L after the laminated block MLB has been cut in the cutting process (step S13), the printed and laminated internal electrode layer 30 is exposed on both ends in the width direction W of the non-printed portion NP on the cut surface CF in a direction intersecting the length direction L of the laminated chip MLC.

[0094] As a result, if there is a misalignment of the internal electrode paste, the non-printed area NP is exposed with both sides sandwiched by the internal electrode paste P, making it possible to clearly visualize and detect the non-printed area NP, and easily detect the misalignment of the internal electrode paste P.

[0095] On the other hand, in the case of a good multilayer ceramic capacitor 1 according to this embodiment, if there is no misalignment of the internal electrode paste, the non-printed portion NP corresponding to the internal electrode notch N is not exposed on the end face LS which is the cut surface CF, and only the stacked internal electrode layer 30 and dielectric layer 20 are exposed.

[0096] Furthermore, as described above, in the inner layer 11, a plurality of internal electrode layers 30 are arranged facing each other via a dielectric layer 20, and the opposing electrode portion 11E, in which the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layer 20, functions substantially as a capacitor. For this reason, in order to secure the capacitance of the multilayer ceramic capacitor 1, it is preferable that the area of ​​the opposing portion 30A of the internal electrode layers 30 be large, and it is preferable that the internal electrode notch portion N is not located in the opposing portion 30A.

[0097] On the other hand, the lead-out portions 30B included in the end-face side outer layer portions LG, which are located at both ends of the length L of the opposing electrode portion 11E, do not affect the capacitance. Therefore, it is preferable that the internal electrode notch portion N be located in the lead-out portion 30B. Furthermore, it is even more preferable that the entire area of ​​the internal electrode notch portion N be located within the range of the lead-out portion 30B.

[0098] In other words, the internal electrode notch N is preferably located within the outer layer portion LG on both ends of the laminate 10, as shown in Figures 4A and 4B, and it is more preferable that the entire area of ​​the internal electrode notch N is located within the outer layer portion LG on both ends of the laminate 10.

[0099] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be explained with reference to Figures 5 to 7D.

[0100] A preferred manufacturing method, as shown in Figure 5, comprises a printing step (step S10) of printing an internal electrode paste P onto a ceramic green sheet CS, a lamination step (step S11) of laminating the ceramic green sheets CS on which the internal electrode paste P is printed to produce a laminated sheet MLS, a pressing step (step S12) of pressurizing the laminated sheet MLS to produce a laminated block MLB, a cutting step (step S13) of cutting the laminated block MLB to produce a laminated chip MLC, a detection step (step S15) of detecting internal electrode paste misalignment, which detects the misalignment of the internal electrode paste based on the state of the unprinted portion NP corresponding to the internal electrode notch on the cut surface CF in a direction intersecting the longitudinal direction L of the laminated chip MLC, a firing step (step S16) of firing the laminated chip MLC to obtain a laminate 10, and an external electrode formation step (step S17) of forming external electrodes on both end faces of the laminate 10.

[0101] Furthermore, the manufacturing method of the multilayer ceramic capacitor 1 may include a polishing step (step S14) to round off the corners and edges.

[0102] The details of each step are explained below.

[0103] First, the printing process (step S10) is performed. A ceramic green sheet CS is prepared as a dielectric sheet for the dielectric layer 20, and an internal electrode paste P is prepared as a conductive paste for the internal electrode layer 30. Both the ceramic green sheet CS and the internal electrode paste P contain a binder and a solvent. The binder and solvent may be known. The paste made of a conductive material is, for example, a metal powder to which an organic binder and an organic solvent are added.

[0104] The internal electrode paste P is printed onto the ceramic green sheet CS using a printing plate designed to form the shape of the internal electrode layer 30 of this embodiment, for example, by screen printing or gravure printing.

[0105] For example, as shown in Figure 6A, an internal electrode paste P with a pattern of multiple internal electrode layers 30 is printed on a single ceramic green sheet CS. In the example in Figure 6A, a cut line CL is shown virtually to be cut in a later cutting step (step S13) to indicate that a single ceramic green sheet contains a pattern of multiple internal electrode layers.

[0106] The printing pattern of the internal electrode paste P on the ceramic green sheet CS is not limited, but in the example shown in Figure 6A, the patterns of the first internal electrode layer 31 and the second internal electrode layer 32 are arranged so that the end faces of each pattern on the end face side of the multilayer ceramic capacitor 1 face each other and are arranged without gaps. As an example of the pattern of one layer of the internal electrode layer 30, region MLSA is shown in Figure 6A.

[0107] In this case, the portion of the cut line CL in region MLSA where the patterns of the first internal electrode layer 31 and the second internal electrode layer 32 face each other corresponds to the end face of the multilayer ceramic capacitor 1. Therefore, the non-printed portion NP corresponding to the internal electrode cutout portion N is positioned at a predetermined distance from the portion corresponding to the end face in contact with the external electrode 40.

[0108] In the printing process (step S10), an internal electrode paste P and a non-printed area NP, which is an area where the internal electrode paste P is not formed, are formed on the ceramic green sheet CS. At this time, in area MLSA, the non-printed area NP is formed so that its entire circumference is surrounded by a metallic material, as shown in Figure 6A. Specifically, the non-printed area NP is approximately triangular in shape, with its entire circumference surrounded by the internal electrode layer as a metallic material. In this embodiment, the area of ​​the non-printed area NP surrounded by the internal electrode paste P is an empty space in the printing process (step S10).

[0109] This prepares a ceramic green sheet CS on which the patterns of the first internal electrode layer 31 and the second internal electrode layer 32 are formed.

[0110] Next, the lamination process (step S11) will be explained using Figure 6B. Figure 6B is a diagram illustrating the portion that will become the inner layer 11 in the lamination process (step S11), and for the sake of explanation, it is shown as if the laminated sheet MLS has been virtually cut by the cut line CL. Also, for the sake of explanation, Figure 6B shows a portion of the virtually laminated laminated sheet MLS separated. In the lamination process (step S11), although not particularly limited, the ceramic green sheets CS are laminated in the following order: the portion that will become the first main surface side outer layer 12 of the laminated body 10, the portion that will become the inner layer 11, and the second main surface side outer layer 13.

[0111] By stacking a predetermined number of ceramic green sheets CS that do not have the pattern of the internal electrode layer 30 printed on them, a portion that becomes the first main surface side outer layer 12 on the first main surface TS1 side is formed.

[0112] On top of that, as shown in Figure 6B, ceramic green sheets CS printed with the pattern of the first internal electrode layer 31 and ceramic green sheets CS printed with the pattern of the second internal electrode layer 32 are sequentially and alternately laminated to form the inner layer portion 11. In the lamination process (step S11), the non-printed portion NP described above becomes a space surrounded all around by the internal electrode paste P as a metallic material, with the top and bottom surfaces surrounded by ceramic green sheets CS.

[0113] A predetermined number of ceramic green sheets CS, which do not have the pattern of the internal electrode layer 30 printed on them, are laminated on top of this inner layer portion 11 to form the second main surface side outer layer portion 13 on the second main surface TS2 side. This gives rise to a laminated sheet MLS.

[0114] Next, the pressurization process (step S12) will be described. The laminated sheet MLS is pressed in the lamination direction T by means of a hydrostatic press or the like to produce a laminated block MLB. In the pressurization process (step S12), a portion of the ceramic green sheet CS placed on the top and bottom surfaces enters the space of the non-printed area NP, which is a space surrounded by the ceramic green sheet CS on the top and bottom surfaces.

[0115] Next, the cutting process (step S13) will be explained using Figures 6C and 6D. In Figures 6C and 6D, the portion of the inner layer 11 of the multilayer chip MLC corresponding to the first end-face side outer layer LG1 or the second end-face side outer layer LG2 includes the ceramic green sheet CS, but for the sake of explanation, it will be described as the internal electrode paste P. Multiple multilayer chip MLCs are obtained by cutting the multilayer block MLB to a predetermined size to form individual pieces. The cut surface CF of the multilayer chip MLC corresponds to the end face LS of the laminate 10. More specifically, the cut surface CF is a surface horizontal in the stacking direction T and the width direction W, or in other words, a surface perpendicular to the length direction L.

[0116] Here, the surface condition of the cut surface CF changes depending on whether or not there is internal electrode paste misalignment. Specifically, if there is no internal electrode paste misalignment, the non-printed area NP corresponding to the internal electrode notch N is not exposed on the cut surface CF because it is cut within the set cut position range. For example, the multilayer chip MLC shown in Figure 6C is a good product with no internal electrode paste misalignment, and the non-printed area NP is not exposed on the cut surface CF.

[0117] On the other hand, if internal electrode paste misalignment occurs, the non-printed portion NP corresponding to the internal electrode notch N is exposed on the cut surface CF by being cut outside the set cut position range. For example, the multilayer chip MLC shown in Figure 6D is a defective product with internal electrode paste misalignment, and the non-printed portion NP corresponding to the internal electrode notch N and the internal electrode paste P arranged on both sides in the width direction W are exposed on the cut surface CF.

[0118] After this, a polishing process (step S14) may be performed to round off the corners and edges of the multilayer MLC chip by barrel polishing or the like. Note that the polishing process may be performed after the detection process, which will be described next.

[0119] Next, the detection process (step S15) will be explained using Figures 4A, 4B, and 7A to 7D. In the detection process (step S15), the internal electrode paste displacement is detected based on the state of the non-printed portion NP corresponding to the internal electrode notch portion N in the cut surface CF oriented in a direction intersecting the longitudinal direction L of the multilayer chip MLC.

[0120] In the multilayer ceramic capacitor 1 according to this embodiment, the state of the unprinted portion NP corresponding to the internal electrode notch N on the cut surface CF changes according to the amount of displacement of the internal electrode paste. Specifically, in the multilayer ceramic capacitor 1 according to this embodiment, the widthwise dimension W of the unprinted portion NP corresponding to the internal electrode notch N exposed on the cut surface CF changes according to the amount of displacement of the internal electrode paste.

[0121] Figures 4A and 4B show the LW cross-section of a good multilayer ceramic capacitor 1 with no internal electrode paste misalignment. Using Figures 4A, 4B, and 7A to 7D, the relationship between the width W dimension of the non-printed portion NP corresponding to the internal electrode notch N exposed on the cut surface CF and the amount of misalignment will be explained according to the amount of misalignment in the detection process (step S15).

[0122] For example, on the first end face LS1 side, as shown in Figure 4A, if the cut is made between the end face LS and the cut line CA0 with a displacement of less than La0, the multilayer chip MLC will have a cross-section as shown in Figure 7A. In this case, the widthwise dimension W of the non-printed portion NP corresponding to the internal electrode notch N is 0. In this embodiment, when the widthwise dimension W of the non-printed portion NP is 0, the displacement is less than La1 and can be judged to be within the allowable range.

[0123] As shown in Figure 4A, when the MLC chip is cut at the cut line CA1 with a displacement of La1, the cross-section will be as shown in Figure 7B. At this time, the widthwise dimension W of the non-printed portion NP corresponding to the internal electrode notch N is d1. In this embodiment, when the widthwise dimension W of the non-printed portion NP is d1, the displacement can be determined to be La1.

[0124] Furthermore, as shown in Figure 4A, when the MLC chip is cut at the cut line CA2 with a displacement of La2, the cross-section will be as shown in Figure 7C. At this time, the widthwise dimension W of the non-printed portion NP corresponding to the internal electrode notch N is d2. In this embodiment, when the widthwise dimension W of the non-printed portion NP is d2, the displacement can be determined to be La2.

[0125] Furthermore, as shown in Figure 4A, when the MLC chip is cut at the cut line CA3 with a displacement of La3, the cross-section will be as shown in Figure 7D. At this time, the widthwise dimension W of the non-printed portion NP corresponding to the internal electrode notch N is d3. In this embodiment, when the widthwise dimension W of the non-printed portion NP is d3, the displacement can be determined to be La3.

[0126] Furthermore, similar to the first end face LS1 side, if the second end face LS2 side is cut between the end face LS and the cut line CB0, as shown in Figure 4B, the multilayer chip MLC will have a cross-section as shown in Figure 7A. In this case, the widthwise dimension W of the non-printed portion NP corresponding to the internal electrode notch N is 0. In this embodiment, when the widthwise dimension W of the non-printed portion NP is 0, the amount of displacement is less than Lb1 and can be judged to be within the allowable range.

[0127] Furthermore, as shown in Figure 4B, when the MLC chip is cut at the cut line CB1 with a displacement of Lb1, the cross-section will be as shown in Figure 7B. At this time, the widthwise dimension W of the non-printed portion NP corresponding to the internal electrode notch N is d1. In this embodiment, when the widthwise dimension W of the non-printed portion NP is d1, the displacement can be determined to be Lb1.

[0128] Furthermore, as shown in Figure 4B, when the MLC chip is cut at the cut line CB2 with a displacement of Lb2, the cross-section will be as shown in Figure 7C. At this time, the widthwise dimension W of the non-printed portion NP corresponding to the internal electrode notch N is d2. In this embodiment, when the widthwise dimension W of the non-printed portion NP is d2, the displacement can be determined to be Lb2.

[0129] Furthermore, as shown in Figure 4B, when the MLC chip is cut at the cut line CB3 with a displacement of Lb3, the cross-section will be as shown in Figure 7D. At this time, the widthwise dimension W of the non-printed portion NP corresponding to the internal electrode notch N is d3. In this embodiment, when the widthwise dimension W of the non-printed portion NP is d3, the displacement can be determined to be Lb3.

[0130] Thus, the non-printed portion NP corresponding to the internal electrode notch N has a shape in which the dimension in the width direction W gradually decreases as it approaches the end face LS side in the length direction L, as described above. Therefore, in any of the above cases, by knowing in advance the correspondence between the amount of displacement and the width direction W of the non-printed portion NP corresponding to the internal electrode notch N, the amount of displacement can be estimated by measuring the width direction W of the non-printed portion NP corresponding to the internal electrode notch N.

[0131] At this stage, multilayer cell condensers (MLCs) that are determined to have no internal electrode paste misalignment or whose misalignment is within the acceptable range proceed to the next process. Multilayer cell condensers that are determined to have internal electrode paste misalignment or whose misalignment is outside the acceptable range do not proceed to the next process and are rejected at this stage.

[0132] Next, the firing process (step S16) will be described. The firing process (step S16) is a process of firing the multilayer chip MLC to obtain the laminate 10. The firing temperature at this time depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably, for example, 900°C or more and 1400°C or less.

[0133] Next, the external electrode formation process (step S17) will be described. In the external electrode formation process (step S17), first, a conductive paste that will become the base electrode layer 50 is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer can be formed by applying a conductive paste containing glass components and metal to the laminate 10 by a method such as dipping, and then performing a baking process. The temperature of the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0134] In this embodiment, the firing process (step S16) and the firing process in the external electrode formation process (step S17) are performed in separate steps, but this is not limited to this. The multilayer MLC chip before firing and the conductive paste applied to the multilayer MLC chip may be fired simultaneously. In this case, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the multilayer MLC chip before firing, and the multilayer MLC chip and the conductive paste applied to the multilayer MLC chip are baked simultaneously to form a laminate 10 with a baked layer.

[0135] Subsequently, a plating layer 60 is formed on the surface of the base electrode layer 50, which consists of a baked layer. In this embodiment, the first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, the second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating treatment, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like in order to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0136] Furthermore, if a conductive resin layer is provided, the conductive resin layer may be positioned to cover the baked layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and a metal component is applied to the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to heat-cur, forming the conductive resin layer. The atmosphere during this heat treatment is N ２ It is preferable that the atmosphere is such that the oxygen concentration is 100 ppm or less, in order to prevent the scattering of resin and to prevent oxidation of various metal components.

[0137] Through the above manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0138] <First Modification of the First Embodiment> In the first embodiment, the non-printed portion NP corresponding to the internal electrode cutout portion N2 had a length in the width direction W that continuously increased along the length direction L as it moved toward the center of the laminate 10, at least in the pull-out portion 30B, but is not limited to this.

[0139] For example, the non-printed portion NP corresponding to the internal electrode notch N2 may have a length in the width direction W that gradually decreases along the length direction L towards the center of the laminate 10, at least in the pull-out portion 30B. Below, the internal electrode notch N2 according to the first modification of the first embodiment will be described with reference to Figures 8A and 8B.

[0140] Figure 8A corresponds to Figure 4A in the first modified example according to the first embodiment. Figure 8B corresponds to Figure 4B in the first modified example according to the first embodiment. Note that configurations similar to those in the embodiments described above may be given the same names and their descriptions may be omitted.

[0141] In the first modified example of the first embodiment, the internal electrode layer 30 of the multilayer ceramic capacitor 1 is provided with an internal electrode notch N2, as shown in Figures 8A and 8B.

[0142] The non-printed area NP corresponding to the internal electrode notch N2 is a region surrounded by the internal electrode paste P, which is a metallic material, in a cross-sectional view of the LW of a good multilayer ceramic capacitor 1 that has no misalignment of the internal electrode paste.

[0143] Specifically, the non-printed portion NP corresponding to the internal electrode notch N2 may have a continuously decreasing length W in the width direction as it moves toward the center of the laminate 10. In this case, the non-printed portion NP corresponding to the internal electrode notch N2 may have a tapered shape that narrows toward the center of the laminate 10. In this case, the length W in the width direction of the non-printed portion NP corresponding to the internal electrode notch N2 decreases monotonically as it moves toward the center of the laminate 10.

[0144] For example, as shown in Figures 8A and 8B, the internal electrode cutout portion N2 according to the first modification of the first embodiment has a substantially triangular shape such that the distance in the width direction decreases as you move from the end face LS side in the length direction L of the laminate 10 toward the center.

[0145] As described above, the non-printed portion NP corresponding to the internal electrode notch N2 in this modified example has a shape in which the dimension in the width direction W gradually increases as it approaches the center of the laminate 10 in the length direction L. Therefore, the amount of displacement and the width direction W of the non-printed portion NP corresponding to the internal electrode notch N2 are proportional. Thus, even in this modified example, as in the first embodiment described above, by knowing the proportionality constant between the amount of displacement and the width direction W of the non-printed portion NP corresponding to the internal electrode notch N2 in advance, the amount of displacement can be estimated by measuring the width direction W of the non-printed portion NP corresponding to the internal electrode notch N2.

[0146] Thus, the non-printed portion NP corresponding to the internal electrode notch N2 has a shape in which the dimension in the width direction W gradually decreases as it approaches the center of the laminate 10 in the length direction L, as described above. Therefore, the amount of displacement and the width direction W of the non-printed portion NP corresponding to the internal electrode notch N2 are proportional. In any of the above cases, by knowing in advance the correspondence between the amount of displacement and the width direction W of the non-printed portion NP corresponding to the internal electrode notch N2, the amount of displacement can be estimated by measuring the width direction W of the non-printed portion NP corresponding to the internal electrode notch N2.

[0147] <Second Modification of the First Embodiment> In the first embodiment and the first modification of the first embodiment, the non-printed portion NP corresponding to the internal electrode cutout portion N had, at least in the pull-out portion 30B, a length in the width direction W that continuously increased or decreased along the length direction L toward the center of the laminate 10, but is not limited to this.

[0148] For example, the non-printed portion NP corresponding to the internal electrode notch N3 may, at least in the lead-out portion 30B, have a length W in the width direction that gradually decreases or increases in steps along the length direction L toward the end face LS. Hereinafter, a method for manufacturing a multilayer ceramic capacitor 1 according to a second modification of the first embodiment will be described with reference to Figures 9A and 9B. Figure 9A is a diagram corresponding to Figure 4A in the second modification of the first embodiment. Figure 9B is a diagram corresponding to Figure 4B in the second modification of the first embodiment. Note that configurations similar to those in the above-described embodiments may be given the same name and their description may be omitted.

[0149] As shown in Figures 9A and 9B, the internal electrode notch N3 has progressively different width dimensions along its length L. These progressively different width dimensions are all distinct.

[0150] More specifically, the internal electrode cutout N3 has multiple portions with different dimensions in the width direction W. Each of these portions with different dimensions in the width direction W extends in the length direction L such that the dimensions in the width direction W are substantially constant for a certain distance. The multiple portions of the internal electrode cutout N3 with different dimensions in the width direction W are arranged without gaps such that the dimensions in the width direction W increase from the end face LS side of the laminate 10 toward the center side.

[0151] For example, the non-printed portion NP corresponding to the internal electrode notch portion N3 may be such that the first portion extends for a first length and has a first width in the length direction L, the second portion extends for a second length and has a second width in the length direction L, and the third portion extends for a third length and has a third width in the length direction L.

[0152] As described above, the non-printed portion NP corresponding to the internal electrode notch N3 in this modified example has a shape in which the dimension in the width direction W gradually increases in the length direction L as it approaches the center of the laminate 10. Therefore, there is a correspondence between the amount of displacement and the width direction W of the non-printed portion NP corresponding to the internal electrode notch N3. Thus, even in this modified example, as in the first embodiment and the first modified example of the first embodiment described above, the amount of displacement can be estimated by measuring the width direction W of the non-printed portion NP corresponding to the internal electrode notch by knowing in advance the correspondence between the amount of displacement and the multiple width dimensions of the internal electrode notch N.

[0153] Thus, the non-printed portion NP corresponding to the internal electrode notch N3 has a shape in which the dimension in the width direction W gradually decreases in the length direction L as it approaches the center of the laminate 10, as described above. Therefore, there is a correspondence between the amount of displacement and the width direction W of the non-printed portion NP corresponding to the internal electrode notch N3. Thus, in any of the above cases, by knowing in advance the correspondence between the amount of displacement and the width direction W of the non-printed portion NP corresponding to the internal electrode notch N3, the amount of displacement can be estimated by measuring the width direction W of the non-printed portion NP corresponding to the internal electrode notch N3.

[0154] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following effects. Multilayer ceramic capacitors are conventionally known. Generally, a multilayer ceramic capacitor comprises a laminate in which a plurality of dielectric layers and internal electrode layers are alternately stacked.

[0155] Such multilayer ceramic capacitors are typically manufactured by forming an internal electrode pattern by printing an internal electrode paste, which is a conductive paste in which metal powder, a conductive component, is dispersed on the surface of a ceramic green sheet, stacking the ceramic green sheets printed with this internal electrode paste, and stacking a predetermined number of ceramic green sheets without the internal electrode paste printed on both the upper and lower sides of the stacked block and pressing it down. The resulting stacked block is then cut at predetermined positions to divide it into individual stacked chips, fired, and then external electrodes are formed.

[0156] However, in multilayer ceramic capacitors manufactured as described above, when stacking ceramic green sheets on which the internal electrode paste is printed, misalignment of the internal electrode paste occurs due to printing misalignment, stacking misalignment, or cutting misalignment. This reduces the effective area of ​​the internal electrode layer, which is the overlapping area of ​​the opposing internal electrode layers across the dielectric layer, making it impossible to obtain the desired capacitance.

[0157] Therefore, it is necessary to inspect for any misalignment of the internal electrode paste during the manufacturing process of multilayer ceramic capacitors. In this process, the edge face of the multilayer chip after the mother block has been cut is observed, and the widthwise misalignment of the internal electrode layer is inspected by observing whether there is any bias in the internal electrode layer exposed from the edge face of the multilayer chip.

[0158] However, this method does not allow observation of longitudinal misalignment of the internal electrode layer. Therefore, it was necessary for operators to manually cut the laminated chips lengthwise during sampling inspection to check for longitudinal misalignment of the internal electrode layer. In this sampling inspection, since operators cut manually, the cut shape was unstable, which could lead to variations in inspection quality. In addition, the need for a separate cutting process and cutting machine resulted in increased manufacturing costs.

[0159] The multilayer ceramic capacitor 1 according to the first embodiment includes a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30, and comprises a laminate 10 including a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W, and a first external electrode 40A disposed on the first end surface LS1 and a second external electrode 40B disposed on the second end surface LS2 The condenser capacitor 1 has an internal electrode layer 30 which has a facing portion 30A that faces another internal electrode layer 30 adjacent to it in the stacking direction T via a dielectric layer 20, and a leading portion 30B that is drawn out from the facing portion 30A to a first end face LS1 or a second end face LS2. The internal electrode layer 30 is provided with an internal electrode notch N which is surrounded all around by the internal electrode layer 30 and the external electrode 40 as a metallic material in a cross-sectional view parallel to the width direction W and the length direction L, and the position of the internal electrode notch N in a cross-section parallel to the stacking direction T and the width direction W changes according to the position in the length direction L.

[0160] This makes it possible to easily and reliably detect misalignments of internal electrodes caused by printing misalignment, stacking misalignment, or cutting misalignment, enabling the provision of high-quality multilayer ceramic capacitors at low cost.

[0161] In the multilayer ceramic capacitor 1 according to the first embodiment, the length of the internal electrode notch N is gradually decreasing or increasing in the width direction W along the length direction L toward the first end face LS1 side or the second end face LS2 side, at least in the lead-out portion 30B.

[0162] This allows for detailed detection of misalignment, enabling more precise responses based on the amount of misalignment. This makes it possible to more easily and reliably detect misalignment of the internal electrode paste P caused by printing misalignment, lamination misalignment, or cutting misalignment, thereby providing a high-quality multilayer ceramic capacitor 1 at low cost.

[0163] In the multilayer ceramic capacitor 1 according to the first embodiment, the internal electrode notch N is positioned at a distance from the first external electrode 40A or the second external electrode 40B, with its entire circumference surrounded by the internal electrode layer 30 in a cross-sectional view parallel to the width direction W and the length direction L.

[0164] As a result, if there is a misalignment of the internal electrode paste, the unprinted area is exposed with both sides sandwiched by the internal electrode paste, making it possible to clearly see and detect the unprinted area and easily detect the misalignment of the internal electrode paste. In addition, since the internal electrode notch N is positioned at a distance from the external electrode 40, contact between the internal electrode layer 30 and the external electrode 40 is ensured.

[0165] In the multilayer ceramic capacitor 1 according to the first embodiment, the entire area of ​​the internal electrode notch N is located within the range of the lead-out portion 30B of the internal electrode layer 30.

[0166] This makes it possible to more easily and reliably detect misalignments of internal electrodes caused by printing misalignment, stacking misalignment, or cutting misalignment, enabling the provision of high-quality multilayer ceramic capacitors at low cost.

[0167] A method for manufacturing a multilayer ceramic capacitor, wherein the multilayer ceramic capacitor 1 includes a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30, and the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W, and the first end surface LS1 The internal electrode layer 30 has a first external electrode 40A positioned on top and a second external electrode 40B positioned on the second end face LS2, and the internal electrode layer 30 has a facing portion 30A that faces another internal electrode layer 30 adjacent to it in the stacking direction T via the dielectric layer 20, and a leading portion 30B that is drawn out from the facing portion 30A to the first end face LS1 or the second end face LS2, and the internal electrode layer 30 has an internal electrode layer 30 and an external electrode layer 30 that are metallic in their periphery when viewed in a cross-sectional view parallel to the width direction W and the length direction L An internal electrode notch N surrounded by electrodes 40 is provided, and the position of the internal electrode notch N in a cross section parallel to the stacking direction T and the width direction W changes according to the position in the length direction L. The method for manufacturing a multilayer ceramic capacitor includes a printing step (step S10) of printing internal electrode paste P onto a ceramic green sheet CS, a stacking step (step S11) of stacking the ceramic green sheets CS on which the internal electrode paste P is printed to produce a stacked sheet MLS, a pressing step (step S12) of pressurizing the stacked sheet MLS to produce a stacked block MLB, a cutting step (step S13) of cutting the stacked block MLB to produce a multilayer chip MLC, and a detection step (step S15) of detecting a misalignment of the printed internal electrode paste P based on the position of the unprinted portion NP corresponding to the internal electrode notch N in the cut surface CF oriented in a direction intersecting the length direction L of the multilayer chip MLC, which changes according to the position in the length direction L.

[0168] This makes it possible to easily and reliably detect misalignments of internal electrodes caused by printing misalignment, stacking misalignment, or cutting misalignment, enabling the provision of high-quality multilayer ceramic capacitors at low cost.

[0169] In the manufacturing method of the multilayer ceramic capacitor 1 according to the first embodiment, the internal electrode notch N, at least in the lead-out portion 30B, has a length in the width direction W that gradually decreases or increases along the length direction L toward the first end face LS1 side or the second end face LS2 side. In the detection step (step S14), the misalignment of the printed internal electrode paste P is detected based on the position of the non-printed portion NP, which changes as the length in the width direction W of the non-printed portion NP gradually decreases or increases depending on the position in the length direction L on the cut surface CF intersecting the length direction L of the multilayer chip MLC. That is, the amount of misalignment and the degree of misalignment are detected as the misalignment of the printed internal electrode paste P based on information regarding the position of the non-printed portion NP, including the arrangement pattern of the non-printed portion NP and the distance in the width direction W, as the state of the non-printed portion NP on the cut surface CF.

[0170] This allows for detailed detection of misalignment, enabling more precise responses based on the amount of misalignment. This makes it possible to more easily and reliably detect misalignment of the internal electrode paste P caused by printing misalignment, lamination misalignment, or cutting misalignment, thereby providing a high-quality multilayer ceramic capacitor 1 at low cost.

[0171] In the manufacturing method of the multilayer ceramic capacitor 1 according to the first embodiment, the internal electrode notch N is positioned at a distance from the first external electrode 40A or the second external electrode 40B, with the entire circumference of the internal electrode notch N surrounded by the internal electrode layer 30 in a cross-sectional view parallel to the width direction W and the length direction L. In the detection step (step S15), if an unprinted portion NP exists on the cut surface CF of the multilayer chip MLC, it is preferable that printed internal electrode paste P is placed on both sides in the width direction of the unprinted portion NP on the cut surface CF of the multilayer chip MLC.

[0172] As a result, if there is a misalignment of the internal electrode paste, the unprinted area is exposed with both sides sandwiched by the internal electrode paste, making it possible to clearly see and detect the unprinted area and easily detect the misalignment of the internal electrode paste. In addition, since the internal electrode notch N is positioned at a distance from the external electrode 40, contact between the internal electrode layer 30 and the external electrode 40 is ensured.

[0173] In the manufacturing method of the multilayer ceramic capacitor 1 according to the first embodiment, it is preferable that the entire area of ​​the internal electrode cutout is located within the range of the lead-out portion.

[0174] This makes it possible to more easily and reliably detect misalignments of internal electrodes caused by printing misalignment, stacking misalignment, or cutting misalignment, enabling the provision of high-quality multilayer ceramic capacitors at low cost.

[0175] In the manufacturing method of the multilayer ceramic capacitor 1 according to the first embodiment, the detection step (step S15) preferably detects the amount of misalignment of the printed internal electrode paste P based on the distance in the width direction W of the non-printed portion NP on the cut surface CF.

[0176] This allows for detailed detection of misalignment, enabling more precise responses based on the amount of misalignment. This makes it possible to more easily and reliably detect misalignment of the internal electrode paste P caused by printing misalignment, lamination misalignment, or cutting misalignment, thereby providing a high-quality multilayer ceramic capacitor 1 at low cost.

[0177] <Second Embodiment> In the above-described embodiment, the amount of misalignment of the printed internal electrode paste P was detected in the detection step (step S14) based on the distance in the width direction W of the non-printed portion NP on the cut surface CF, but the embodiment is not limited to this. For example, in the detection step (step S15), the amount of misalignment of the printed internal electrode paste P may be detected based on the arrangement of the non-printed portion NP on the cut surface CF.

[0178] The manufacturing method of the multilayer ceramic capacitor 1 according to the second embodiment will be described below with reference to Figures 10A to 11D. Figure 10A corresponds to Figure 4A according to the second embodiment. Figure 10B corresponds to Figure 4B according to the second embodiment. Figure 11A is an external perspective view showing a multilayer chip when the multilayer block is cut from the end face LS to the cut line CA0 or from the end face LS to the cut line CB0 by the cutting process according to the second embodiment. Figure 11B is an external perspective view showing a multilayer chip when the multilayer block is cut from the cut line CA0 to the cut line CA1 or from the cut line CB0 to the cut line CB1 by the cutting process according to the second embodiment.

[0179] Figure 11C is an external perspective view showing a laminated chip when the laminated block is cut from cut line CA1 to cut line CA2 or from cut line CB1 to cut line CB2 by the cutting process according to the second embodiment. Figure 11D is an external perspective view showing a laminated chip when the laminated block is cut from cut line CA2 to cut line CA3 or from cut line CB2 to cut line CB3 by the cutting process according to the second embodiment. Note that in the case of a configuration similar to the above-described embodiment, the same name may be used and the description may be omitted.

[0180] In the internal electrode layer 30 of the multilayer ceramic capacitor 1 according to the second embodiment, an internal electrode notch NB is provided, as shown in Figures 10A and 10B. The internal electrode notch NB includes a first internal electrode notch NB1 and a second internal electrode notch NB2 which is positioned offset in the longitudinal direction L from the first internal electrode notch NB1.

[0181] The non-printed portion NBC corresponding to the first internal electrode notch NB1 is a region surrounded by the internal electrode layer 30 as a metallic material on its entire circumference in a cross-sectional view of the LW of a good multilayer ceramic capacitor 1 without internal electrode paste misalignment. The non-printed portion NBC corresponding to the first internal electrode notch NB1 is rectangular in shape. However, it is not limited to this, and may have the same shape as in the above-described embodiment.

[0182] The non-printed area NBC corresponding to the second internal electrode notch NB2 is a region surrounded by the internal electrode layer 30 as a metallic material on its entire circumference in a cross-sectional view of the LW of a good multilayer ceramic capacitor 1 without internal electrode paste misalignment. The non-printed area NBC corresponding to the second internal electrode notch NB2 is substantially rectangular in shape. However, it is not limited to this, and may have the same shape as in the above-described embodiment.

[0183] Preferably, the first internal electrode notch NB1 and the second internal electrode notch NB2 partially overlap in the LT cross-sectional view. In this way, the overlapping state of the first internal electrode notch NB1 and the second internal electrode notch NB2 can also be used to determine the amount of misalignment, making it possible to detect the positional misalignment of the internal electrodes caused by printing misalignment, lamination misalignment, and cutting misalignment in more detail.

[0184] With this configuration, in the detection step (step S15), the amount of misalignment of the printed internal electrode paste P can be detected based on the position of the internal electrode notch exposed on the cut surface CF, according to the amount of misalignment.

[0185] Using Figures 10A to 11D, the relationship between the position of the non-printed portion NPB corresponding to the internal electrode notch NB exposed on the cut surface CF and the amount of displacement in the detection process (step S15) will be explained.

[0186] On the first end face LS1 side, as shown in Figure 10A, when the displacement is less than La0, the multilayer chip MLC is cut between the end face LS and the cut line CC0, resulting in a cross-section as shown in Figure 11A. At this time, none of the internal electrode notches NB are exposed on the cut surface CF. In this embodiment, when none of the internal electrode notches NB are exposed on the cut surface CF, the displacement is less than La0, and it can be determined that the internal electrode paste displacement is within the acceptable range.

[0187] Furthermore, as shown in Figure 10A, when the displacement is between La0 and La1, the multilayer MLC chip is cut between cut line CC0 and cut line CC1, resulting in a cross-section as shown in Figure 11B. At this time, the unprinted portion NPB1 corresponding to the first internal electrode notch NB1 of the internal electrode notches NB is exposed on the cut surface CF. In this embodiment, when the unprinted portion NPB1 corresponding to the first internal electrode notch NB1 of the internal electrode notches NB is exposed on the cut surface CF, it can be determined that the displacement is between La0 and La1. In other words, when the unprinted portion NBC is exposed at the position of the unprinted portion NPB1 on the cut surface CF, it can be determined that the displacement is between La0 and La1.

[0188] Furthermore, as shown in Figure 10A, when the displacement is between La1 and La2, the multilayer MLC chip is cut between cut line CC1 and cut line CC2, resulting in a cross-section as shown in Figure 11C. At this time, the cut surface CF exposes the non-printed portion NPB1 corresponding to the first internal electrode notch NB1 and the non-printed portion NPB2 corresponding to the second internal electrode notch NB2 of the internal electrode notch NB. In this embodiment, when the cut surface CF exposes the non-printed portion NPB1 corresponding to the first internal electrode notch NB1 and the non-printed portion NPB2 corresponding to the second internal electrode notch NB2 of the internal electrode notch NB, it can be determined that the displacement is between La1 and La2. In other words, when the non-printed portion NPB is exposed at the positions of the non-printed portion NPB1 and the non-printed portion NPB2 on the cut surface CF, it can be determined that the displacement is between La1 and La2.

[0189] Furthermore, as shown in Figure 10A, when the displacement is between La2 and La3, the multilayer MLC chip is cut between cut line CC2 and cut line CC3, resulting in a cross-section as shown in Figure 11D. At this time, the unprinted portion NPB2 corresponding to the second internal electrode notch NB2 of the internal electrode notch NB is exposed on the cut surface CF. In this embodiment, when the unprinted portion NPB2 corresponding to the second internal electrode notch NB2 of the internal electrode notch NB is exposed on the cut surface CF, it can be determined that the displacement is between La2 and La3. In other words, when the unprinted portion NPB is exposed at the position of the unprinted portion NPB2 on the cut surface CF, it can be determined that the displacement is between La2 and La3.

[0190] On the second end face LS2 side, as shown in Figure 10B, when the displacement is less than Lb0, the multilayer chip MLC is cut between the end face LS and the cut line CD0, resulting in the cross-section shown in Figure 11A. At this time, none of the internal electrode notches NB are exposed on the cut surface CF. In this embodiment, when none of the internal electrode notches NB are exposed on the cut surface CF, the displacement is less than Lb0, and it can be determined that the internal electrode paste displacement is within the acceptable range.

[0191] Furthermore, as shown in Figure 10B, when the displacement is between Lb0 and Lb1, the multilayer MLC chip is cut between cut line CD0 and cut line CD1, resulting in a cross-section as shown in Figure 11B. At this time, the unprinted portion NPB1 corresponding to the first internal electrode notch NB1 of the internal electrode notches NB is exposed on the cut surface CF. In this embodiment, when the unprinted portion NPB1 corresponding to the first internal electrode notch NB1 of the internal electrode notches NB is exposed on the cut surface CF, it can be determined that the displacement is between Lb0 and Lb1. In other words, when the unprinted portion NPB is exposed at the position of the unprinted portion NPB1 on the cut surface CF, it can be determined that the displacement is between Lb0 and Lb1.

[0192] Furthermore, as shown in Figure 10B, when the displacement is between Lb1 and Lb2, the multilayer MLC chip is cut between cut line CD1 and cut line CD2, resulting in a cross-section as shown in Figure 11C. At this time, the cut surface CF exposes the unprinted portion NPB1 corresponding to the first internal electrode notch NB1 and the unprinted portion NPB2 corresponding to the second internal electrode notch NB2 of the internal electrode notch NB. In this embodiment, when the cut surface CF exposes the unprinted portion NPB1 corresponding to the first internal electrode notch NB1 and the unprinted portion NPB2 corresponding to the second internal electrode notch NB2 of the internal electrode notch NB, it can be determined that the displacement is between Lb1 and Lb2. In other words, when the unprinted portion NPB is exposed at the positions of the unprinted portion NPB1 and the unprinted portion NPB2 on the cut surface CF, it can be determined that the displacement is between Lb1 and Lb2.

[0193] Furthermore, as shown in Figure 10B, when the displacement is between Lb2 and Lb3, the multilayer MLC chip is cut between cut line CD2 and cut line CD3, resulting in a cross-section as shown in Figure 11D. At this time, the unprinted portion NPB2 corresponding to the second internal electrode notch NB2 of the internal electrode notch NB is exposed on the cut surface CF. In this embodiment, when the unprinted portion NPB2 corresponding to the second internal electrode notch NB2 of the internal electrode notch NB is exposed on the cut surface CF, it can be determined that the displacement is between La2 and La3. In other words, when the unprinted portion NPB is exposed at the position of the unprinted portion NPB2 on the cut surface CF, it can be determined that the displacement is between Lb2 and Lb3.

[0194] Thus, by pre-setting the relationship between the position and displacement of the non-printed portion NPB corresponding to the internal electrode notch NB, as described above, the displacement can be estimated by detecting the non-printed portion NPB exposed on the cut surface CF.

[0195] In this embodiment, the internal electrode notch NB had two internal electrode notches, a first internal electrode notch NB1 and a second internal electrode notch NB2. However, it is not limited to this and may have three or more internal electrode notches.

[0196] Furthermore, in this embodiment, the internal electrode notch NB has one internal electrode notch, and the position of the internal electrode notch may change as it moves toward the center side or the end face LS side of the laminate 10 in the length direction L. For example, the internal electrode notch may extend on the internal electrode layer 30 with a constant width in a direction intersecting the length direction L. Even in this case, the arrangement of the non-printed portion NPB corresponding to the internal electrode notch changes as it moves toward the center side of the laminate 10 in the length direction L, so that the amount of misalignment of the printed internal electrode paste P can be detected based on the arrangement of the non-printed portion NPB corresponding to the internal electrode notch.

[0197] Based on the above, in the manufacturing method of the multilayer ceramic capacitor 1 according to the second embodiment, it is preferable that the detection step (step S15) detects the amount of misalignment of the printed internal electrode paste P based on the arrangement of the non-printed portion NPB on the cut surface CF.

[0198] This makes it easy to detect misalignment, allowing for appropriate countermeasures to be taken. This enables even easier and more reliable detection of misalignment of the internal electrode paste P caused by printing misalignment, lamination misalignment, or cutting misalignment, making it possible to provide a low-cost, high-quality multilayer ceramic capacitor 1.

[0199] In the above embodiment, the internal electrode cutout was substantially symmetrical with respect to a center line passing through the center of the width direction W of the laminate 10 in a cross-sectional view of LW, but this is not limited to this.

[0200] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the individual desirable configurations described in the above embodiments also constitutes the present invention.

[0201] 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 30A Opposing part 30B Lead-out part 40A First external electrode 40B Second external electrode CS Ceramic green sheet CF Cut surface L Length direction LS1 First end face LS2 Second end face MLS Laminate sheet MLB Laminate block MLC Laminate chip N Internal electrode notch NP Non-printed part P Internal electrode paste S10 Printing process S11 Lamination process S12 Pressing process S13 Cutting process S14 Detection process T Lamination direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of stacked dielectric layers and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the internal electrode layer has a facing portion facing another adjacent internal electrode layer in the stacking direction via the dielectric layer, and a leading portion drawn out from the facing portion to the first end surface or the second end surface; the internal electrode layer is provided with an internal electrode notch whose entire circumference is surrounded by a metallic material in a cross-sectional view parallel to the width direction and the length direction, and the position of the internal electrode notch in the cross-section parallel to the stacking direction and the width direction changes according to its position in the length direction.

2. The multilayer ceramic capacitor according to claim 1, wherein the internal electrode notch has a length in the width direction that gradually decreases or increases along the length direction toward the first end face side or the second end face side, at least in the lead-out portion.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the internal electrode notch is positioned at a distance from the first external electrode or the second external electrode, with its entire circumference surrounded by the internal electrode layer in a cross-sectional view parallel to the width direction and the length direction.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the entire area of ​​the internal electrode cutout is located within the range of the lead-out portion of the internal electrode layer.

5. A method for manufacturing a multilayer ceramic capacitor, wherein the multilayer ceramic capacitor includes a plurality of stacked dielectric layers and a plurality of internal electrode layers, and comprises a laminate including a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, the internal electrode layer having a facing portion facing another adjacent internal electrode layer in the stacking direction via a dielectric layer, and a lead portion drawn out from the facing portion to the first end surface or the second end surface, the internal electrode layer is provided with an internal electrode notch portion surrounded by a metal material in a cross-sectional view parallel to the width direction and the length direction, the position of the internal electrode notch portion in the cross-section parallel to the stacking direction and the width direction changes according to the position in the length direction, and the manufacturing method is A method for manufacturing a multilayer ceramic capacitor, comprising: a printing step of printing an internal electrode paste onto a ceramic green sheet; a lamination step of stacking the ceramic green sheets on which the internal electrode paste is printed to produce a laminated sheet; a pressing step of pressing the laminated sheet to produce a laminated block; a cutting step of cutting the laminated block to produce a laminated chip; and a detection step of detecting a misalignment of the printed internal electrode paste based on the position of the unprinted portion corresponding to the internal electrode notch in the longitudinal direction of the cut surface of the laminated chip that intersects the longitudinal direction.

6. The method for manufacturing a multilayer ceramic capacitor according to claim 5, wherein the internal electrode notch portion has a length that gradually decreases or increases in the width direction along the length direction toward the first end face side or the second end face side, and in the detection step, the misalignment of the printed internal electrode paste is detected based on the position of the non-printed portion, which changes as the length of the non-printed portion in the width direction gradually decreases or increases depending on the position in the length direction of the cut surface of the multilayer chip that intersects the length direction.

7. The method for manufacturing a multilayer ceramic capacitor according to claim 5 or 6, wherein the internal electrode notch is positioned at a distance from the first external electrode or the second external electrode, such that in a cross-sectional view parallel to the width direction and the length direction, the entire circumference of the internal electrode notch is surrounded by the internal electrode layer, and in the detection step, if the non-printed portion is present on the cut surface of the multilayer chip, printed internal electrode paste is arranged on both sides in the width direction of the non-printed portion on the cut surface of the multilayer chip.

8. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 5 to 7, wherein the entire area of ​​the internal electrode notch is arranged within the range of the lead-out portion.

9. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 5 to 8, wherein the detection step detects the amount of misalignment of the printed internal electrode paste based on the distance in the width direction of the non-printed portion on the cut surface.

10. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 5 to 8, wherein the detection step detects the amount of misalignment of the printed internal electrode paste based on the arrangement of the non-printed portion on the cut surface.

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