Laminated ceramic electronic component

Abstract

Provided is a laminated ceramic electronic component that makes it possible to prevent the occurrence of cracks in a laminate. A laminated ceramic electronic component 1 is provided with: a laminate 10 which includes a plurality of ceramic layers 20 and a plurality of internal electrode layers 30 and has a first main surface TS1 and a second main surface TS2 facing each other in the height direction T, a first side surface WS1 and a second side surface WS2 facing each other in the width direction W which is orthogonal to the height direction T, and a first end surface LS1 and a second end surface LS2 facing each other in the length direction L which is orthogonal to the height direction T and the width direction W; and a pair of external electrodes 40 disposed apart from each other at both ends in the length direction L of the laminate 10, wherein the external electrodes 40 have a base electrode layer 50 containing a metallic component and a plating layer 60 disposed on the base electrode layer 50, and have a non-metal layer NM between the base electrode layer 50 and the plating layer 60.

Description

Multilayer ceramic electronic components

[0001] This invention relates to multilayer ceramic electronic components.

[0002] Conventionally, multilayer ceramic capacitors are known as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor comprises a laminate in which a plurality of dielectric layers and internal electrode layers are alternately stacked, and external electrodes provided on both end faces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, wherein the external electrodes include a base electrode layer formed by firing.

[0003] Japanese Patent Publication No. 2003-243249

[0004] In the multilayer ceramic capacitor described in Patent Document 1, the external electrode (external electrode layer) not only serves to electrically connect with the internal electrode (internal electrode layer), but also to prevent moisture from entering the end face of the laminate from the outside. On the other hand, if the substrate on which the multilayer ceramic capacitor is mounted bends, force may be applied to this external electrode, potentially causing cracks to occur in the laminate of the multilayer ceramic capacitor.

[0005] The present invention aims to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0006] The multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of ceramic layers and a plurality of internal conductor layers, and having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, and a pair of external electrodes spaced apart from each other at each end of the laminate in the length direction, wherein the external electrodes have a base electrode layer containing a metal component and a plating layer disposed on the base electrode layer, and a non-metallic layer between the base electrode layer and the plating layer.

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0008] This is an external perspective view of a multilayer ceramic capacitor according to the embodiment. This is a cross-sectional view taken along line II-II in Figure 1. This is a cross-sectional view taken along line III-III in Figure 2. This is a cross-sectional view taken along line IVA-IVA in Figure 2. This is a cross-sectional view taken along line IVB-IVB in Figure 2. This is an enlarged cross-sectional view of the portion indicated by V in Figure 2. This is a diagram showing a double-gang multilayer ceramic capacitor. This is a diagram showing a triple-gang multilayer ceramic capacitor. This is a diagram showing a quadruple-gang multilayer ceramic capacitor.

[0009] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment of this disclosure will be described with reference to the drawings. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the embodiment. Figure 2 is a cross-sectional view taken along line II-II of Figure 1. Figure 3 is a cross-sectional view taken along line III-III of Figure 2. Figure 4A is a cross-sectional view taken along line IVA-IVA of Figure 2. Figure 4B is a cross-sectional view taken along line IVB-IVB of Figure 2.

[0010] As shown in Figure 1, the multilayer ceramic capacitor 1 according to this embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 comprises a laminate 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 40 arranged spaced apart from each other at both ends of the laminate 10.

[0011] In Figure 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T is also the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In Figure 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the stacking direction T. In Figure 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 are arranged at one end and the other end of the laminate 10 in the length direction L, respectively.

[0012] Figures 1 to 4B show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross-section shown in Figure 2 is also called the LT cross-section. The cross-section shown in Figure 3 is also called the WT cross-section. The cross-sections shown in Figures 4A and 4B are also called the LW cross-section.

[0013] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the lamination direction T, a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the lamination direction T, and a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the lamination direction T and the length direction L.

[0014] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension in the length direction L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. If the dimension in the stacking direction T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.05 mm or more and 10 mm or less. If the dimension in the width direction W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.05 mm or more and 10 mm or less.

[0016] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12 and a second main surface-side outer layer 13 arranged to sandwich the inner layer 11 in the lamination direction T.

[0017] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers, which are alternately stacked in the stacking direction T. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0018] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as the above. Alternatively, the dielectric material may have minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components. The dielectric material may have BaTiO as its main component. ３ It is particularly preferable that the material contains [a specific substance].

[0019] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 10 or more and 1200 or less. This number of dielectric layers 20 is the sum of the number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The multiple internal electrode layers 30 include a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with a dielectric layer 20 in between them. The first internal electrode layers 31 are drawn out to the first end face LS1. The second internal electrode layers 32 are drawn out to the second end face LS2. In the following, when it is not necessary to explain the first internal electrode layers 31 and the second internal electrode layers 32 separately, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layer 30.

[0021] As shown in Figure 4A, the first internal electrode layer 31 has a first opposing portion 31A and a first leading portion 31B. The first opposing portion 31A is a region that faces the second internal electrode layer 32 with the dielectric layer 20 in between, and is located inside the laminate 10. The first leading portion 31B is a portion that is drawn out from the first opposing portion 31A to the first end face LS1, and is exposed to the first end face LS1.

[0022] As shown in Figure 4B, the second internal electrode layer 32 has a second opposing portion 32A and a second leading portion 32B. The second opposing portion 32A is a region that faces the first internal electrode layer 31 with the dielectric layer 20 in between, and is located inside the laminate 10. The second leading portion 32B is a portion that is drawn out from the second opposing portion 32A to the second end face LS2, and is exposed to the second end face LS2.

[0023] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0025] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 1000 or less.

[0028] As shown in Figures 2 and 3, the first main surface-side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface-side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface-side outer layer 12 and the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 4A and 4B show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0030] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3, 4A, and 4B show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0031] The laminate 10 has an end-face side outer layer. The end-face side outer layer has a first end-face side outer layer LG1 and a second end-face side outer layer LG2. The first end-face side outer layer LG1 is a portion located between the opposing electrode portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion 31B. That is, the first end-face side outer layer LG1 is an assembly of the portions of multiple dielectric layers 20 on the first end face LS1 side and multiple first lead portions 31B. The second end-face side outer layer LG2 is a portion located between the opposing electrode portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion 32B. That is, the second end-face side outer layer LG2 is an assembly of the portions of multiple dielectric layers 20 on the second end face LS2 side and multiple second lead portions 32B. Figures 2, 4A, and 4B show the longitudinal range L of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called the L gap or end gap.

[0032] As shown in Figures 1 and 2, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10, and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0033] The basic configurations of the first external electrode 40A and the second external electrode 40B are the same. Furthermore, the first external electrode 40A and the second external electrode 40B have shapes that are generally symmetrical with respect to the WT cross-section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to explain the first external electrode 40A and the second external electrode 40B separately, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0034] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is in contact with the first lead-out portion 31B of each of the multiple first internal electrode layers 31 exposed on the first end face LS1. As a result, the first external electrode 40A is electrically connected to the multiple first internal electrode layers 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is in contact with the second lead-out portion 32B of each of the multiple second internal electrode layers 32 exposed on the second end face LS2. As a result, the second external electrode 40B is electrically connected to the multiple second internal electrode layers 32. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, within the laminate 10, capacitance is formed when the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0037] As shown in FIG. 2, FIG. 4A and FIG. 4B, the first external electrode 40A comprises a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. Further, the second external electrode 40B comprises a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0038] It should be noted that the basic configurations of the first base electrode layer 50A and the second base electrode layer 50B are the same. Further, the first base electrode layer 50A and the second base electrode layer 50B each have a generally plane-symmetrical shape with respect to the WT cross-section at the center in the length direction L of the multilayer ceramic capacitor 1. Therefore, hereinafter, when there is no need to separately describe the first base electrode layer 50A and the second base electrode layer 50B, the first base electrode layer 50A and the second base electrode layer 50B may be collectively referred to as the base electrode layer 50.

[0039] It should be noted that the basic configurations of the first plating layer 60A and the second plating layer 60B are the same. Further, the first plating layer 60A and the second plating layer 60B each have a generally plane-symmetrical shape with respect to the WT cross-section at the center in the length direction L of the multilayer ceramic capacitor 1. Therefore, hereinafter, when there is no need to separately describe the first plating layer 60A and the second plating layer 60B, the first plating layer 60A and the second plating layer 60B may be collectively referred to as the plating layer 60.

[0040] Accordingly, the external electrode 40 comprises a base electrode layer 50 and a plating layer 60 disposed on the base electrode layer 50.

[0041] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead-out portion 31B of each of the plurality of first internal electrode layers 31 exposed at the first end face LS1. In the present embodiment, the first base electrode layer 50A is formed to extend from above the first end face LS1 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1 and a part of the second side surface WS2.

[0042] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portion 32B of each of the plurality of second internal electrode layers 32 exposed at the second end face LS2. In the present embodiment, the second base electrode layer 50B extends from above the second end face LS2 to part of the first main surface TS1, part of the second main surface TS2, and part of the first side face WS1 and part of the second side face WS2.

[0043] In the present embodiment, the first base electrode layer 50A and the second base electrode layer 50B are baked layers. It is preferable that the baked layer contains a metal component and either one of a glass component or a ceramic component, or contains both of them. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au and the like. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li and the like. For the ceramic component, the same type of ceramic material as the dielectric layer 20 may be used, or a different type of ceramic material may be used. The ceramic component is, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ and contains at least one selected from the above.

[0044] The baked layer is formed, for example, by applying a conductive paste containing glass and metal to the laminate 10 and baking the paste. The baked layer can be formed by co-firing a pre-firing laminated chip, which is the material of the laminate 10 having a plurality of internal electrodes and dielectric layers, and the conductive paste applied to the laminated chip. Alternatively, after firing the laminated chip to obtain the laminate 10, the baked layer may also be formed by applying the conductive paste to the laminate 10 and baking the paste. In the case of the co-firing method described above, it is preferable that the baked layer is formed by baking a material added with a ceramic material instead of a glass component. In that case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the ceramic material to be added. Note that the baked layer may be a multi-layer structure.

[0045] The thickness of the first base electrode layer 50A located on the first end face LS1, corresponding to the length L, is preferably, for example, 10 μm to 220 μm in the central part of the first base electrode layer 50A in the lamination direction T and width direction W.

[0046] The thickness of the second base electrode layer 50B located on the second end face LS2, corresponding to the length L, is preferably, for example, 10 μm to 220 μm in the central part of the stacking direction T and width direction W of the second base electrode layer 50B.

[0047] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided in this portion, corresponding to the lamination direction T, is preferably, for example, 3 μm to 40 μm, at the center of the first base electrode layer 50A in the length direction L and width direction W.

[0048] When the first base electrode layer 50A is also provided on a part of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided in this part, corresponding to the width direction W, is preferably, for example, 3 μm or more and 40 μm or less in the central part of the length direction L and the lamination direction T of the first base electrode layer 50A provided in this part.

[0049] When a second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the lamination direction T, is preferably, for example, 3 μm to 40 μm, at the center of the second base electrode layer 50B in the length direction L and width direction W.

[0050] When a second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the width direction W, is preferably, for example, 3 μm to 40 μm, at the center of the second base electrode layer 50B provided in this portion, in the length direction L and the lamination direction T.

[0051] The first plating layer 60A is positioned to cover the first underlay electrode layer 50A.

[0052] The second plating layer 60B is positioned to cover the second under electrode layer 50B.

[0053] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0054] The first plating layer 60A is arranged to cover the first underlay electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0055] The second plating layer 60B is arranged to cover the second under electrode layer 50B. In this embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0056] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B and the second Sn plating layer 62B is preferably between 1 μm and 15 μm.

[0057] The above describes the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminate 10 and the external electrode 40, is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. Furthermore, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is 0.05 mm or more and 10 mm or less. Also, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is 0.05 mm or more and 10 mm or less.

[0058] Figure 5 is an enlarged cross-sectional view of the portion indicated by V in Figure 2. The basic configuration of the first external electrode 40A and the second external electrode 40B is the same, and the first external electrode 40A and the second external electrode 40B have a shape that is generally symmetrical with respect to the WT cross section in the center of the length L of the multilayer ceramic capacitor 1. Therefore, in the following description, Figure 5, which shows a part of the first external electrode 40A, will be used as a representative example of the first external electrode 40A and the second external electrode 40B. As shown in Figure 5, the multilayer ceramic capacitor 1 according to this embodiment has a non-metallic layer NM between the base electrode layer 50 and the plating layer 60.

[0059] The non-metallic layer NM is, for example, a void layer. The non-metallic layer NM may also be a glass layer. The non-metallic layer NM may also be a layer in which void layers and glass layers are mixed.

[0060] The thickness of the nonmetallic layer NM is preferably 0.1 μm or more and 0.2 μm or less. For example, when the nonmetallic layer NM is placed between the base electrode layer 50 placed on the first end face and the plating layer 60 placed on the base electrode layer 50, the thickness of the nonmetallic layer NM in the length direction L in a cross-sectional view parallel to the length direction L and the height direction T (LT cross-sectional view) is preferably 0.1 μm or more and 0.2 μm or less. In addition, the nonmetallic layer NM may be placed at one or more locations between the base electrode layer 50 placed on the first end face LS1 and the plating layer 60 placed on the base electrode layer 50. For example, in this embodiment, the nonmetallic layer NM is placed at two locations between the base electrode layer 50 placed on the first end face LS1 and the plating layer 60 placed on the base electrode layer 50.

[0061] Furthermore, when a nonmetallic layer NM is placed between the base electrode layer 50, which is located on the first corner R portion R1 or the second corner R portion R2 as described later, and the plating layer 60, which is located on the base electrode layer 50, it is preferable that the thickness of the nonmetallic layer NM in the direction normal to the surface of the first corner R portion R1 or the second corner R portion R2 in an LT cross-sectional view is 0.1 μm or more and 0.2 μm or less. In addition, the nonmetallic layer NM may be placed at one or more locations between the base electrode layer 50, which is located on the first corner R portion R1 or the second corner R portion R2, and the plating layer 60, which is located on the base electrode layer 50. For example, in this embodiment, the nonmetallic layer NM is placed at two locations between the base electrode layer 50, which is located on the first corner R portion R1 and the second corner R portion R2, and the plating layer 60, which is located on the base electrode layer 50.

[0062] Furthermore, when a nonmetallic layer NM is placed between the base electrode layer 50 placed on the first main surface and the plating layer 60 placed on the base electrode layer 50, it is preferable that the thickness of the nonmetallic layer NM in the stacking direction T in the LT cross-sectional view is 0.1 μm or more and 0.2 μm or less. Also, the nonmetallic layer NM may be placed at one or more locations between the base electrode layer 50 placed on the first main surface TS1 and the plating layer 60 placed on the base electrode layer 50. For example, in this embodiment, the nonmetallic layer NM is placed at two locations between the base electrode layer 50 placed on the first main surface TS1 and the plating layer 60 placed on the base electrode layer 50, but it is not limited to this.

[0063] In a cross-sectional view using the LT (Longitude) method, the length of the non-metallic layer NM along the surface of the underlying electrode layer 50 is preferably 1 μm or more, and more preferably 3 μm or more. This more reliably suppresses the transmission of stress from the mounting surface to the laminate 10, and effectively suppresses the occurrence of cracks in the laminate. Furthermore, when multiple non-metallic layers NM are arranged between the underlying electrode layer 50 and the plating layer 60 arranged on the underlying electrode layer 50, in a cross-sectional view using the LT (Longitude) method, the length of each of the multiple non-metallic layers NM along the surface of the underlying electrode layer 50 is preferably 1 μm or more, and more preferably 3 μm or more. This more reliably suppresses the transmission of stress from the mounting surface to the laminate 10, and effectively suppresses the occurrence of cracks in the laminate.

[0064] In a cross-sectional view using the LT (Longitude) method, the length of the non-metallic layer NM along the surface of the underlying electrode layer 50 is preferably five times or more the thickness of the non-metallic layer NM, and more preferably ten times or more. This more reliably suppresses the transmission of stress from the mounting surface to the laminate 10, and effectively suppresses the occurrence of cracks in the laminate. Furthermore, when multiple non-metallic layers NM are arranged between the underlying electrode layer 50 and the plating layer 60 placed on the underlying electrode layer 50, in a cross-sectional view using the LT (Longitude) method, the length of each of the multiple non-metallic layers NM along the surface of the underlying electrode layer 50 is preferably five times or more, and more preferably ten times or more. This more reliably suppresses the transmission of stress from the mounting surface to the laminate 10, and effectively suppresses the occurrence of cracks in the laminate.

[0065] In a cross-sectional view using the LT (Longitude) method, the ratio B / A of the length B of the non-metallic layer NM disposed on the base electrode layer 50 along the contour line of the base electrode layer 50 to the length A along the contour line of the surface of the base electrode layer 50 is preferably 10% or more and 80% or less. In a cross-sectional view using the LT (Longitude) method, the ratio B / A of the length B of the non-metallic layer NM disposed on the base electrode layer 50 along the contour line of the surface of the base electrode layer 50 to the length A along the contour line of the surface of the base electrode layer 50 is more preferably 10% or more and 40% or less. When multiple non-metallic layers NM are disposed between the base electrode layer 50 and the plating layer 60 disposed on the base electrode layer 50, the length B used is the sum of the lengths of each of the multiple non-metallic layers NM along the surface of the base electrode layer 50.

[0066] The first main surface TS1 is, for example, the main surface facing the mounting surface. The nonmetallic layer NM is preferably disposed between the base electrode layer 50 located on the first main surface TS1 and the plating layer 60 on the base electrode layer 50. Furthermore, the nonmetallic layer NM may also be disposed between the base electrode layer 50 located on the second main surface TS2 and the plating layer 60 on the base electrode layer 50. In addition, the nonmetallic layer NM is preferably disposed between the base electrode layer 50 located on at least one of the first end surface LS1 and the second end surface LS2 and the plating layer 60 on the base electrode layer 50.

[0067] Here, the laminate 10 has a first corner R portion R1 that connects the first end face LS1 and the first main face TS1 by a curved surface, and a second corner R portion R2 that connects the second end face LS2 and the first main face TS1 by a curved surface. Furthermore, the basic configuration of the first corner R portion R1 and the second corner R portion R2 is the same, and the first corner R portion R1 and the second corner R portion R2 have a shape that is generally symmetrical with respect to the WT cross section at the center of the length L of the multilayer ceramic capacitor 1.Therefore, in the following, when it is not necessary to explain the first corner R portion R1 and the second corner R portion R2 separately, the first corner R portion R1 and the second corner R portion R2 may be collectively referred to as the corner R portion.

[0068] In this case, it is preferable that the nonmetallic layer NM is positioned between the base electrode layer 50 located at the first corner R portion R1 and the second corner R portion R2, and the plating layer 60 located on the base electrode layer 50.

[0069] Thus, the nonmetallic layer NM of this embodiment preferably comprises a first main surface-side nonmetallic layer NMT disposed between a base electrode layer 50 disposed on the first main surface TS1 and a plating layer 60 disposed on the base electrode layer 50; an end-face-side nonmetallic layer NML disposed between a base electrode layer 50 disposed on the first end face LS1 and the second end face LS2 and a plating layer 60 disposed on the base electrode layer 50; and a corner R-part nonmetallic layer NMR disposed between a base electrode layer 50 disposed on the first corner R-part R1 and the second corner R-part R2 and a plating layer 60 disposed on the base electrode layer 50. The first main surface-side nonmetallic layer NMT and the corner R-part nonmetallic layer NMR may be connected. The corner R-part nonmetallic layer NMR and the end-face-side nonmetallic layer NML may be connected. This allows for more effective stress release during substrate deflection, thereby suppressing the occurrence of cracks in the laminate 10. The end-face nonmetallic layer NML and the corner R portion nonmetallic layer NMR may be separated. The corner R portion nonmetallic layer NMR and the end-face nonmetallic layer NML may be separated. This allows for effective stress release during substrate deflection while maintaining a state in which the base electrode layer 50 and the plating layer 60 are appropriately bonded.

[0070] Furthermore, in a cross-sectional view parallel to the length direction L and the height direction T (LT cross-sectional view), the ratio of the length NMTL of the first main surface-side nonmetallic layer NMT along the surface of the base electrode layer 50 to the length TSL of the base electrode layer 50 arranged on the first main surface TS1 is greater than the ratio of the length NMLL of the end face-side nonmetallic layer NML along the base electrode layer 50 to the length LSL of the base electrode layer 50 arranged on the first end face LS1 and the second end face LS2. Note that if multiple nonmetallic layers NM are arranged between the base electrode layer 50 and the plating layer 60 arranged on the base electrode layer 50, the total length obtained by adding the lengths of each of the multiple first main surface-side nonmetallic layers NMT along the surface of the base electrode layer 50 is used as the length NMTL. Furthermore, the length NMLL mentioned above is the total length obtained by adding the lengths of each of the multiple end-face side non-metallic layers NML along the surface of the underlying electrode layer 50. To illustrate with the example in Figure 5, the length NMTL mentioned above is the total length obtained by adding the lengths NMTL1 and NMTL2 of the two first main surface side non-metallic layers NMT. ​​The length NMLL mentioned above is the total length obtained by adding the lengths NMLL1 and NMLL2 of the two end-face side non-metallic layers NML.

[0071] Furthermore, the first main surface nonmetallic layer NMT and the corner R portion nonmetallic layer NMR may be present. This makes it possible to effectively release stress when the substrate flexes. In this case, the end face nonmetallic layer NML may or may not be present. If the end face nonmetallic layer NML is present, stress can be released more effectively. If the end face nonmetallic layer NML is not present, stress can be released when the substrate flexes while maintaining a state in which the base electrode layer 50 and the plating layer 60 are appropriately bonded. In addition, since a large bonding area between the base electrode layer 50 and the plating layer 60 can be secured, ESR characteristics can also be secured.

[0072] Furthermore, the substrate may have a first main surface nonmetallic layer NMT and an end surface nonmetallic layer NML. This allows for effective stress relief during substrate deflection. In this case, the substrate may or may not have a corner R nonmetallic layer NMR. If a corner R nonmetallic layer NMR is present, stress relief can be achieved more effectively. If a corner R nonmetallic layer NMR is not present, stress can be relieved during substrate deflection while maintaining a state of appropriate bonding between the base electrode layer 50 and the plating layer 60. In addition, since the bonding area between the base electrode layer 50 and the plating layer 60 can be secured, ESR characteristics can also be ensured.

[0073] Furthermore, a nonmetallic layer NMR at the corner radius and a nonmetallic layer NML on the end face side may be present. This allows stress to be released when the substrate flexes. In this case, a first nonmetallic layer NMT on the main surface side may or may not be present. If the first nonmetallic layer NMT on the main surface side is present, stress can be released more effectively. If the first nonmetallic layer NMT on the main surface side is not present, stress can be released when the substrate flexes while maintaining a state in which the base electrode layer 50 and the plating layer 60 are appropriately bonded. In addition, since the bonding area between the base electrode layer 50 and the plating layer 60 can be secured, ESR characteristics can also be secured.

[0074] Furthermore, the substrate may have at least one of the following: the first main surface nonmetallic layer NMT, the corner R portion nonmetallic layer NMR, and the end face side nonmetallic layer NML. This allows stress to be released when the substrate flexes. For example, only the first main surface side nonmetallic layer NMT may be present. This also allows stress to be released effectively. For example, only the corner R portion nonmetallic layer NMR may be present. This allows stress to be released when the substrate flexes while maintaining a state in which the base electrode layer 50 and the plating layer 60 are appropriately bonded. For example, only the end face side nonmetallic layer NML may be present. This allows stress to be released when the substrate flexes while maintaining a state in which the base electrode layer 50 and the plating layer 60 are bonded. In these cases, a large bonding area between the base electrode layer 50 and the plating layer 60 can be secured, and thus ESR characteristics can also be secured.

[0075] Next, the measurement methods for various parameters in this embodiment will be described. These parameters can be confirmed by the following methods.

[0076] First, the multilayer ceramic capacitor is polished from either the first or second side until it reaches a point halfway across its width (W). This exposes the LT cross-section at the center of the multilayer ceramic capacitor's width.

[0077] The LT cross-section exposed by polishing is observed using a scanning electron microscope (SEM). Specifically, the portion of the LT cross-section including the underlying electrode layer is captured as a backscattered electron image. In the backscattered electron image, differences in resistance values ​​are reflected as contrast. Therefore, metallic parts appear white, and non-metallic parts appear black. The observation magnification is set according to the content to be observed. For example, if the presence of a non-metallic layer NM is to be confirmed for each part, the imaging magnification is set to 2000x, and the portion A1 to A6 shown in Figure 2 of the backscattered electron image is set as the measurement target range.

[0078] Specifically, the measurement target range A1 is set to the region between the base electrode layer 50 and the plating layer 60 located on the first end face LS1.

[0079] Furthermore, the measurement target range A2 is set to the region between the base electrode layer 50 and the plating layer 60 located at the first corner R portion R1.

[0080] Furthermore, the measurement target range A3 is set to the region between the underlay electrode layer 50 and the plating layer 60, which are placed on the first main surface TS1.

[0081] Specifically, the measurement target range A4 is set to the region between the underlay electrode layer 50 and the plating layer 60 located on the second end face LS2.

[0082] Furthermore, the measurement target range A5 is set to the region between the base electrode layer 50 and the plating layer 60 located at the second corner R portion R2.

[0083] Furthermore, the measurement target range A6 is set to the region between the underlay electrode layer 50 and the plating layer 60, which are located on the first main surface TS1.

[0084] Image analysis software (Mitani Corporation, WINROOF) is used to binarize the backscattered electron image of the underlying electrode layer, identifying the metallic portion and the multiple non-metallic portions present within it. Using this binarized image, various parameters such as the thickness of the non-metallic portion, its length along the surface of the underlying electrode layer, and the length of the non-metallic portions placed on the underlying electrode layer along the surface of the underlying electrode layer are measured.

[0085] Various parameters are measured for two measurement target areas each of the first end face LS1 and the second end face LS2, the first corner radius R1 and the second corner radius R2, and the first main surface TS1 on the first end face LS1 side and the second main surface TS2 on the second end face LS2 side.

[0086] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0087] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0088] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known substances.

[0089] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0090] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer portion 12 on the first main surface TS1 side. On top of this, dielectric sheets with printed patterns for the first internal electrode layer 31 and dielectric sheets with printed patterns for the second internal electrode layer 32 are sequentially stacked to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer portion 13 on the second main surface TS2 side. This completes the production of the laminated sheet.

[0091] Laminated sheets are pressed in the height direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0092] The laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0093] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0094] A conductive paste, which will serve as the base electrode layer, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer is a baked layer. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer. The temperature of this baking process is preferably 700°C to 900°C.

[0095] Furthermore, when firing the laminated chip before firing and the conductive paste applied to the laminated chip simultaneously, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminate 10 with a baked layer.

[0096] Subsequently, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0097] The non-metallic layer NM, which is placed between the base electrode layer 50 and the plating layer 60, is formed, for example, by performing a predetermined treatment on the surface of the base electrode layer 50 formed on the laminate 10.

[0098] For example, if it is desired to form a nonmetallic layer NM, which is a void, between the base electrode layer 50 and the plating layer 60, first an organic substance is applied to the portion of the surface of the base electrode layer 50 where the nonmetallic layer NM is to be formed. Then, the process of forming the plating layer 60 is carried out as described above, and after the plating film is formed, the organic substance is volatilized, thereby forming the nonmetallic layer NM, which is a void, between the base electrode layer 50 and the plating layer 60.

[0099] Furthermore, if it is desired to form a non-metallic layer NM, which is a glass layer, between the base electrode layer 50 and the plating layer 60, a glass layer is formed on the portion of the surface of the base electrode layer 50 where the non-metallic layer NM is to be formed. Subsequently, by performing the process of forming the plating layer 60 as described above, the non-metallic layer NM, which is a glass layer, is formed between the base electrode layer 50 and the plating layer 60.

[0100] Furthermore, if it is desired to form a non-metallic layer NM, which is a glass layer, between the base electrode layer 50 and the plating layer 60, the conductive paste that will become the baking layer should contain a larger amount of glass components than usual. In particular, it is preferable to contain a larger amount of glass components in the conductive paste used for the portion of the surface of the base electrode layer 50 where the non-metallic layer NM is to be formed. Subsequently, during the baking process, glass is discharged onto the surface of the baking layer, and a glass layer is formed. After that, by performing the process to form the plating layer 60 as described above, the non-metallic layer NM, which is a glass layer, is formed between the base electrode layer 50 and the plating layer 60.

[0101] Through the above manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0102] Note that the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 5. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 6A, 6B, and 6C.

[0103] The multilayer ceramic capacitor 1 shown in Figure 6A is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 6B is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 6C is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0104] The multilayer ceramic capacitor 1 may be a two-terminal type with two external electrodes, or a multi-terminal type with multiple external electrodes.

[0105] In the embodiments described above, a multilayer ceramic capacitor was given as an example of a multilayer ceramic electronic component in which a dielectric layer 20 made of dielectric ceramic is used as the ceramic layer. However, the multilayer ceramic electronic components of this disclosure are not limited to this. For example, the ceramic electronic components of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer, and thermistors using semiconductor ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, and examples of semiconductor ceramics include spinel ceramics.

[0106] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following effects.

[0107] The multilayer ceramic capacitor 1 according to the embodiment includes a plurality of dielectric layers 20 (ceramic layers 20) and a plurality of internal electrode layers 30 (internal conductor layers 30), and comprises a laminate 10 having a first main surface TS1 and a second main surface TS2 facing each other in the height direction T, a first side surface WS1 and a second side surface WS2 facing each other in the width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing each other in the length direction L perpendicular to the height direction T and the width direction W, and a pair of external electrodes 40 spaced apart from each other at both ends of the laminate 10 in the length direction L, the external electrodes 40 having a base electrode layer 50 containing a metal component and a plating layer 60 disposed on the base electrode layer 50, and a non-metallic layer NM between the base electrode layer 50 and the plating layer 60.

[0108] This makes it possible to suppress the occurrence of cracks in the laminate when the substrate is deflected.

[0109] In the multilayer ceramic capacitor 1 according to this embodiment, it is preferable that the nonmetallic layer NM includes a void layer.

[0110] This makes it possible to more effectively suppress the occurrence of cracks in the laminate when the substrate is deflected.

[0111] In the multilayer ceramic capacitor 1 according to this embodiment, the nonmetallic layer NM preferably includes a glass layer.

[0112] This ensures moisture resistance while suppressing the occurrence of cracks in the laminate when the substrate flexes.

[0113] In the multilayer ceramic capacitor 1 according to this embodiment, the thickness of the nonmetallic layer NM is preferably 0.1 μm or more and 0.2 μm or less.

[0114] This ensures moisture resistance while suppressing the occurrence of cracks in the laminate when the substrate flexes. Note that if the thickness of the non-metallic layer exceeds 0.2 μm, flexure resistance improves, and the effect of suppressing crack occurrence in the laminate when the substrate flexes is enhanced, but ESR and moisture resistance performance deteriorate. Furthermore, unintended plating peeling becomes more likely. On the other hand, if the thickness of the non-metallic layer is less than 0.1 μm, the effect on flexure resistance is limited.

[0115] In the multilayer ceramic capacitor 1 according to the embodiment, in a cross-sectional view parallel to the length direction L and the height direction T, the ratio B / A of the length B of the nonmetallic layer NM disposed on the base electrode layer 50 along the surface of the base electrode layer 50 to the length A along the surface of the base electrode layer 50 is preferably 10% or more and 80% or less.

[0116] This ensures moisture resistance while suppressing the occurrence of cracks in the laminate when the substrate flexes. When the ratio B / A exceeds 80%, flexure resistance improves, and the effect of suppressing crack occurrence in the laminate when the substrate flexes is enhanced, but ESR and moisture resistance performance decrease. Furthermore, unintended plating peeling becomes more likely. On the other hand, when the ratio B / A is less than 10%, the effect on flexure resistance is limited.

[0117] In the multilayer ceramic capacitor 1 according to this embodiment, it is preferable that the nonmetallic layer NM is placed between the base electrode layer 50 and the plating layer 60, which are arranged on the first main surface TS1.

[0118] This makes it possible to more effectively suppress the occurrence of cracks in the laminate when the substrate is deflected.

[0119] In the multilayer ceramic capacitor 1 according to the embodiment, it is preferable that the nonmetallic layer NM is positioned between the base electrode layer 50, which is located on the first end face LS1 and the second end face LS2, and the plating layer 60.

[0120] This makes it possible to suppress the occurrence of cracks in the laminate when the substrate is deflected, and also suppress the occurrence of chipping cracks due to external impacts.

[0121] In the multilayer ceramic capacitor 1 according to this embodiment, the laminate 10 has a first corner R portion R1 that connects a first end face LS1 and a first main surface TS1 by a curved surface, and a second corner R portion R2 that connects a second end face LS2 and the first main surface TS1 by a curved surface, and it is preferable that the nonmetallic layer NM is disposed between the base electrode layer 50 arranged in the first corner R portion R1 and the second corner R portion R2 and the plating layer 60.

[0122] This makes it possible to suppress the occurrence of cracks in the laminate when the substrate is deflected, and also suppress the occurrence of chipping cracks due to external impacts.

[0123] In the multilayer ceramic capacitor 1 according to the embodiment, the nonmetallic layer NM has a first main surface-side nonmetallic layer NMT disposed between a base electrode layer 50 disposed on a first main surface TS1 and a plating layer 60, and an end face-side nonmetallic layer NML disposed between a base electrode layer 50 disposed on a first end face LS1 and a second end face LS2 and a plating layer 60. Preferably, the ratio of the length of the first main surface-side nonmetallic layer, which is the ratio of the length NMTL of the first main surface-side nonmetallic layer NMT along the surface of the base electrode layer 50 to the length TSL of the base electrode layer 50 disposed on the first main surface TS1, is greater than the ratio of the length NMLL of the end face-side nonmetallic layer NML along the base electrode layer 50 to the length LSL of the base electrode layer 50 disposed on the first end face LS1 and the second end face LS2.

[0124] This ensures ESR and moisture resistance performance, suppresses unintended plating peeling, and prevents crack formation in the laminate when the substrate flexes.

[0125] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0126] 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 20 Dielectric layer (ceramic layer) 30 Internal electrode layer (internal conductor layer) 40 External electrode 50 Underlay electrode layer 60 Plating layer L Length direction LS1 First end face LS2 Second end face NM Nonmetallic layer T Height direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface

Claims

1. A laminate comprising a plurality of ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction; a pair of external electrodes spaced apart from each other at each end of the laminate in the length direction, the external electrodes comprising a base electrode layer containing a metal component and a plating layer disposed on the base electrode layer, and a non-metallic layer between the base electrode layer and the plating layer.

2. The multilayer ceramic electronic component according to claim 1, wherein the nonmetallic layer includes a void layer.

3. The multilayer ceramic electronic component according to claim 1, wherein the nonmetallic layer includes a glass layer.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the thickness of the nonmetallic layer is 0.1 μm or more and 0.2 μm or less.

5. In a cross-sectional view parallel to the length and height directions, the ratio B / A of the length B of the non-metallic layer disposed on the base electrode layer along the surface of the base electrode layer to the length A along the surface of the base electrode layer is 10% or more and 80% or less, according to any one of claims 1 to 4.

6. The multilayer ceramic electronic component according to any one of claims 1 to 5, wherein the nonmetallic layer is disposed between the under electrode layer and the plating layer, which are arranged on the first main surface.

7. The multilayer ceramic electronic component according to any one of claims 1 to 6, wherein the nonmetallic layer is disposed between the under electrode layer, which is arranged on the first end face and the second end face, and the plating layer.

8. The laminate has a first corner R portion connecting the first end face and the first main surface by a curved surface, and a second corner R portion connecting the second end face and the first main surface by a curved surface, and the nonmetallic layer is disposed between the base electrode layer arranged in the first corner R portion and the second corner R portion and the plating layer, the multilayer ceramic electronic component according to any one of claims 1 to 7.

9. The multilayer ceramic electronic component according to any one of claims 1 to 8, wherein the nonmetallic layer comprises a first main surface-side nonmetallic layer disposed between the underlay electrode layer disposed on the first main surface and the plating layer, and an end-face-side nonmetallic layer disposed between the underlay electrode layer disposed on the first end face and the second end face and the plating layer, wherein the ratio of the length of the first main surface-side nonmetallic layer along the surface of the underlay electrode layer to the length of the underlay electrode layer disposed on the first main surface is greater than the ratio of the length of the end-face-side nonmetallic layer along the underlay electrode layer to the length of the underlay electrode layer disposed on the first end face and the second end face.

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