Semiconductor device, electric circuit, and electronic apparatus

Abstract

A semiconductor device according to an embodiment of the present technology comprises a stacked semiconductor, a gate electrode, a source electrode, a drain electrode, a field plate electrode, and an insulating film. The gate electrode, the source electrode, and the drain electrode are provided above the stacked semiconductor. The source electrode and the drain electrode are provided at positions facing each other with the gate electrode interposed therebetween. The insulating film and the field plate electrode are provided above the stacked semiconductor and between the gate electrode and the drain electrode. The field plate electrode is provided above the stacked semiconductor via the insulating film. A gate-electrode-side edge of the field plate electrode has such a shape that a distance between the gate-electrode-side edge and the gate electrode varies depending on location.

Description

Semiconductor devices, electrical circuits, and electronic equipment

[0001] This technology relates to semiconductor devices, electrical circuits, and electronic equipment.

[0002] Nitride semiconductor high electron mobility transistors (HEMTs) possess characteristics such as high voltage resistance, high heat resistance, high saturation electron velocity, and high channel electron concentration. Therefore, they are expected to be applied to small, high-performance power conversion devices and high-frequency devices such as power amplifiers (see, for example, Patent Document 1).

[0003] Japanese Patent Publication No. 2004-20048

[0004] Incidentally, in nitride semiconductor-based HEMTs, suppression of current collapse is desirable. Therefore, it is desirable to provide semiconductor devices, electrical circuits, and electronic devices that can suppress current collapse.

[0005] A semiconductor device according to one embodiment of this technology comprises a multilayer semiconductor, a gate electrode, a source electrode, a drain electrode, a field plate electrode, and an insulating film. The gate electrode, source electrode, and drain electrode are provided above the multilayer semiconductor. The source electrode and drain electrode are provided at positions facing each other with the gate electrode in between. The insulating film and the field plate electrode are provided above the multilayer semiconductor and between the gate electrode and the drain electrode. The field plate electrode is provided above the multilayer semiconductor via the insulating film. In the field plate electrode, the edge on the gate electrode side has a shape in which the distance between the edge on the gate electrode side and the gate electrode varies depending on the location.

[0006] An electrical circuit according to one embodiment of this technology includes the semiconductor device described above.

[0007] An electronic device according to one embodiment of this technology includes the above-described semiconductor device.

[0008] Figure 1 is a cross-sectional view showing an example configuration of a semiconductor device according to one embodiment of this technology. Figure 2 is a cross-sectional view showing an example configuration of another part of the semiconductor device in Figure 1. Figure 3 is a plan view showing an example configuration of the semiconductor devices in Figures 1 and 2. Figure 4 is a cross-sectional view showing an example of the manufacturing process of the semiconductor devices in Figures 1 to 3. Figure 5 is a cross-sectional view showing an example of the manufacturing process following Figure 4. Figure 6 is a cross-sectional view showing an example of the manufacturing process following Figure 5. Figure 7 is a plan view showing an example of the manufacturing process following Figure 5. Figure 8 is a plan view showing an example of the manufacturing process following Figure 6. Figure 9 is a cross-sectional view showing an example of the manufacturing process following Figure 7. Figure 10 is a plan view showing a modified configuration of the semiconductor device in Figure 3. Figure 11 is a plan view showing a modified configuration of the semiconductor device in Figure 3. Figure 12 is a plan view showing a modified configuration of the gate electrode and field plate electrode. Figure 13 is a plan view showing a modified configuration of the gate electrode and field plate electrode. Figure 14 is a plan view showing a modified configuration of the gate electrode and field plate electrode. Figure 15 is a plan view showing a modified configuration of the semiconductor device in Figure 3. Figure 16 is a diagram showing an example of the circuit configuration of an antenna switch circuit. Figure 17 shows an example of a circuit configuration for a wireless communication device. Figure 18 shows an example of a circuit configuration for a power amplifier module.

[0009] The embodiments of this technology will be described in detail below with reference to the drawings.

[0010] <1. Background> High electron-mobility transistors (HEMTs) made of nitride semiconductors have characteristics such as high voltage resistance, high heat resistance, high saturation electron velocity, and high channel electron concentration. For this reason, they are expected to be applied to small and high-performance power conversion devices and high-frequency devices such as power amplifiers.

[0011] Incidentally, an example of a nitride semiconductor-based HEMT is a HEMT using AlInN as the barrier layer. In a HEMT using AlInN as the barrier layer, by setting the In composition of AlInN to approximately 17-18%, the lattice constant of the barrier layer can be made equal to the lattice constant of GaN used in the channel layer. Such a lattice-matched HEMT can be expected to have not only good crystallinity but also a high sheet electron concentration (>1 × 10⁻¹⁶). １３ cm－２ ) and low sheet resistance (<300 Ω / □) can be obtained. For this reason, nitride semiconductor-based HEMTs are considered to be very promising devices for high-frequency device applications.

[0012] In nitride semiconductor HEMTs, when the channel electron concentration is high, the depletion layer extension is suppressed when a voltage is applied to the gate or drain, resulting in an increased electric field strength near the gate. When the electric field strength near the gate increases, side effects such as a decrease in breakdown voltage, an increase in off-leak, and an increase in gate-drain capacitance occur. When a nitride semiconductor HEMT is applied to a power amplifier, an increase in gate-drain capacitance reduces the gain of the power amplifier. To address these problems, it is possible to weaken the electric field strength near the gate and further reduce the gate-drain capacitance by providing a field plate.

[0013] To fully obtain the effect of electric field strength reduction, the field plate needs to be as close to the gate as possible. However, forming the field plate close to the gate is not easy. When the field plate is formed in a separate process from the gate, manufacturing process issues necessitate forming the field plate at a certain distance from the gate. For example, when using a so-called gate-rust process, where the gate is formed after the ohmic process as a milling technique, microfabrication becomes difficult due to the unevenness of the substrate, making it difficult to bring the gate and field plate close together. Even when the field plate is formed simultaneously with the gate, manufacturing process issues necessitate forming the field plate at a certain distance from the gate. For example, when using lift-off technology, it is necessary to set a wider aperture spacing in the photoresist layer in order to leave the lift-off layer, which serves as the substrate for the photoresist layer, during development. Therefore, it is difficult to bring the gate and field plate close together.

[0014] Therefore, the applicant conceived of a technology that could reduce the distance between the gate and the field plate without being subject to manufacturing process constraints.

[0015] Preferred embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0016] Furthermore, in this specification and drawings, multiple components having substantially identical or similar functional configurations may be distinguished by adding different numbers after the same reference numeral. However, if there is no need to particularly distinguish each of multiple components having substantially identical or similar functional configurations, only the same reference numeral will be used. Also, similar components of different embodiments may be distinguished by adding different letters after the same reference numeral. However, if there is no need to particularly distinguish each of similar components, only the same reference numeral will be used.

[0017] Furthermore, the drawings referenced in the following description are for illustrating and facilitating understanding of one embodiment of this disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from those of the actual product. In addition, the semiconductor device shown in the drawings may be modified in design as appropriate, taking into consideration the following description and known technology. Also, in the description using a cross-sectional view of the semiconductor device, the vertical direction of the stacked structure of the semiconductor device corresponds to the direction in which the substrate and electrodes in the semiconductor device face each other, and may differ from the vertical direction according to the actual gravitational acceleration.

[0018] Furthermore, in the following explanation, expressions relating to size and shape do not refer only to mathematically defined numerical values ​​or geometrically defined shapes, but also include differences that are industrially acceptable in the manufacturing process of semiconductor devices, as well as shapes that are similar to those defined.

[0019] The explanation will proceed in the following order: 1. Embodiment (Semiconductor Device) 1-1. Configuration 1-2. Manufacturing Method 1-3. Effects 2. Modified Examples (Semiconductor Device) 3. Application Examples (Wireless Communication Devices, etc.)

[0020] <1. Embodiments> [1-1. Configuration] A semiconductor device 1 according to one embodiment of the present technology will be described. The semiconductor device 1 corresponds to a specific example of the "semiconductor device" in one embodiment of the present disclosure. The semiconductor device 1 is an element that functions as a high electron mobility transistor (HEMT). Figures 1 and 2 show examples of cross-sectional configurations of the semiconductor device 1. Figure 3 shows an example of a planar configuration of the semiconductor device 1. Figure 1 shows an example of a cross-sectional configuration along line A-A in Figure 3. Figure 2 shows an example of a cross-sectional configuration along line B-B in Figure 3.

[0021] The semiconductor device 1 comprises a substrate 10 and a multilayer semiconductor 20 formed on the substrate 10 as a crystal growth substrate. The multilayer semiconductor 20 corresponds to a specific example of the "multilayer semiconductor" in one embodiment of this disclosure. For crystal growth, for example, the MOCVD (metal organic chemical vapor deposition) method is used.

[0022] The multilayer semiconductor 20 is composed of a nitride semiconductor. The multilayer semiconductor 20 has a heterojunction structure including a buffer layer 21, a channel layer 22, a spacer layer 23, a barrier layer 24, and a cap layer 25, as shown in Figures 1 and 2, for example. In the multilayer semiconductor 20, electrons accumulate at a high concentration near the heterojunction interface of the channel layer 22, forming a so-called two-dimensional electron gas region 28 (2DEG). This two-dimensional electron gas region 28 exhibits high electron mobility. In particular, the barrier layer 24 induces an extremely high electron concentration on the surface of the channel layer 22.

[0023] The substrate 10 is made of, for example, a semi-insulating single-crystal gallium nitride (GaN), which is a group III-V compound semiconductor. By mitigating the lattice constant mismatch with the buffer layer 21, a substrate with a different lattice constant from the channel layer 22 can be used for the substrate 10. Examples of substrates with a different lattice constant from the channel layer 22 include silicon (Si) substrates, silicon carbide (SiC) substrates, and sapphire substrates. As a Si substrate, for example, a single-crystal Si(111) substrate with the (111) plane as the main plane is preferred.

[0024] The buffer layer 20 is made of a nitride semiconductor formed on the substrate 10 by epitaxial growth. When the lattice constants of the substrate 10 and the channel layer 22 are different from each other, controlling the lattice constant by means of the buffer layer 20 can improve the crystal quality of the channel layer 22 and control the warpage of the substrate 10 after the channel layer 22 is formed. For example, it is assumed that the substrate 10 is a single-crystal Si substrate and the channel layer 22 is a GaN layer. In this case, the buffer layer 20 is, for example, Al ｘ１ Ga （１－ｘ１－ｙ１） In ｙ１ N (0≦x1≦1, 0≦y1<1, 0<x1+y1≦1). The buffer layer 20 is made of, for example, aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (AlInGaN).

[0025] The channel layer 22 constitutes a part of a current path between a source electrode 31 described later and a drain electrode 32 described later. The channel layer 22 is a region where carriers (two-dimensional electron gas) are accumulated due to a difference in polarization charge amount between the channel layer 22 and the barrier layer 40. The channel layer 22 is made of a nitride semiconductor formed on the buffer layer 20 by epitaxial growth. The channel layer 22 is, for example, Al ｘ２ Ga （１－ｘ２－ｙ２） In ｙ２ N (0≦x2<1, 0≦y2<1, x2+y2≦1). The channel layer 30 is made of, for example, GaN, AlGaN or AlInGaN. The channel layer 30 may be made of undoped GaN to which no impurities are added. This suppresses impurity scattering of carriers in the channel layer 30 and realizes carrier transport with high mobility.

[0026] A back barrier layer may be provided between the channel layer 22 and the buffer layer 20. The back barrier layer is made of, for example, AlGaN or indium gallium nitride (InGaN). As long as the back barrier layer is a material that forms a conduction band barrier from the channel layer 22 toward the buffer layer 20, it may be Al ｘ３Ga （１－ｘ３－ｙ３） In ｙ３ N (0≦x3≦1, 0≦y3≦1, x3+y3≦1) may be used for configuration.

[0027] The spacer layer 23 is formed of a nitride semiconductor formed by epitaxial growth on the channel layer 22. The spacer layer 23 is made of, for example, AlN. Assume that the spacer layer 23 made of binary compound AlN is provided between the channel layer 22 and the barrier layer 24. At this time, carriers (two-dimensional electron gas) are generated at the interface between the spacer layer 23 and the channel layer 22. The distance between the barrier layer 24 and the two-dimensional electron gas in this case is increased by the thickness of the spacer layer 23, compared with the distance between the barrier layer 24 and the two-dimensional electron gas when the spacer layer 23 is not provided. As a result, the influence of alloy scattering from the barrier layer 24 formed of a ternary or quaternary compound is reduced, and carrier mobility can be increased. The spacer layer 23 may contain Ga or In due to the influence of diffusion from the channel layer 22 or the barrier layer 24. The spacer layer 23 may be Al ｘ４ Ga （１－ｘ４－ｙ４） In ｙ４ N (0≦x4<1, 0≦y4<1, x4+y4≦1) may be used for configuration. If a decrease in carrier mobility is acceptable, the spacer layer 23 may be omitted.

[0028] The barrier layer 24 is formed of a nitride semiconductor formed by epitaxial growth on the spacer layer 23. The barrier layer 24 is made of, for example, aluminum indium nitride (AlInN). Assume that the channel layer 22 is made of GaN. In this case, the barrier layer 24 may be made of AlInN with an In composition of 17 to 18% that lattice-matches with GaN. The barrier layer 24 may be made of AlInN with a low In composition to an extent that does not impair crystallinity, in order to achieve reduction of on-resistance through lower sheet resistance. Examples of the In composition ratio that does not impair crystallinity include 10% or 14%.

[0029] The material used for the barrier layer 24 may be a nitride semiconductor in which a two-dimensional electron gas accumulates in the channel layer 22 due to the difference in polarization charge between the barrier layer 24 and the channel layer 22. The barrier layer 24 can be any nitride semiconductor material such as Al. ｘ５ Ga （１－ｘ５－ｙ５） In ｙ５ It may be composed of N (0 ≤ x 5 ≤ 1, 0 ≤ y 5 < 1, x 5 + y 5 ≤ 1). The barrier layer 24 is made of Al without impurities. ｘ５ Ga （１－ｘ５－ｙ５） In ｙ５ It may also be composed of N. In this case, impurity scattering of carriers in the channel layer 22 is suppressed, and carrier transport with high mobility is realized. When increasing the two-dimensional electron gas concentration, a nitride semiconductor doped with n-type impurities such as Si and Ge may be used for the barrier layer 24.

[0030] The sheet carrier concentration, mainly consisting of two-dimensional electron gas, is 7 × 10⁻⁶. １２ cm －２ The value may be greater than this. The sheet resistance may be less than 300 Ω / □. When the barrier layer 24 is made of AlInN with an In composition of 17-18% that is lattice-matched with GaN, the sheet carrier concentration mainly consisting of two-dimensional electron gas is 1 × 10 １３ cm －２ It can be a larger value than this. In this case, the sheet resistance can be a value in the range of 180 Ω / □ to 250 Ω / □. The sheet carrier concentration and sheet resistance are not limited to the above values ​​near the gate electrode and may be controlled by the gate formation process to be a desired value. The barrier layer 24 may be formed directly on the channel layer 22 without the spacer layer 23.

[0031] The cap layer 25 is composed of a nitride semiconductor formed on the barrier layer 24 by epitaxial growth. The cap layer 25 is composed of, for example, GaN. When a high-Al composition material such as AlInN is used as the material for the barrier layer 24, the high-Al composition material is easily oxidized in the atmosphere. By forming the cap layer 25 on the barrier layer 24, oxidation of the barrier layer 24 can be suppressed. If oxidation of the barrier layer 24 is not a problem, the cap layer 25 may be omitted.

[0032] The multilayer semiconductor 20 is provided with recesses 29a and 29b, which reach the channel layer 22, at locations facing the source electrode 31 and drain electrode 32, which will be described later. The recesses 29a and 29b are formed on the multilayer semiconductor 20 by, for example, dry etching or wet etching. The recesses 29a and 29b are deep enough so that the two-dimensional electron gas region 28 is exposed on the inner walls of the recesses 29a and 29b. The recesses 29a and 29b are deep enough to form a depression of about 20 nm in the channel layer 22. The side walls of the recesses 29a and 29b are, for example, parallel to the normal of the substrate 10. The side walls of the recesses 29a and 29b may also be tapered, for example, intersecting the normal of the substrate 10.

[0033] The multilayer semiconductor 20 is further composed of contact layers 26 and 27, as shown in Figures 1 and 2, for example. Contact layer 26 is formed in recess 29a. Contact layer 27 is formed in recess 29b. Contact layer 26 is in contact with a two-dimensional electron gas region 28 exposed on the inner wall of recess 29a. Contact resistance can be reduced by contacting the two-dimensional electron gas region 28 with contact layers 26 and 27. Contact layer 27 is in contact with a two-dimensional electron gas region 28 exposed on the inner wall of recess 29b.

[0034] The contact layers 26 and 27 are formed such that their outermost surfaces are higher than the outermost surface of the cap layer 25. The outermost surfaces of the contact layers 26 and 27 may be at the same height as the outermost surface of the cap layer 25, or even lower, as long as the contact resistance does not increase or the increase in contact resistance is within an acceptable range. The contact layers 26 and 27 are composed of nitride semiconductors formed by methods such as MOCVD, MBE (Molecular Beam Epitaxy), PLD (Pulsed Laser Deposition), and sputtering. The contact layers 26 and 27 may have C-axis oriented surfaces as their main component. The contact layers 26 and 27 may be composed of polycrystalline or amorphous materials.

[0035] The contact layers 26 and 27 may be composed of nitride semiconductors doped with a high concentration of n-type impurities. This reduces the contact resistance between the contact layer 26 and the source electrode 31 described later. It also reduces the contact resistance between the contact layer 27 and the drain electrode 32 described later. Examples of n-type impurities added to the contact layers 26 and 27 include Si and Ge. The carrier concentration of the contact layers 26 and 27 is 1 × 10⁻⁶. １９ cm －３ The values ​​may be greater than or equal to the carrier concentration. During the process of forming the contact layers 26 and 27, n-type impurities at a concentration equal to or greater than the carrier concentration are added to the contact layers 26 and 27. The n-type impurities may be added to the contact layers 26 and 27 while they are being deposited. The n-type impurities may also be added after the contact layers 26 and 27 have been deposited, for example, by ion implantation or diffusion. The sheet resistance of the contact layers 26 and 27 may be 250 Ω / □ or less. The carrier mobility of the contact layers 26 and 27 is 30 cm². ２ It may be greater than / V·s. Contact layers 26 and 27 are Al ｘ６ Ga （１－ｘ６－ｙ６） In ｙ６ It may be constructed by N (0 ≤ x6 ≤ 1, 0 ≤ y6 ≤ 1, x6 + y6 ≤ 1).

[0036] The semiconductor device 1 further comprises a source electrode 31, a drain electrode 32, a gate electrode 33, a field plate electrode 34, and an insulating film 40. The source electrode 31, drain electrode 32, gate electrode 33, field plate electrode 34, and insulating film 40 are provided above the multilayer semiconductor 20. The drain electrode 32 and gate electrode 33 are provided in positions facing each other with the gate electrode 33 in between. The insulating film 40 is provided between the gate electrode 33 and the drain electrode 32. The field plate electrode 34 is provided above the multilayer semiconductor 20 via the insulating film. The field plate electrode 34 is connected to the source electrode 31 via wiring 50. The field plate electrode 34 may, if necessary, not be connected to any of the source electrode 31, drain electrode 32, and gate electrode 33, and may be electrically floating. The field plate electrode 34 may, if necessary, be connected to the gate electrode 33 or to the drain electrode 32.

[0037] The source electrode 31 corresponds to a specific example of the "source electrode" in one embodiment of the present disclosure. The drain electrode 32 corresponds to a specific example of the "drain electrode" in one embodiment of the present disclosure. The gate electrode 33 corresponds to a specific example of the "gate electrode" in one embodiment of the present disclosure. The field plate electrode 34 corresponds to a specific example of the "field plate electrode" in one embodiment of the present disclosure. The insulating film 40 corresponds to a specific example of the "insulating film" in one embodiment of the present disclosure.

[0038] The insulating film 40 is, for example, SiN, SiO ２ , SiON or Al ２ O ３ The insulating film 40 is provided with openings 40a, 40b, and 40c. Opening 40a is provided in a location facing the contact layer 26 and the source electrode 31. Opening 40b is provided in a location facing the contact layer 27 and the drain electrode 32. Opening 40c is provided in a location facing the gate electrode 33. The gate electrode 33 is in contact with the cap layer 25 through opening 40c.

[0039] The source electrode 31 is formed on the contact layer 26. The source electrode 31 is in contact with the contact layer 26. The drain electrode 32 is formed on the contact layer 27. The drain electrode 32 is in contact with the contact layer 27. The source electrode 31 and the drain electrode 32 are laminates containing, for example, Ti, Al, Ni, and Au in order from the contact layer 26 and 27 sides. The source electrode 31 and the drain electrode 32 are heat-treated as needed. The gate electrode 33 is laminates containing, for example, Ni and Au in order from the cap layer 25 side. The gate electrode 33 may be composed of one or more materials selected from, for example, Ni, Au, Pt, Ti, Mo, and Pd.

[0040] The semiconductor device 1 may have an MIS gate structure instead of an insulating film 40 and a gate electrode 33, for example, an insulating film and a gate electrode that contacts the cap layer 25 through the insulating film. The insulating film in the MIS gate structure may be, for example, Al ２ O ３ , HfO ２ , or SiO ２ It is composed of the following. The insulating film in the MIS gate structure is, for example, Al ２ O ３ , HfO ２ and SiO ２ The configuration may consist of stacking at least two of the materials. The gate electrode in the MIS gate structure is, for example, a stack containing Ni and Au in order from the cap layer 25 side.

[0041] The field plate electrode 34 has the role of mitigating the electric field strength near the gate electrode 33. The field plate electrode 34 is positioned close to the gate electrode 33. The field plate electrode 34 and the gate electrode 33 are made of the same material. The field plate electrode 34 is, for example, a laminate containing Ni and Au in order from the cap layer 25 side. The field plate electrode 34 is positioned at a predetermined distance of 0.5 μm or less from the gate electrode 33. In the field plate electrode 34, the edge 34E on the gate electrode 33 side has a shape in which the distance between the edge 34E on the gate electrode 33 side and the gate electrode 33 varies depending on the location, as shown in Figure 3, for example. In the gap between the gate electrode 33 and the edge 34E, the distance D1 at the narrowest point is, for example, 0.5 μm or less.

[0042] The field plate electrode 34 has a plurality of recesses 34A on its edge 34E. The plurality of recesses 34A are regularly arranged on the edge 34E. The field plate electrode 34 has, for example, a comb-tooth shape. On the edge 34E, the areas where the recesses 34A are not formed are convex portions 34C. In other words, the field plate electrode 34 has a plurality of recesses 34A and a plurality of convex portions 34C arranged alternately on its edge 34E. The shape of the tip portion of each convex portion 34C is, for example, a square shape, as shown in Figure 3. The distance between the convex portion 34C and the gate electrode 33 corresponds to the distance D1 described above. The distance D2 between the recess 34A furthest from the gate electrode 33 and the gate electrode 33 is, for example, 1 μm or more.

[0043] The width W1 of the protrusion 34C is, for example, equal to the width W2 of the recess 34A. The relationship between widths W1 and W2 is not limited to the above. The larger the ratio of widths W1 to W2 (W1 / W2), the weaker the electric field strength near the gate electrode 33. This reduces off-leakage, improves breakdown voltage, and suppresses current collapse. When the semiconductor device 1 is used as an amplifier, the larger the ratio of widths W1 to W2 (W1 / W2), the lower the gate-drain capacitance and the higher the gain (especially MSG).

[0044] [1-2. Manufacturing Method] Next, the manufacturing method of the semiconductor device 1 will be described. Figures 4 to 9 show the manufacturing process of the semiconductor device 1. Figures 4(A), 5(A), 6(A), and 9(A) show examples of the cross-sectional configuration of the wafer during the manufacturing process, corresponding to the line A-A in Figure 3. Figures 4(B), 5(B), 6(B), and 9(B) show examples of the cross-sectional configuration of the wafer during the manufacturing process, corresponding to the line B-B in Figure 3. Figures 7 and 8 show examples of the planar configuration of the wafer during the manufacturing process.

[0045] First, a multilayer semiconductor 20 is formed on a substrate 10 using a method such as MOCVD. Next, an insulating film 40 is formed at predetermined locations on the multilayer semiconductor 20. Openings 40a, 40b, and 40c are formed in the insulating film 40. The contact layer 26 is exposed at opening 40a. The contact layer 27 is exposed at opening 40b. The cap layer 25 is exposed at opening 40c. Next, a source electrode 31 is formed on the contact layer 26, and a drain electrode 32 is formed on the contact layer 27 (Figures 4(A) and 4(B)).

[0046] Next, a lift-off layer 110 and a photoresist layer 120 are sequentially formed on the entire surface including the insulating film 40 and contact layers 26 and 27 (Figures 5(A) and 5(B)). Then, by developing predetermined locations on the photoresist layer 120 and the lift-off layer 110, openings H1 and H2 are formed in the photoresist layer 120 and an opening H3 is formed in the lift-off layer 110 (Figures 6(A), 6(B), 7, and 8). Figure 7 illustrates the surface layout of the photoresist layer 120. Figure 8 illustrates the surface layout of the photoresist layer 120 when the photoresist layer 120 is not shown.

[0047] The opening H1 is, for example, rectangular in shape in a plan view, extending in a predetermined direction. In the opening H2, the edge 120E on the opening H1 side has a shape in which the distance between the edge 120E on the opening H1 side and the opening H1 varies depending on the location. In the gap between the edge 120E and the opening H1, the distance D3 at the narrowest point is, for example, 0.5 μm or less.

[0048] The opening H2 has a plurality of recesses 120A on its edge 120E. The plurality of recesses 120A are regularly arranged on the edge 120E. The opening H2 has, for example, a comb-tooth shape. On the edge 120E, the areas where the recesses 120A are not formed are convex portions 120C. In other words, the edge 120E of the opening H2 is alternately provided with a plurality of recesses 120A and a plurality of convex portions 120C. The distance between the convex portions 120C and the opening H1 corresponds to the distance D3 described above. The distance D4 between the location of the recess 120A furthest from the opening H1 and the opening H1 is, for example, 1 μm or more. The width W3 of the convex portions 120C is, for example, equal to the width W4 of the recesses 120A. The relationship between widths W3 and W4 is not limited to the above.

[0049] In the development process described above for the photoresist layer 120 and the lift-off layer 110, the portion of the lift-off layer 110 facing the periphery of the openings H1 and H2 is over-etched. As a result, the portion of the lift-off layer 110 facing the portion sandwiched between the opening H1 and the protrusion 120C is removed by development, creating a void G. On the other hand, a residue 111 remains in the lift-off layer 110 directly beneath the recess 120A, and is not removed by development. This residue 111 supports the recess 120A. Thus, the portion of the photoresist layer 120 sandwiched between the opening H1 and the protrusion 120C is also supported by the residue 111. As a result, deformation of the portion of the photoresist layer 120 sandwiched between the opening H1 and the protrusion 120C is suppressed.

[0050] Next, using the photoresist layer 120 as a mask, a metal layer 130 is formed, for example, by vapor deposition or sputtering. At this time, a gate electrode 33 is formed in the opening H1 and a field plate electrode 34 is formed in the opening H2 (Figures 9(A) and 9(B)). After that, the lift-off layer 110 and the photoresist layer 120 are removed at once. In this way, the semiconductor device 1 is manufactured.

[0051] [1-3. Effects] Next, the effects of semiconductor device 1 will be explained in comparison with conventional semiconductor devices.

[0052] In conventional semiconductor devices, the field plate electrode is formed such that the distance between the field plate electrode and the gate electrode is constant, regardless of the position of the gate electrode side edge of the field plate electrode.

[0053] In this embodiment, the edge 34E of the field plate electrode 34 provided between the gate electrode 33 and the drain electrode 32 has a shape in which the distance between the edge 34E and the gate electrode 33 varies depending on the location. As a result, a portion of the field plate electrode 34 can be formed closer to the gate electrode 33 compared to conventional semiconductor devices. Consequently, compared to conventional semiconductor devices, the electric field strength near the gate electrode 33 is reduced, off-leakage is reduced, breakdown voltage is improved, and current collapse is suppressed. When the semiconductor device 1 is used as an amplifier, the gate-drain capacitance is reduced, and the gain (especially MSG) is improved.

[0054] In this embodiment, multiple protrusions 34C are provided on the edge 34E of the field plate electrode 34. This allows a portion of the field plate electrode 34 (each protrusion 34C) to be formed closer to the gate electrode 33 compared to conventional semiconductor devices. As a result, compared to conventional semiconductor devices, the electric field strength near the gate electrode 33 is reduced, off-leakage is reduced, breakdown voltage is improved, and current collapse is suppressed. When the semiconductor device 1 is used in an amplifier, the gate-drain capacitance is reduced, and the gain (especially MSG) is improved.

[0055] In this embodiment, multiple protrusions 34C are regularly arranged on the edge 34E of the field plate electrode 34. This allows a portion of the field plate electrode 34 (each protrusion 34C) to be formed closer to the gate electrode 33 compared to conventional semiconductor devices. As a result, compared to conventional semiconductor devices, the electric field strength near the gate electrode 33 is reduced, off-leakage is reduced, breakdown voltage is improved, and current collapse is suppressed. When the semiconductor device 1 is used in an amplifier, the gate-drain capacitance is reduced, and the gain (especially MSG) is improved.

[0056] In this embodiment, the field plate electrode 34 has a comb-like shape. This allows a portion of the field plate electrode 34 (each tip of the comb teeth) to be formed closer to the gate electrode 33 compared to conventional semiconductor devices. As a result, compared to conventional semiconductor devices, the electric field strength near the gate electrode 33 is reduced, off-leakage is reduced, breakdown voltage is improved, and current collapse is suppressed. When the semiconductor device 1 is used in an amplifier, the gate-drain capacitance is reduced, and the gain (especially MSG) is improved.

[0057] In this embodiment, the gate electrode 33 and the field plate electrode 34 are made of the same material. This makes it possible to form the gate electrode 33 and the field plate electrode 34 together using the lift-off method. As a result, compared to conventional semiconductor devices, a portion of the field plate electrode 34 can be formed closer to the gate electrode 33. Therefore, compared to conventional semiconductor devices, the electric field strength near the gate electrode 33 is reduced, off-leakage is reduced, breakdown voltage is improved, and current collapse is suppressed. When the semiconductor device 1 is used in an amplifier, the gate-drain capacitance is reduced, and the gain (especially MSG) is improved.

[0058] In this embodiment, the multilayer semiconductor 20 is made of a nitride semiconductor. This makes it possible to apply the semiconductor device 1 to small and high-performance power conversion devices, power amplifiers, and other high-frequency devices.

[0059] <2. Modified Examples> Next, modified examples of the semiconductor device 1 according to the above embodiment will be described. In the following, common components will be given common reference numerals, and descriptions of common components will be omitted as appropriate.

[0060] [Modification 1] In the above embodiment, the field plate electrode 34 may have not only a plurality of protrusions 34C, but also a plurality of protrusions 34B, as shown in Figure 10. The plurality of protrusions 34C are provided on the edge of the field plate electrode 34 on the drain electrode 32 side. The plurality of protrusions 34B are regularly provided on the edge of the field plate electrode 34 on the drain electrode 32 side. The plurality of protrusions 34B are arranged with a regularity that is the same as the regularity of the plurality of protrusions 34C. The field plate electrode 34 is, for example, fishbone shaped.

[0061] In this modified example, the field plate electrode 34 has a fishbone shape. Even in this case, as in the above embodiment, the electric field strength near the gate electrode 33 is reduced, off-leakage is reduced, breakdown voltage is improved, and current collapse is suppressed compared to a conventional semiconductor device. When the semiconductor device 1 is used in an amplifier, the gate-drain capacitance is reduced, and the gain (especially MSG) is improved.

[0062] [Modification 2] In the above embodiment, the field plate electrode 34 may have a plurality of U-shaped protrusions 34F on the edge 34E on the gate electrode 33 side, for example, as shown in Figure 11. The plurality of protrusions 34F are regularly provided on the edge 34E on the gate electrode 33 side of the field plate electrode 34. The field plate electrode 34 has a meander shape, for example.

[0063] In this modified example, the field plate electrode 34 has a meander shape. Even in this case, as in the above embodiment, the electric field strength near the gate electrode 33 is reduced, off-leakage is reduced, breakdown voltage is improved, and current collapse is suppressed compared to a conventional semiconductor device. When the semiconductor device 1 is used as an amplifier, the gate-drain capacitance is reduced, and the gain (especially MSG) is improved.

[0064] [Modification 3] In the above embodiment and modifications 1 to 2, the shape of the tip portion of each protrusion 34C may be a shape different from a square shape. In the above embodiment and modifications 1 to 2, the shape of the tip portion of each protrusion 34C may be a circular or elliptical shape, for example, as shown in Figure 12. In the above embodiment and modifications 1 to 2, the shape of the tip portion of each protrusion 34C may be a triangular shape with a pointed tip, for example, as shown in Figure 13. In the above embodiment and modifications 1 to 2, the shape of the tip portion of each protrusion 34C may be a trapezoidal shape with a tapered tip, for example, as shown in Figure 14. Even if the shape of the tip portion of each protrusion 34C is as described above, compared to conventional semiconductor devices, the electric field strength near the gate electrode 33 is reduced, off-leak is reduced, withstand voltage is improved, and current collapse is suppressed. When the semiconductor device 1 is used as an amplifier, the gate-drain capacitance is reduced, and the gain (especially MSG) is improved.

[0065] [Modification 4] In the above embodiment and modifications 1 to 3, for example, as shown in Figure 15, the distance between each protrusion 34C and the gate electrode 33 may differ depending on the location of the protrusion 34C. In the above embodiment and modifications 1 to 3, the distance between one or more protrusions 34C, which are part of the plurality of protrusions 34C, and the gate electrode 33 may be a distance D3 that is longer than the distance D1 at the narrowest point. Even if the distance between each protrusion 34C and the gate electrode 33 differs depending on the location of the protrusion 34C, compared to conventional semiconductor devices, the electric field strength near the gate electrode 33 is reduced, off-leak is reduced, withstand voltage is improved, and current collapse is suppressed. When the semiconductor device 1 is used in an amplifier, the gate-drain capacitance is reduced and the gain (especially MSG) is improved.

[0066] <3. Application Examples> Next, application examples of HEMT1 according to the above embodiment and modified examples 1 to 4 will be described. In the following, common components will be assigned common reference numerals, and explanations of common components will be omitted as appropriate.

[0067] [Application Example A] Figure 16 shows an example of an antenna switch circuit 2. The antenna switch circuit 2 is used in mobile communication systems such as mobile phones. The antenna switch circuit 2 includes, for example, a first terminal IN, a second terminal IO, a third terminal OUT, a first switching element SW1, and a second switching element SW2.

[0068] A transmission signal is input to the first terminal IN. The second terminal IO is connected to the antenna. The received signal received by the antenna is output from the third terminal OUT. The first switching element SW1 is connected between the first terminal IN and the second terminal IO. The second switching element SW2 is connected between the second terminal IO and the third terminal OUT. Both or one of the first switching element SW1 and the second switching element SW2 are composed of the semiconductor device 1 according to the above embodiment and modifications 1 to 4.

[0069] A third switching element SW3 is connected between the first terminal IN and the power supply (ground in this example). A fourth switching element SW4 is connected between the third terminal OUT and the power supply (ground in this example). Both or one of the third switching element SW3 and the fourth switching element SW4 are composed of the semiconductor device 1 according to the above embodiment and modifications 1 to 4.

[0070] In the antenna switch circuit 2, when transmitting, that is, when the transmitting system of the wireless communication device outputs a transmission signal to the antenna, the first switching element SW1 and the fourth switching element SW4 become conductive. Furthermore, the second switching element SW2 and the third switching element SW3 become non-conductive. At this time, the transmission signal is input from the first terminal IN and output to the second terminal IO via the first switching element SW1.

[0071] When receiving a signal, that is, when the signal received by the antenna is input to the receiving system of the wireless communication device, the first switching element SW1 and the fourth switching element SW4 become non-conductive. Furthermore, the second switching element SW2 and the third switching element SW3 become conductive. At this time, the received signal received by the antenna is input from the second terminal IO and output to the third terminal OUT via the second switching element SW2.

[0072] As described above, the semiconductor device 1 according to the above embodiment and its modifications 1 to 4 is used in this application example. This makes it possible to realize an antenna switch circuit 2 with low off-leakage, high voltage resistance, suppressed current collapse, and good switching characteristics.

[0073] [Application Example B] Figure 17 shows an example of a wireless communication device 3. The wireless communication device 3 is a multi-functional mobile phone system that includes, for example, voice, data communication, and LAN connectivity. The wireless communication device 3 includes, for example, an antenna ANT, an antenna switch circuit 2, a high-power amplifier HPA, a high-frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), and a baseband unit BB. The wireless communication device 3 further includes, for example, an audio output unit MIC, a data output unit DT, and an interface unit I / F. The interface unit I / F is an interface that can communicate with external devices via, for example, a wireless LAN (W-LAN; Wireless Local Area Network), Bluetooth (registered trademark), etc. The antenna switch circuit 2 has, for example, the configuration shown in Figure 16. The high-frequency integrated circuit RFIC and the baseband unit BB are connected by the interface unit I / F.

[0074] In the wireless communication device 3, when transmitting, that is, when the transmitting system of the wireless communication device 3 outputs a transmission signal to the antenna ANT, the transmission signal output from the baseband section BB is output to the antenna ANT via a high-frequency integrated circuit (RFIC), a high-power amplifier (HPA), and an antenna switch circuit 2.

[0075] When receiving a signal, that is, when the signal received by the antenna ANT is input to the receiving system of the wireless communication device 3, the received signal is input to the baseband unit BB via the antenna switch circuit 2 and the high-frequency integrated circuit RFIC. The signal processed by the baseband unit BB is output from output units such as the audio output unit MIC, the data output unit DT, and the interface unit I / F.

[0076] Thus, in this application example, the semiconductor device 1 according to the above embodiment and its modifications 1 to 4 is used. This makes it possible to realize a wireless communication device 3 with low off-leakage, high withstand voltage, suppressed current collapse, and good switching characteristics.

[0077] [Application Example C] Figure 18 shows an example of a power amplifier module 4. The power amplifier module 4 is composed of multiple power amplifiers connected in stages on the same board, including the semiconductor device 1 according to the above embodiment and modifications 1 to 4. Figure 18 shows the circuit configuration of the power amplifier module 4 that conforms to the W-CDMA specification requirements.

[0078] As shown in Figure 18, the power amplifier module 4 comprises an input matching circuit 51, a pre-stage power amplifier 52, an intermediate matching circuit 53, a post-stage power amplifier 54, and an output matching circuit 55. The gain of the pre-stage power amplifier 52 is set to 15.0 dB, and the gain of the post-stage power amplifier 54 is set to 14.0 dB.

[0079] The pre-amplifier 52 and the post-amplifier 54 are configured to include the semiconductor device 1 according to the above embodiment and modifications 1 to 4 as amplifying elements. Each of the power amplifiers 52 and 54 achieves the different gains described above by making the distance Lfp between the gate electrode and the field plate electrode different.

[0080] Thus, in this application example, the semiconductor device 1 according to the above embodiment and its modifications 1 to 4 is used. This makes it possible to realize a power amplifier module 4 that can obtain high-precision gain (especially MSG).

[0081] The present technology has been described above with reference to embodiments, modifications, and application examples. However, the present technology is not limited to the above embodiments, and various modifications are possible. The effects described herein are merely illustrative. The effects of the present technology are not limited to those described herein. The present technology may have effects other than those described herein.

[0082] Furthermore, for example, this technology can take the following configurations: <1> A semiconductor device comprising: a multilayer semiconductor; a gate electrode provided above the multilayer semiconductor, and a source electrode and a drain electrode facing each other with the gate electrode in between; an insulating film provided above the multilayer semiconductor and between the gate electrode and the drain electrode; and a field plate electrode provided above the multilayer semiconductor and between the gate electrode and the drain electrode via the insulating film, wherein the edge of the field plate electrode on the gate electrode side has a shape in which the distance between the edge of the gate electrode side and the gate electrode varies depending on the location. <2> The semiconductor device according to <1>, wherein the field plate electrode has a plurality of recesses on the edge of the gate electrode side. <3> The semiconductor device according to <2>, wherein the plurality of recesses are regularly provided on the edge of the field plate electrode on the gate electrode side. <4> The semiconductor device according to <3>, wherein the field plate electrode has a comb-tooth shape, a fishbone shape, or a meander shape. <5> The semiconductor device according to any one of <1> to <4>, wherein the gate electrode and the field plate electrode are made of the same material. <6> The semiconductor device according to any one of <1> to <5>, wherein the multilayer semiconductor is composed of a nitride semiconductor. <7> The semiconductor device according to any one of <1> to <6>, wherein the field plate electrode is connected to the source electrode. <8> The semiconductor device comprises a multilayer semiconductor, the semiconductor device having a gate electrode provided above the multilayer semiconductor, and a source electrode and a drain electrode facing each other with the gate electrode in between, an insulating film provided above the multilayer semiconductor and between the gate electrode and the drain electrode, and a field plate electrode provided above the multilayer semiconductor and between the gate electrode and the drain electrode via the insulating film, wherein the edge of the field plate electrode on the gate electrode side has a shape in which the distance between the edge of the gate electrode side and the gate electrode differs depending on the location.<9> Electronic device comprising a semiconductor device, the semiconductor device comprising: a multilayer semiconductor; a gate electrode provided above the multilayer semiconductor, and a source electrode and a drain electrode facing each other with the gate electrode in between; an insulating film provided above the multilayer semiconductor and between the gate electrode and the drain electrode; and a field plate electrode provided above the multilayer semiconductor and between the gate electrode and the drain electrode via the insulating film, wherein the edge of the field plate electrode on the gate electrode side has a shape in which the distance between the edge of the gate electrode side and the gate electrode differs depending on the location.

[0083] In a semiconductor device, electrical circuit, and electronic device according to one embodiment of this technology, the field plate electrode provided between the gate electrode and the drain electrode has a shape in which the distance between the gate electrode edge and the gate electrode varies depending on the location. As a result, a portion of the field plate electrode can be formed closer to the gate electrode compared to conventional semiconductor devices. Consequently, compared to conventional semiconductor devices, the electric field strength near the gate electrode 33 is reduced, off-leakage is reduced, breakdown voltage is improved, and current collapse is suppressed. When the semiconductor device 1 is used in an amplifier, the gate-drain capacitance is reduced, and the gain (especially MSG) is improved.

[0084] This application claims priority based on Japanese Patent Application No. 2025-053743, filed with the Japan Patent Office on 27 March 2025, and all contents of that application are incorporated herein by reference.

[0085] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A semiconductor device comprising: a multilayer semiconductor; a gate electrode provided above the multilayer semiconductor, and a source electrode and a drain electrode facing each other with the gate electrode in between; an insulating film provided above the multilayer semiconductor and between the gate electrode and the drain electrode; and a field plate electrode provided above the multilayer semiconductor and between the gate electrode and the drain electrode via the insulating film, wherein the edge of the field plate electrode on the gate electrode side has a shape in which the distance between the edge of the gate electrode side and the gate electrode varies depending on the location.

2. The semiconductor device according to claim 1, wherein the field plate electrode has a plurality of protrusions on the edge of the gate electrode side.

3. The semiconductor device according to claim 2, wherein the plurality of protrusions are regularly provided on the edge of the field plate electrode on the gate electrode side.

4. The semiconductor device according to claim 3, wherein the field plate electrode is comb-shaped, fishbone-shaped, or meander-shaped.

5. The semiconductor device according to claim 1, wherein the gate electrode and the field plate electrode are made of the same material.

6. The semiconductor device according to claim 1, wherein the multilayer semiconductor is composed of a nitride semiconductor.

7. The semiconductor device according to claim 1, wherein the field plate electrode is connected to the source electrode.

8. An electrical circuit comprising a semiconductor device, the semiconductor device having a multilayer semiconductor, a gate electrode provided above the multilayer semiconductor, and a source electrode and a drain electrode facing each other with the gate electrode in between, an insulating film provided above the multilayer semiconductor and between the gate electrode and the drain electrode, and a field plate electrode provided above the multilayer semiconductor and between the gate electrode and the drain electrode via the insulating film, wherein the edge of the field plate electrode on the gate electrode side has a shape in which the distance between the edge of the gate electrode side and the gate electrode differs depending on the location.

9. Electronic device comprising a semiconductor device, the semiconductor device comprising: a multilayer semiconductor; a gate electrode provided above the multilayer semiconductor, and a source electrode and a drain electrode facing each other with the gate electrode in between; an insulating film provided above the multilayer semiconductor and between the gate electrode and the drain electrode; and a field plate electrode provided above the multilayer semiconductor and between the gate electrode and the drain electrode via the insulating film, wherein the edge of the field plate electrode on the gate electrode side has a shape in which the distance between the edge of the gate electrode side and the gate electrode varies depending on the location.

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