Gallium nitride semiconductor device

Abstract

A gallium nitride semiconductor device according to the present invention comprises: a gallium nitride semiconductor laminated body that includes a p-type gallium nitride semiconductor layer; a passivation layer that covers the gallium nitride semiconductor laminated body; an n-type gallium nitride semiconductor layer that is on the passivation layer; and an electrode that is in contact with the n-type gallium nitride semiconductor layer. The passivation layer has an opening at an upper surface of the p-type gallium nitride semiconductor layer, and the n-type gallium nitride semiconductor layer forms a tunnel junction with the p-type gallium nitride semiconductor layer at the opening.

Description

Gallium Nitride-based Semiconductor Device

[0001] One embodiment of the present invention relates to a structure and a manufacturing method of a gallium nitride-based semiconductor device including a gallium nitride semiconductor layer.

[0002] In devices fabricated using gallium nitride, a relatively high contact resistance between a p-type gallium nitride semiconductor layer and an electrode has been a problematic issue. To reduce the contact resistance between a p-type gallium nitride semiconductor layer and an electrode, there has been disclosed a structure in which a tunnel junction is formed by stacking an n-type gallium nitride semiconductor layer doped with a high concentration of an impurity element on a p-type gallium nitride semiconductor layer, and an electrode in contact with the n-type gallium nitride semiconductor layer is further provided (see Patent Document 1).

[0003] Japanese Unexamined Patent Publication No. 2019-062204

[0004] To form a tunnel junction, it is necessary to form an n-type gallium nitride semiconductor layer heavily doped with donor impurities on the p-type gallium nitride semiconductor layer. However, when the n-type gallium nitride semiconductor layer is formed by metal organic chemical vapor deposition (MOCVD), hydrogen mixes into the p-type gallium nitride semiconductor layer and inactivates the acceptors, which is a problem. On the other hand, Patent Document 1 discloses a method for forming an n-type gallium nitride semiconductor layer by sputtering, but it is difficult to achieve a large area in processes using a single crystal substrate such as a gallium nitride substrate (GaN wafer) or a sapphire substrate, resulting in the problem of high manufacturing cost.

[0005] A gallium nitride-based semiconductor device according to an embodiment of the present invention includes: a gallium nitride-based semiconductor laminate including a p-type gallium nitride semiconductor layer; a passivation layer covering the gallium nitride-based semiconductor laminate; an n-type gallium nitride-based semiconductor layer on the passivation layer; and an electrode in contact with the n-type gallium nitride-based semiconductor layer. The passivation layer has an opening on the upper surface of the p-type gallium nitride semiconductor layer, and the n-type gallium nitride-based semiconductor layer forms a tunnel junction with the p-type gallium nitride semiconductor layer at the opening.

[0006] A method for fabricating a gallium nitride-based semiconductor device according to one embodiment of the present invention includes forming a gallium nitride-based semiconductor stack including a p-type gallium nitride semiconductor layer, forming a passivation layer covering the gallium nitride-based semiconductor stack, forming contact holes in the passivation layer to expose the p-type gallium nitride semiconductor layer, and depositing an n-type gallium nitride-based semiconductor layer on the p-type gallium nitride semiconductor layer exposed by the passivation layer and the contact holes by sputtering to form a tunnel junction with the p-type gallium nitride semiconductor layer.

[0007] This shows a cross-sectional view of a gallium nitride-based semiconductor device according to one embodiment of the present invention. This shows the manufacturing process This shows the manufacturing process for a gallium nitride-based semiconductor device according to one embodiment of the present invention. This shows the manufacturing process for a gallium nitride-based semiconductor device according to one embodiment of the present invention. This shows the manufacturing process for a gallium nitride-based semiconductor device according to one embodiment of the present invention. This shows the manufacturing process for a gallium nitride-based semiconductor device according to one embodiment of the present invention.

[0008] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described below. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals (or numerals followed by A, B, etc.), and detailed explanations may be omitted as appropriate. Furthermore, the words "first" and "second" attached to each element are convenient indicators used to distinguish each element and have no further meaning unless specifically explained.

[0009] [First Embodiment] This embodiment will describe in detail the structure and manufacturing method of the gallium nitride-based semiconductor device 100.

[0010] Figure 1 shows a cross-sectional structure of a gallium nitride-based semiconductor device 100 according to this embodiment. The gallium nitride-based semiconductor device 100 includes a gallium nitride-based semiconductor laminate 102, a passivation layer 104, an n-type gallium nitride-based semiconductor layer 106, a first electrode 108, and a second electrode 110. The gallium nitride-based semiconductor laminate 102 is provided on a support substrate 150. The gallium nitride-based semiconductor laminate 102 may be bonded to the support substrate 150 by direct bonding, or it may be bonded via a bonding layer 120 as shown in Figure 1.

[0011] The gallium nitride semiconductor laminate 102 has a structure in which multiple semiconductor layers formed of gallium nitride semiconductors are stacked. Gallium nitride semiconductors are semiconductors that contain gallium nitride as a component. Specifically, gallium nitride semiconductors include semiconductors made from nitrides of elements belonging to Group 13 of the periodic table, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), and indium gallium nitride (InGaN). Furthermore, when gallium nitride semiconductors are classified by conductivity type, in addition to p-type and n-type, intrinsic or substantially intrinsic gallium nitride semiconductor layers are included. An intrinsic or substantially intrinsic gallium nitride semiconductor refers to a gallium nitride semiconductor layer in which impurity elements for the purpose of controlling valence electrons are not intentionally added, excluding unavoidable impurity elements such as hydrogen, oxygen, and carbon. In the following explanation, an intrinsic or substantially intrinsic gallium nitride semiconductor layer may also be called an undoped gallium nitride semiconductor.

[0012] The gallium nitride semiconductor device 100 shown in Figure 1 is a device that functions as a light-emitting diode, and the gallium nitride semiconductor laminate 102 is a laminate of an undoped gallium nitride semiconductor layer 1022, an n-type gallium nitride semiconductor layer 1024, a light-emitting layer 1026, and a p-type gallium nitride semiconductor layer 1028. Figure 1 also shows a structure in which a first distributed Bragg reflective layer 1023 is inserted between the undoped gallium nitride semiconductor layer 1022 and the n-type gallium nitride semiconductor layer 1024. The first distributed Bragg reflective layer 1023 is an additional component and may be omitted. That is, the n-type gallium nitride semiconductor layer 1024 may be directly laminated on top of the undoped gallium nitride semiconductor layer 1022.

[0013] As mentioned above, the undoped gallium nitride semiconductor layer 1022 is a layer formed from a gallium nitride semiconductor that does not intentionally contain impurity elements for the purpose of controlling valence electrons. The n-type gallium nitride semiconductor layer 1024 is a layer formed from a gallium nitride semiconductor to which donor impurities such as silicon (Si) or germanium (Ge) are added. The light-emitting layer 1026 is a region where electrons transported from the n-type gallium nitride semiconductor layer 1024 and holes transported from the p-type gallium nitride semiconductor layer 1028 recombine to emit light. The light-emitting layer 1026 is also formed from a gallium nitride-based semiconductor, but its structure is not limited. The light-emitting layer 1026 may have a multiple quantum well (MQW) structure. The multiple quantum well (MQW) structure may have, for example, a structure in which quantum wells are formed by a gallium nitride (GaN) layer and an indium gallium nitride (InGaN) layer. The p-type gallium nitride semiconductor layer 1028 is a layer formed of a gallium nitride semiconductor to which acceptor impurities such as magnesium (Mg), zinc (Zn), cadmium (Cd), and calcium (Ca) are added.

[0014] The first distributed Bragg reflective layer 1023 has a structure in which layers with different refractive indices are alternately stacked with a thickness of 1 / 4 wavelength. Each layer of the first distributed Bragg reflective layer 1023 may be formed of an insulating thin film or a conductive thin film. The first distributed Bragg reflective layer 1023 has a high reflectivity because the reflected waves in each layer reinforce each other due to Bragg reflection caused by the interference effect of light. By arranging the first distributed Bragg reflective layer 1023 between the undoped gallium nitride semiconductor layer 1022 and the n-type gallium nitride semiconductor layer 1024, the light emitted by the light-emitting layer 1026 can be prevented from passing through to the support substrate 150, thereby increasing the light emission intensity.

[0015] As shown in Figure 1, the gallium nitride semiconductor laminate 102 has a region where a portion of the p-type gallium nitride semiconductor layer 1028 and the light-emitting layer 1026 are removed so that the second electrode 110 can contact the n-type gallium nitride semiconductor layer 1024. In a plan view, this region is the area where the upper surface of the n-type gallium nitride semiconductor layer 1024 is exposed from the p-type gallium nitride semiconductor layer 1028 and the light-emitting layer 1026 formed in the upper layer. The second electrode 110 is provided in this region.

[0016] The gallium nitride semiconductor laminate 102 is covered on its sides and top by a passivation layer 104. The passivation layer 104 is made of an insulating material such as silicon nitride, silicon oxynitride, or aluminum oxide. The passivation layer 104 may have a structure in which a silicon oxide film and a silicon nitride film are laminated. The passivation layer 104 has a first opening 1042 and a second opening 1044. The first opening 1042 exposes the top surface of the p-type gallium nitride semiconductor layer 1028, and the second opening 1044 exposes the top surface of the n-type gallium nitride semiconductor layer 1024.

[0017] The passivation layer 104 may also be provided so as to cover the surface of the bonding layer 120 and the support substrate 150 that are exposed from the gallium nitride semiconductor laminate 102. With this configuration, the portion where the gallium nitride semiconductor laminate 102 and the support substrate 150 are bonded can be protected.

[0018] An n-type gallium nitride semiconductor layer 106 is provided on the upper side of the passivation layer 104. The n-type gallium nitride semiconductor layer 106 may be formed of n-type gallium nitride (GaN) or n-type aluminum gallium nitride (AlGaN). The n-type gallium nitride semiconductor layer 106 contains a higher concentration of donor impurities compared to the n-type gallium nitride semiconductor layer 1024. The concentration of donor impurities in the n-type gallium nitride semiconductor layer 106 is 1 × 10⁻⁶. ２０ / cm ３ The above 5 x 10 ２１ / cm ３ The following is preferable:

[0019] The n-type gallium nitride semiconductor layer 106 is provided in a region that overlaps with the first opening 1042. In other words, the n-type gallium nitride semiconductor layer 106 is provided so as to be in contact with the p-type gallium nitride semiconductor layer 1028 at the first opening 1042.

[0020] The n-type gallium nitride semiconductor layer 106 is fabricated by sputtering. In sputtering, a sintered gallium nitride body is used as the sputtering target. Elements such as silicon (Si) or germanium (Ge) used as donor impurities may be added to the sputtering target, or they may be incorporated into the n-type gallium nitride semiconductor layer 106 during film formation by co-sputtering using pellets of silicon (Si) or germanium (Ge).

[0021] An inert gas such as argon is used as the sputtering gas. In the sputtering method, there is no hydrogen that is intentionally introduced during film formation, and no hydrogen is generated during the film formation process by sputtering. Therefore, only hydrogen that inevitably remains or is generated exists in the film formation space (inside the film formation chamber of the sputtering apparatus), and the partial pressure of this hydrogen is extremely small compared to the pressure of the gas introduced as the sputtering gas, so that hydrogen does not mix into the p-type gallium nitride semiconductor layer 1028 during film formation. In other words, it is possible to prevent the p-type gallium nitride semiconductor layer 1028 from becoming highly resistive as the n-type gallium nitride semiconductor layer 106 is formed. Furthermore, even if hydrogen is present in the film formation space, the mixing of hydrogen can be minimized because the gallium nitride semiconductor laminate 102 is covered with a passivation layer 104, except for the region of the first opening 1042. The passivation layer 104 functions not only during the deposition of the n-type gallium nitride semiconductor layer 106, but also as a protective film that blocks the intrusion of hydrogen from the external environment during subsequent heat treatment and processes. This makes it possible to suppress the re-inactivation of the acceptors of the p-type gallium nitride semiconductor layer 1028 in areas other than the opening 1042.

[0022] In this way, by employing the sputtering method, it is possible to deposit an n-type gallium nitride semiconductor layer 106 with a high concentration of donor impurities while preventing the p-type gallium nitride semiconductor layer 1028 from becoming highly resistive. As a result, a tunnel junction can be formed between the p-type gallium nitride semiconductor layer 1028 and the n-type gallium nitride semiconductor layer 106.

[0023] The p-type gallium nitride semiconductor layer 1028 may be formed of multiple layers. For example, as shown in Figure 1, the structure may have a first p-type gallium nitride semiconductor layer 1028A provided on the side of the light-emitting layer 1026, and a second p-type gallium nitride semiconductor layer 1028B provided on the side of the n-type gallium nitride semiconductor layer 106. The dopant (acceptor impurity) concentrations of the first p-type gallium nitride semiconductor layer 1028A and the second p-type gallium nitride semiconductor layer 1028B may be different. For example, the dopant concentration of the second p-type gallium nitride semiconductor layer 1028B may be higher than that of the first p-type gallium nitride semiconductor layer 1028A. A higher dopant concentration in the second p-type gallium nitride semiconductor layer 1028B allows for the formation of a good tunnel junction with the n-type gallium nitride semiconductor layer 106. Furthermore, the relatively low dopant concentration of the first p-type gallium nitride semiconductor layer 1028A allows for the formation of a good interface with the light-emitting layer 1026.

[0024] The first electrode 108 and the second electrode 110 are formed from a metallic material capable of forming ohmic contact with an n-type gallium nitride semiconductor layer. Titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), niobium (Nb), etc., can be used as the metallic material forming the first electrode 108 and the second electrode 110. In addition to these metallic materials, the first electrode 108 and the second electrode 110 may also have a layered structure using aluminum (Al) and gold (Au) (Ti / Al / Ti / Au), or a layered structure using aluminum (Al), nickel (Ni), and gold (Au) (Ti / Al / Ni / Au).

[0025] The first electrode 108 is provided so as to be in contact with the n-type gallium nitride semiconductor layer 106, and the second electrode 110 is provided so as to be in contact with the n-type gallium nitride semiconductor layer 1024 at a position overlapping with the second opening 1044. The first electrode 108 is provided on the n-type gallium nitride semiconductor layer 106, but since it is connected to the p-type gallium nitride semiconductor layer 1028 through a tunnel junction, it can be considered as the anode electrode (sometimes called the "p electrode"), and the second electrode 110 is connected to the n-type gallium nitride semiconductor layer 1024, so it can be considered as the cathode electrode (sometimes called the "n electrode").

[0026] As shown in Figure 1, a second distributed Bragg reflective layer 107 may be provided on the n-type gallium nitride semiconductor layer 106. By sandwiching the light-emitting layer 1026 between the first distributed Bragg reflective layer 1023 and the second distributed Bragg reflective layer 107 in this way, the emitted light can be enhanced.

[0027] In the gallium nitride semiconductor device 100 shown in Figure 1, the light-emitting layer 1026 emits light when a forward bias is applied between the first electrode 108 and the second electrode 110. At this time, the relationship between the p-type gallium nitride semiconductor layer 1028 and the n-type gallium nitride semiconductor layer 106 is reverse-biased. Since a tunnel junction is formed between the p-type gallium nitride semiconductor layer 1028 and the n-type gallium nitride semiconductor layer 106, a current (reverse current in this region) flows according to the magnitude of the forward bias. Therefore, the first electrode 108 and the p-type gallium nitride semiconductor layer 1028 are in a state where current flows in substantially the same way as when an ohmic contact is formed.

[0028] The structure of the gallium nitride semiconductor laminate 102 shown in Figure 1 is just one example, and any structure that can function as a light-emitting diode may have a different laminated structure, except for the configuration of the p-type gallium nitride semiconductor layer 1028 and the n-type gallium nitride semiconductor layer 106 on the light-emitting layer 1026. For example, the gallium nitride semiconductor laminate 102 may have electron injection layers or hole injection layers sandwiching the light-emitting layer 1026. Some of the layers constituting the gallium nitride semiconductor laminate 102 may be omitted, or layers not shown may be added. Furthermore, the undoped gallium nitride semiconductor layer 1022, the n-type gallium nitride semiconductor layer 1024, and the p-type gallium nitride semiconductor layer 1028 may be formed from aluminum gallium nitride (AlGaN) semiconductor or indium gallium nitride (InGaN) semiconductor instead of gallium nitride (GaN) semiconductor.

[0029] Next, with reference to Figures 2A to 2D and 3A to 3F, an example of a method for manufacturing a gallium nitride-based semiconductor device 100 having the structure shown in Figure 1 is presented.

[0030] Figures 2A to 2D show the process of transferring a gallium nitride-based semiconductor laminate 102, fabricated on a single-crystal substrate 180 such as a sapphire substrate, onto a support substrate 150. Figure 2A shows the stage in which the gallium nitride-based semiconductor layers stacked on the single-crystal substrate 180 are separated into elements, and the gallium nitride-based semiconductor laminate 102 is formed. As explained with reference to Figure 1, the gallium nitride-based semiconductor laminate 102 has a structure in which multiple gallium nitride-based semiconductor layers are stacked. The gallium nitride-based semiconductor laminate 102 is fabricated on a gallium nitride substrate or a sapphire substrate by the MOCVD method. Alternatively, as disclosed in International Publication No. 2022 / 210402 and International Publication No. 2023 / 223858, it may be a gallium nitride-based semiconductor laminate fabricated on a glass substrate by the sputtering method (in this case, the single-crystal substrate is replaced with an amorphous substrate).

[0031] A release layer 101 is provided between the gallium nitride-based semiconductor laminate 102 and the single crystal substrate 180. The release layer 101 is made of a material that can absorb the laser light used in the release process. The release layer 101 may be made of, for example, gallium nitride. Therefore, the region of the undoped gallium nitride semiconductor layer 1022 on the single crystal substrate 180 side can be considered as the release layer 101.

[0032] Figure 2B shows the step of peeling off the gallium nitride-based semiconductor laminate 102 by irradiating the peeling layer 101 with laser light from the side of the single crystal substrate 180. A carrier substrate 182 is provided in advance on the upper surface of the gallium nitride-based semiconductor laminate 102. The carrier substrate 182 is an adhesive film made of an ultraviolet-absorbing polymer or the like. In the peeling process, laser light is irradiated from the side of the single crystal substrate 180. Specifically, laser light with energy greater than the band gap of gallium nitride (3.4 eV, equivalent to a wavelength of 365 nm) (for example, excimer laser light with a wavelength of 248 nm or 308 nm, or the third harmonic of a YAG laser with a wavelength of 355 nm) is irradiated from the side of the single crystal substrate 180.

[0033] By irradiating with laser light, part or all of the peeling layer 101 evaporates, sublimes, or thermally decomposes, reducing the adhesion force of the gallium nitride-based semiconductor laminate 102 to the single crystal substrate 180. As a result, as shown in Figure 2C, the gallium nitride-based semiconductor laminate 102 can be peeled off from the single crystal substrate 180. Multiple gallium nitride-based semiconductor laminates 102 are formed on the single crystal substrate 180, but by using a carrier substrate 182, multiple gallium nitride-based semiconductor laminates 102 can be peeled off simultaneously.

[0034] Figure 2D shows the step of peeling the gallium nitride semiconductor laminate 102 from the carrier substrate 182 and transferring it to the support substrate 150. The carrier substrate 182 is positioned so that the gallium nitride semiconductor laminate 102 aligns with the bonding layer 120. Then, by irradiating the back side (the side opposite to the side to which the gallium nitride semiconductor laminate 102 is adhered) with laser light to volatilize the adhesive, the carrier substrate 182 can be peeled off while the gallium nitride semiconductor laminate 102 remains on the support substrate 150.

[0035] Figures 3A and 3B show in detail the steps of bonding the gallium nitride-based semiconductor laminate 102 to the support substrate 150.

[0036] For example, a glass substrate can be used as the support substrate 150. There are no limitations on the thickness of the support substrate 150; for example, a glass substrate with a thickness of 0.5 mm to 1.0 mm can be used. The glass substrate is generally made of an amorphous material that does not have a crystalline structure, but a crystalline structure may be present in minute regions. It is preferable that the support substrate 150 has a heat resistance of about 600°C. Furthermore, the upper limit of the thermal expansion coefficient of the support substrate 150 is 4.2 × 10⁻⁶. －６ Less than 4.2 ppm / K, and even less than 4.0 × 10 －６ It is preferable that the concentration is less than 4.0 ppm / K, and the lower limit is 3.0 × 10⁻⁶. －６ It exceeds / K (3.0 ppm / K), and even exceeds 3.5 × 10 －６ It is preferable that the value exceeds 3.5 ppm / K.

[0037] By using a glass substrate as the support substrate 150, a large area can be achieved. To prevent metal contamination of the gallium nitride-based semiconductor laminate 102, it is preferable to use a glass substrate with a low alkali metal content. As the glass substrate, for example, a glass substrate called aluminoborosilicate glass or aluminosilicate glass can be used. Such glass substrates are used in liquid crystal displays and organic electroluminescent (organic EL) displays, and it is possible to select a large-area glass substrate called mother glass that is available on the market.

[0038] The bonding layer 120 is a member that bonds the support substrate 150 and the gallium nitride-based semiconductor laminate 102. The bonding layer 120 may be formed of an inorganic material, or may be formed of an organic material. As the inorganic material, for example, a solder material is used. As the solder material, for example, a tin-lead (Sn-Pb) alloy, a tin-silver-copper (Sn-Ag-Cu) alloy, a tin-copper-nickel (Sn-Cu-Ni) alloy or the like can be used. Further, a ceramic adhesive can be used as the inorganic material. As the organic material, for example, an epoxy adhesive, a silicone adhesive, or a polyurethane adhesive can be used.

[0039] The bonding layer 120 may be formed on the side of the support substrate 150, may be formed on the side of the gallium nitride-based semiconductor laminate 102, or may be formed on both the support substrate 150 and the gallium nitride-based semiconductor laminate 102.

[0040] FIG. 3C shows the step of etching the p-type gallium nitride semiconductor layer 1028 and a part of the light-emitting layer 1026 to expose a partial region of the n-type gallium nitride semiconductor layer 1024. A resist mask for protecting the gallium nitride-based semiconductor laminate 102 is formed by a photolithography process, and etching is performed, whereby the n-type gallium nitride semiconductor layer 1024 can be partially exposed.

[0041] FIG. 3D shows the step of forming the passivation layer 104. The passivation layer 104 is formed so as to cover the entire surface of the support substrate 150 by a sputtering method or a plasma CVD method. The passivation layer 104 is formed of, for example, a silicon nitride film. The thickness of the passivation layer 104 is arbitrary, and for example, the passivation layer 104 is formed to have a thickness of 0.2 μm to 5 μm. Thereafter, a resist mask is formed on the passivation layer 104 by a photolithography process, and etching is performed, whereby a first opening 1042 and a second opening 1044 can be formed in the passivation layer 104.

[0042] FIG. 3E shows the step of forming an n-type gallium nitride-based semiconductor layer 106. The n-type gallium nitride-based semiconductor layer is formed on the entire surface of a support substrate 150 by a sputtering method so as to cover the upper surface of a passivation layer 104. The thickness of the n-type gallium nitride-based semiconductor layer is arbitrary, and for example, the layer is formed to have a thickness of 0.05 μm to 5 μm. The sputtering method enables film formation at a significantly lower temperature compared to the MOCVD method (usually 1000° C. or higher). Accordingly, even when a large-area glass substrate with limited heat resistance is used as the support substrate 150, a high-quality tunnel junction can be formed while preventing distortion and cracking of the substrate.

[0043] Thereafter, by a photolithography process, a resist mask is formed on the n-type gallium nitride-based semiconductor layer 106, and etching is performed, whereby the n-type gallium nitride-based semiconductor layer 106 can be formed on the p-type gallium nitride semiconductor layer 1028 in a region overlapping at least the first opening 1042. Thereafter, heat treatment may be performed at a temperature of 600° C. or lower to form a favorable tunnel junction with the p-type gallium nitride semiconductor layer 1028.

[0044] FIG. 3F shows the step of forming a first electrode 108 and a second electrode 110. The first electrode 108 and the second electrode 110 can also be formed by forming a predetermined metal film on the entire surface of the support substrate 150 by a sputtering method, forming a resist mask by a photolithography process, and performing etching. Since both the first electrode 108 and the second electrode 110 are in contact with an n-type gallium nitride-based semiconductor layer, the same electrode material can be used and patterning can be performed in the same process. That is, since both the first electrode 108 and the second electrode 110 are configured to be in contact with an n-type layer, they can be collectively formed in the same process using the same material (for example, Ti / Al or the like). This contributes to reducing the number of masks and lowering manufacturing costs.

[0045] By following the above steps, a gallium nitride-based semiconductor device 100, as shown in Figure 1, can be manufactured. Figures 3A to 3F show the process of manufacturing a gallium nitride-based semiconductor device 100 by bonding one gallium nitride-based semiconductor laminate 102 onto a support substrate 150. As shown in Figures 2A to 2D, a large-area glass substrate can be used as the support substrate 150, and multiple gallium nitride-based semiconductor devices 100 can be manufactured simultaneously on a single support substrate 150. As a result, the productivity of the gallium nitride-based semiconductor device 100 can be increased, and manufacturing costs can be reduced.

[0046] In this embodiment, the gallium nitride-based semiconductor laminate 102 is shown as a light-emitting diode structure, but the gallium nitride-based semiconductor device 100 is not limited to a light-emitting diode. By changing the stacking order and arrangement within the gallium nitride-based semiconductor layers, various semiconductor devices such as transistors and thyristors can be realized.

[0047] [Second Embodiment] This embodiment describes an example in which the gallium nitride-based semiconductor laminate 102 differs from that of the first embodiment. In the following description, the differences from the first embodiment will be the focus, and the descriptions of common parts will be omitted as appropriate.

[0048] Figure 4 shows the cross-sectional structure of the gallium nitride-based semiconductor device 100 according to this embodiment. In the gallium nitride-based semiconductor device 100, the configuration of the support substrate 150, the bonding layer 120, the gallium nitride-based semiconductor laminate 102, the n-type gallium nitride-based semiconductor layer 106, the first electrode 108, and the second electrode 110 is the same as in the first embodiment.

[0049] Similar to the first embodiment, a passivation layer 104 is provided, but the lower end of the undoped gallium nitride semiconductor layer 1022 and the junction layer 120 are exposed from the passivation layer 104. The undoped gallium nitride semiconductor layer 1022 is provided to improve the crystallinity of the n-type and p-type gallium nitride semiconductor layers stacked on top, and is also provided to bond with the support substrate 150. It is not a region that directly interacts with the device when it is operating. Therefore, even if a portion of the undoped gallium nitride semiconductor layer 1022 is exposed from the passivation layer 104, it does not affect the characteristics or reliability of the device.

[0050] Figures 5A to 5D show the process of transferring a gallium nitride-based semiconductor laminate 102, which is fabricated on a single crystal substrate 190 such as a gallium nitride substrate (GaN wafer), onto a support substrate 150.

[0051] Figure 5A shows the state of the gallium nitride-based semiconductor laminate 102, which is stacked on a single crystal substrate 190, before device isolation. While the gallium nitride-based semiconductor laminate 102 is formed on the single crystal substrate 190, etching is performed to expose the n-type gallium nitride semiconductor layer 1024. Furthermore, a passivation layer 104 is provided so as to cover the gallium nitride-based semiconductor laminate 102. Then, a carrier substrate 182 is provided on top of the passivation layer 104.

[0052] Figure 5B shows the step of thinning the single crystal substrate 190. Thinning of the single crystal substrate 190 is performed by chemical mechanical polishing (CMP). The degree of thinning of the single crystal substrate 190 is arbitrary, but for example, it may be ground and polished to the extent that the undoped gallium nitride semiconductor layer 1022 is exposed.

[0053] Figure 5 shows the step of separating the gallium nitride semiconductor laminate 102 into individual pieces. This process is also called dicing. Dicing involves irradiating the thinned single crystal substrate 190 with laser light to damage it. Then, by applying an external force, the gallium nitride semiconductor laminate 102 is separated into individual pieces. For example, by using a stretchable film as the carrier substrate 182 and stretching the film, the gallium nitride semiconductor laminate 102 can be separated into individual pieces.

[0054] Figure 5D shows the step of peeling the gallium nitride semiconductor laminate 102 from the carrier substrate 182 and transferring it to the support substrate 150. The carrier substrate 182 is positioned so that the gallium nitride semiconductor laminate 102 aligns with the bonding layer 120. Then, by irradiating the back side (the side opposite to the side to which the gallium nitride semiconductor laminate 102 is adhered) with laser light to volatilize the adhesive, the carrier substrate 182 can be peeled off while leaving the gallium nitride semiconductor laminate 102 on the support substrate 150.

[0055] In the above process, the passivation layer 104 is provided before individualization, thereby protecting the gallium nitride-based semiconductor laminate 102. Furthermore, according to the above process, the sides are also protected by the passivation film before chipping (individualization), so it can be prevented from suffering physical and chemical damage during the transfer process.

[0056] Figures 6A and 6B show in detail the step of bonding the gallium nitride-based semiconductor laminate 102 to the support substrate 150 using a bonding layer 120. Similar to the first embodiment, by using a glass substrate as the support substrate 150, a large area can be achieved, and by transferring multiple gallium nitride-based semiconductor laminates 102, subsequent processes can be processed in a single step.

[0057] Figure 6C shows the step of forming the first opening 1042 in the passivation layer 104. Then, Figure 6D shows the step of forming the n-type gallium nitride semiconductor layer 106. The n-type gallium nitride semiconductor layer 106 is formed in the same manner as in the first embodiment.

[0058] Figure 6E shows the step of forming the second opening 1044 in the passivation layer 104. In this embodiment, the step of forming the second opening 1044 alone is shown, but the second opening 1044 may be formed simultaneously with the first opening 1042 in the step shown in Figure 6D. Figure 6F shows the step of forming the first electrode 108 and the second electrode 110.

[0059] By following the above steps, a gallium nitride-based semiconductor device 100, as shown in Figure 4, can be manufactured. Figures 6A to 6F show the process of manufacturing a gallium nitride-based semiconductor device 100 by bonding one gallium nitride-based semiconductor laminate 102 onto a support substrate 150. As shown in Figures 5A to 5D, by using a large-area glass substrate as the support substrate 150, multiple gallium nitride-based semiconductor devices 100 can be manufactured simultaneously on a single support substrate 150. As a result, the productivity of the gallium nitride-based semiconductor device 100 can be increased, and manufacturing costs can be reduced. Furthermore, in this embodiment, a passivation layer 104 is provided before the gallium nitride-based semiconductor laminate 102 is separated into individual pieces, so contamination and degradation of the gallium nitride-based semiconductor laminate 102 can be prevented in the steps prior to transfer to the support substrate 150.

[0060] This embodiment, like the first embodiment, shows a light-emitting diode structure as the gallium nitride semiconductor laminate 102, but the gallium nitride semiconductor device 100 is not limited to a light-emitting diode. By changing the stacking order and arrangement within the gallium nitride semiconductor layers, various semiconductor devices such as transistors and thyristors can be realized.

[0061] A light-emitting diode (LED) can be provided by the structure and manufacturing method of a gallium nitride-based semiconductor device 100 according to one embodiment of the present invention. This light-emitting diode (LED) can be provided as an individual component. The individual component can be used, for example, as a light source for a lighting fixture or as a light source for a backlight of a liquid crystal display. Furthermore, a microLED display can be provided using the light-emitting diode (LED) provided according to one embodiment of the present invention.

[0062] A gallium nitride-based semiconductor device 100 according to one embodiment of the present invention can provide small-signal transistors and power transistors by changing the stacked structure. Specifically, by applying the tunnel junction configuration disclosed in one embodiment of the present invention to the contact structure between the source and drain and the electrodes, it is possible to provide transistors with low contact resistance, low power consumption, and excellent operating characteristics.

[0063] 100: Gallium nitride semiconductor device, 101: Exfoliation layer, 102: Gallium nitride semiconductor laminate, 1022: Undoped gallium nitride semiconductor layer, 1023: First distributed Bragg reflective layer, 1024: n-type gallium nitride semiconductor layer, 1026: Light-emitting layer, 1028: p-type gallium nitride semiconductor layer, 1028A: First p-type gallium nitride semiconductor layer, 1028B: Second p-type gallium nitride semiconductor layer, 104: Passivation layer, 1042: First aperture, 1044: Second aperture, 106: n-type gallium nitride semiconductor layer, 107: Second distributed Bragg reflective layer, 108: First electrode, 110: Second electrode, 120: Bonding layer, 150: ・BR>X holding substrate, 180, 190: Single crystal substrate, 182: Carrier substrate

Claims

1. A gallium nitride semiconductor device comprising: a gallium nitride semiconductor laminate including a p-type gallium nitride semiconductor layer; a passivation layer covering the gallium nitride semiconductor laminate; an n-type gallium nitride semiconductor layer on the passivation layer; and an electrode in contact with the n-type gallium nitride semiconductor layer, wherein the passivation layer has an opening on the upper surface of the p-type gallium nitride semiconductor layer, and the n-type gallium nitride semiconductor layer forms a tunnel junction with the p-type gallium nitride semiconductor layer at the opening.

2. The gallium nitride semiconductor device according to claim 1, wherein the p-type gallium nitride semiconductor layer comprises a first p-type gallium nitride semiconductor layer and a second p-type gallium nitride semiconductor layer on the first p-type gallium nitride semiconductor layer, the dopant concentration of the second p-type gallium nitride semiconductor layer is higher than the dopant concentration of the first p-type gallium nitride semiconductor layer, and the second p-type gallium nitride semiconductor layer forms a tunnel junction with the n-type gallium nitride semiconductor layer.

3. The gallium nitride semiconductor device according to claim 2, wherein the n-type gallium nitride semiconductor layer is an n-type gallium nitride semiconductor layer or an n-type aluminum gallium nitride semiconductor layer.

4. The donor impurity concentration of the n-type gallium nitride semiconductor layer or the n-type aluminum gallium nitride semiconductor layer is 1 × 10 ２０ / cm ３ The above 5 x 10 ２１ / cm ３ The gallium nitride semiconductor device according to claim 3, which is as follows:

5. The gallium nitride semiconductor device according to claim 1, wherein the gallium nitride semiconductor laminate is bonded to the support substrate with a bonding layer in between.

6. The gallium nitride semiconductor device according to claim 5, wherein the passivation layer covers the upper surface and side surface of the gallium nitride semiconductor laminate and the side surface of the junction layer.

7. The gallium nitride semiconductor device according to claim 5, wherein the passivation layer covers the top and side surfaces of the gallium nitride semiconductor laminate, and the junction layer is exposed from the passivation layer.

8. The gallium nitride semiconductor device according to claim 2, wherein the gallium nitride semiconductor laminate includes an undoped gallium nitride semiconductor layer, an n-type gallium nitride semiconductor layer above the undoped gallium nitride semiconductor layer, and a light-emitting layer between the n-type gallium nitride semiconductor layer and the first p-type gallium nitride semiconductor layer, and a distributed Bragg reflective layer is provided between the undoped gallium nitride semiconductor layer and the n-type gallium nitride semiconductor layer.

9. A method for manufacturing a gallium nitride semiconductor device, characterized by forming a gallium nitride semiconductor laminate including a p-type gallium nitride semiconductor layer, forming a passivation layer covering the gallium nitride semiconductor laminate, forming contact holes in the passivation layer to expose the p-type gallium nitride semiconductor layer, and depositing an n-type gallium nitride semiconductor layer on the p-type gallium nitride semiconductor layer exposed by the passivation layer and the contact holes by sputtering to form a tunnel junction with the p-type gallium nitride semiconductor layer.

10. A method for manufacturing a gallium nitride semiconductor device according to claim 9, comprising forming the p-type gallium nitride semiconductor layer with a first p-type gallium nitride semiconductor layer and a second p-type gallium nitride semiconductor layer on the first p-type gallium nitride semiconductor layer, wherein the dopant concentration of the second p-type gallium nitride semiconductor layer is higher than that of the first p-type gallium nitride semiconductor layer, and depositing the n-type gallium nitride semiconductor layer on the second p-type gallium nitride semiconductor layer exposed by the contact hole by sputtering.

11. The method for manufacturing a gallium nitride semiconductor device according to claim 10, wherein the n-type gallium nitride semiconductor layer is formed from an n-type gallium nitride semiconductor layer or an n-type aluminum gallium nitride semiconductor layer.

12. The donor impurity concentration of the n-type gallium nitride semiconductor layer or the n-type aluminum gallium nitride semiconductor layer is 1 × 10⁻⁶ ２０ / cm ３ The above 5 x 10 ２１ / cm ３ A method for fabricating the gallium nitride-based semiconductor device described in claim 11, wherein the device is formed as follows.

13. A method for manufacturing a gallium nitride semiconductor device according to claim 9, comprising stacking a plurality of gallium nitride semiconductor layers on a single crystal substrate to form an element isolation region, forming the gallium nitride semiconductor laminate on the single crystal substrate, separating the gallium nitride semiconductor laminate from the single crystal substrate and bonding it to a support substrate via a bonding layer, and forming the passivation layer on the support substrate so as to cover the gallium nitride semiconductor laminate.

14. A method for manufacturing a gallium nitride semiconductor device according to claim 13, wherein the passivation layer is formed to cover the upper surface and side surface of the gallium nitride semiconductor laminate and the side surface of the junction layer.

15. A method for manufacturing a gallium nitride semiconductor device according to claim 9, comprising: stacking a plurality of gallium nitride semiconductor layers on a single crystal substrate to form the gallium nitride semiconductor laminate; forming the passivation layer so as to cover the gallium nitride semiconductor laminate on the single crystal substrate; and separating the gallium nitride semiconductor laminate from the single crystal substrate and bonding it to a support substrate via a bonding layer.

16. A method for manufacturing a gallium nitride semiconductor device according to claim 9, comprising forming the gallium nitride semiconductor laminate on a single crystal substrate using an undoped gallium nitride semiconductor layer, an n-type gallium nitride semiconductor layer above the undoped gallium nitride semiconductor layer, an emissive layer above the n-type gallium nitride semiconductor layer, and the p-type gallium nitride semiconductor layer above the emissive layer.

17. A method for manufacturing a gallium nitride-based semiconductor device according to claim 16, wherein a distributed Bragg reflective layer is formed between the undoped gallium nitride semiconductor layer and the n-type gallium nitride semiconductor layer.

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