Semiconductor element and semiconductor device

Abstract

Provided is a semiconductor element comprising an oxide semiconductor layer provided in a wiring layer, wherein, in a plan view of the semiconductor element, the oxide semiconductor layer is surrounded by a first barrier layer, and the first barrier layer includes a metal film.

Description

Semiconductor devices and semiconductor devices

[0001] This disclosure relates to semiconductor devices and semiconductor devices.

[0002] In recent years, as an example of a semiconductor device, development has been progressing on a display device that uses electroluminescent (EL) elements as light-emitting elements. This display device has, for example, multiple light-emitting elements composed of a lower electrode, a light-emitting layer stacked on the lower electrode, and an upper electrode stacked on the light-emitting layer. Furthermore, in addition to the light-emitting elements described above, the display device has a drive circuit that includes multiple transistors (semiconductor elements) for driving the light-emitting elements.

[0003] In recent years, it has been proposed to form some of multiple transistors as thin-film transistors (TFTs). By making some of the multiple transistors thin-film transistors, it becomes possible to place these transistors, for example, within a wiring layer located above the semiconductor substrate. As a result, the layout size of the above-mentioned drive circuit can be reduced, and a display device, which is an example of a semiconductor device, can be miniaturized.

[0004] Japanese Patent Publication No. 2020-107898 Japanese Patent Publication No. 2023-086839

[0005] Thin-film transistors have an oxide semiconductor layer, and this oxide semiconductor layer is susceptible to oxidation and reduction due to the influence of the surrounding film. Therefore, in order to obtain a thin-film transistor with desired characteristics (e.g., threshold voltage), it is necessary to suitably adjust and stabilize the characteristics of the oxide semiconductor layer.

[0006] Therefore, this disclosure proposes a semiconductor device and a semiconductor device that can adjust and stabilize the properties of an oxide semiconductor layer.

[0007] The present disclosure provides a semiconductor device comprising an oxide semiconductor layer provided within a wiring layer, wherein, in a plan view of the semiconductor device, the oxide semiconductor layer is surrounded by a first barrier layer, and the first barrier layer includes a metal film.

[0008] Furthermore, the present disclosure provides a semiconductor device comprising a wiring layer and a first semiconductor element, wherein the first semiconductor element comprises a first oxide semiconductor layer provided within the wiring layer, and in a plan view of the first semiconductor element, the first oxide semiconductor layer is surrounded by a first barrier layer, the first barrier layer comprising a metal film.

[0009] This is a schematic diagram showing an example of the overall structure of a display device according to an embodiment of this disclosure. This is a circuit diagram showing an example of a pixel of a display device according to an embodiment of this disclosure. This is a schematic diagram showing an example of a cross-sectional structure of a pixel according to a comparative example. This is a cross-sectional view showing an example of the detailed structure of a thin-film transistor according to the first embodiment of this disclosure. This is a plan view showing an example of the detailed structure of a thin-film transistor according to the first embodiment of this disclosure. This is a cross-sectional view showing an example of the detailed structure of a thin-film transistor according to a modified example of the first embodiment of this disclosure. This is a plan view (1) showing an example of the detailed structure of a thin-film transistor according to the second embodiment of this disclosure. This is a plan view (2) showing an example of the detailed structure of a thin-film transistor according to the second embodiment of this disclosure. This is a plan view (3) showing an example of the detailed structure of a thin-film transistor according to the second embodiment of this disclosure. This is a plan view (4) showing an example of the detailed structure of a thin-film transistor according to the second embodiment of this disclosure. This is a plan view (5) showing an example of the detailed structure of a thin-film transistor according to the second embodiment of this disclosure. This is a plan view (6) showing an example of the detailed structure of a thin-film transistor according to the second embodiment of this disclosure. This is a cross-sectional view (1) showing an example of the detailed structure of a thin-film transistor according to the third embodiment of this disclosure. This is a cross-sectional view (2) showing an example of the detailed structure of a thin-film transistor according to the third embodiment of this disclosure. This is a cross-sectional view (part 3) showing an example of the detailed structure of a thin-film transistor according to the third embodiment of this disclosure. This is a cross-sectional view (part 1) showing an example of the detailed structure of a thin-film transistor according to the fourth embodiment of this disclosure. This is a cross-sectional view (part 2) showing an example of the detailed structure of a thin-film transistor according to the fourth embodiment of this disclosure. This is a cross-sectional view (part 1) showing an example of the detailed structure of the main part of a display device according to the fifth embodiment of this disclosure. This is a cross-sectional view (part 2) showing an example of the detailed structure of the main part of a display device according to the fifth embodiment of this disclosure. This is a cross-sectional view (part 3) showing an example of the detailed structure of the main part of a display device according to the fifth embodiment of this disclosure. This is a cross-sectional view showing an example of the detailed structure of the main part of a display device according to the sixth embodiment of this disclosure. This is a plan view showing an example of the detailed structure of the main part of a display device according to the sixth embodiment of this disclosure. This is a cross-sectional view showing an example of the detailed structure of the main part of a display device according to the seventh embodiment of this disclosure.This is a cross-sectional view showing an example of the detailed structure of a thin-film transistor according to the eighth embodiment of this disclosure. This is a cross-sectional view (1) for explaining the manufacturing method of a thin-film transistor device according to the ninth embodiment of this disclosure. This is a cross-sectional view (2) for explaining the manufacturing method of a thin-film transistor device according to the ninth embodiment of this disclosure. This is a cross-sectional view (3) for explaining the manufacturing method of a thin-film transistor device according to the ninth embodiment of this disclosure. This is a cross-sectional view (4) for explaining the manufacturing method of a thin-film transistor device according to the ninth embodiment of this disclosure. This is a cross-sectional view (1) for explaining the manufacturing method of a thin-film transistor device according to modification 1 of the ninth embodiment of this disclosure. This is a cross-sectional view (2) for explaining the manufacturing method of a thin-film transistor device according to modification 1 of the ninth embodiment of this disclosure. This is a cross-sectional view for explaining the manufacturing method of a thin-film transistor device according to modification 2 of the ninth embodiment of this disclosure. This is a cross-sectional view for explaining the manufacturing method of a thin-film transistor device according to modification 3 of the ninth embodiment of this disclosure. This is a front view showing an example of the appearance of a digital still camera. This is a rear view showing an example of the appearance of a digital still camera. This is an external view of a head-mounted display. This is an external view of a see-through head-mounted display. This is an external view of a television device. This is an external view of a smartphone. This is a diagram (1) showing the internal configuration of an automobile. This is a diagram (part 2) showing the internal structure of an automobile.

[0010] Preferred embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numeral to avoid redundant explanation. In addition, in this specification and drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding a different alphabet after the same reference numeral. However, if there is no particular need to distinguish each of multiple components having substantially the same or similar functional configurations, only the same reference numeral will be used.

[0011] In addition, the drawings referred to in the following description are for facilitating the description and understanding of an embodiment of the present disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from actual ones. Furthermore, the design of the apparatus shown in the drawings can be appropriately modified in consideration of the following description and known techniques.

[0012] Descriptions of specific shapes in the following description do not only mean geometrically defined shapes. Specifically, descriptions of specific lengths and shapes in the following description shall also include cases where there are differences (errors, distortions) within an allowable range in the display device (which is an example of a semiconductor device), the manufacturing processes thereof, and the use and operation thereof, as well as shapes similar to the described shape.

[0013] In addition, in the following description of circuits (electrical connections), unless otherwise specified, "electrically connected" means connecting a plurality of elements such that electricity (a signal) can conduct between them. In addition, "electrically connected" in the following description shall include not only cases where a plurality of elements are directly and electrically connected, but also cases where they are indirectly and electrically connected via other elements.

[0014] The description will be given in the following order: 1. Display device according to an embodiment of the present disclosure 1.1 Display device 1.2 Pixel 2. Background that led to the creation of the embodiment of the present disclosure 3. First embodiment 3.1 Detailed structure 3.2 Modification 4. Second embodiment 5. Third embodiment 6. Fourth embodiment 7. Fifth embodiment 8. Sixth embodiment 9. Seventh embodiment 10. Eighth embodiment 11. Ninth embodiment 11.1 Manufacturing method 11.2 Modification 12. Summary 13. Application examples 14. Supplementary note

[0015] <<1. Display device according to an embodiment of the present disclosure>> <1.1 Display device> First, with reference to FIG. 1, an example of the overall structure of a display device 10 according to an embodiment of the present disclosure, which can be used as a display device or a lighting device that is an example of a semiconductor device, will be described. FIG. 1 is a schematic diagram illustrating an example of the overall structure of the display device 10 according to an embodiment of the present disclosure.

[0016] The display device 10 is, for example, a device in which light-emitting elements such as OLEDs (Organic Light Emitting Diodes) or Micro-OLEDs are formed in an array. Such a display device 10 can be applied to, for example, display devices for VR (Virtual Reality), MR (Mixed Reality), or AR (Augmented Reality), electronic viewfinders (EVFs), or small projectors.

[0017] Furthermore, in the embodiments of this disclosure, the light-emitting element may be a self-emissive element as well as a current-driven electro-optic element. For example, in addition to OLEDs, current-driven electro-optic elements include inorganic EL elements, LED elements, semiconductor laser elements, etc. Furthermore, an organic EL display device using an OLED as the light-emitting element has the following features. Specifically, because the OLED is a self-emissive element, the organic EL display device has higher image visibility compared to liquid crystal display devices, which are also planar display devices, and is easy to make lighter and thinner because it does not require lighting members such as backlights. Moreover, because the response speed of OLED is very fast, on the order of a few microseconds, the organic EL display device does not produce afterimages when displaying moving images.

[0018] Here, as an example, we will explain using an active-matrix organic EL display device that uses a current-driven light-emitting element, such as an OLED, which changes its luminescence depending on the current flowing through the device, as the light-emitting element. Hereafter, "active-matrix organic EL display device" will simply be referred to as "display device".

[0019] As shown in Figure 1, the display device 10 has a configuration comprising a pixel array section 30 in which a plurality of pixels 20, including light-emitting elements, are arranged in a matrix-like (two-dimensional) arrangement on a semiconductor substrate (not shown), and a drive circuit section arranged around the pixel array section 30. The drive circuit section includes, for example, a write scanning section 40, a first drive scanning section 50, a second drive scanning section 60, and a signal output section 70 mounted on the same display panel 80 as the pixel array section 30, and drives each pixel 20 of the pixel array section 30.

[0020] Here, if the display device 10 is color-compatible, one pixel (unit pixel / pixel), which is the unit that forms a color image, is composed of multiple subpixels (subpixels / subpixels). In this case, each subpixel corresponds to pixel 20 in Figure 1. More specifically, in a color-compatible display device 10, one pixel 20 may be composed of three subpixels, for example, a subpixel that emits red light, a subpixel that emits green light, and a subpixel that emits blue light. Alternatively, the display device 10 may be composed of one, two, or more subpixels, and is not particularly limited. Furthermore, one pixel 20 is not limited to a combination of subpixels of the three primary colors, such as red, green, and blue, but may also be composed of subpixels of one or more additional colors in addition to the three primary color subpixels. More specifically, the display device 10 may, for example, configure one pixel 20 by adding a sub-pixel that emits white light to improve brightness, or configure one pixel 20 by adding at least one sub-pixel that emits complementary color light to expand the color reproduction range.

[0021] In the pixel array section 30, scan lines 31 (31) are provided along the row direction (arrangement direction of the pixels 20 in the pixel row / horizontal direction) for the m row and n column arrangement of pixels 20. １ ~31 ｍ ), and drive line 32 (32 １ ~32 ｍ ) is wired for each pixel row. Furthermore, for an array of m rows and n columns of pixels 20, signal lines 34 (34 １ ~34 ｎ) are wired for each pixel column.

[0022] Scan line 31 １ to 31 ｍ are each electrically connected to the output terminal of the corresponding row of the write scanning section 40. Drive line 32 １ to 32 ｍ are each electrically connected to the output terminal of the corresponding row of the drive scanning section 50. Signal line 34 １ to 34 ｎ are each electrically connected to the output terminal of the corresponding column of the signal output section 70.

[0023] The write scanning section 40 is configured by a shift register circuit or the like. When writing the signal voltage of a video signal to each pixel 20 of the pixel array section 30, the write scanning section 40 applies a write scan signal WS (WS １ to 31 ｍ ) to the scan line 31 (31 １ to WS ｍ ) sequentially, whereby each pixel 20 of the pixel array section 30 can be scanned sequentially on a row-by-row basis.

[0024] The first drive scanning section 50, similar to the write scanning section 40, is configured by a shift register circuit or the like. The drive scanning section 50, in synchronization with the line-sequential scanning performed by the write scanning section 40, applies a light emission control signal DS (DS １ to 32 ｍ ) to the drive line 32 (32 １ to DS ｍ ) to control light emission / non-light emission (extinction) of the pixels 20.

[0025] The signal output section 70 outputs a signal voltage of a video signal (hereinafter simply referred to as "signal voltage") V ｓｉｇ and a reference voltage V ｏｆｓ selectively in accordance with luminance information supplied from a signal supply source (not shown). Here, the reference voltage V ｏｆｓ corresponds to a voltage serving as a reference for the signal voltage V ｓｉｇ of the video signal, or is a voltage in the vicinity thereof.

[0026] The signal voltage V ｓｉｇ / Reference voltage V ｏｆｓ This is the signal line 34 (34 １ ~34 ｎ The data is written to each pixel 20 of the pixel array 30 via the write scanning unit 40 in units of pixel rows selected by line sequential scanning. That is, the signal output unit 70 outputs a signal voltage V ｓｉｇ It can be written in units of pixel rows (lines).

[0027] In the display device 10, by switching off the drive transistor Tr1 (see Figure 2) included in the pixel 20 (described later), the current supply to the light-emitting element EL (see Figure 2) included in the pixel 20 is cut off, and as a result the light emission of the light-emitting element EL is suppressed, so black gradation can be displayed. However, when the drive transistor Tr1 is switched off, current may leak between the source and drain of the drive transistor Tr1, which may reduce the contrast when displaying black gradation. Therefore, in order to avoid a decrease in contrast when displaying black gradation, the drive unit of the display device 10 has a second drive scanning unit 60, and further, a second drive line 33 (33) along the row direction. １ ~33 ｍ ) is wired for each pixel row. Second drive line 33 １ ~33 ｍ These are connected to the output terminals of the corresponding rows of the second drive scanning unit 60.

[0028] In detail, the second drive scanning unit 60 is configured with a shift register circuit and the like, similar to the write scanning unit 40. This second drive scanning unit 60 synchronizes with the line sequential scanning by the write scanning unit 40 to the second drive line 33 (33 １ ~33 ｍ ) drive signal AZ (AZ １ ~AZ ｍ By supplying (), control can be performed to prevent the pixel 20 from emitting light during the non-emitting period.

[0029] The example of the overall structure shown in Figure 1 is just one example of the overall structure of the display device 10 according to the embodiment of this disclosure, and the structure of the display device 10 according to the embodiment of this disclosure is not limited to the structure shown in Figure 1.

[0030] <1.2 Pixels> Next, the circuit configuration of the pixels (pixel circuits) 20 of the display device 10 according to the embodiment of the present disclosure shown in Figure 1 will be described. Figure 2 is a circuit diagram showing an example of the pixels 20 of the display device 10 according to the embodiment of the present disclosure.

[0031] In the embodiments of this disclosure, as shown in Figure 2, the pixel 20 is composed of a light-emitting element EL and a drive circuit that drives it. The light-emitting element EL is an example of a current-driven electro-optic element whose luminescence changes according to the current value flowing through the device, and is, for example, an OLED. The cathode of the light-emitting element EL is, for example, a node V for discharging current. ｓｓ It is electrically connected to it.

[0032] The drive circuit consists of multiple transistors electrically connected to the light-emitting element EL (drive transistor Tr1, writing transistor Tr2, light emission control transistor Tr3, switching transistor Tr4), and capacitance units C1 and C2. The anode of the light-emitting element EL is electrically connected to the drive transistor Tr1, and when current flows through the drive transistor Tr1, it can emit light.

[0033] Furthermore, the drive transistor (also called the light-emitting transistor) Tr1 and the write transistor (also called the data write control transistor) Tr2 are, for example, field-effect transistors (FETs). More specifically, the drive transistor Tr1 is a P-channel type transistor, and the write transistor Tr2 is an N-channel type transistor. Also, the light-emitting control transistor (also called the power supply control transistor) Tr3 and the switching transistor (also called the quenching control transistor) Tr4 are, for example, field-effect transistors. More specifically, the light-emitting control transistor Tr3 is a P-channel type transistor, and the switching transistor Tr4 is an N-channel type transistor.

[0034] More specifically, as shown in Figure 2, the source and drain of the drive transistor Tr1 are connected to the power supply voltage V via the drain of the light emission control transistor Tr3, which will be described later.ＤＤ The power node (current source) and the anode electrode of the light-emitting element EL are electrically connected, respectively. In addition, the source and drain of the writing transistor Tr2 are connected to the signal line (V ｓｉｇ The gate of the drive transistor Tr1 is electrically connected to the power supply voltage V, and the gate of the writing transistor Tr2 is electrically connected to the scan line (WS). In addition, the light emission control transistor Tr3 is electrically connected to the power supply voltage V ＤＤ The power supply node and the source of the drive transistor Tr1 are electrically connected. Additionally, the switching transistor Tr4 is electrically connected between the drain of the drive transistor Tr1 and the current discharge node Vss.

[0035] The drive transistor Tr1 can drive the light-emitting element EL by supplying a drive current to the light-emitting element EL that corresponds to the holding voltage (signal voltage) of the capacitance section C1, which will be described later.

[0036] The writing transistor Tr2 receives the signal voltage V supplied from the signal output unit 70. ｓｉｇ The signal can be sampled and written to the gate of the drive transistor Tr1. Here, "writing" means applying a signal voltage to the gate node, so that the potential of the gate node is maintained at a potential based on that signal voltage.

[0037] Furthermore, the light emission control transistor Tr3 controls the emission / non-emission of the light-emitting element EL under the drive of the light emission control signal DS.

[0038] The switching transistor Tr4 controls the light-emitting element EL to not emit light during its non-emitting period, under the drive signal AZ. In other words, by becoming conductive, the switching transistor Tr4 plays the role of creating a bypass path around the light-emitting element EL so that no current is supplied to the light-emitting element EL. In this way, even if current leaks between the source and drain of the drive transistor Tr1 when it is switched to the off state, the switching transistor Tr4 becomes conductive, preventing current from being supplied to the light-emitting element EL. As a result, this configuration makes it possible to suppress the decrease in contrast when displaying black tones.

[0039] Furthermore, the capacitance unit C1 is connected between the gate and source of the drive transistor Tr1 and holds the signal voltage Vsig written by sampling by the write transistor Tr2. The drive transistor Tr1 drives the light-emitting element EL by supplying a drive current to the light-emitting element EL corresponding to the holding voltage of the capacitance unit C1.

[0040] Furthermore, the capacitance section C2 connects the source of the drive transistor Tr1 to a node with a fixed potential (for example, the power supply voltage V). ＤＤ It is connected between the power node and the capacitor C2. The capacitance C2 is connected to the signal voltage V ｓｉｇ This suppresses fluctuations in the source voltage of the drive transistor Tr1 when data is written to it, and also has the effect of setting the gate-source voltage Vgs of the drive transistor Tr1 to the threshold voltage Vth of the drive transistor Tr1.

[0041] Note that the circuit configuration example shown in Figure 2 is just one example of the circuit configuration of the pixel 20 in this embodiment, and the circuit configuration of the pixel 20 in this embodiment is not limited to the circuit configuration shown in Figure 2.

[0042] <<2. Background to the Creation of the Embodiments of the Disclosure>> Next, before describing the details of the embodiments of the Disclosure, the background to the creation of the embodiments of the Disclosure will be explained with reference to Figure 3. Figure 3 is a schematic diagram showing an example of the cross-sectional structure of a pixel 20a related to a comparative example. Here, the comparative example refers to a pixel 20a that the inventor had been studying before creating the embodiments of the Disclosure.

[0043] Up to this point, the inventors have been studying a pixel 20a related to a comparative example as shown in Figure 3. In the comparative example shown in Figure 3, a wiring layer 200 is provided on a semiconductor substrate 100, and a light-emitting part 300, which is a light-emitting element EL, is provided on the wiring layer 200. The semiconductor substrate 100 is also provided with, for example, a drive transistor Tr1 and a light-emitting control transistor Tr3, which are included in the drive circuit. Above the wiring layer 200, for example, a write transistor Tr2 and a switching transistor Tr4, which are included in the drive circuit, are provided. The write transistor Tr2 and the switching transistor Tr4 are configured as thin-film transistors.

[0044] In detail, among the multiple transistors, for example, the drive transistor Tr1 (labeled "Drv" in Figure 3) and the light emission control transistor Tr3 (labeled "DS" in Figure 3) are provided on the semiconductor substrate 100. Specifically, the drive transistor Tr1 and the light emission control transistor Tr3 have gate electrodes 102 provided via a gate insulating film on a region with an n-type conductivity that functions as a channel region provided within the semiconductor substrate 100. Furthermore, these transistors Tr1 and Tr3 are provided within the semiconductor substrate 100 so as to sandwich the channel region and have a source / drain consisting of a diffusion region 104 containing impurities with a p-type conductivity. These transistors are also isolated from other elements by a shallow trench isolation (STI) 106 provided within the semiconductor substrate 100.

[0045] Furthermore, as shown in Figure 3, a wiring layer 200 is provided on the semiconductor substrate 100, and the wiring layer 200 includes an insulating film 202, wiring 204, and vias 206, etc. Although not shown, a barrier film may be provided within the wiring layer 200 to prevent the diffusion of metal species from the wiring 204, etc.

[0046] Furthermore, as shown in Figure 3, among the multiple transistors, the writing transistor Tr2 (labeled "WS" in Figure 3) and the switching transistor Tr4 (labeled "AZ" in Figure 3) are thin-film transistors provided within the wiring layer 200. More specifically, the writing transistor Tr2 and the switching transistor Tr4 each have an oxide semiconductor layer 210 provided within the wiring layer 200 and a gate electrode 212 that contacts the oxide semiconductor layer 210 via a gate insulating film.

[0047] Furthermore, as shown in Figure 3, a light-emitting unit 300, which is a light-emitting element (EL), is provided on the wiring layer 200. The light-emitting element (EL) mainly comprises an anode electrode 310 provided on the wiring layer 200, a light-emitting layer 314 stacked on the anode electrode 310 that emits light, and a cathode electrode 312 stacked on the light-emitting layer 314 that transmits light from the light-emitting layer 314. For example, the light-emitting element (EL) can be an OLED (Organic Light-Emitting Diode) having a light-emitting layer 314 made of an organic material.

[0048] In other words, in the comparative example, the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided on the semiconductor substrate 100. Furthermore, in the comparative example, the writing transistor Tr2 and the switching transistor Tr4 are provided as thin-film transistors within the wiring layer 200 stacked on the semiconductor substrate 100. In this way, in the comparative example, thin-film transistors can be stacked while ensuring high breakdown voltage for the specified transistors, thereby reducing the size of the drive circuit. As a result, the display device 10 can be miniaturized according to the comparative example.

[0049] Furthermore, the writing transistor Tr2 and the switching transistor Tr4, which are provided as thin-film transistors, use the oxide semiconductor layer 210 as a channel. In the comparative example, by using such thin-film transistors, not only can the display device 10 be miniaturized, but low power consumption can also be achieved because the leakage current of Tr2 and Tr3 is small.

[0050] The oxide semiconductor layer 210, which forms the channel of a thin-film transistor, is made of, for example, indium-gallium-zinc oxide (IGZO) and has the property of being easily oxidized and reduced by the influence of surrounding layers. Specifically, when the oxide semiconductor layer 210 is reduced by electrons donated from surrounding layers, it becomes less resistive and becomes a conductor. On the other hand, when the oxide semiconductor layer 210 is oxidized by electrons taken from surrounding layers, it becomes more resistive and becomes a semiconductor, and further oxidation changes it into an insulator. Therefore, in order to obtain a thin-film transistor with desired characteristics (e.g., threshold voltage), it is strongly required to suitably adjust and stabilize the characteristics of the oxide semiconductor layer 210. In addition, it is preferable not only to adjust the characteristics of the oxide semiconductor layer 210 for each thin-film transistor, but also to adjust the characteristics for each region of the oxide semiconductor layer 210 (channel region, source region, drain region). However, in the comparative example, it is difficult to suitably adjust and stabilize the characteristics of the oxide semiconductor layer 210 because oxygen and hydrogen diffuse from surrounding films such as the insulating film 202.

[0051] Therefore, in view of these circumstances, the inventors have come up with the following embodiments of the disclosure, which are capable of adjusting and stabilizing the properties of the oxide semiconductor layer 210. The details of the embodiments of the disclosure created by the inventors will be described in order below.

[0052] <<3. First Embodiment>> <3.1 Detailed Structure> First, the detailed structure of the thin-film transistor (semiconductor element) Tr5 according to the first embodiment of the present disclosure will be described with reference to Figures 4A and 4B. Figure 4A is a cross-sectional view showing an example of the detailed structure of the thin-film transistor Tr5 according to this embodiment, and in detail shows a cross-sectional view (also referred to as a cross-sectional view in this specification) when the thin-film transistor Tr5 is cut in the stacking direction. Figure 4B is a plan view (also referred to as a plan view in this specification) showing an example of the detailed structure of the thin-film transistor Tr5 according to this embodiment, and in detail shows a cross-sectional view when the thin-film transistor Tr5 is cut along the line B-B' shown in Figure 4A. In these figures, the gate region of the thin-film transistor Tr5 is denoted by "G", and the source / drain regions are denoted by "S" and "D", respectively.

[0053] As shown in Figure 4A, the thin-film transistor Tr5 according to this embodiment is provided within a wiring layer 200 laminated on a semiconductor substrate (not shown), such as a silicon substrate. The wiring layer 200 has an insulating film 202 and a plurality of wirings 204. In this embodiment, the insulating film 202 is, for example, silicon oxide (SiO₂), which is an oxygen-containing film. ｘ ) etc. More specifically, the insulating film 202 can be formed from, for example, silicon oxide deposited by CVD (Chemical Vapor Deposition) using TEOS (Tetra Ethoxy Silane), or silicon oxide deposited at low temperature. In this embodiment, the wiring 204 can be formed from, for example, a metal film or alloy film of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or a lamination thereof.

[0054] In this embodiment, the lower surface and / or upper surface of the wiring layer 200 (more specifically, the insulating film 202) may be covered with a barrier layer (second barrier layer) 250 that prevents the diffusion of metal species from the wiring 204, as shown in Figure 4A. The barrier layer 250 is silicon nitride (SiN ｘIt can be formed from an insulating material such as ) or silicon carbonitride (SiCN). In this embodiment, the barrier layer 250 may also have the effect of diffusing hydrogen and reducing other materials.

[0055] Furthermore, in this embodiment, although not shown in the figures, a light-emitting section 300 including, for example, a light-emitting element EL may be provided above the wiring layer 200. In such a case, the light-emitting element EL may be electrically connected to the thin-film transistor Tr5 described below.

[0056] Furthermore, in this embodiment, the thin-film transistor Tr5 has an oxide semiconductor layer (first oxide semiconductor layer) 210 provided within the wiring layer 200, and a gate electrode 212 provided on the channel region of the oxide semiconductor layer 210 via a gate insulating film 214. More specifically, as shown in Figure 4A, in this embodiment, the channel region of the thin-film transistor Tr5 is located in the center of the oxide semiconductor layer 210, and the source / drain regions of the thin-film transistor Tr5 are located at both ends of the oxide semiconductor layer 210.

[0057] The oxide semiconductor layer 210 can be formed from an oxide film containing, for example, at least one element selected from the group consisting of aluminum (Al), indium (In), gallium (Ga), tin (Sn), silicon (Si), hafnium (Hf), and zinc (Zn). More specifically, the oxide semiconductor layer 210 may be, for example, indium oxide (In ２ O ３ ), tin-indium oxide (In ２ O ３ Sn is added as a dopant, for example, ITO), indium-gallium-zinc oxide (ZnO) ４ In and Ga are added as dopants, for example, IGZO), indium-gallium oxide (In ２ O ３ -Ga ２ O ３These can be formed from aluminum zinc oxide (ZnO with Al added as a dopant, e.g., AZO), indium zinc oxide (ZnO with In added as a dopant, e.g., IZO), indium tin zinc oxide (ZnO with In and Sn added as dopants, e.g., ITZO), indium aluminum zinc oxide (ZnO with In and Al added as dopants, e.g., IAZO), etc. In this embodiment, since these oxide semiconductors have extremely small leakage currents, leakage in the thin-film transistor Tr5 can be suppressed.

[0058] In this embodiment, the oxide semiconductor layer 210 is not limited to being provided in a strip shape as shown in Figure 4B; for example, the drain region, channel region, and source region may have different widths.

[0059] Furthermore, the gate insulating film 214 of the thin-film transistor Tr5 is provided on the channel region located in the center of the oxide semiconductor layer 210, and can be formed from an oxide film or nitride film containing, for example, silicon (Si), hafnium (Hf), or aluminum (Al). More specifically, the gate insulating film 214 may be, for example, silicon oxide (SiO ｘ ), silicon nitride (SiN ｘ ), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum oxide (AlO ｘ ), aluminum oxynitride (AlON), hafnium oxide (HfO ｘ It can be formed from materials such as oxyhafnium nitride (HfON), etc.

[0060] Furthermore, the gate electrode 212 of the thin-film transistor Tr5 is provided on the gate insulating film 214, as shown in Figure 4A. The gate electrode 212 can also be formed from a metal film, nitride film, or alloy thereof, which contains at least one element selected from the group consisting of silicon (Si), aluminum (Al), titanium (Ti), tungsten (W), niobium (Nb), and molybdenum (Mo). More specifically, the gate electrode 212 can be made from, for example, tungsten (W), titanium nitride (TiNb), or ｘIt can be formed from materials such as polysilicon (poly-Si).

[0061] Furthermore, in this embodiment, as shown in Figure 4A, the edges of the oxide semiconductor layer 210, which forms the source / drain region of the thin-film transistor Tr5, are electrically connected to the wiring 204 located above the via 206 via the via 206. The via 206 can be formed from, for example, a metal film such as tungsten (W) or copper (Cu).

[0062] Furthermore, in this embodiment, as shown in Figure 4A, the drain region of the thin-film transistor Tr5 is electrically connected to the barrier layer (first barrier layer) 222 via vias 206 and wiring 204. Furthermore, as shown in Figure 4A, the barrier layer 222 is provided so as to penetrate the wiring layer 200. Also, as shown in Figure 4B, the barrier layer 222 has, for example, a rectangular frame shape and is provided so as to surround the oxide semiconductor layer 210 of the thin-film transistor Tr5. In other words, in this embodiment, the barrier layer 222 has a wall-like shape that surrounds the oxide semiconductor layer 210 from two directions (left and right) in a cross-sectional view and from four directions (up, down, left, and right) in a plan view. Also, the barrier layer 222 can be formed from a metal film such as tungsten (W) or copper (Cu).

[0063] As described above, in this embodiment, the barrier layer 222 is provided so as to sandwich the oxide semiconductor layer 210 of the thin-film transistor Tr5 from both sides in a cross-sectional view of the thin-film transistor Tr5, and surround it in a plan view of the thin-film transistor Tr5. Furthermore, since the barrier layer 222 is made of a metallic material, it is possible to suppress the diffusion of oxygen and hydrogen from the insulating film 202 and the barrier layer 250, which are films located outside the barrier layer 222, into the oxide semiconductor layer 210. In other words, in this embodiment, by providing the barrier layer 222 as described above, it is possible to suppress the unintentional oxidation or reduction of the oxide semiconductor layer 210, which can lead to changes in its properties.

[0064] In this embodiment, the barrier layer 222 is not limited to penetrating the entire insulating film 202 of the wiring layer 200 in a cross-sectional view, as shown in Figure 4A; for example, it may penetrate only a part of the insulating film 202. Furthermore, in this embodiment, as will be described later, it is not limited to having a rectangular frame shape in a plan view.

[0065] In addition, in this embodiment, as shown in Figure 4A, it is preferable that the surface of the barrier layer 222 is covered with a barrier film 230. The barrier film 230 is aluminum oxide (AlO ｘ ), silicon oxide (SiO ｘ ) or silicon nitride (SiN ｘ ) can be formed from the like. In other words, in this embodiment, the barrier layer surrounding the oxide semiconductor layer 210 is preferably a laminate of a metal film and an oxide film or a nitride film. In this embodiment, by covering the barrier layer 222 with the barrier film 230, it is possible to suppress the diffusion of hydrogen, oxygen, etc. from films located outside the barrier layer 222 and the barrier film 230 into the oxide semiconductor layer 210. Furthermore, in this embodiment, by covering the barrier layer 222 with the barrier film 230, it is possible to prevent the diffusion of metal species from the barrier layer 222. Furthermore, the barrier film 230 can be formed by, for example, sputtering, CVD, etc.

[0066] Furthermore, in this embodiment, as shown in Figure 4A, the source region of the thin-film transistor Tr5 is electrically connected to the plug 220 via vias 206 and wiring 204. Furthermore, as shown in Figure 4A, the plug 220 is provided so as to penetrate the wiring layer 200. Also, as shown in Figure 4B, the plug 220 is provided adjacent to the oxide semiconductor layer 210 within the region surrounded by the barrier layer 222. As shown in Figure 4B, the plug 220 has, for example, a rectangular shape and can be formed from a metal film such as tungsten (W) or copper (Cu).

[0067] In this embodiment, the plug 220 is not limited to penetrating the entire insulating film 202 of the wiring layer 200 in cross-sectional view, as shown in Figure 4A, but may, for example, penetrate only a part of the insulating film 202. Furthermore, in this embodiment, the plug 220 is not limited to having a rectangular shape in plan view, but may, for example, be circular, elliptical, or polygonal.

[0068] Furthermore, as shown in Figure 4A, a cross-sectional view of the thin-film transistor Tr5, the plug 220 is located between the barrier layer 222 and the oxide semiconductor layer 210. In addition, the plug 220 is formed from a metallic material.

[0069] In addition, in this embodiment, as shown in Figure 4A, it is preferable that the surface of the plug 220 is also covered with the barrier film 230. In other words, in this embodiment, it is preferable that the plug 220 is a laminate of a metal film and an oxide film or a nitride film. In this embodiment, by covering the plug 220 with the barrier film 230, the diffusion of metal species from the plug 220 can be prevented. Furthermore, by doing so, it is possible to suppress the diffusion of oxygen, hydrogen gas, etc., from the insulating film 202, etc., which is a film located outside the barrier layer 250 and the barrier layer 222, into the interior of the plug 220 and to the oxide semiconductor layer 210 via the wiring layer 200 and wiring 204.

[0070] As described above, in this embodiment, the barrier layer 222 made of a metal material is provided so as to surround the oxide semiconductor layer 210. Therefore, in this embodiment, it is possible to suppress the diffusion of oxygen and hydrogen from the insulating film 202 and the barrier layer 250, which are films located outside the barrier layer 222, into the oxide semiconductor layer 210. In other words, according to this embodiment, it is possible to suppress the unintentional oxidation or reduction of the oxide semiconductor layer 210, which can cause changes in its properties. As a result, according to this embodiment, the properties of the oxide semiconductor layer 210 can be suitably adjusted and stabilized.

[0071] Furthermore, in this embodiment, by surrounding the oxide semiconductor layer 210 with the barrier layer 222, the influence of external electrical noise and other factors on the thin-film transistor Tr5 can be suppressed.

[0072] In this embodiment, the barrier layer 222 is not limited to being electrically connected to the drain region of the thin-film transistor Tr5, and the plug 220 is not limited to being electrically connected to the source region of the thin-film transistor Tr5. For example, in this embodiment, the barrier layer 222 may be electrically connected to the source region of the thin-film transistor Tr5, and the plug 220 may be electrically connected to the drain region of the thin-film transistor Tr5. Furthermore, in this embodiment, the thin-film transistor Tr5 is not limited to the form shown in Figures 4A and 4B, but can take on various forms.

[0073] <3.2 Modified Examples> Next, the detailed structure of the thin-film transistor Tr5 according to a modified example of this embodiment will be described with reference to Figure 4C. Figure 4C is a cross-sectional view showing an example of the detailed structure of the thin-film transistor Tr5 according to this modified example, and more specifically, it shows a cross-sectional view when the thin-film transistor Tr5 is cut in the stacking direction. In Figure 4C, the gate region of the thin-film transistor Tr5 is denoted with "G", and the source / drain regions are denoted with "S" and "D", respectively. In the following description, points common to the above-described embodiment will be omitted.

[0074] In this modified example, unlike the embodiment described above, the barrier layer 222 is not electrically connected to the drain region of the thin-film transistor Tr5, as shown in Figure 4C. Furthermore, in this modified example shown in Figure 4C, unlike the embodiment described above, there is no plug 220 that is electrically connected to the source region of the thin-film transistor Tr5. However, this modified example is not limited to the form without the plug 220 as shown in Figure 4C, and a plug 220 as described above may be provided.

[0075] In this modified example, the barrier layer 222, similar to that in this embodiment, sandwiches the oxide semiconductor layer 210, which forms the channel region of the thin-film transistor Tr5, from both sides in a cross-sectional view of the thin-film transistor Tr5, and surrounds it in a plan view of the thin-film transistor Tr5. Furthermore, since the barrier layer 222 is formed from a metallic material, it is possible to suppress the diffusion of oxygen and hydrogen from the insulating film 202 and barrier layer 250, which are films located outside the barrier layer 222, into the oxide semiconductor layer 210. In other words, in this modified example as well, by providing the barrier layer 222 as described above, it is possible to suppress the unintentional oxidation or reduction of the oxide semiconductor layer 210, which would cause a change in its properties.

[0076] <<4. Second Embodiment>> Next, with reference to Figures 5A to 5E, variations in the planar structure of the thin-film transistor Tr5 according to the second embodiment of this disclosure will be described. Figures 5A to 5E are plan views showing an example of the detailed structure of the thin-film transistor Tr5 according to this embodiment, and more specifically, they show a cross-sectional view of the thin-film transistor Tr5 cut along the line B-B' shown in Figure 4A. In these figures, the source and drain regions of the thin-film transistor Tr5 are labeled "S" and "D", respectively. In the following description, points common to the first embodiment described above will be omitted.

[0077] In this embodiment, as shown in the upper part of Figure 5A, the barrier layer 222 may be positioned close to the left and right edges of the oxide semiconductor layer 210 in the figure, and away from the top and bottom edges of the oxide semiconductor layer 210 in the figure. Alternatively, in this embodiment, as shown in the lower part of Figure 5A, the barrier layer 222 may be positioned away from the left and right edges of the oxide semiconductor layer 210 in the figure, and close to the top and bottom edges of the oxide semiconductor layer 210 in the figure. In this embodiment, the amount of oxygen and hydrogen diffusing from the film surrounding the oxide semiconductor layer 210 to the oxide semiconductor layer 210 can be adjusted by adjusting the positional relationship between the barrier layer 222 and the oxide semiconductor layer 210, or by adjusting the area of ​​the region surrounded by the barrier layer 222. Therefore, according to this embodiment, the characteristics of the thin-film transistor Tr5 can be controlled by the shape, size, and position of the barrier layer 222.

[0078] Furthermore, in this embodiment, the width W of the barrier layer 222 may be narrowed, as shown in the upper part of Figure 5B, or widened, as shown in the lower part of Figure 5B. In this embodiment, the ability of the barrier layer 222 to block oxygen and hydrogen can be adjusted by adjusting the width W of the barrier layer 222. Therefore, according to this embodiment, the characteristics of the thin-film transistor Tr5 can be controlled by the width W of the barrier layer 222.

[0079] Furthermore, in this embodiment, the film thickness t of the barrier film 230 may be increased, as shown in the upper part of Figure 5C, or decreased, as shown in the lower part of Figure 5C. In this embodiment, the ability of the barrier film 230 to block hydrogen, oxygen, etc., can be adjusted by adjusting the film thickness t of the barrier film 230. Therefore, according to this embodiment, the characteristics of the thin-film transistor Tr5 can be controlled by the film thickness t of the barrier film 230.

[0080] Furthermore, in this embodiment, as shown in Figure 5D, the barrier layer 222 may be covered with a laminated film of barrier film 230 and barrier film 232. Also, in this embodiment, the barrier layer 222 may be covered with a barrier film consisting of three or more laminated layers. For example, if it is desired to suppress the diffusion of hydrogen into the oxide semiconductor layer 210, it is preferable to form the barrier film 232 closest to the oxide semiconductor layer 210 from a material that has high hydrogen barrier properties and does not easily allow hydrogen to diffuse, as shown in the example in Figure 5D. Also, for example, in the example shown in Figure 5D, the barrier film 230 may be formed from silicon oxide and the barrier film 232 may be formed from aluminum oxide. In this embodiment, the ability to block hydrogen, oxygen, etc. can be adjusted by covering the barrier layer 222 with a barrier film consisting of two or more laminated layers. Therefore, according to this embodiment, the characteristics of the thin-film transistor Tr5 can be more controlled by covering the barrier layer 222 with a barrier film consisting of two or more laminated layers.

[0081] Furthermore, in this embodiment, as shown in the upper part of Figure 5E, the barrier layer 222 may be an elliptical frame. In other words, in this embodiment, the shape of the barrier layer 222 in plan view is not particularly limited as long as it surrounds the oxide semiconductor layer 210. According to this embodiment, the characteristics of the thin-film transistor Tr5 can be controlled by the shape, size, and position of the barrier layer 222.

[0082] Furthermore, in this embodiment, it is not limited to the entire surface (both sides) of the barrier layer 222 being covered by the barrier film 230, but as shown on the left side of Figure 5E, a part (one side) of the surface of the barrier layer 222 may be covered by the barrier film 230. In this embodiment, the ability to block hydrogen, oxygen, etc. can be adjusted by adjusting the area of ​​the surface of the barrier layer 222 covered by the barrier film 230, or by adjusting the range covered by the barrier film 230. Therefore, according to this embodiment, the characteristics of the thin-film transistor Tr5 can be controlled.

[0083] Furthermore, in this embodiment, as shown in the lower part of Figure 5E, a slit 224 may be provided in a part of the barrier layer 222. In other words, in this embodiment, a part of the barrier layer 222 surrounding the oxide semiconductor layer 210 may be cut. In this embodiment, by providing a slit 224, oxygen or hydrogen can easily diffuse into the region of the oxide semiconductor layer 210 near the slit 224, thereby allowing control of the characteristics of a specific region of the oxide semiconductor layer 210. Moreover, according to this embodiment, the degree of freedom in the layout of the thin-film transistor Tr5 can be increased, making it possible to reduce the area of ​​the substrate on which the thin-film transistor Tr5 is mounted.

[0084] Furthermore, in this embodiment, the plug 220 and the oxide semiconductor layer 210 are not limited to being aligned in a straight line, but may be aligned vertically in the figure, as shown in Figure 5F.

[0085] In this embodiment, the thin-film transistor Tr5 is not limited to the configurations shown in Figures 5A to 5F, but can take on various forms.

[0086] <<5. Third Embodiment>> Next, with reference to Figures 6A to 6C, variations in the cross-sectional structure of the thin-film transistor Tr5 according to the third embodiment of the present disclosure will be described. Figures 6A to 6C are cross-sectional views showing an example of the detailed structure of the thin-film transistor Tr5 according to the present embodiment, and more specifically, they show a cross-sectional view when the thin-film transistor Tr5 is cut in the stacking direction. In these figures, the gate region of the thin-film transistor Tr5 is denoted by "G", and the source / drain regions are denoted by "S" and "D", respectively. In the following description, points common to the first and second embodiments described above will be omitted.

[0087] In this embodiment, as shown in Figure 6A, an oxygen supply layer 240 may be provided superimposed on the oxide semiconductor layer 210 to supply oxygen to the oxide semiconductor layer 210. The oxygen supply layer 240 is a film that supplies oxygen to the oxide semiconductor layer 210 by desorbing oxygen, for example, by heating. Alternatively, the oxygen supply layer 240 may be an oxidizing film that has the effect of oxidizing by taking electrons from the surrounding film. More specifically, the oxygen supply layer 240 can be formed from an oxide film or oxynitride film containing silicon (Si), hafnium (Hf), or aluminum (Al), for example. More specifically, the oxygen supply layer 240 may be a silicon oxide (SiO₂) film deposited at 300°C or below to contain a large amount of oxygen. ｘ (x > 2)) or silicon oxide deposited by CVD using TEOS. In this embodiment, by providing an oxygen supply layer 240 superimposed on the oxide semiconductor layer 210, the properties of the oxide semiconductor layer 210 can be suitably adjusted by supplying oxygen to the oxide semiconductor layer 210 and causing oxidation. More specifically, in this embodiment, for example, by providing an oxygen supply layer 240 superimposed on the oxide semiconductor layer 210, the threshold value of the thin-film transistor Tr5 can be increased by supplying oxygen to the oxide semiconductor layer 210.

[0088] Furthermore, in this embodiment, as shown in Figure 6B, an oxygen supply layer 240 superimposed on the channel region of the oxide semiconductor layer 210 and a hydrogen supply layer 242 superimposed on the source region / drain region of the oxide semiconductor layer 210 may be provided. The hydrogen supply layer 242 is, for example, a reducing film that provides electrons to the oxide semiconductor layer 210 and has a reducing effect, and specifically reduces the oxide semiconductor layer 210 by releasing hydrogen to the oxide semiconductor layer 210. In detail, the hydrogen supply layer 242 is, for example, silicon nitride (SiN ｘ) etc. In this embodiment, by providing an oxygen supply layer 240 superimposed on the channel region of the oxide semiconductor layer 210, the characteristics of the channel region can be suitably adjusted by supplying oxygen to the channel region and oxidizing it. Furthermore, in this embodiment, by providing a hydrogen supply layer 242 superimposed on the source region / drain region of the oxide semiconductor layer 210, the characteristics of the source region / drain region can be suitably controlled by supplying hydrogen to the source region / drain region. More specifically, in this embodiment, for example, by supplying hydrogen to the source region and drain region of the oxide semiconductor layer 210 with the hydrogen supply layer 242, the resistance in the source / drain region of the thin-film transistor Tr5 can be reduced. In other words, according to this embodiment, the characteristics of the channel region, source region and drain region can be suitably controlled.

[0089] Furthermore, in this embodiment, as shown in Figure 6C, the oxygen supply layer 240 and the hydrogen supply layer 242 may be stacked so as to be superimposed on the oxide semiconductor layer 210.

[0090] Furthermore, in this embodiment, for example, nitric oxide (NO), nitrogen dioxide (NO) is used as the working layer that acts on the oxide semiconductor layer 210. ２ A layer that releases ) or moisture may be provided superimposed on the oxide semiconductor layer 210.

[0091] In this embodiment, the thin-film transistor Tr5 is not limited to the form shown in Figures 6A to 6C, but can take on various forms.

[0092] <<6. Fourth Embodiment>> Next, with reference to Figures 7A and 7B, variations in the form of the barrier film 230 in the thin-film transistor Tr5 according to the fourth embodiment of the present disclosure will be described. Figures 7A and 7B are cross-sectional views showing an example of the detailed structure of the thin-film transistor Tr5 according to this embodiment, and more specifically, they show a cross-sectional view when the thin-film transistor Tr5 is cut in the stacking direction. In these figures, the gate region of the thin-film transistor Tr5 is denoted by "G", and the source / drain regions are denoted by "S" and "D", respectively. In the following description, points common to the first to third embodiments described above will be omitted.

[0093] In this embodiment, the barrier film 230 may cover the upper part of the thin-film transistor Tr5. More specifically, as shown in Figure 7A, the barrier film 230 may cover the gate electrode 212 and the wiring 204 electrically connected to the barrier layer 222 and plug 220. In this embodiment, by covering the oxide semiconductor layer 210 with the barrier film 230 from above, it is possible to suppress the unintentional oxidation and reduction of the oxide semiconductor layer 210, which would cause a change in its properties. Furthermore, in this embodiment, by covering the gate electrode 212 and the wiring 204 with the barrier film 230, it is possible to prevent the diffusion of metal species from the gate electrode 212 and the wiring 204.

[0094] Furthermore, in this embodiment, as shown in Figure 7B, the barrier film 230 may cover the gate electrode 212 and the oxide semiconductor layer 210. In this embodiment, it is possible to suppress the unintentional oxidation and reduction of the oxide semiconductor layer 210, which can alter its properties. In particular, if there is a film above the oxide semiconductor layer 210 that may diffuse hydrogen or the like, directly covering the oxide semiconductor layer 210 with the barrier film 230 can suppress the unintentional reduction of the oxide semiconductor layer 210, which can alter its properties.

[0095] In this embodiment, the thin-film transistor Tr5 is not limited to the form shown in Figures 7A and 7B, but can take on various forms.

[0096] <<7. Fifth Embodiment>> Next, with reference to Figures 8A to 8C, a variation of the display device 10 (an example of a semiconductor device) including a plurality of thin-film transistors Tr5 (first semiconductor element) and thin-film transistors Tr6 (second semiconductor element) according to the fifth embodiment of the present disclosure will be described. Figures 8A to 8C are cross-sectional views showing an example of the detailed structure of the main part of the display device 10 (pixel 20) according to this embodiment, and in detail, they show cross-sectional views when the thin-film transistors Tr5 and Tr6 are cut in the stacking direction. In these figures, the gate region of the thin-film transistor Tr5 is denoted with "G", and the source / drain regions are denoted with "S" and "D", respectively. In the following description, points common to the first to fourth embodiments described above will be omitted.

[0097] In this embodiment, as shown in Figure 8A, a thin-film transistor Tr6 is provided adjacent to the thin-film transistor Tr5 in a plan view of the thin-film transistor Tr5. In this embodiment, the thin-film transistor Tr5 can be the thin-film transistor Tr5 of the first to fourth embodiments described above.

[0098] In this embodiment, the thin-film transistor Tr6, like the thin-film transistor Tr5, has an oxide semiconductor layer (second oxide semiconductor layer) 210 provided within the wiring layer 200, and a gate electrode 212 provided on the oxide semiconductor layer 210 via a gate insulating film 214. In this embodiment, the ends of the oxide semiconductor layer 210, which form the source / drain region of the thin-film transistor Tr6, are electrically connected to the wiring 204 via vias 206. Furthermore, in this embodiment, the drain region of the thin-film transistor Tr6 is electrically connected to a barrier layer (third barrier layer) 222 via vias 206 and the wiring 204. In addition, the barrier layer 222 of the thin-film transistor Tr6 is provided so as to penetrate the insulating film 202 of the wiring layer 200. Furthermore, as shown in Figure 4B, the barrier layer 222 of the thin-film transistor Tr6 is provided so as to surround the oxide semiconductor layer 210 of the thin-film transistor Tr6.

[0099] Thus, in the thin-film transistor Tr6, the barrier layer 222 is provided so as to sandwich the oxide semiconductor layer 210 of the thin-film transistor Tr6 from both sides in a cross-sectional view of the thin-film transistor Tr6, and surround it in a plan view of the thin-film transistor Tr6. Furthermore, since the barrier layer 222 is formed from a metallic material, it is possible to suppress the diffusion of oxygen and hydrogen from the insulating film 202 and barrier layer 250, which are films located outside the barrier layer 222, into the oxide semiconductor layer 210 of the thin-film transistor Tr6. In addition, in the thin-film transistor Tr6, it is preferable that the surface of the barrier layer 222 of the thin-film transistor Tr6 is also covered with a barrier film 230.

[0100] Furthermore, in this embodiment as well, the source region of the thin-film transistor Tr6 is electrically connected to the plug 220 via vias 206 and wiring 204. The plug 220 of the thin-film transistor Tr6 is provided so as to penetrate the insulating film 202 of the wiring layer 200. The plug 220 of the thin-film transistor Tr6 is also provided adjacent to the oxide semiconductor layer 210 within the region surrounded by the barrier layer 222. In addition, it is preferable that the surface of the plug 220 of the thin-film transistor Tr6 is also covered with the barrier film 230.

[0101] Furthermore, in this embodiment, as shown in Figure 8B, an oxygen supply layer 240 may be provided in the thin-film transistors Tr5 and Tr6. Alternatively, in this embodiment, a hydrogen supply layer 242 may be provided instead of the oxygen supply layer 240.

[0102] Furthermore, in this embodiment, as shown in Figure 8B, the spacing a of the barrier layer 222 of the thin-film transistor Tr5 ５The spacing a6 of the barrier layer 222 of the thin-film transistor Tr6 may be different. In this embodiment, the area of ​​the region surrounded by the barrier layer 222 can be adjusted by changing the spacing a of the barrier layer 222 in each thin-film transistor Tr5 and Tr6. Therefore, according to this embodiment, the amount of oxygen and hydrogen diffusing from the film located around the oxide semiconductor layer 210 to the oxide semiconductor layer 210 can be adjusted for each thin-film transistor Tr5 and Tr6. As a result, according to this embodiment, the characteristics of thin-film transistors Tr5 and Tr6 can be suitably differentiated while using the same manufacturing process.

[0103] Furthermore, in this embodiment, as shown in Figure 8C, the thin-film transistor Tr5 may be provided with an oxygen supply layer 240, and the thin-film transistor Tr6 may be provided with a hydrogen supply layer 242. Alternatively, in this embodiment, the thin-film transistor Tr5 may be provided with a hydrogen supply layer 242, and the thin-film transistor Tr6 may be provided with an oxygen supply layer 240. In this way, in this embodiment, by changing the type of working layer superimposed on the oxide semiconductor layer 210 of each thin-film transistor Tr5, Tr6, the characteristics of the thin-film transistors Tr5, Tr6 can be suitably differentiated.

[0104] In this embodiment, the main components of the display device 10 are not limited to the configurations shown in Figures 8A to 8C, but can take on various configurations.

[0105] <<8. Sixth Embodiment>> Next, with reference to Figures 9A and 9B, variations in the structure of the main part of the display device 10, including a plurality of thin-film transistors Tr5 and Tr6, according to the sixth embodiment of the present disclosure will be described. Figure 9A is a cross-sectional view showing an example of the detailed structure of the main part of the display device 10 according to this embodiment, and in detail, it shows a cross-sectional view when the thin-film transistors Tr5 and Tr6 are cut in the stacking direction. Figure 9B is a plan view showing an example of the detailed structure of the main part of the display device 10 according to this embodiment, and in detail, it shows a cross-sectional view when the thin-film transistors Tr5 and Tr6 are cut along the line B-B' shown in Figure 9A. In these figures, the gate region of the thin-film transistor Tr5 is denoted with "G", and the source / drain regions are denoted with "S" and "D", respectively. In the following description, points common to the first to fifth embodiments described above will be omitted.

[0106] In this embodiment, as shown in Figure 9A, a thin-film transistor Tr6 is provided adjacent to thin-film transistor Tr5 in a plan view of thin-film transistor Tr5. Furthermore, in this embodiment, as shown in Figures 9A and 9B, the barrier layer 222 of thin-film transistor Tr5 and the barrier layer 222 of thin-film transistor Tr6 are connected. In this embodiment, by having the two thin-film transistors Tr5 and Tr6 share a portion of the barrier layer 222, the layout area of ​​thin-film transistors Tr5 and Tr6 can be reduced.

[0107] In this embodiment, the main components of the display device 10 are not limited to the configurations shown in Figures 9A and 9B, but can take on various configurations.

[0108] <<9. Seventh Embodiment>> Next, with reference to Figure 10, a variation in the structure of the main part of the display device 10, which includes a plurality of thin-film transistors Tr5 and Tr6, according to the seventh embodiment of the present disclosure will be described. Figure 10 is a cross-sectional view showing an example of the detailed structure of the main part of the display device 10 according to this embodiment, and more specifically, it shows a cross-sectional view when the thin-film transistors Tr5 and Tr6 are cut in the stacking direction. In Figure 10, the gate region of the thin-film transistor Tr5 is denoted by "G", and the source / drain regions are denoted by "S" and "D", respectively. In the following description, points common to the first to sixth embodiments described above will be omitted.

[0109] In this embodiment, as shown in Figure 10, in a cross-sectional view of thin-film transistor Tr5, thin-film transistor Tr6 is provided below thin-film transistor Tr5. In other words, in this embodiment, thin-film transistors Tr5 and Tr6 are stacked. Furthermore, in this embodiment, as shown in Figure 10, the plug 220 of thin-film transistor Tr5 and the plug 220 of thin-film transistor Tr6 may be connected. Note that in this embodiment, thin-film transistors Tr5 and Tr6 can be thin-film transistor Tr5 of the first to fourth embodiments described above.

[0110] Furthermore, in this embodiment as well, as shown in Figure 10, the spacing a of the barrier layers 222 of the thin-film transistor Tr5 and the spacing a of the barrier layers 222 of the thin-film transistor Tr6 may be different. Moreover, in this embodiment as well, as shown in Figure 10, it is preferable to cover the upper part of the thin-film transistor Tr6 located below with the barrier film 230.

[0111] In this embodiment, the main components of the display device 10 are not limited to the form shown in Figure 10, but can take on various forms.

[0112] <<10. Eighth Embodiment>> Next, the detailed structure of the thin-film transistor Tr7 according to the eighth embodiment of the present disclosure will be described with reference to Figure 11. Figure 11 is a cross-sectional view showing an example of the detailed structure of the thin-film transistor Tr7 according to this embodiment, and more specifically, it shows a cross-sectional view when the thin-film transistor Tr7 is cut in the stacking direction. In Figure 11, the gate region of the thin-film transistor Tr5 is denoted with "G", and the source / drain regions are denoted with "S" and "D", respectively. In the following description, the explanation of points common to the first to seventh embodiments described above will be omitted.

[0113] The thin-film transistor Tr5 described so far has one oxide semiconductor layer 210 and a gate electrode 212 provided on the oxide semiconductor layer 210 via a gate insulating film 214. On the other hand, in this embodiment, as shown in Figure 11, the thin-film transistor Tr7 has two oxide semiconductor layers 210, a gate electrode 212 sandwiched from above and below by the two oxide semiconductor layers 210, and two gate insulating films 214 sandwiched between the oxide semiconductor layer 210 and the gate electrode 212. In this embodiment, the source region of the thin-film transistor Tr6 is one of the oxide semiconductor layers 210 (the upper oxide semiconductor layer 210 in the figure), and is electrically connected to the plug 220 via via 206 and wiring 204. In this embodiment, the drain region of the thin-film transistor Tr6 is the other oxide semiconductor layer 210 (the lower oxide semiconductor layer 210 in the figure), and is electrically connected to the barrier layer 222 via via 206 and wiring 204. In this way, the layout area of ​​the thin-film transistor Tr7 can be reduced in this embodiment.

[0114] In this embodiment, although the structure of the thin-film transistor Tr7 differs from that of the thin-film transistor Tr5 described previously, the barrier layer 222 made of a metal material is provided so as to surround the oxide semiconductor layer 210. Therefore, in this embodiment, it is possible to suppress the diffusion of oxygen and hydrogen from the insulating film 202 and the barrier layer 250, which are films located outside the barrier layer 222, into the oxide semiconductor layer 210. In other words, in this embodiment as well, it is possible to suppress the unintentional oxidation or reduction of the oxide semiconductor layer 210, which can lead to changes in its properties.

[0115] In this embodiment, the thin-film transistor Tr7 is not limited to the form shown in Figure 11, but can take on various forms.

[0116] <<11. Ninth Embodiment>> <11.1 Manufacturing Method> Next, as the ninth embodiment of the present disclosure, an example of a method for manufacturing a thin-film transistor Tr5 will be described with reference to Figures 12A to 12D. Figures 12A to 12D are cross-sectional views illustrating the method for manufacturing a thin-film transistor Tr5 according to this embodiment.

[0117] First, as shown in the upper part of Figure 12A, an insulating film 202 and wiring 204 are deposited on top of a semiconductor substrate (not shown). Next, as shown in the second part from the top of Figure 12A, a barrier layer 250 and a barrier film 230 are deposited. Then, as shown in the third part from the top of Figure 12A, the insulating film 202 is laminated on the barrier film 230. Furthermore, as shown in the fourth part from the top of Figure 12A, an oxide semiconductor layer 210 is formed on the insulating film 202, and a gate insulating film 214 is deposited on top of it. Finally, as shown in the lower part of Figure 12A, a gate electrode 212 is deposited on the gate insulating film 214.

[0118] Next, as shown in the upper part of Figure 12B, a thin-film transistor Tr5 is created by processing the gate electrode 212 and the gate insulating film 214. Furthermore, as shown in the second part from the top of Figure 12B, an insulating film 202 is further layered to embed the thin-film transistor Tr5. Next, as shown in the third part from the top of Figure 12B, a trench 400 is formed in the insulating film 202. Furthermore, as shown in the lower part of Figure 12B, a via 206 is formed to embed the trench 400.

[0119] Next, as shown in the upper part of Figure 12C, trenches 402 are formed in the insulating film 202. Here, the trenches 402 are provided so as to penetrate not only the insulating film 202 but also the barrier film 230. Furthermore, as shown in the second part from the top of Figure 12C, the barrier film 230 is deposited so as to cover the sides of the trenches 402. Next, as shown in the third part from the top of Figure 12C, the barrier film 230 laminated on the upper surface of the insulating film 202 is removed using dry etching or the like. Furthermore, as shown in the lower part of Figure 12C, metal films that will become the barrier layer 222 and plugs 220 are deposited so as to fill the trenches 402.

[0120] Next, as shown in the upper part of Figure 12D, the metal film protruding from the trench 402 is removed using a method such as CMP (Chemical Mechanical Polishing). Furthermore, as shown in the lower part of Figure 12D, wiring 204 is formed on the insulating film 202. In this way, the thin-film transistor Tr5 according to this embodiment can be fabricated.

[0121] In this embodiment, the method for manufacturing the thin-film transistor Tr5 is not limited to the method shown in Figures 12A to 12D.

[0122] <11.2 Modifications> (Modification 1) Next, as Modification 1, another example of a method for manufacturing a thin-film transistor Tr5 will be described with reference to Figures 13A and 13B. Figures 13A and 13B are cross-sectional views illustrating the method for manufacturing a thin-film transistor Tr5 according to Modification 1 of this embodiment.

[0123] In this modified example 1, first, the manufacturing process of the thin-film transistor Tr5 according to this embodiment is carried out as shown in Figures 12A and 12B. Next, as shown in the upper part of Figure 13A, a trench 402 is formed in the insulating film 202. Here, the trench 402 is provided so as to penetrate not only the insulating film 202 but also the barrier film 230 and the barrier layer 250. Furthermore, as shown in the second part from the top of Figure 13A, the barrier film 230 is formed so as to cover the side surface of the trench 402. Next, as shown in the third part from the top of Figure 13A, the barrier film 230 laminated on the upper surface of the insulating film 202 is removed using dry etching or the like. Furthermore, as shown in the lower part of Figure 13A, a metal film that will become the barrier layer 222 and plug 220 is formed so as to fill the trench 402.

[0124] Next, as shown in the upper part of Figure 13B, the metal film protruding from the trench 402 is removed using a CMP method or the like. Furthermore, as shown in the lower part of Figure 13B, wiring 204 is formed on the insulating film 202. In this way, a thin-film transistor Tr5 can be fabricated.

[0125] (Modification 2) Next, as Modification 2, another example of a method for manufacturing a thin-film transistor Tr5 will be described with reference to Figure 14. Figure 14 is a cross-sectional view illustrating the method for manufacturing a thin-film transistor Tr5 according to Modification 2 of this embodiment.

[0126] In this modified example 2, first, the steps shown in Figures 12A and 12B of the manufacturing method for the thin-film transistor Tr5 according to this embodiment are performed. Next, as shown in the upper part of Figure 14, a trench 402 is formed in the insulating film 202. Here, the trench 402 is provided so as to penetrate only the insulating film 202. Furthermore, as shown in the second part from the top of Figure 14, etching is performed to remove the barrier film 230 located at the bottom of the trench 402, and the residue is deposited on the side surface of the trench 402, forming a barrier film 230 that covers the side surface of the trench 402. In other words, in this modified example 2, the step of forming the barrier film 230 can be omitted, thereby suppressing increases in manufacturing time and manufacturing cost for the thin-film transistor Tr5.

[0127] Furthermore, as shown in the lower part of Figure 14, a metal film that will form the barrier layer 222 and the plug 220 is formed so as to fill the trench 402. After that, the thin-film transistor Tr5 can be manufactured by performing the steps shown in Figure 12D of the manufacturing method of the thin-film transistor Tr5 according to this embodiment.

[0128] (Modification 3) Next, as Modification 3, another example of a method for manufacturing a thin-film transistor Tr5 will be described with reference to Figure 15. Figure 15 is a cross-sectional view illustrating the method for manufacturing a thin-film transistor Tr5 according to Modification 3 of this embodiment.

[0129] In this modified example 3, first, the steps shown in Figures 12A and 12B of the manufacturing method for the thin-film transistor Tr5 according to this embodiment are performed. Here, the trench 402 is provided so as to penetrate not only the insulating film 202 but also the barrier film 230 and the barrier layer 250. Furthermore, in this modified example 3, the steps shown in the second row from the top of Figure 12C and the third row from the top of Figure 12C of the manufacturing method for the thin-film transistor Tr5 according to this embodiment are performed.

[0130] Next, in this modified example 3, as shown in the upper part of Figure 15, a trench 404 wider than the trench 402 is formed above the trench 402. Then, as shown in the second row from the top of Figure 15, metal films that will form the barrier layer 222, plug 220, and wiring 204 are deposited so as to fill the trenches 402 and 404. Furthermore, as shown in the lower part of Figure 15, the metal film protruding from the trench 404 is removed using a CMP method or the like. In this way, a thin-film transistor Tr5 can be manufactured. Thus, in this modified example 3, by manufacturing the barrier layer 222, plug 220, and wiring 204 simultaneously, the increase in manufacturing time and manufacturing cost of the thin-film transistor Tr5 can be suppressed.

[0131] Furthermore, the thin-film transistor Tr5 according to the embodiment of this disclosure can be manufactured using methods, apparatus, and conditions commonly used in the manufacture of semiconductor devices.

[0132] Examples of the methods mentioned above include PVD (Physical Vapor Deposition), CVD, and ALD (Atomic Layer Deposition). PVD methods include vacuum deposition, EB (electron beam) deposition, various sputtering methods (magnetron sputtering, RF (Radio Frequency)-DC (Direct Current) coupled bias sputtering, ECR (Electron Cyclotron Resonance) sputtering, opposing target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE (Molecular Beam Epitaxy)), and laser transfer. Furthermore, CVD methods include plasma CVD, thermal CVD, metal-organic (MO) CVD, and photo-CVD. Other methods include electrolytic plating, electroless plating, spin coating, immersion, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, as well as stamping, spraying, air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calender coater. Patterning methods include chemical etching such as shadow masks, laser transfer, and photolithography, as well as physical etching using ultraviolet light or lasers. In addition, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0133] <<12. Summary>> As described above, in each embodiment of the present disclosure, the barrier layer 222 made of a metal material is provided so as to surround the oxide semiconductor layer 210. Therefore, in each embodiment of the present disclosure, the diffusion of oxygen and hydrogen into the oxide semiconductor layer 210 can be suppressed. In other words, according to each embodiment of the present disclosure, it is possible to suppress the oxide semiconductor layer 210 from being unintentionally oxidized or reduced and having its properties changed. As a result, according to each embodiment of the present disclosure, the properties of the oxide semiconductor layer 210 can be suitably adjusted and stabilized.

[0134] Furthermore, in each embodiment of this disclosure, the thin-film transistor Tr5 can be protected from the effects of electrical noise by surrounding the oxide semiconductor layer 210 with the barrier layer 222.

[0135] Furthermore, the display device 10 according to the embodiment of this disclosure can be applied to, for example, display devices for VR (Virtual Reality), MR (Mixed Reality), or AR (Augmented Reality), display devices for smartphones, television equipment, electronic viewfinders (EVF), or small projectors. The display device 10 can also be applied to various lighting devices.

[0136] Furthermore, the technology of this disclosure may be applied not only to the display device 10, but also to various semiconductor devices such as memory (storage device).

[0137] Furthermore, each embodiment of this disclosure is not limited to the form shown in the figures, but can be modified in various ways and can also be combined with one another.

[0138] <<13. Examples of Application>> For example, the technology relating to this disclosure may be applied to the display units of various electronic devices. Therefore, examples of electronic devices to which this technology can be applied will be described below.

[0139] (Specific Example 1) Figure 16A is a front view showing an example of the external appearance of the digital still camera 500, and Figure 16B is a rear view showing an example of the external appearance of the digital still camera 500. This digital still camera 500 is a single-lens reflex type with interchangeable lenses, and has an interchangeable shooting lens unit (interchangeable lens) 512 located approximately in the center of the front of the camera body 511, and a grip portion 513 for the photographer to hold on the left side of the front.

[0140] A monitor 514 is provided on the back of the camera body 511, slightly to the left of the center. An electronic viewfinder (eyepiece) 515 is provided above the monitor 514. The photographer can determine the composition by looking through the electronic viewfinder 515 and visually confirming the light image of the subject guided by the shooting lens unit 512. The display device 10 according to the embodiment of this disclosure can be used as the monitor 514 and the electronic viewfinder 515.

[0141] (Specific Example 2) Figure 17 is an external view of a head-mounted display 600. The head-mounted display 600 has, for example, an eyeglass-shaped display unit 611 and ear hooks 612 on both sides for attachment to the user's head. In this head-mounted display 600, the display device 10 according to the embodiment of this disclosure can be used as the display unit 611.

[0142] (Specific Example 3) Figure 18 is an external view of the see-through head-mounted display 634. The see-through head-mounted display 634 consists of a main body 632, an arm 633, and a lens barrel 631.

[0143] The main body 632 is connected to the arm 633 and the eyeglasses 630. Specifically, the long end of the main body 632 is connected to the arm 633, and one side of the main body 632 is connected to the eyeglasses 630 via a connecting member. The main body 632 may also be directly attached to the head of a person.

[0144] The main body 632 houses a control board for controlling the operation of the see-through head-mounted display 634 and a display unit. The arm 633 connects the main body 632 to the lens barrel 631 and supports the lens barrel 631. Specifically, the arm 633 is connected to the end of the main body 632 and the end of the lens barrel 631, respectively, and fixes the lens barrel 631 in place. The arm 633 also houses signal lines for communicating image-related data provided from the main body 632 to the lens barrel 631.

[0145] The lens barrel 631 projects image light, provided from the main body 632 via the arm 633, through the eyepiece lens towards the eyes of the user wearing the see-through head-mounted display 634. In this see-through head-mounted display 634, the display device 10 according to the embodiment of this disclosure can be used in the display section of the main body 632.

[0146] (Specific Example 4) Figure 19 shows an example of the appearance of a television device 710. This television device 710 has, for example, a video display screen section 711 including a front panel 712 and a filter glass 713, and this video display screen section 711 is configured with a display device 10 according to the embodiment of this disclosure.

[0147] (Specific Example 5) Figure 20 shows an example of the appearance of a smartphone 800. The smartphone 800 has a display unit 802 that displays various information, and an operation unit consisting of buttons, etc. that accept user input. The display unit 802 may be the display device 10 according to this embodiment.

[0148] (Specific Example 6) Figures 21A and 21B show the internal configuration of an automobile having a display device 10 according to the present disclosure as a display device. More specifically, Figure 21A shows the interior of the automobile from the rear to the front, and Figure 21B shows the interior of the automobile from the diagonally rear to the diagonally front.

[0149] The automobile shown in Figures 21A and 21B includes a center display 911, a console display 912, a head-up display 913, a digital rear mirror 914, a steering wheel display 915, and a rear entertainment display 916. Some or all of these displays can be fitted with the display device 10 according to the embodiment of this disclosure.

[0150] The center display 911 is positioned on the center console 907, facing the driver's seat 901 and the passenger seat 902. Figures 21A and 21B show an example of a horizontally elongated center display 911 extending from the driver's seat 901 to the passenger seat 902, but the screen size and placement of the center display 911 are arbitrary. The center display 911 can display information detected by various sensors (not shown). As a specific example, the center display 911 can display images captured by an image sensor, distance images to obstacles in front of or to the side of the vehicle measured by a ToF (Time of Flight) sensor, and the body temperature of passengers detected by an infrared sensor. The center display 911 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information.

[0151] Safety-related information includes information such as drowsiness detection, distraction detection, detection of mischief by a passenger, seatbelt fastening status, and detection of an unattended occupant. This information is detected, for example, by a sensor (not shown) placed on top of the back of the center display 1911. Operation-related information is detected by sensing occupant gestures using sensors. The detected gestures may include the operation of various equipment in the vehicle. For example, the sensor detects the operation of air conditioning equipment, navigation systems, AV (Audio / Visual) systems, lighting systems, etc. Life logs include the life logs of all occupants. For example, life logs include records of each occupant's actions while riding in the vehicle. By acquiring and saving life logs, it is possible to confirm the state of the occupants at the time of an accident. Health-related information is detected by sensing the occupant's body temperature using a temperature sensor and inferring the occupant's health status based on the detected body temperature. Alternatively, the occupant's face may be captured using an image sensor, and the occupant's health status may be inferred from the facial expression captured. Furthermore, the system may engage in automated voice conversations with the occupants and infer their health status based on their responses. Authentication / identification-related information includes keyless entry functions that use sensors for facial recognition and functions that automatically adjust seat height and position based on facial recognition. Entertainment-related information includes functions that use sensors to detect information on how the occupants operate the AV equipment and functions that use sensors to recognize the occupants' faces and provide content suitable for the occupants through the AV equipment.

[0152] The console display 912 can be used, for example, to display life log information. The console display 912 is located near the shift lever 908 on the center console 907 between the driver's seat 901 and the passenger seat 902. The console display 912 can also display information detected by various sensors (not shown). In addition, the console display 912 may display an image of the area around the vehicle captured by an image sensor, or it may display an image showing the distance to obstacles around the vehicle.

[0153] The head-up display 913 is virtually displayed behind the windshield 904 in front of the driver's seat 901. The head-up display 913 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 913 is often virtually positioned in front of the driver's seat 901, it is suitable for displaying information directly related to the operation of the vehicle, such as the vehicle's speed and fuel (battery) level.

[0154] The digital rearview mirror 914 can not only display the area behind the vehicle but also show the condition of the passengers in the rear seat. By placing a sensor (not shown) on top of the back of the digital rearview mirror 914, it can be used, for example, to display life log information.

[0155] The steering wheel display 915 is positioned near the center of the steering wheel 906 of the automobile. The steering wheel display 915 can be used to display at least one of the following: safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 915 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, or information related to the operation of AV equipment, air conditioning equipment, etc.

[0156] The rear entertainment display 916 is mounted on the back of the driver's seat 901 and the passenger seat 902, and is intended for viewing by rear-seat passengers. The rear entertainment display 916 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the rear entertainment display 916 is in front of the rear-seat passengers, it displays information relevant to the rear-seat passengers. For example, it may display information related to the operation of AV equipment or air conditioning equipment, or it may display the results of measurements of the rear-seat passengers' body temperature, etc., taken by a temperature sensor (not shown).

[0157] <<14. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person with ordinary skill in the art of the present disclosure may conceive of various modifications or alterations within the scope of the technical ideas described in the claims, and these will naturally also fall within the technical scope of the present disclosure.

[0158] Furthermore, the effects described herein are merely descriptive or illustrative and not limiting. In other words, the technology relating to this disclosure may produce other effects that are obvious to those skilled in the art from the description herein, in addition to or instead of the effects described herein.

[0159] Furthermore, this technology can also take the following configurations: (1) A semiconductor element comprising an oxide semiconductor layer provided in a wiring layer, wherein, in a plan view of the semiconductor element, the oxide semiconductor layer is surrounded by a first barrier layer, and the first barrier layer includes a metal film. (2) The semiconductor element according to (1) above, wherein, in a cross-sectional view of the semiconductor element, the first barrier layer penetrates the wiring layer. (3) The semiconductor element according to (1) or (2) above, wherein the first barrier layer consists of a laminate further including an oxide film or a nitride film. (4) The semiconductor element according to any one of (1) to (3) above, wherein the first barrier layer is electrically connected to one of the drain region and the source region of the oxide semiconductor layer. (5) The semiconductor element according to (4) above, wherein, in a plan view of the semiconductor element, the other of the drain region and the source region of the oxide semiconductor layer is electrically connected to a plug provided in the region surrounded by the first barrier layer, and the plug includes the metal film. (6) The semiconductor element according to (5) above, wherein in a cross-sectional view of the semiconductor element, the plug penetrates the wiring layer. (7) The semiconductor element according to (5) or (6) above, wherein the plug is made of a laminate further comprising an oxide film or a nitride film. (8) The semiconductor element according to any one of (5) to (7) above, wherein the metal film comprises tungsten or copper. (9) The semiconductor element according to any one of (1) to (8) above, wherein the surface of the wiring layer is covered with a second barrier layer. (10) The semiconductor element according to (9) above, wherein the second barrier layer is made of silicon nitride or silicon carbonitride. (11) The semiconductor element according to any one of (1) to (10) above, wherein in a plan view of the semiconductor element, the first barrier layer has a rectangular frame shape. (12) The semiconductor element according to (11) above, wherein in a plan view of the semiconductor element, the first barrier layer has a slit. (13) The semiconductor element according to any one of (1) to (12) above, further comprising an oxygen supply layer superimposed on the oxide semiconductor layer and supplying oxygen to the oxide semiconductor layer.(14) A semiconductor element according to any one of (1) to (13), further comprising a hydrogen supply layer superimposed on the oxide semiconductor layer and supplying hydrogen to the oxide semiconductor layer. (15) A semiconductor element according to (1), wherein the semiconductor element comprises two oxide semiconductor layers and a gate electrode sandwiched from above and below by the two oxide semiconductor layers. (16) A semiconductor element according to any one of (1) to (15), wherein the oxide semiconductor layer contains at least one element selected from the group consisting of aluminum, indium, gallium, tin, silicon, hafnium, and zinc. (17) A semiconductor element according to any one of (1) to (16), wherein the wiring layer is laminated on a semiconductor substrate, and the semiconductor element is electrically connected to a light-emitting element provided above the wiring layer. (18) A semiconductor device comprising a wiring layer and a first semiconductor element, wherein the first semiconductor element comprises a first oxide semiconductor layer provided in the wiring layer, and in a plan view of the first semiconductor element, the first oxide semiconductor layer is surrounded by a first barrier layer, and the first barrier layer comprises a metal film. (19) The semiconductor device according to (18) above, further comprising a second semiconductor element provided next to the first semiconductor element in a plan view of the first semiconductor element, wherein the second semiconductor element comprises a second oxide semiconductor layer provided in the wiring layer, and in a plan view of the second semiconductor element, the second oxide semiconductor layer is surrounded by a third barrier layer, and the third barrier layer comprises a metal film. (20) The semiconductor device according to (18) above, further comprising a second semiconductor device provided so as to be superimposed on the first semiconductor device in a cross-sectional view of the first semiconductor device, wherein the second semiconductor device comprises a second oxide semiconductor layer provided in the wiring layer, and in a plan view of the second semiconductor device, the second oxide semiconductor layer is surrounded by a third barrier layer, and the third barrier layer includes a metal film.

[0160] 10 Display device 20, 20a Pixel 30 Pixel array 31 Scan line 32 Drive line 33 Second drive line 34 Signal line 40, 50, 60 Scanning unit 70 Signal output unit 80 Display panel 100 Semiconductor substrate 102, 212 Gate electrode 104 Diffusion region 106 Element isolation unit 200 Wiring layer 202 Insulating film 204 Wiring 206 Via 210 Oxide semiconductor layer 214 Gate insulating film 220 Plug 222 Barrier layer 224 Slit 230, 232 Barrier film 240 Oxygen supply layer 242 Hydrogen supply layer 250 Barrier layer 300 Light-emitting unit 310 Anode electrode 312 Cathode electrode 314 Light-emitting layer 400, 402, 404 Trench

Claims

1. A semiconductor element comprising an oxide semiconductor layer provided within a wiring layer, wherein, in a plan view of the semiconductor element, the oxide semiconductor layer is surrounded by a first barrier layer, and the first barrier layer includes a metal film.

2. The semiconductor element according to claim 1, wherein, in a cross-sectional view of the semiconductor element, the first barrier layer penetrates the wiring layer.

3. The semiconductor device according to claim 1, wherein the first barrier layer comprises a laminate further including an oxide film or a nitride film.

4. The semiconductor device according to claim 1, wherein the first barrier layer is electrically connected to one of the drain region and the source region of the oxide semiconductor layer.

5. The other of the drain region and source region of the oxide semiconductor layer is electrically connected to a plug provided in a region surrounded by the first barrier layer in a plan view of the semiconductor element, the plug includes the metal film, according to claim 4.

6. The semiconductor element according to claim 5, wherein, in a cross-sectional view of the semiconductor element, the plug penetrates the wiring layer.

7. The semiconductor element according to claim 5, wherein the plug comprises a laminate further comprising an oxide film or a nitride film.

8. The semiconductor element according to claim 5, wherein the metal film comprises tungsten or copper.

9. The semiconductor element according to claim 1, wherein the surface of the wiring layer is covered with a second barrier layer.

10. The semiconductor device according to claim 9, wherein the second barrier layer is made of silicon nitride or silicon carbonitride.

11. The semiconductor element according to claim 1, wherein, in a plan view of the semiconductor element, the first barrier layer has a rectangular frame shape.

12. The semiconductor element according to claim 11, wherein, in a plan view of the semiconductor element, the first barrier layer has a slit.

13. The semiconductor device according to claim 1, further comprising an oxygen supply layer superimposed on the oxide semiconductor layer and supplying oxygen to the oxide semiconductor layer.

14. The semiconductor element according to claim 1, further comprising a hydrogen supply layer superimposed on the oxide semiconductor layer and supplying hydrogen to the oxide semiconductor layer.

15. The semiconductor device according to claim 1, comprising two oxide semiconductor layers and a gate electrode sandwiched between the two oxide semiconductor layers from above and below.

16. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one element selected from the group consisting of aluminum, indium, gallium, tin, silicon, hafnium, and zinc.

17. The semiconductor element according to claim 1, wherein the wiring layer is laminated on a semiconductor substrate, and the semiconductor element is electrically connected to a light-emitting element provided above the wiring layer.

18. A semiconductor device comprising a wiring layer and a first semiconductor element, wherein the first semiconductor element comprises a first oxide semiconductor layer provided within the wiring layer, and in a plan view of the first semiconductor element, the first oxide semiconductor layer is surrounded by a first barrier layer, and the first barrier layer includes a metal film.

19. The semiconductor device according to claim 18, further comprising a second semiconductor device provided adjacent to the first semiconductor device in a plan view of the first semiconductor device, wherein the second semiconductor device comprises a second oxide semiconductor layer provided in the wiring layer, and in a plan view of the second semiconductor device, the second oxide semiconductor layer is surrounded by a third barrier layer, the third barrier layer comprising a metal film.

20. The semiconductor device according to claim 18, further comprising a second semiconductor device provided so as to be superimposed on the first semiconductor device in a cross-sectional view of the first semiconductor device, wherein the second semiconductor device comprises a second oxide semiconductor layer provided in the wiring layer, and in a plan view of the second semiconductor device, the second oxide semiconductor layer is surrounded by a third barrier layer, and the third barrier layer includes a metal film.

Images