Sic single crystal, sic boule, sic substrate, and sic epitaxial wafer

WO2026204125A1PCT designated stage Publication Date: 2026-10-01RESONAC CORP
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Patent Information

Application Number
PCT/JP2026/007533
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-03-28
Filing Date
2026-02-27
Publication Date
2026-10-01

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Abstract

In this SiC single crystal, if respective measurement regions of a first outer peripheral region, a second outer peripheral region, a third outer peripheral region, and a fourth outer peripheral region are observed following a cleaning step that includes at least pure water cleaning, after etching, with molten KOH at 500°C for 15 minutes, an annular outer peripheral region having a width of 5 mm from the outer peripheral end of the Si surface, the proportion of first etch pits among etch pits originating from threading dislocations in each measurement region is 90% or more. If a first etch pit is viewed in plan view, the first etch pit has a first diagonal line, a second diagonal line, and a third diagonal line. The absolute value of the difference in length between the second diagonal line and the third diagonal line is 10.0% or less of the length which is longer among the second diagonal line length and the third diagonal line length.
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Description

SiC single crystal, SiC boule, SiC substrate and SiC epitaxial wafer

[0001] The present disclosure relates to a SiC single crystal, a SiC boule, a SiC substrate, and a SiC epitaxial wafer. The present application claims priority based on Japanese Patent Application No. 2025-055390 filed in Japan on March 28, 2025, the content of which is incorporated herein by reference.

[0002] Silicon carbide (SiC) has a breakdown electric field one order of magnitude larger and a band gap three times larger than those of silicon (Si). Further, silicon carbide (SiC) has characteristics such as thermal conductivity approximately three times higher than that of silicon (Si). Therefore, silicon carbide (SiC) is expected to be applied to power devices, high-frequency devices and the like. In addition, devices using silicon carbide (SiC) can operate in a high temperature range of 150° C. or higher. For this reason, in recent years, SiC epitaxial wafers have come to be used as substrates for the semiconductor devices described above.

[0003] A semiconductor device using SiC is referred to as a SiC device. A SiC device is produced using a SiC epitaxial wafer. A SiC epitaxial wafer is obtained by laminating a SiC epitaxial layer on the surface of a SiC substrate. The SiC substrate is a substrate before the SiC epitaxial layer is laminated thereon. The SiC substrate is cut out from, for example, a SiC boule (also referred to as a SiC ingot). The SiC boule is a SiC single crystal processed into a cylindrical shape.

[0004] The performance of a SiC device is affected by the SiC epitaxial wafer, the SiC substrate and the SiC boule that form the base of the SiC device. Defects and dislocations exist in SiC single crystals. There are various types of defects and dislocations. For example, threading screw dislocations (TSD), threading edge dislocations (TED), threading mixed dislocations (TMD) and the like are crystal defects extending in the <0001> c-axis direction. Further, for example, basal plane dislocations (BPD), stacking faults (SF) and the like are crystal defects within the (0001) c-plane.

[0005] For example, Patent Document 1 describes that the surface of a SiC single crystal can be etched with molten KOH, and the types of defects and dislocations can be distinguished from the shape of the etch pits revealed by the etching.

[0006] Japanese Patent Publication No. 2023-177969

[0007] Among etch pits classified as specific defects or dislocations, some have different shapes. The inventors have found that the shape of the etch pit affects the machining accuracy when processing SiC devices.

[0008] This disclosure has been made in view of the above-mentioned problems and aims to provide SiC single crystals, SiC boules, SiC substrates, and SiC epitaxial wafers that can be used to fabricate high-precision SiC devices.

[0009] The inventors have found that SiC substrates having etch pits of a specific shape offer high processing accuracy when fabricating SiC devices, and that using SiC substrates with etch pits of a specific shape makes it easier to fabricate high-precision SiC devices.

[0010] This disclosure provides the following means to solve the above problems.

[0011] (1) In the SiC single crystal according to the first embodiment, the annular outer region with a width of 5 mm from the outer edge of the Si plane is divided into four equal regions, which are designated as the first outer region, the second outer region, the third outer region, and the fourth outer region. After etching the Si plane with molten KOH at 500°C for 15 minutes, a cleaning process including at least pure water cleaning is performed, and when the measurement regions of the first outer region, the second outer region, the third outer region, and the fourth outer region are observed, the proportion of first etch pits among the etch pits originating from through dislocations in each measurement region is 90% or more. The first etch pit has a first diagonal, a second diagonal, and a third diagonal when viewed from above. The second diagonal and the third diagonal are each inclined from the <11-20> direction relative to the first diagonal. The absolute value of the difference between the lengths of the second diagonal and the third diagonal is 10.0% or less of the longer of the two diagonals.

[0012] (2) In the SiC single crystal according to the above embodiment, the length of the first diagonal may be shorter than the length of the second diagonal and the length of the third diagonal.

[0013] (3) In the SiC single crystal according to the above embodiment, the central region enclosed by a circle with a radius of 5 mm from the center is divided into four equal regions, which are designated as the first central region, the second central region, the third central region, and the fourth central region. After etching the Si surface with molten KOH at 500°C for 15 minutes, a cleaning process including at least pure water cleaning is performed, and when the measurement regions of the first central region, the second central region, the third central region, and the fourth central region are observed, the proportion of the first etch pit among the etch pits originating from threading dislocations may be 90% or more in each measurement region.

[0014] (4) In the SiC single crystal according to the above embodiment, the through dislocation may be a through edge dislocation.

[0015] (5) The SiC single crystal according to the above embodiment may have a polytype of 4H.

[0016] (6) The SiC Boule according to the second embodiment includes the SiC single crystal according to the above embodiment.

[0017] (7) The SiC substrate according to the third embodiment includes the SiC single crystal according to the above embodiment.

[0018] (8) The SiC epitaxial wafer according to the fourth embodiment includes the SiC substrate according to the above embodiment and a SiC epitaxial layer formed on the SiC substrate.

[0019] (9) The SiC epitaxial wafer according to the fifth embodiment comprises a SiC substrate and a SiC epitaxial layer formed on the SiC substrate. The annular outer region with a width of 5 mm from the outer edge of the first surface of the SiC epitaxial layer is divided into four equal regions, which are designated as the first outer region, the second outer region, the third outer region, and the fourth outer region. The first surface is etched with molten KOH at 500°C for 15 minutes, and after a cleaning process including at least pure water cleaning, the measurement regions of the first outer region, the second outer region, the third outer region, and the fourth outer region are observed, and in each measurement region, the proportion of first etch pits among the etch pits originating from through dislocations is 90% or more. The first etch pit has a first diagonal, a second diagonal, and a third diagonal when viewed from above. The second and third diagonals are each inclined from the <11-20> direction relative to the first diagonal. The absolute value of the difference in length between the second and third diagonals is 10.0% or less of the longer of the two diagonals.

[0020] By using the SiC single crystal, SiC boule, SiC substrate, and SiC epitaxial wafer described herein, high-precision SiC devices can be fabricated.

[0021] This is a perspective view of a SiC boule according to the first embodiment. This is a plan view of a SiC boule according to the first embodiment. This is a plan view of an etch pit. This is a cross-sectional view of a SiC substrate according to the second embodiment. This is a cross-sectional view of a SiC epitaxial wafer according to the third embodiment.

[0022] This embodiment will now be described in detail with reference to the drawings as appropriate. The drawings used in the following description may be enlarged for convenience to clearly illustrate the features of this embodiment, and the dimensional ratios of each component may differ from those of the actual components. The materials, dimensions, etc., exemplified in the following description are examples only, and this disclosure is not limited to them. It is possible to modify and implement these examples as appropriate without altering the essence of the invention.

[0023] In this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. While crystallography dictates that negative exponents are represented by a "-" (bar) above the number, in this specification, the negative sign is placed before the number.

[0024] First, let's define the directions. The thickness direction of the SiC single crystal, SiC Boule, SiC substrate, and SiC epitaxial wafer is defined as the Z direction. The Z direction may be the <0001> direction of the SiC single crystal, SiC Boule, SiC substrate, and SiC epitaxial wafer, or it may be tilted by an offset angle relative to the <0001> direction. One direction of the plane perpendicular to the Z direction is defined as the X direction. On the plane perpendicular to the Z direction, the direction perpendicular to the X direction is defined as the Y direction. The X direction corresponds to the <11-20> direction when the SiC single crystal, SiC Boule, SiC substrate, and SiC epitaxial wafer are viewed from the Z direction in a plan view. The Y direction corresponds to the <1-100> direction when the SiC single crystal, SiC Boule, SiC substrate, and SiC epitaxial wafer are viewed from the Z direction in a plan view.

[0025] "SiC Boule" Figure 1 is a perspective view of a SiC Boule 10 according to this embodiment. The SiC Boule 10 is an example of a SiC single crystal. The SiC Boule 10 has a first face S1, a second face S2, and a side surface S3. The first face S1 is, for example, a Si face. The first face S1 is, for example, a (0001) face, or a face inclined by an offset angle with respect to the (0001) face. The second face S2 is a face opposite to the first face S1. The side surface S3 is a face connecting the first face S1 and the second face S2. An orientation flat OF for defining the crystal orientation may be formed on the SiC Boule 10. Alternatively, a notch may be formed instead of the orientation flat OF.

[0026] The offset angle is the angle between a plane perpendicular to the Z direction, which is the thickness direction of the SiC Boule 10, and the (0001) plane in the actual crystal. The SiC Boule 10 may or may not have an offset angle in the <11-20> direction. If the SiC Boule 10 has an offset angle in the <11-20> direction, the angle is, for example, greater than 0.000° and less than or equal to 10.000°, preferably between 0.100° and 8.000°, more preferably between 3.500° and 4.500°, and even more preferably 4.000°. The SiC Boule 10 may or may not have an offset angle in the <1-100> direction. It is preferable that the SiC Boule 10 does not have an offset angle in the <1-100> direction.

[0027] The polytype of SiC Boule 10 is not particularly specified. The polytype of SiC Boule 10 may be any of 2H, 3C, 4H, 6H, or 15R. The polytype of SiC Boule 10 may be 4H or 6H, for example. The polytype of SiC Boule 10 is 4H, for example.

[0028] The diameter and thickness of the SiC boule 10 are not particularly limited. The diameter of the SiC boule 10 is, for example, 6 inches or more, preferably 8 inches or more, more preferably 10 inches or more, and even more preferably 12 inches or more.

[0029] The diameter of the SiC boule 10 is, for example, 145 mm or more, preferably 149 mm or more. The diameter of the SiC boule 10 is, for example, 155 mm or less, preferably 151 mm or less. The diameter of the SiC boule 10 is, for example, 195 mm or more, preferably 199 mm or more. The diameter of the SiC boule 10 is, for example, 205 mm or less, preferably 201 mm or less. The diameter of the SiC boule 10 is, for example, 245 mm or more, preferably 249 mm or more. The diameter of the SiC boule 10 is, for example, 255 mm or less, preferably 251 mm or less. The diameter of the SiC boule 10 is, for example, 295 mm or more, preferably 299 mm or more. The diameter of the SiC boule 10 is, for example, 305 mm or less, preferably 301 mm or less.

[0030] To obtain many SiC devices from a single SiC boule 10, a large diameter of the SiC boule 10 is preferable. On the other hand, as the diameter of the SiC boule 10 increases, it becomes significantly more difficult to improve the in-plane uniformity of the Si surface, and this difficulty increases especially when the diameter is 8 inches or more. High in-plane uniformity of the Si surface is necessary to obtain high-precision SiC devices. The SiC boule 10 according to this embodiment has high in-plane uniformity, which is particularly desirable for diameters of 8 inches or more.

[0031] Figure 2 is a plan view of the first surface S1 of the SiC Boolean 10. The first surface S1 of the SiC Boolean 10 has an outer peripheral region 1 and a central region 2. The outer peripheral region 1 is an annular region with a width of 5 mm from the outer edge. The central region 2 is the region enclosed by a circle with a radius of 5 mm from the center C of the first surface S1. The center C is the center of the circle that circumscribes the first surface S1.

[0032] The outer perimeter region 1 can be divided into four regions: the first outer perimeter region 1A, the second outer perimeter region 1B, the third outer perimeter region 1C, and the fourth outer perimeter region 1D. The first outer perimeter region 1A, the second outer perimeter region 1B, the third outer perimeter region 1C, and the fourth outer perimeter region 1D are four equal divisions of the outer perimeter region 1.

[0033] The first outer region 1A is the region containing the first point P1, which is shifted from the center C in the direction of [11-20]. The second outer region 1B is the region containing the second point P2, which is shifted from the center C in the direction of [-1-120]. The third outer region 1C is the region containing the third point P3, which is shifted from the center C in the direction of [-1100]. The fourth outer region 1D is the region containing the fourth point P4, which is shifted from the center C in the direction of [1-100].

[0034] For example, the outer perimeter region 1 may be divided into four parts by a first boundary line BL1 tilted +45° with respect to the <11-20> direction and a second boundary line BL2 tilted -45° with respect to the <11-20> direction. For example, among the regions divided by the first boundary line BL1 and the second boundary line BL2, the region located shifted from the center C in the [11-20] direction may be designated as the first outer perimeter region 1A, the region located shifted from the center C in the [-1-120] direction may be designated as the second outer perimeter region 1B, the region located shifted from the center C in the [-1100] direction may be designated as the third outer perimeter region 1C, and the region located shifted from the center C in the [1-100] direction may be designated as the fourth outer perimeter region 1D.

[0035] Central region 2 can be divided into four regions: the first central region 2A, the second central region 2B, the third central region 2C, and the fourth central region 2D. The first central region 2A, the second central region 2B, the third central region 2C, and the fourth central region 2D are four equal divisions of central region 2.

[0036] The first central region 2A is the region containing the fifth point P5, which is shifted from the center C in the direction of [11-20]. The second central region 2B is the region containing the sixth point P6, which is shifted from the center C in the direction of [-1-120]. The third central region 2C is the region containing the seventh point P7, which is shifted from the center C in the direction of [-1100]. The fourth central region 2D is the region containing the eighth point P8, which is shifted from the center C in the direction of [1-100].

[0037] For example, among the regions divided by the first boundary line BL1 and the second boundary line BL2, the region shifted in the direction of [11-20] from the center C may be designated as the first central region 2A, the region shifted in the direction of [-1-120] from the center C may be designated as the second central region 2B, the region shifted in the direction of [-1100] from the center C may be designated as the third central region 2C, and the region shifted in the direction of [1-100] from the center C may be designated as the fourth central region 2D.

[0038] When the first surface S1 is etched with molten KOH for 15 minutes, etch pits appear on the first surface S1. After etching, the first surface S1 is washed with pure water to remove residue and accurately determine the shape of the etch pits. Etch pits are holes formed by etching, and their shape differs depending on the defect or dislocation that causes them. For example, the shape of an etch pit can be used to distinguish whether it originates from a basal plane dislocation or from a through dislocation. Through dislocations include through helical dislocations, through edge dislocations, mixed through dislocations, and micropipes. The type of through dislocation can also be distinguished from the shape of the etch pit. For example, an etch pit with a medium hexagonal shape and a core is caused by a through helical dislocation (TSD), while an etch pit with a small hexagonal shape and a core is caused by a through edge dislocation (TED).

[0039] When observing the measurement regions of the first outer region 1A, the second outer region 1B, the third outer region 1C, and the fourth outer region 1D, the proportion of first etch pits among the etch pits originating from through dislocations is 90% or more in each measurement region. Considering productivity, the proportion of first etch pits among the etch pits originating from through dislocations in each measurement region may be 99% or less, 98% or less, or 95% or less. Furthermore, to facilitate the acquisition of SiC devices with higher precision, this proportion may be 100%. Furthermore, the proportion of first etch pits among the etch pits originating from through edge dislocations may also be 90% or more. Furthermore, considering productivity, the proportion of first etch pits among the etch pits originating from through edge dislocations in each measurement region may be 99% or less, 98% or less, or 95% or less. Furthermore, to facilitate the acquisition of SiC devices with higher precision, this proportion may be 100%.

[0040] Etch pits are observed, for example, using an optical microscope or an electron microscope. The measurement area is a single field of view observed with the optical microscope or electron microscope. The size of the measurement area is, for example, 1.0 mm. 2 These are the areas covered.

[0041] Preferably, the measurement region in the first outer peripheral region 1A is, for example, in the vicinity of the first point P1. Preferably, the measurement region in the second outer peripheral region 1B is, for example, in the vicinity of the second point P2. Preferably, the measurement region in the third outer peripheral region 1C is, for example, in the vicinity of the third point P3. Preferably, the measurement region in the fourth outer peripheral region 1D is, for example, in the vicinity of the fourth point P4. Here, the vicinity refers to a range within ±30° based on the line segment connecting any of the first point P1, the second point P2, the third point P3, or the fourth point P4 to the center C, and may also be a range within ±20° or a range within ±10°.

[0042] Alternatively, a region where a plurality of etch pits are observed may be selected as the measurement region. The number of etch pits included in the measurement region may be 10 or more, or 100 or more.

[0043] FIG. 3 is a schematic plan view of an etch pit EP derived from a threading dislocation. The etch pit EP is a hole formed in the first surface S1, and has a contrast different from that of a flat portion. The planar view shape of the etch pit EP is the shape of the outer periphery of the hole.

[0044] For example, in 4H—SiC, the planar view shape of the etch pit EP derived from a threading dislocation is substantially hexagonal. The substantially hexagonal shape includes those in which each side of the hexagon is curved, and those in which each corner of the hexagon is rounded. For the substantially hexagonal etch pit EP, three diagonal lines connecting two opposite vertices among the six vertices can be drawn. Hereinafter, the three diagonal lines are referred to as a first diagonal line L1, a second diagonal line L2, and a third diagonal line L3.

[0045] The first diagonal line L1 is a diagonal line extending along the <11-20> direction. The angle formed between the first diagonal line L1 and the <11-20> direction is, for example, not less than -0.100° and not more than 0.100°, and may be 0.000°. The second diagonal line L2 and the third diagonal line L3 are each diagonal lines inclined from the <11-20> direction more than the first diagonal line L1. The second diagonal line L2 is rotated approximately 60° from the first diagonal line L1, for example. For example, the angle formed between the second diagonal line L2 and the <11-20> direction is, for example, not less than 60.000° - 0.100° and not more than 60.000° + 0.100°, and may be 60.000°. The third diagonal line L3 is rotated approximately 120° from the first diagonal line L1, for example. For example, the angle formed between the third diagonal line L3 and the <11-20> direction is, for example, not less than 120.000° - 0.100° and not more than 120.000° + 0.100°, and may be 120.000°.

[0046] Here, a method for setting the three diagonal lines of an etch pit EP will be described. For example, when each vertex of a hexagon is distinct, three diagonal lines can be drawn by connecting opposing vertices with straight lines. The case where each vertex is distinct refers to the case where adjacent sides are connected to each other in a bent manner. The bending point of adjacent sides serves as the vertex.

[0047] When each vertex of the hexagon is rounded and a distinct vertex cannot be defined, the diagonal line is drawn by the following procedure. First, draw an inscribed circle that is inscribed in the etch pit EP. Draw a tangent line at the intersection point CP1 between the inscribed circle and the outer periphery of the etch pit EP. Then, among the intersection points CP2 of the respective tangent lines, opposing intersection points CP2 are connected to each other by a straight line. The intersection points between this straight line and the outer periphery of the etch pit EP are defined as vertices V1, V2, V3, V4, V5, and V6, respectively. Then, the straight line connecting the opposing vertices serves as the diagonal line. For example, in the example shown in FIG. 3, the straight line connecting the vertex V1 and the vertex V2 is the first diagonal line L1, the straight line connecting the vertex V3 and the vertex V4 is the second diagonal line L2, and the straight line connecting the vertex V5 and the vertex V6 is the third diagonal line L3.

[0048] The first etch pit is an etch pit that satisfies the condition that the absolute value of the difference in lengths between the second diagonal L2 and the third diagonal L3 is 10.0% or less of the length of the longer of the two diagonals L2 and L3. The absolute value of the difference in lengths between the second diagonal L2 and the third diagonal L3 may be 10.0% or less, 8.0% or less, 6.0% or less, 5.0% or less, or 4.0% or less of the length of the longer of the two diagonals L2 and L3. Of course, the absolute value of the difference in lengths between the second diagonal L2 and the third diagonal L3 may also be 0% of the length of the longer of the two diagonals L2 and L3. Here, an absolute value of 0% for the difference in lengths between the second diagonal L2 and the third diagonal L3 means that the lengths of the second diagonal L2 and the third diagonal L3 are the same. Furthermore, considering productivity, the absolute value of the difference between the lengths of the second diagonal L2 and the third diagonal L3 does not have to be 0% of the length of the longer of the two diagonals L2 and L3; it may be 0.1% or more, 0.5% or more, or 1.0% or more.

[0049] The length of the first diagonal L1 may be shorter than the lengths of the second diagonal L2 and the third diagonal L3. In principle, if the (0001) plane is tilted in the <11-20> direction, the length of the first diagonal L1 should be shorter than the lengths of the second diagonal L2 and the third diagonal L3. However, the length of the first diagonal L1 may be affected by residual stress in the crystal, carrier concentration, impurities that do not become carriers, other etch pits, etc., so there may be cases where this principle is not met. If the shape of the etch pit satisfies the condition that the length of the first diagonal L1 is shorter than the lengths of the second diagonal L2 and the third diagonal L3, it becomes easier to fabricate a higher precision SiC device.

[0050] The proportion of first etch pits can be determined by dividing the number of first etch pits within the measurement area by the total number of etch pits within the measurement area. All etch pits within the measurement area are analyzed to determine whether or not they are first etch pits.

[0051] When observing the measurement regions of the first central region 2A, the second central region 2B, the third central region 2C, and the fourth central region 2D, the proportion of first etch pits among the etch pits originating from through dislocations may be 90% or more in each measurement region. Considering productivity, the proportion of first etch pits among the etch pits originating from through dislocations may be 99% or less, 98% or less, or 95% or less in each measurement region. Furthermore, to facilitate the acquisition of SiC devices with higher precision, this proportion may be 100%. Furthermore, the proportion of first etch pits among the etch pits originating from through edge dislocations may also be 90% or more. Furthermore, considering productivity, the proportion of first etch pits among the etch pits originating from through edge dislocations may be 99% or less, 98% or less, or 95% or less in each measurement region. Furthermore, to facilitate the acquisition of SiC devices with higher precision, this proportion may be 100%.

[0052] The definition of the measurement area is the same as the definition of the measurement area for the outer perimeter. The definition of the first etch pit is the same as the definition of the first etch pit for the outer perimeter.

[0053] Next, the manufacturing method of the SiC boule 10 according to this embodiment will be described. First, a SiC single crystal is grown. The SiC single crystal may be produced by, for example, sublimation, gas method, or solution method. By processing the grown SiC single crystal into a cylindrical shape, a SiC boule (SiC ingot) is obtained.

[0054] Next, the first surface S1 of the SiC boule 10 is etched with molten KOH. Then, the etched first surface S1 is cleaned by a cleaning process. The cleaning process includes at least a pure water cleaning step. The cleaning process also includes a drying step after cleaning. In addition to the pure water cleaning step, the cleaning process may also include a cleaning step with an organic solvent. For example, ethanol, acetone, etc. can be used as the organic solvent. Then, the etch pits measured in each measurement area of ​​the outer peripheral region 1 of the etched first surface S1 are observed. The shape of the etch pits can be accurately determined by performing the cleaning process.

[0055] If 90% or more of the etch pits measured in each measurement area are first etch pits, then the SiC Boolean 10 according to this embodiment has been obtained. Conversely, if this condition is not met, the first surface S1 is machined. Specifically, the first surface S1 is tilted and ground. When the first surface S1 is tilted and ground, the tilt of the first surface S1 changes. The tilt of the first surface S1 is a parameter that contributes to the shape of the etch pit EP.

[0056] The processing and cleaning of the first surface S1, and the observation of the first surface S1 are repeated until the condition that 90% or more of the etch pits measured in each measurement area are first etch pits is met. By repeating this processing, cleaning, and observation, the SiC Boule 10 according to this embodiment is obtained.

[0057] In this embodiment, the SiC Boolean 10 exhibits small differences in the shape of the etch pits EP between two measurement points in the <11-20> direction and two measurement points in the <1-100> direction, with respect to the center C. The shape of the etch pits EP also changes depending on the inclination of the crystal plane. Small variation in the shape of the etch pits EP at four different measurement points means that the in-plane uniformity of the Si plane is high. The SiC device is formed on the Si plane of a SiC substrate sliced ​​from the SiC Boolean 10. Small inclination and variation of the Si plane allow for high-precision fabrication of the SiC device. In other words, using the SiC Boolean 10 according to this embodiment allows for the fabrication of high-precision SiC devices.

[0058] "SiC Substrate" Figure 4 is a cross-sectional view of the SiC substrate 20 according to this embodiment. The SiC substrate 20 is an example of a SiC single crystal. The plan view of the SiC substrate 20 is the same as the plan view of the SiC Boolean 10 shown in Figure 2.

[0059] The SiC substrate 20 is obtained by slicing the SiC Boolean 10. The SiC substrate 20 has the same configuration as the SiC Boolean 10, except for its thickness. For example, the diameter, polytype, offset angle, and other conditions of the SiC substrate 20 are the same as those of the SiC Boolean 10.

[0060] The first surface S1 of the SiC substrate 20 has an outer peripheral region 1 and a central region 2. The outer peripheral region 1 is an annular region with a width of 5 mm from the outer edge. The SiC substrate 20 may have a bevel portion B formed on its outer periphery. The bevel portion B is formed by removing the corners of the edges of the SiC substrate 20. The bevel portion B is often provided to prevent cracking or chipping of the SiC substrate 20. When the SiC substrate 20 has a bevel portion B, the outer peripheral edge means the edge of the outer periphery of the flat first surface S1 and does not include the bevel portion B. The central region 2 is a region enclosed by a circle with a radius of 5 mm from the center C of the first surface S1.

[0061] When observing the measurement regions of the first outer peripheral region 1A, second outer peripheral region 1B, third outer peripheral region 1C, and fourth outer peripheral region 1D of the first surface S1 of the SiC substrate 20, the proportion of first etch pits among the etch pits originating from through dislocations is 90% or more in each measurement region. Furthermore, when observing the measurement regions of the first central region 2A, second central region 2B, third central region 2C, and fourth central region 2D of the first surface S1 of the SiC substrate 20, the proportion of first etch pits among the etch pits originating from through dislocations may also be 90% or more in each measurement region. In each measurement region of the SiC substrate 20, the proportion of first etch pits among the etch pits originating from through dislocations may be the same as the proportion in the SiC Boolean 10.

[0062] The SiC substrate 20 can be manufactured by slicing the SiC Boule 10 described above. If the first surface S1 of the SiC Boule 10 satisfies predetermined conditions, then the first surface S1 of each SiC substrate 20 manufactured by slicing the SiC Boule 10 will also satisfy predetermined conditions. This is because the crystallinity of the SiC Boule 10 is inherited in the Z direction, and the SiC substrate 20, from which a portion in the Z direction has been cut out, also has similar crystallinity.

[0063] The SiC substrate 20 according to this embodiment exhibits high in-plane uniformity of the Si surface, similar to the SiC Boolean 10. By using the SiC substrate 20, which has small tilt and variation in the Si surface, SiC devices can be manufactured with high precision. In other words, using the SiC substrate 20 according to this embodiment enables the manufacture of high-precision SiC devices.

[0064] Here, an example is shown in which the SiC substrate 20 consists of a single substrate obtained by slicing from a SiC Boule 10, but the SiC substrate 20 is not limited to this case. For example, the SiC substrate may be a laminated substrate in which multiple substrates are bonded together. The laminated substrate may have, for example, a base substrate and a SiC single crystal substrate bonded to the base substrate. The base substrate is not particularly limited and may be, for example, polycrystalline SiC, single crystal SiC, SiC sintered body, ceramic, single crystal Si, SiO 2 A film-coated Si is also acceptable. The SiC single crystal substrate is sliced ​​from the SiC Boule 10 prepared by the procedure described above. The first surface of the SiC single crystal substrate satisfies the condition that in each measurement region, the proportion of first etch pits among the etch pits originating from threading dislocations is 90% or more. The bonded substrate can be prepared by bonding the base substrate and the SiC single crystal substrate together.

[0065] "SiC Epitaxial Wafer" Figure 5 is a cross-sectional view of the SiC epitaxial wafer 30 according to this embodiment. The SiC epitaxial wafer 30 is an example of a SiC single crystal. The plan view of the SiC epitaxial wafer 30 is the same as the plan view of the SiC Boolean 10 shown in Figure 2.

[0066] The SiC epitaxial wafer 30 has a SiC substrate 31 and a SiC epitaxial layer 32. For example, the diameter, polytype, offset angle, and other conditions of the SiC epitaxial wafer 30 are the same as those of the SiC Boolean 10.

[0067] The SiC substrate 31 may be the same as the SiC substrate 20 described above. That is, when observing the measurement areas of the first outer peripheral region 1A, second outer peripheral region 1B, third outer peripheral region 1C, and fourth outer peripheral region 1D of the first surface S1 of the SiC substrate 31, the proportion of first etch pits among the etch pits originating from through dislocations in each measurement area is 90% or more. Also, when observing the measurement areas of the first central region 2A, second central region 2B, third central region 2C, and fourth central region 2D of the first surface S1 of the SiC substrate 31, the proportion of first etch pits among the etch pits originating from through dislocations in each measurement area may be 90% or more. In each measurement area of ​​the SiC substrate 31, the proportion of first etch pits among the etch pits originating from through dislocations may be the same as the proportion in the SiC Boolean 10.

[0068] Furthermore, the shape of the etch pits on the first surface S1 of the SiC substrate 31 does not need to be known. Even if the first surface S1 does not satisfy the above conditions, it is sufficient if the first surface S1' of the SiC epitaxial layer 32, which will be described later, satisfies the above conditions.

[0069] The SiC epitaxial layer 32 is laminated on the first surface S1 of the SiC substrate 31. The SiC epitaxial layer 32 is made of SiC. The SiC epitaxial layer 32 undergoes crystal growth, inheriting the crystallinity of the SiC substrate 31.

[0070] The first surface S1' of the SiC epitaxial layer 32 has an outer peripheral region 1 and a central region 2. The definitions of the outer peripheral region 1 and the central region 2 are the same as those for the SiC substrate 20.

[0071] When observing the measurement regions of the first outer peripheral region 1A, second outer peripheral region 1B, third outer peripheral region 1C, and fourth outer peripheral region 1D of the first surface S1' of the SiC epitaxial layer 32, the proportion of first etch pits among the etch pits originating from through dislocations is 90% or more in each measurement region. Furthermore, when observing the measurement regions of the first central region 2A, second central region 2B, third central region 2C, and fourth central region 2D of the first surface S1' of the SiC epitaxial layer 32, the proportion of first etch pits among the etch pits originating from through dislocations may also be 90% or more in each measurement region. In each measurement region of the SiC epitaxial layer 32, the proportion of first etch pits among the etch pits originating from through dislocations may be the same as the proportion in the SiC Boolean 10.

[0072] A SiC epitaxial wafer 30 can be fabricated by epitaxially growing a SiC epitaxial layer 32 on a SiC substrate 31. If the first surface S1 of the SiC substrate 31 satisfies predetermined conditions, the first surface S1' of the SiC epitaxial layer 32 grown on the first surface S1 will also satisfy predetermined conditions. This is because the crystallinity of the SiC substrate 31 is inherited by the SiC epitaxial layer 32, and the SiC epitaxial layer 32 also has similar crystallinity.

[0073] The SiC epitaxial wafer 30 according to this embodiment exhibits high in-plane uniformity of the Si surface, similar to the SiC Boolean 10. By using the SiC epitaxial wafer 30, which has small tilt and variation in the Si surface, SiC devices can be manufactured with high precision. The element structure of the SiC device is formed within the SiC epitaxial layer 32. Using the SiC epitaxial wafer 30 according to this embodiment, high-precision SiC devices can be manufactured.

[0074] While preferred embodiments of this disclosure have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the gist of this disclosure as described in the claims.

[0075] 1 Outer Peripheral Region 1A First Outer Peripheral Region 1B Second Outer Peripheral Region 1C Third Outer Peripheral Region 1D Fourth Outer Peripheral Region 2 Central Region 2A First Central Region 2B Second Central Region 2C Third Central Region 2D Fourth Central Region 10 SiC Boule 20, 31 SiC Substrate 30 SiC Epitaxial Wafer 32 SiC Epitaxial Layer B Bevel BL1 First Boundary Line BL2 Second Boundary Line C Center CP1, CP2 Intersection EP Etch Pit L1 First Diagonal L2 Second Diagonal L3 Third Diagonal OF Orientation Flat P1 First Point P2 Second Point P3 Third Point P4 Fourth Point P5 Fifth Point P6 Sixth Point P7 Seventh Point P8 Eighth Point S1, S1' First Surface S2 Second Surface S3 Side V1, V2, V3, V4, V5, V6 Vertex

Claims

1. A SiC single crystal in which a ring-shaped outer region with a width of 5 mm from the outer edge of the Si surface is divided into four equal regions, which are designated as the first outer region, the second outer region, the third outer region, and the fourth outer region. After etching the Si surface with molten KOH at 500°C for 15 minutes, and after a cleaning process including at least pure water washing, when the measurement regions of the first, second, third, and fourth outer regions are observed, the proportion of first etch pits among the etch pits originating from through dislocations in each measurement region is 90% or more. The first etch pit has a first diagonal, a second diagonal, and a third diagonal when viewed from above, the second and third diagonals are each inclined from the <11-20> direction relative to the first diagonal, and the absolute value of the difference in length between the second and third diagonals is 10.0% or less of the length of the longer of the two diagonals.

2. The SiC single crystal according to claim 1, wherein the length of the first diagonal is shorter than the lengths of the second diagonal and the third diagonal.

3. A SiC single crystal according to claim 1, wherein a central region enclosed by a circle with a radius of 5 mm from the center is divided into four equal regions, which are designated as the first central region, the second central region, the third central region, and the fourth central region, and after etching the Si surface with molten KOH at 500°C for 15 minutes, a cleaning process including at least pure water washing is performed, and when the measurement regions of the first central region, the second central region, the third central region, and the fourth central region are observed, the proportion of the first etch pits among the etch pits originating from threading dislocations in each measurement region is 90% or more.

4. The SiC single crystal according to claim 1, wherein the through dislocation is a through edge dislocation.

5. The SiC single crystal according to claim 1, wherein the polytype is 4H.

6. A SiC boule comprising the SiC single crystal described in claim 1.

7. A SiC substrate comprising the SiC single crystal described in claim 1.

8. A SiC epitaxial wafer comprising a SiC substrate according to claim 7 and a SiC epitaxial layer formed on the SiC substrate.

9. The SiC substrate and the SiC epitaxial layer formed on the SiC substrate are provided, wherein the annular outer region with a width of 5 mm from the outer edge of the first surface of the SiC epitaxial layer is divided into four equal regions, which are designated as the first outer region, the second outer region, the third outer region, and the fourth outer region, and after etching the first surface with molten KOH at 500°C for 15 minutes, and after a cleaning process including at least pure water washing, when the measurement regions of the first outer region, the second outer region, the third outer region, and the fourth outer region are observed, the proportion of first etch pits among the etch pits originating from through dislocations in each measurement region is 90% or more, and the first etch pit has a first diagonal, a second diagonal, and a third diagonal when viewed from above, and the second diagonal and the third diagonal are each inclined from the <11-20> direction relative to the first diagonal. A SiC epitaxial wafer in which the absolute value of the difference between the lengths of the second diagonal and the third diagonal is 10.0% or less of the length of the longer of the two diagonals.