Power conversion device

Abstract

This power conversion device makes it possible to achieve zero-voltage soft switching without directly controlling a plurality of switches for zero-voltage soft switching by a control device, and reduces current distortion. A signal generation circuit (52) generates a control signal for each of a plurality of switches (8). A control device (51) generates, in an n-th control cycle, a plurality of first PWM signals (SU1, SV1, SW1) and a plurality of second PWM signals (SU2, SV2, SW2) in an (n +1)-th control cycle. The control device (51) stops operation of a power conversion circuit (11) if an input current detection value by a current detection unit (16) exceeds a current protection threshold. If it is determined that two-phase resonance currents simultaneously flow through a resonance inductor (L1) in the (n +1)-th control cycle at the time of the n-th control cycle, the control device (51) increases the current protection threshold in the (n +1)-th control cycle.

Description

Power converter

[0001] This disclosure relates to a power conversion device, and more particularly to a power conversion device capable of converting DC power to AC power.

[0002] Patent document 1 discloses a power conversion device.

[0003] The power converter disclosed in Patent Document 1 includes a first DC terminal and a second DC terminal, a power conversion circuit, a plurality of AC terminals, a plurality of switches, a plurality of resonance capacitors, a resonance inductor, a capacitor, and a control device. The power conversion circuit includes a plurality of first switching elements and a plurality of second switching elements. In the power conversion circuit, a plurality of switching circuits in which the plurality of first switching elements and the plurality of second switching elements are connected in series in one-to-one correspondence are connected in parallel with each other. In the power conversion circuit, the plurality of first switching elements are connected to the first DC terminal, and the plurality of second switching elements are connected to the second DC terminal. The plurality of AC terminals correspond one-to-one to the plurality of switching circuits. Each of the plurality of AC terminals is connected to a connection point between the first switching element and the second switching element in the corresponding switching circuit among the plurality of switching circuits. The plurality of switches correspond one-to-one to the plurality of switching circuits. Each of the plurality of switches has a first end connected to the connection point between the first switching element and the second switching element in the corresponding switching circuit among the plurality of switching circuits, and a second end commonly connected to a common connection point. The plurality of resonance capacitors correspond one-to-one to the plurality of switches. Each of the plurality of resonance capacitors is connected between the first end of the corresponding switch among the plurality of switches and the second DC terminal. The resonance inductor has a first end and a second end. In the resonance inductor, the first end of the resonance inductor is connected to the common connection point. The capacitor is connected between the second end of the resonance inductor and the second DC terminal. The control device controls the plurality of first switching elements, the plurality of second switching elements and the plurality of switches. When the control device determines that two-phase resonance currents corresponding to two of the plurality of switching circuits simultaneously flow through the resonance inductor, the control device performs control (shift control) to shift the on-periods of the first switching element and the second switching element in one of the two switching circuits, respectively.

[0004] In the power converter disclosed in Patent Document 1, soft switching can be performed more reliably.

[0005] In the power conversion device disclosed in Patent Document 1, the control device needs to generate and output multiple first PWM signals, multiple second PWM signals, and multiple control signals, which results in a large control device.

[0006] Furthermore, in the power conversion device disclosed in Patent Document 1, the current distortion of the load current may increase due to the difference in line voltage generated by shifting the ON periods of the first switching element and the second switching element in a single switching circuit.

[0007] International Publication No. 2023 / 074636

[0008] The object of this disclosure is to provide a power conversion device that can perform zero-voltage soft switching without directly controlling multiple switches for zero-voltage soft switching in the control device, and that can reduce current distortion.

[0009] A power conversion device according to one embodiment of the present disclosure comprises a first DC terminal, a second DC terminal, a power conversion circuit, a plurality of AC terminals, a plurality of switches, a plurality of resonant capacitors, a resonant inductor, a regenerative capacitor, a current detection unit, a control device, and a signal generation circuit. The power conversion circuit has a plurality of first switching elements and a plurality of second switching elements. In the power conversion circuit, a plurality of switching circuits, each in which the plurality of first switching elements and the plurality of second switching elements are connected in series in a one-to-one relationship, are connected in parallel to each other. In the power conversion circuit, the plurality of first switching elements are connected to the first DC terminal. In the power conversion circuit, the plurality of second switching elements are connected to the second DC terminal. The plurality of AC terminals correspond one-to-one to the plurality of switching circuits. Each of the plurality of AC terminals is connected to the connection point of the first switching element and the second switching element in the corresponding switching circuit among the plurality of switching circuits, and load current flows through it. The plurality of switches correspond one-to-one to the plurality of switching circuits. Each of the plurality of switches has a first end and a second end. Each of the plurality of switches has its first end connected to the connection point of the first switching element and the second switching element in the corresponding switching circuit among the plurality of switching circuits. The plurality of resonant capacitors correspond one-to-one with the plurality of switches. Each of the plurality of resonant capacitors is connected between the first end and the second DC terminal of the corresponding switch among the plurality of switches. The resonant inductor has a third end and a fourth end. In the resonant inductor, the third end is connected to the second end of the plurality of switches. The regenerative capacitor has a fifth end and a sixth end. In the regenerative capacitor, the fifth end is connected to the second DC terminal, and the sixth end is connected to the fourth end of the resonant inductor. The current detection unit detects the input current flowing from the first DC terminal to the power conversion circuit.The control device generates a plurality of first PWM signals to control the plurality of first switching elements and a plurality of second PWM signals to control the plurality of second switching elements, based on a plurality of duty cycle command values ​​of a plurality of phases corresponding one-to-one to the plurality of switching circuits. The signal generation circuit provides each of the plurality of switches with a control signal whose potential changes between a high level and a low level. For each of the plurality of switching circuits, the control device sets a second dead time period by adding a predetermined time to a first dead time period, which is set in advance so that the on periods of the first switching element and the second switching element do not overlap between the high-level period of the first PWM signal to the first switching element and the high-level period of the second PWM signal to the second switching element. The predetermined time is determined according to the current value of the load current, the inductance of the resonant inductor and the voltage value of the regenerative capacitor. For each of the plurality of switches, the signal generation circuit generates the control signal having a high-level period corresponding to the second dead time period for the corresponding switching circuit among the plurality of switching circuits. The control device generates the plurality of first PWM signals and the plurality of second PWM signals in the nth control cycle, where n is a natural number. The control device stops the operation of the power conversion circuit if the input current detected by the current detection unit exceeds the current protection threshold. If the control device determines during the nth control cycle that two-phase resonant currents corresponding to two of the plurality of switching circuits flow simultaneously through the resonant inductor in the (n+1)th control cycle, it increases the current protection threshold in the (n+1)th control cycle.

[0010] Figure 1 is a circuit diagram of a system equipped with a power converter according to Embodiment 1. Figure 2 is a circuit block diagram of the signal generation circuit in the same power converter. Figure 3 is an explanatory diagram of the relationship between the duty cycle command value and the load current used in the control device of the same power converter. Figure 4 is an explanatory diagram of the operation of the same power converter. Figure 5 is a timing chart for explaining the operation of the same power converter. Figure 6 is a timing chart for explaining the operation of the same power converter. Figure 7 is a timing chart for explaining the operation of the same power converter. Figure 8 is a timing chart for explaining the operation of the same power converter. Figure 9 is a flowchart for explaining the operation of the same power converter. Figure 10 is an explanatory diagram of the operation when the polarity of the U-phase load current and the V-phase load current are both positive and the U-phase load current and the V-phase load current overlap. Figure 11 is an explanatory diagram of the operation when the polarity of the U-phase load current and the V-phase load current are both negative and the U-phase load current and the V-phase load current overlap. Figure 12 is a circuit diagram of a system equipped with a power conversion device according to Embodiment 2.

[0011] (Embodiment 1) Below, the power conversion device 100 according to Embodiment 1 will be described with reference to Figures 1 to 11.

[0012] (1) Overall Configuration of the Power Converter The power converter 100 includes, for example, a first DC terminal 31, a second DC terminal 32, and a plurality (for example, three) AC terminals 41, as shown in Figure 1. A DC power supply E1 is connected between the first DC terminal 31 and the second DC terminal 32 of the power converter 100, and an AC load RA1 is connected to the plurality of AC terminals 41. The AC load RA1 is, for example, a three-phase servo motor. The power converter 100 converts the DC output from the DC power supply E1 into AC power and outputs it to the AC load RA1. The DC power supply E1 includes, for example, an AC-DC converter, a DC-DC converter, a solar cell, or a fuel cell. In the power converter 100, if the plurality of AC terminals 41 are three AC terminals 41, the AC power is, for example, three-phase AC power having U-phase, V-phase, and W-phase.

[0013] The power converter 100 comprises a power conversion circuit 11, a plurality (for example, three) of switches 8, a plurality (for example, three) of resonant capacitors 9, a resonant inductor L1, a regenerative capacitor 15, a current detection unit 16, a control device 51, and a signal generation circuit 52. Each of the plurality of switches 8 is, for example, a bidirectional switch. The power converter 100 further comprises a protection circuit 17 and a capacitor C10.

[0014] The power conversion circuit 11 has a plurality (for example, three) of first switching elements 1 and a plurality (for example, three) of second switching elements 2. In the power conversion circuit 11, a plurality (for example, three) of switching circuits 10, each consisting of a plurality of first switching elements 1 and a plurality of second switching elements 2 connected in a one-to-one series relationship, are connected in parallel to each other. In the power conversion circuit 11, the plurality of first switching elements 1 are connected to a first DC terminal 31, and the plurality of second switching elements 2 are connected to a second DC terminal 32.

[0015] The multiple AC terminals 41 correspond one-to-one with the multiple switching circuits 10. Each of the multiple AC terminals 41 is connected to the connection point 3 of the first switching element 1 and the second switching element 2 in the corresponding switching circuit 10 among the multiple switching circuits 10.

[0016] The multiple switches 8 correspond one-to-one with the multiple switching circuits 10. Each of the multiple switches 8 has a first end 81 and a second end 82. The first end 81 of each of the multiple switches 8 is connected to the connection point 3 of the first switching element 1 and the second switching element 2 in the corresponding switching circuit 10 among the multiple switching circuits 10.

[0017] Multiple resonant capacitors 9 correspond one-to-one with multiple switches 8. Each of the multiple resonant capacitors 9 is connected between the first terminal 81 and the second DC terminal 32 of the corresponding switch 8 among the multiple switches 8.

[0018] The resonant inductor L1 has a third terminal and a fourth terminal. In the resonant inductor L1, the third terminal is connected to the second terminal 82 of a plurality (for example, three) switches 8.

[0019] The regenerative capacitor 15 has a fifth terminal 153 and a sixth terminal 154. In the regenerative capacitor 15, the fifth terminal 153 is connected to the second DC terminal 32, and the sixth terminal 154 is connected to the fourth terminal of the resonant inductor L1.

[0020] The current detection unit 16 detects the input current Iin flowing from the first DC terminal 31 to the power conversion circuit 11.

[0021] The control device 51 generates a plurality of first PWM (Pulse Width Modulation) signals SU1, SV1, SW1 for controlling a plurality of first switching elements 1, and a plurality of second PWM signals SU2, SV2, SW2 for controlling a plurality of second switching elements 2.

[0022] The signal generation circuit 52 generates multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 for controlling multiple switches 8.

[0023] (2) Details of the power converter In the following description, for the sake of convenience, the switching circuits 10 corresponding to the U-phase, V-phase, and W-phase may be referred to as switching circuit 10U, switching circuit 10V, and switching circuit 10W, respectively. Also, in the following description, the first switching element 1 and the second switching element 2 of switching circuit 10U may be referred to as the first switching element 1U and the second switching element 2U. Also, in the following description, the first switching element 1 and the second switching element 2 of switching circuit 10V may be referred to as the first switching element 1V and the second switching element 2V. Also, in the following description, the first switching element 1 and the second switching element 2 of switching circuit 10W may be referred to as the first switching element 1W and the second switching element 2W. Furthermore, in the following, the connection point 3 between the first switching element 1U and the second switching element 2U may be referred to as connection point 3U, the connection point 3 between the first switching element 1V and the second switching element 2V may be referred to as connection point 3V, and the connection point 3 between the first switching element 1W and the second switching element 2W may be referred to as connection point 3W. Furthermore, in the following, the AC terminal 41 connected to connection point 3U may be referred to as AC terminal 41U, the AC terminal 41 connected to connection point 3V may be referred to as AC terminal 41V, and the AC terminal 41 connected to connection point 3W may be referred to as AC terminal 41W. Furthermore, in the following, the resonant capacitor 9 connected in parallel to the second switching element 2U may be referred to as resonant capacitor 9U, the resonant capacitor 9 connected in parallel to the second switching element 2V may be referred to as resonant capacitor 9V, and the resonant capacitor 9 connected in parallel to the second switching element 2W may be referred to as resonant capacitor 9W. Furthermore, in the following, the switch 8 connected to connection point 3U may be referred to as switch 8U, the switch 8 connected to connection point 3V as switch 8V, and the switch 8 connected to connection point 3W as switch 8W.

[0024] In the power converter 100, for example, the high-potential output terminal (positive terminal) of the DC power supply E1 is connected to the first DC terminal 31, and the low-potential output terminal (negative terminal) of the DC power supply E1 is connected to the second DC terminal 32. In addition, in the power converter 100, for example, the U-phase terminal, V-phase terminal, and W-phase terminal of the AC load RA1 are connected to the three AC terminals 41U, 41V, and 41W, respectively.

[0025] In the power conversion circuit 11, each of the multiple (three in the example of Figure 1) first switching elements 1 and each of the multiple (three in the example of Figure 1) second switching elements 2 has a control terminal, a first main terminal, and a second main terminal. The control terminals of the multiple first switching elements 1 and the multiple second switching elements 2 are connected to the control device 51. In each of the multiple switching circuits 10 of the power conversion device 100, the first main terminal of the first switching element 1 is connected to the first DC terminal 31, the second main terminal of the first switching element 1 is connected to the first main terminal of the second switching element 2, and the second main terminal of the second switching element 2 is connected to the second DC terminal 32. In each of the multiple switching circuits 10, the first switching element 1 is a high-side switching element (P-side switching element), and the second switching element 2 is a low-side switching element (N-side switching element). Each of the multiple first switching elements 1 and the multiple second switching elements 2 is, for example, an IGBT (Insulated Gate Bipolar Transistor). Therefore, the control terminal, first main terminal, and second main terminal of each of the multiple first switching elements 1 and the multiple second switching elements 2 are the gate terminal, collector terminal, and emitter terminal, respectively.

[0026] The power conversion circuit 11 further includes a plurality of first diodes 4 connected in antiparallel in a one-to-one relationship to a plurality of first switching elements 1 (three), and a plurality of second diodes 5 connected in antiparallel in a one-to-one relationship to a plurality of second switching elements 2 (three). In each of the plurality of first diodes 4, the anode of the first diode 4 is connected to the second main terminal (emitter terminal) of the first switching element 1 corresponding to the first diode 4, and the cathode of the first diode 4 is connected to the first main terminal (collector terminal) of the first switching element 1 corresponding to the first diode 4. In each of the plurality of second diodes 5, the anode of the second diode 5 is connected to the second main terminal (emitter terminal) of the second switching element 2 corresponding to the second diode 5, and the cathode of the second diode 5 is connected to the first main terminal (collector terminal) of the second switching element 2 corresponding to the second diode 5.

[0027] At the connection point 3U between the first switching element 1U and the second switching element 2U, the U-phase terminal of the AC load RA1 is connected via the AC terminal 41U. At the connection point 3V between the first switching element 1V and the second switching element 2V, the V-phase terminal of the AC load RA1 is connected via the AC terminal 41V. At the connection point 3W between the first switching element 1W and the second switching element 2W, the W-phase terminal of the AC load RA1 is connected via the AC terminal 41W.

[0028] Multiple resonant capacitors 9 correspond one-to-one with multiple switches 8. Each of the multiple resonant capacitors 9 is connected between the first terminal 81 and the second DC terminal 32 of the corresponding switch 8 among the multiple switches 8. The power converter 100 has multiple (three in the example of Figure 1) resonant circuits. Each of the multiple resonant circuits includes a resonant capacitor 9 and a resonant inductor L1. In this embodiment, the resonant inductor L1 is common to the multiple resonant circuits.

[0029] Each of the multiple switches 8 has a third switching element 6 and a fourth switching element 7. Each of the multiple (three in the example of Figure 1) third switching elements 6 and each of the multiple (three in the example of Figure 1) fourth switching elements 7 has a control terminal, a first main terminal, and a second main terminal. The control terminals of the multiple third switching elements 6 and the multiple fourth switching elements 7 are connected to the signal generation circuit 52. Each of the multiple third switching elements 6 and the multiple fourth switching elements 7 is, for example, an IGBT. Therefore, the control terminal, first main terminal, and second main terminal of each of the multiple third switching elements 6 and the multiple fourth switching elements 7 are the gate terminal, collector terminal, and emitter terminal, respectively. In each of the multiple switches 8, the third switching element 6 and the fourth switching element 7 are connected in reverse series. In each of the multiple switches 8, the first main terminal (collector terminal) of the third switching element 6 is connected to the first main terminal (collector terminal) of the fourth switching element 7. In each of the multiple switches 8, the second main terminal (emitter terminal) of the third switching element 6 is connected to the connection point 3 of the corresponding switching circuit 10 among the multiple switching circuits 10, and the second main terminal (emitter terminal) of the fourth switching element 7 is connected to the resonant inductor L1. Furthermore, each of the multiple switches 8 has a diode 61 connected in antiparallel to the third switching element 6 and a diode 71 connected in antiparallel to the fourth switching element 7.

[0030] In the power converter 100, switch 8U is connected to the connection point 3U between the first switching element 1U and the second switching element 2U. Switch 8V is connected to the connection point 3V between the first switching element 1V and the second switching element 2V. Switch 8W is connected to the connection point 3W between the first switching element 1W and the second switching element 2W. For convenience of explanation, the third switching element 6 and the fourth switching element 7 of switch 8U may be referred to as the third switching element 6U and the fourth switching element 7U, respectively; the third switching element 6 and the fourth switching element 7 of switch 8V may be referred to as the third switching element 6V and the fourth switching element 7V, respectively; and the third switching element 6 and the fourth switching element 7 of switch 8W may be referred to as the third switching element 6W and the fourth switching element 7W, respectively.

[0031] Multiple switches 8 are controlled by a signal generation circuit 52. In other words, the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W are controlled by the signal generation circuit 52.

[0032] The resonant inductor L1 has a third terminal and a fourth terminal. In the resonant inductor L1, the third terminal is connected to the second terminal 82 of the plurality of switches 8. More specifically, the third terminal of the resonant inductor L1 is connected to a common connection point 25 to which the second terminals 82 of the plurality of switches 8 are connected. The fourth terminal of the resonant inductor L1 is connected to the sixth terminal 154 of the regenerative capacitor 15.

[0033] The regenerative capacitor 15 is connected between the fourth terminal of the resonant inductor L1 and the second DC terminal 32. The regenerative capacitor 15 is, for example, a film capacitor.

[0034] The protection circuit 17 includes a third diode 13 and a fourth diode 14. The third diode 13 is connected between the common connection point 25 and the first DC terminal 31. The anode of the third diode 13 is connected to the common connection point 25. Also, the cathode of the third diode 13 is connected to the first DC terminal 31. The fourth diode 14 is connected between the common connection point 25 and the second DC terminal 32. The anode of the fourth diode 14 is connected to the second DC terminal 32. Also, the cathode of the fourth diode 14 is connected to the common connection point 25. Therefore, the fourth diode 14 is connected in series with the third diode 13.

[0035] Capacitor C10 is connected between the first DC terminal 31 and the second DC terminal 32, and is connected in parallel to the power conversion circuit 11. Capacitor C10 is, for example, an electrolytic capacitor.

[0036] As described above, the current detection unit 16 detects the input current Iin flowing from the first DC terminal 31 to the power conversion circuit 11. More specifically, the current detection unit 16 detects the input current Iin flowing from the DC power supply E1 to the power conversion circuit 11 via the first DC terminal 31. The current detection unit 16 is a current detection resistor, but it is not limited to a current detection resistor; for example, a current transformer may also be used.

[0037] The control device 51 controls a plurality of first switching elements 1 and a plurality of second switching elements 2. The control device 51 includes a computer system. The computer system mainly consists of a processor and memory as hardware. The processor executes a program recorded in the memory of the computer system, thereby realizing the function of the control device 51 in this disclosure. The processor of the computer system is composed of one or more electronic circuits including semiconductor integrated circuits (ICs) or large-scale integrated circuits (LSIs). The integrated circuits such as ICs and LSIs referred to here are named differently depending on the degree of integration, and include integrated circuits called system LSIs, VLSIs (Very Large Scale Integrations), or ULSIs (Ultra Large Scale Integrations). Furthermore, FPGAs (Field-Programmable Gate Arrays) that are programmed after the manufacture of the LSI, or logic devices that allow for the reconstruction of junction relationships or circuit compartments within the LSI, can also be used as processors. The plurality of electronic circuits may be aggregated on a single chip or distributed across multiple chips. Multiple chips may be integrated into a single device or distributed across multiple devices. The computer system referred to here includes a microcontroller having one or more processors and one or more memories. Therefore, the microcontroller also consists of one or more electronic circuits, including semiconductor integrated circuits or large-scale integrated circuits.

[0038] The control device 51 outputs multiple first PWM signals SU1, SV1, and SW1 to control the on / off state of each of the multiple first switching elements 1U, 1V, and 1W. Each of the multiple first PWM signals SU1, SV1, and SW1 is a PWM signal whose potential level changes between, for example, a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level. The first switching elements 1U, 1V, and 1W are turned on when the first PWM signals SU1, SV1, and SW1 are at a high level and turned off when they are at a low level, respectively. The control device 51 also outputs multiple second PWM signals SU2, SV2, and SW2 to control the on / off state of each of the multiple second switching elements 2U, 2V, and 2W. Each of the multiple second PWM signals SU2, SV2, and SW2 is a PWM signal whose potential level changes between, for example, a first potential level (hereinafter also referred to as the low level) and a second potential level (hereinafter also referred to as the high level) that is higher than the first potential level. The second switching elements 2U, 2V, and 2W are turned on when the second PWM signals SU2, SV2, and SW2 are at a high level and turned off when they are at a low level, respectively.

[0039] The control device 51 generates a plurality of first PWM signals SU1, SV1, SW1 and a plurality of second PWM signals SU2, SV2, SW2 based on the three-phase duty command values ​​du, dv, dw (see Figure 3) of the three-phase modulation scheme. Figure 3 shows a U-phase modulated wave with the U-phase duty command value du as the instantaneous value, a V-phase modulated wave with the V-phase duty command value dv as the instantaneous value, and a W-phase modulated wave with the W-phase duty command value dw as the instantaneous value. The U-phase modulated wave, V-phase modulated wave, and W-phase modulated wave are sinusoidal and have a phase difference of 120° from each other. The length of one period of each of the U-phase modulated wave, V-phase modulated wave, and W-phase modulated wave is the same. The control device 51 generates the three-phase modulated duty command values ​​du, dv, dw based on information regarding the state of the AC load RA1. When the AC load RA1 is a three-phase servo motor, information regarding the state of the AC load RA1 includes, for example, the detected values ​​from a plurality (three) of current sensors 18a, 18b, and 18c that detect the output currents (hereinafter also referred to as load currents) iU, iV, and iW flowing through the U-phase, V-phase, and W-phase terminals of the AC load RA1, respectively. Each of the three current sensors 18a, 18b, and 18c is a current detection resistor, but it is not limited to current detection resistors; for example, a current transformer may also be used.

[0040] As shown in Figure 4, the control device 51 generates multiple first PWM signals SU1, SV1, SW1 and multiple second PWM signals SU2, SV2, SW2 using the carrier signal CA1 and three phase duty cycle command values ​​du, dv, dw (see Figure 3) for each period of the triangular wave carrier signal CA1. Note that one period of the carrier signal CA1 is shorter than one period of each of the U-phase modulated wave, V-phase modulated wave, and W-phase modulated wave. Also, the first PWM signal SW1 and the second PWM signal SW2 are not shown in Figure 4.

[0041] The control device 51 generates a first PWM signal SU1 and a second PWM signal SU2 to be supplied to the first switching element 1U and the second switching element 2U, respectively, based on the carrier signal CA1 and the duty cycle command value du. The control device 51 also generates a first PWM signal SV1 and a second PWM signal SV2 to be supplied to the first switching element 1V and the second switching element 2V, respectively, based on the carrier signal CA1 and the duty cycle command value dv of the V phase. The control device 51 also generates a first PWM signal SW1 and a second PWM signal SW2 to be supplied to the first switching element 1W and the second switching element 2W, respectively, based on the carrier signal CA1 and the duty cycle command value dw of the W phase.

[0042] In this embodiment, the control device 51 sets the maximum value of the carrier signal CA1 to 1 and the minimum value to 0. The control device 51 also sets the maximum value (corresponding to 100%) of each of the three-phase duty command values ​​du, dv, and dw to 1 and the minimum value (corresponding to 0%) to 0. In this embodiment, when the duty command value du of the U phase is greater than 0.5, the polarity of the U phase load current iU is positive, and when the duty command value du of the U phase is less than 0.5, the polarity of the U phase load current iU is negative. In this embodiment, when the duty command value dv of the V phase is greater than 0.5, the polarity of the V phase load current iV is positive, and when the duty command value dv of the V phase is less than 0.5, the polarity of the V phase load current iV is negative. Furthermore, in this embodiment, when the duty cycle command value dw of the W phase is greater than 0.5, the polarity of the load current iW of the W phase is positive, and when the duty cycle command value dw of the W phase is less than 0.5, the polarity of the load current iW of the W phase is negative. In addition, the control device 51 may set the maximum and minimum values ​​of the carrier signal CA1 to values ​​other than 1 and 0, respectively, and the maximum and minimum values ​​of the three-phase duty cycle command values ​​du, dv, and dw to values ​​other than 1 and 0, respectively. In this case, when the duty cycle command value du of the U phase is greater than {(maximum value of duty cycle command value du) - (minimum value of duty cycle command value du)} / 2, the polarity of the load current iU of the U phase is positive, and when it is less than {(maximum value of duty cycle command value du) - (minimum value of duty cycle command value du)} / 2, the polarity of the load current iU of the U phase is negative. Furthermore, if the duty cycle command value dv of the V phase is greater than {(maximum value of duty cycle command value dv) - (minimum value of duty cycle command value dv)} / 2, the polarity of the V phase load current iV is positive, and if it is less than {(maximum value of duty cycle command value dv) - (minimum value of duty cycle command value dv)} / 2, the polarity of the V phase load current iV is negative. Also, if the duty cycle command value dw of the W phase is greater than {(maximum value of duty cycle command value dw) - (minimum value of duty cycle command value dw)} / 2, the polarity of the W phase load current iW is positive, and if it is less than {(maximum value of duty cycle command value dw) - (minimum value of duty cycle command value dw)} / 2, the polarity of the W phase load current iW is negative.

[0043] The duty cycles of the first PWM signal SU1 and the second PWM signal SU2 generated by the control device 51 each change based on the duty command value du. The control device 51 compares the duty command value du with the carrier signal CA1 to generate the first PWM signal SU1. More specifically, the control device 51 compares the duty command value du with the carrier signal CA1, and generates the first PWM signal SU1 which becomes a high level during a period in which the duty command value du is larger than the carrier signal CA1, and becomes a low level during a period in which the duty command value du is equal to or less than the carrier signal CA1. Further, the control device 51 inverts the first PWM signal SU1 to generate the second PWM signal SU2. Furthermore, the control device 51 sets a first dead time period Td1 (see FIG. 5) between the high level period of the first PWM signal SU1 and the high level period of the second PWM signal SU2 so that the on-period of the first switching element 1U and the on-period of the second switching element 2U do not overlap.

[0044] The duty cycles of the first PWM signal SV1 and the second PWM signal SV2 generated by the control device 51 each change based on the duty command value dv. The control device 51 compares the duty command value dv with the carrier signal CA1 to generate the first PWM signal SV1. More specifically, the control device 51 compares the duty command value dv with the carrier signal CA1, and generates the first PWM signal SV1 which becomes a high level during a period in which the duty command value dv is larger than the carrier signal CA1, and becomes a low level during a period in which the duty command value dv is equal to or less than the carrier signal CA1. Further, the control device 51 inverts the first PWM signal SV1 to generate the second PWM signal SV2. Furthermore, the control device 51 sets a first dead time period Td1 (see FIG. 6) between the high level period of the first PWM signal SV1 and the high level period of the second PWM signal SV2 so that the on-period of the first switching element 1V and the on-period of the second switching element 2V do not overlap.

[0045] The duty cycles of the first PWM signal SW1 and the second PWM signal SW2 generated by the control device 51 each change based on the duty command value dw. The control device 51 compares the duty command value dw with the carrier signal CA1 to generate the first PWM signal SW1. More specifically, the control device 51 compares the duty command value dw with the carrier signal CA1, and generates the first PWM signal SW1 that becomes high level during a period in which the duty command value dw is larger than the carrier signal CA1, and becomes low level during a period in which the duty command value dw is equal to or less than the carrier signal CA1. Further, the control device 51 inverts the first PWM signal SW1 to generate the second PWM signal SW2. In addition, the control device 51 sets a first dead time period Td1 (see FIG. 7) between the high level period of the first PWM signal SW1 and the high level period of the second PWM signal SW2 so that the ON period of the first switching element 1W and the ON period of the second switching element 2W do not overlap.

[0046] The plurality of switches 8, the resonance inductor L1, the plurality of resonance capacitors 9, and the regenerative capacitor 15 are provided to perform zero-voltage soft switching for the plurality of first switching elements 1 and the plurality of second switching elements 2.

[0047] The switch 8U can pass the charging current flowing through the path of regenerative capacitor 15 - resonance inductor L1 - switch 8U - resonance capacitor 9U when the third switching element 6U is in the ON state and the fourth switching element 7U is in the OFF state. The charging current is the current that charges the resonance capacitor 9U. The switch 8U can pass the discharging current flowing through the path of resonance capacitor 9U - switch 8U - resonance inductor L1 - regenerative capacitor 15 when the third switching element 6U is in the OFF state and the fourth switching element 7U is in the ON state. The discharging current is the current that discharges the charge of the resonance capacitor 9U.

[0048] Switch 8V allows the charging current flowing through the path of regenerative capacitor 15 - resonant inductor L1 - switch 8V - resonant capacitor 9V to pass through when the third switching element 6V is ON and the fourth switching element 7V is OFF. The charging current is the current that charges the resonant capacitor 9V. Switch 8V allows the discharge current flowing through the path of resonant capacitor 9V - switch 8V - resonant inductor L1 - regenerative capacitor 15 to pass through when the third switching element 6V is OFF and the fourth switching element 7V is ON. The discharge current is the current that discharges the charge from the resonant capacitor 9V.

[0049] Switch 8W can pass the charging current flowing through the path of regenerative capacitor 15 - resonant inductor L1 - switch 8W - resonant capacitor 9W when the third switching element 6W is ON and the fourth switching element 7W is OFF. The charging current is the current that charges the resonant capacitor 9W. Switch 8W can pass the discharge current flowing through the path of resonant capacitor 9W - switch 8W - resonant inductor L1 - regenerative capacitor 15 when the third switching element 6W is OFF and the fourth switching element 7W is ON. The discharge current is the current that discharges the charge from the resonant capacitor 9W.

[0050] In this embodiment, the control device 51 sets the dead time period between the high-level period of the first PWM signal to the first switching element 1 and the high-level period of the second PWM signal to the second switching element 2 for each of the plurality of switching circuits 10 to a second dead time period Td2 (see Figures 4 to 7), which is determined by the first dead time period Td1 and a predetermined time. The second dead time period Td2 includes the first dead time period Td1. The second dead time period Td2 has a length equal to the length of the first dead time period Td1 plus a predetermined time (the sum of the length of the first dead time period Td1 and the length of the predetermined time). In other words, the control device 51 uses the second dead time period Td2, which is the first dead time period Td1 extended by a predetermined time, as the dead time period.

[0051] The first dead time period Td1 is a period set for each of the multiple switching circuits 10 between the high-level period of the first PWM signal to the first switching element 1 and the high-level period of the second PWM signal to the second switching element 2, during which both the first PWM signal to the first switching element 1 and the second PWM signal to the second switching element 2 are set to a low level so that the on periods of the first switching element 1 and the second switching element 2 do not overlap (there is no period in which both the first switching element 1 and the second switching element 2 are on). In this embodiment, for example, the length of the resonant half-period corresponding to each of the multiple switches 8 is designed according to the length of the first dead time period Td1 for each of the multiple switching circuits 10. The resonant half-period is half of the resonant period. The resonant period is the reciprocal of the resonant frequency of the resonant circuit including the switch 8, the resonant inductor L1, and one resonant capacitor 9. Therefore, if the inductance of the resonant inductor L1 is L and the capacitance of the resonant capacitor 9 is C, then the resonant half-period is π × (L・C) １／２ The length of the resonant half-period is set to be shorter than, for example, the length of the first dead time period Td1.

[0052] The length of the resonant half-period of a resonant circuit including a resonant inductor L1 and a resonant capacitor 9U is set to be shorter than the length of a first dead time period Td1 (see Figure 5) set between the high-level period of the first PWM signal SU1 and the high-level period of the second PWM signal SU2. The length of the resonant half-period of a resonant circuit including a resonant inductor L1 and a resonant capacitor 9V is set to be shorter than the length of a first dead time period Td1 (see Figure 6) set between the high-level period of the first PWM signal SV1 and the high-level period of the second PWM signal SV2. The length of the resonant half-period of a resonant circuit including a resonant inductor L1 and a resonant capacitor 9W is set to be shorter than the length of a first dead time period Td1 (see Figure 7) set between the high-level period of the first PWM signal SW1 and the high-level period of the second PWM signal SW2.

[0053] If the resonant period is Tres, then Tres / 2, which is the resonant half-period, is shorter than the first dead time period Td1. It is desirable that the end of the resonant half-period coincides with the end of the first dead time period Td1 for the switching circuit 10 corresponding to the switch 8. Figure 5 illustrates the first PWM signal SU1, the second PWM signal SU2, the output signal from the output terminal Q (see Figure 2) of the preceding multivibrator M11 (see Figure 2) of the logic circuit 521 (see Figure 2) of the signal generation circuit 52, the output signal from the inverting output terminal (represented as Q with an overline in Figures 2 and 5) of the subsequent multivibrator M12 (see Figure 2) of the logic circuit 521, the control signal SU6, the current iL1 flowing through the resonant inductor L1, the load current iU, and the voltage V1u across the first switching element 1U. Figure 5 also illustrates the first dead time period Td1, the additional time Tadu, and the second dead time period Td2. In the example in Figure 5, the start and end times of the second dead time period Td2 are time t10 and time t13, respectively. Figure 6 also illustrates the first PWM signal SV1, the second PWM signal SV2, the output signal from the output terminal Q of the preceding multivibrator M11 of the logic circuit 523 (see Figure 2) of the signal generation circuit 52, the output signal from the inverting output terminal (represented as Q with an overline in Figures 2 and 6) of the subsequent multivibrator M12 of the logic circuit 523, the control signal SV6, the current iL1 flowing through the resonant inductor L1, the load current iV, and the voltage V1v across the first switching element 1V. Furthermore, Figure 6 illustrates the first dead time period Td1, the additional time Tadv, and the second dead time period Td2. In the example in Figure 6, the start and end times of the second dead time period Td2 are time t20 and time t23, respectively.Figure 7 also illustrates the first PWM signal SW1, the second PWM signal SW2, the output signal from the output terminal Q of the preceding multivibrator M11 of the logic circuit 525 (see Figure 2) of the signal generation circuit 52, the output signal from the inverting output terminal (shown as Q with an overline in Figure 7) of the subsequent multivibrator M12 of the logic circuit 525, the control signal SW6, the current iL1 flowing through the resonant inductor L1, the load current iW, and the voltage V1w across the first switching element 1W. The first dead time period Td1, the additional time Tadw, and the second dead time period Td2 are also illustrated. In the example in Figure 7, the start and end times of the second dead time period Td2 are time points t30 and t33, respectively. In Figures 5 to 7, the voltage value of the DC power supply E1 is shown as Vd.

[0054] The length of the resonant half-period described above is shorter than the length of the first dead time period Td1, but it may also be 90% to 110% of the length of the first dead time period Td1.

[0055] The second dead time period Td2 is the first dead time period Td1 plus a predetermined time determined by the current value of the load current and the voltage value of the regenerative capacitor 15. In this embodiment, the predetermined time calculated by the control device 51 is, for example, an additional time determined by the current value of the load current, the voltage value of the regenerative capacitor 15, and the inductance of the resonant inductor L1. The current value of the load current is, for example, the detection result of the load current by a current sensor (analog detection value) or its signal processing value (A / D converted digital detection value), or an estimated value of the load current. The detection result of the load current or its signal processing value at this time is the detection value of the load current at the carrier cycle in which the additional time is added to the first dead time period Td1, or at the timing closest to that carrier cycle. In the control device 51, the detected value of the load current used in the calculation of a predetermined time is either the detected value of the load current from the current sensor (analog value) or the detected value (digital value) after A / D conversion of the detected value of the load current from the current sensor (analog value) by the second A / D conversion unit 514 (see Figure 1) described later. The estimated value of the load current at this time is the value obtained by estimating the load current in the carrier cycle in which the additional time is added to the first dead time period Td1. The inductance of the resonant inductor L1 is a value that is stored in advance in the control device 51. Hereinafter, the inductance of the resonant inductor L1 will be described as L. The voltage value of the regenerative capacitor 15 is the detected value of the voltage V15 of the regenerative capacitor 15 (potential V15 at the sixth terminal 154 of the regenerative capacitor 15). In the example of Figure 5, the additional time Tadu is a value obtained by the calculation Tadu = iU × (L / V15). In the example in Figure 6, the additional time Tadv is calculated using the formula Tadv = iV × (L / V15). In the example in Figure 7, the additional time Tadw is calculated using the formula Tadw = iW × (L / V15).

[0056] The predetermined time length, which is the same as the length of the additional time, is an ideal design example, and may be between 90% and 110% of the additional time.

[0057] In the power converter 100, a signal generation circuit 52, separate from the control device 51, controls multiple switches 8.

[0058] The signal generation circuit 52 generates control signals SU6, SU7, SV6, SV7, SW6, and SW7 to control the on / off state of the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W, respectively. The signal generation circuit 52 outputs these signals to the gate terminals of the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W.

[0059] The signal generation circuit 52 generates a control signal for each of the multiple switches 8 that has a high-level period corresponding to the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10.

[0060] In the signal generation circuit 52, the start time of the high-level period of the control signal generated for each of the multiple switches 8 is made to follow the start timing of the second dead time period Td2. In this disclosure, "making the start time of the high-level period of the control signal follow the start timing of the second dead time period Td2" means that the start time of the high-level period of the control signal (start time) is between the start time (start time) and the end time (end time) of the second dead time period Td2, and the time length between the start time of the high-level period of the control signal and the end time of the second dead time period Td2 is greater than or equal to the length of the first dead time period Td1.

[0061] In this embodiment, the signal generation circuit 52 delays the start of the high-level period of the control signal to each of the multiple switches 8 by a specified time T1 (see Figures 5 to 7) from the start of the second dead time period Td2, and delays the end of the high-level period of the control signal to each of the multiple switches 8 from the end of the second dead time period Td2. The length of the high-level period of the control signal to each of the multiple switches 8 (fixed length T2) is longer than the length of the first dead time period Td1.

[0062] The signal generation circuit 52 generates a control signal for each of the multiple switches 8 using either a first PWM signal to the first switching element 1 of the corresponding switching circuit 10 or a second PWM signal to the second switching element 2. In this embodiment, as shown in Figure 2, the signal generation circuit 52 has multiple logic circuits 521 to 526 and multiple gate drive circuits 531 to 536. In the signal generation circuit 52, the multiple logic circuits 521 to 526 correspond one-to-one with the multiple gate drive circuits 531 to 536.

[0063] The logic circuit 521 is configured to generate a control signal SU6 using the second PWM signal SU2. The logic circuit 521 detects the falling edge of the second PWM signal SU2 to the second switching element 2U and generates a control signal SU6 having a high-level period of fixed length T2.

[0064] The logic circuit 522 is configured to generate a control signal SU7 using a first PWM signal SU1. The logic circuit 522 detects the falling edge of the first PWM signal SU1 to the first switching element 1U and generates a control signal SU7 having a high-level period of fixed length T2.

[0065] The logic circuit 523 is configured to generate a control signal SV6 using the second PWM signal SV2. The logic circuit 523 detects the falling edge of the second PWM signal SV2 to the second switching element 2V and generates a control signal SV6 having a high-level period of fixed length T2.

[0066] The logic circuit 524 is configured to generate a control signal SV7 using a first PWM signal SV1. The logic circuit 524 detects the falling edge of the first PWM signal SV1 to the first switching element 1V and generates a control signal SV7 having a high-level period of fixed length T2.

[0067] The logic circuit 525 is configured to generate a control signal SW6 using the second PWM signal SW2. The logic circuit 525 detects the falling edge of the second PWM signal SW2 to the second switching element 2W and generates a control signal SW6 having a high-level period of fixed length T2.

[0068] The logic circuit 526 is configured to generate a control signal SW7 using a first PWM signal SW1. The logic circuit 526 detects the falling edge of the first PWM signal SW1 to the first switching element 1W and generates a control signal SW7 having a high-level period of fixed length T2.

[0069] Each of the logic circuits 521 to 526 includes, for example, two multivibrators M11 and M12 connected in series. Each of the two multivibrators M11 and M12 is an edge-triggered monostable multivibrator. In each of the logic circuits 521 to 526, the inverting output terminal of the preceding multivibrator M11 (represented by Q with an overline in Figure 2) is connected to the inverting trigger terminal of the following multivibrator M12. In each of the logic circuits 521 to 526, the specified time T1 is the length of the CR time constant determined by the capacitance of the capacitor C11 connected to the preceding multivibrator M11 and the resistance of the resistor R11. Furthermore, in each of the multiple logic circuits 521 to 526, the fixed length T2 is the length of the CR time constant, which is determined by the capacitance of the capacitor C12 connected to the subsequent multivibrator M12 and the resistance of the resistor R12.

[0070] The logic circuit 521 receives the second PWM signal SU2 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SU6 from the output terminal Q of the subsequent multivibrator M12. The control signal SU6 is supplied to the third switching element 6U via the gate drive circuit 531.

[0071] The logic circuit 522 receives the first PWM signal SU1 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SU7 from the output terminal Q of the subsequent multivibrator M12. The control signal SU7 is supplied to the fourth switching element 7U via the gate drive circuit 532.

[0072] The logic circuit 523 receives the second PWM signal SV2 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SV6 from the output terminal Q of the subsequent multivibrator M12. The control signal SV6 is supplied to the third switching element 6V via the gate drive circuit 533.

[0073] The logic circuit 524 receives the first PWM signal SV1 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SV7 from the output terminal Q of the subsequent multivibrator M12. The control signal SV7 is supplied to the fourth switching element 7V via the gate drive circuit 534.

[0074] The logic circuit 525 receives the second PWM signal SW2 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SW6 from the output terminal of the subsequent multivibrator M12. The control signal SW6 is supplied to the third switching element 6W via the gate drive circuit 535.

[0075] The logic circuit 526 receives the first PWM signal SW1 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SW7 from the output terminal of the subsequent multivibrator M12. The control signal SW7 is supplied to the fourth switching element 7W via the gate drive circuit 536.

[0076] (3) Operation of the power converter In the following, the current iL1 flowing through the resonant inductor L1 will be described as positive when flowing in the direction of the arrow in Figure 1, and negative when flowing in the opposite direction to the arrow in Figure 1. Furthermore, the load currents iU, iV, and iW flowing through the U-phase, V-phase, and W-phase terminals of the AC load RA1 will be described as positive when flowing in the direction of the arrow in Figure 1, and negative when flowing in the opposite direction to the arrow in Figure 1. Furthermore, the currents i9U, i9V, and i9W flowing through the resonant capacitors 9U, 9V, and 9W will be described as positive when flowing in the direction of the arrow in Figure 1, and negative when flowing in the opposite direction to the arrow in Figure 1. Therefore, in the discharge operation where the resonant capacitors 9U, 9V, and 9W are discharged, the polarity of the currents i9U, i9V, and i9W is positive, and in the charging operation where the resonant capacitors 9U, 9V, and 9W are charged, the polarity of the currents i9U, i9V, and i9W is negative. Furthermore, in the following explanation, the voltage value of the DC power supply E1 will be Vd (see Figures 5 to 8).

[0077] Furthermore, in the following, the switching element targeted for zero-voltage soft switching (first switching element 1 or second switching element 2) will also be referred to as the target switching element.

[0078] The following describes the basic operation of zero-voltage soft switching for each of the multiple first switching elements 1 and the multiple second switching elements 2, with reference to Figures 5 to 8. The basic operation is the operation when resonant currents do not flow simultaneously through two or more of the multiple switches 8 to the resonant inductor L1. After describing the basic operation, the operation when the control device 51 determines that two-phase resonant currents are flowing simultaneously will be described.

[0079] (3.1) Basic Operation In the power converter 100, when the target switching element is the first switching element 1 (hereinafter also referred to as the target first switching element 1), and the polarity of the load current flowing to the AC terminal 41 connected to the target first switching element 1 is positive, the signal generation circuit 52 turns on the third switching element 6 corresponding to the target first switching element 1. As a result, the power converter 100 causes the resonant inductor L1 and the resonant capacitor 9 connected to the target first switching element 1 to resonate, charging the resonant capacitor 9 from the regenerative capacitor 15, and setting the voltage across the target first switching element 1 to zero. As a result, the power converter 100 can achieve zero-voltage soft switching of the target first switching element 1.

[0080] Furthermore, in the power converter 100, if the target switching element is the second switching element 2 (hereinafter also referred to as the target second switching element 2), and the polarity of the load current flowing to the AC terminal 41 connected to the target second switching element 2 is negative, the signal generation circuit 52 turns on the fourth switching element 7 corresponding to the target second switching element 2. As a result, the power converter 100 causes the resonant capacitor 9 and the resonant inductor L1 connected to the target second switching element 2 to resonate, causing the resonant capacitor 9 to discharge and reducing the voltage across the target second switching element 2 to zero. As a result, the power converter 100 can achieve zero-voltage soft switching of the target second switching element 2.

[0081] When the control device 51 sets a second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time (additional time) to the first dead time period Td1 by shortening the high-level period of the second PWM signal to the second switching element 2.

[0082] For example, when the control device 51 sets a second dead time period Td2 for the switching circuit 10U, as shown in Figure 5, if the polarity of the load current iU is positive, it shortens the predetermined time (additional time Tadu) of the high-level period of the second PWM signal SU2 to the second switching element 2U, thereby adding a predetermined time (additional time Tadu) to the first dead time period Td1.

[0083] Figure 5 shows the case where the target switching element is the first switching element 1U of the switching circuit 10U, illustrating the first PWM signal SU1, the second PWM signal SU2, the output signal from the output terminal Q of the preceding multivibrator M11 of the logic circuit 521 (see Figure 2) of the signal generation circuit 52, the output signal from the inverting output terminal (shown as Q with an overline in Figure 5) of the subsequent multivibrator M12 of the logic circuit 521, the control signal SU6, the current iL1 flowing through the resonant inductor L1, the load current iU, and the voltage V1u across the first switching element 1U.

[0084] When the target switching element is the first switching element 1U, in the switching circuit 10U, the voltage V2u across the second switching element 2U (not shown in Figure 5) becomes Vd at time t13, when the second dead time period Td2 immediately preceding the high-level period of the first PWM signal SU1 ends, and the voltage V1u across the first switching element 1U becomes zero at time t13, when the second dead time period Td2 immediately preceding the high-level period of the first PWM signal SU1 ends. Therefore, when the first PWM signal SU1 changes from a low level to a high level at time t13, the first switching element 1U is soft-switched to zero voltage. In the example shown in Figure 5, the current iL1 flowing through the resonant inductor L1 begins to flow from time t11, when the high-level period of the control signal SU6 starts, reaches the same value as the load current iU at time t12, after a predetermined time (additional time Tadu) has elapsed from time t11, reaches the same value as the load current iU at time t13, when the second dead time period Td2 ends, and becomes zero at time t14, after a second predetermined time Tad2, which is the same length as the first predetermined time (additional time Tadu), has elapsed from time t13. In the signal generation circuit 52, at time t11, after a predetermined time T1 has elapsed from time t10, when the second PWM signal SU2 changes from a high level to a low level, the control signal SU6 changes from a low level to a high level, and at time t14, after a fixed length T2 has elapsed from time t11, the control signal SU6 changes from a high level to a low level. The current iL1 flowing between time point t12 and time point t13 is the resonant current (charging current of the resonant capacitor 9U) flowing from the regenerative capacitor 15 through the resonant inductor L1 to the resonant capacitor 9U.

[0085] In the following, the period T01 in which the absolute value of the current iL1 increases from zero to the absolute value of the load current (load current iU in the example of Figure 5) will be referred to as the first period T01, the period T02 in which the absolute value of the current iL1 is greater than the load current (load current iU in the example of Figure 5) will be referred to as the second period T02, and the period T03 in which the absolute value of the current iL1 decreases from the absolute value of the load current (load current iU in the example of Figure 5) to zero will be referred to as the third period T03. In the power converter 100, when the current iL1 increases from zero to iL1 = load current in the first period T01, the device transitions from the first period T01 to the second period T02, and when a resonant current flows in the second period T02 and the PWM signal to the target switching element changes from a low level to a high level, the device transitions from the second period T02 to the third period T03.

[0086] In Figure 5, the first period T01 is the period from time t11 to t12. The length of the first period T01 is the same as the first predetermined time (additional time Tadu). During the first period T01, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in the off state, and the third switching element 6U is in the on state. During the first period T01, the current iL1 flows through the path of regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U - AC terminal 41U. Also during the first period T01, the load current iU flows through the path of second diode 5, which is connected in antiparallel to the second switching element 2U - AC terminal 41U - AC load RA1.

[0087] In Figure 5, the second period T02 is the period from time t12 to t13. The length of the second period T02 is the same as the length of the resonant half-period. During the second period T02, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in the off state, and the third switching element 6U is in the on state. During the second period T02, the current iL1 flows through the path of regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U, and is divided into a current flowing to the AC terminal 41U and a current flowing to the resonant capacitor 9U (resonant current). During the second period T02, the resonant capacitor 9U is charged by the current flowing through it.

[0088] In Figure 5, the third period T03 is the period from time t13 to t14. The length of the third period T03 is the same as the second predetermined time Tad2. During the third period T03, from time t13 until the second predetermined time Tad2 has elapsed, the first switching element 1U and the third switching element 6U are each in the ON state, and the second switching element 2U and the fourth switching element 7U are each in the OFF state. After the second predetermined time Tad2 has elapsed from time t13, the first switching element 1U is in the ON state, and the second switching element 2U, the third switching element 6U, and the fourth switching element 7U are each in the OFF state. Therefore, during the third period T03, until the control signal SU6 changes from a high level to a low level, the current iL1 flows through the path of regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U - connection point 3U - AC terminal 41U. Furthermore, during the third period T03, after the control signal SU6 changes to a low level, the current iL1 flows through the path of regenerative capacitor 15 - resonant inductor L1 - third diode 13. This reduces the current iL1 to zero. Also during the third period T03, the load current iU flows through the path of first DC terminal 31 - first switching element 1U - AC terminal 41U - AC load RA1.

[0089] When the control device 51 sets a second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is negative, it adds a predetermined time (additional time Tadu) to the first dead time period Td1 by shortening the high-level period of the first PWM signal to the first switching element 1.

[0090] For example, when the control device 51 sets a second dead time period Td2 for the switching circuit 10U, as shown in Figure 8, if the polarity of the load current iU is negative, it adds a predetermined time (additional time Tadu) to the first dead time period Td1 by shortening a predetermined time (additional time Tadu) of the high-level period of the first PWM signal SU1 to the first switching element 1U.

[0091] Figure 8 shows the case where the target switching element is the second switching element 2U of the switching circuit 10U, illustrating the first PWM signal SU1, the second PWM signal SU2, the output signal from the output terminal Q of the preceding multivibrator M11 of the logic circuit 522 (see Figure 2) of the signal generation circuit 52, the output signal from the inverting output terminal (shown as Q with an overline in Figure 8) of the subsequent multivibrator M12 of the logic circuit 522, the control signal SU7, the current iL1 flowing through the resonant inductor L1, the load current iU, and the voltage V2u across the second switching element 2U.

[0092] When the target switching element is the second switching element 2U, in the switching circuit 10U, the voltage V1u across the first switching element 1U (not shown in Figure 8) becomes Vd at time t43, when the second dead time period Td2 ends immediately before the high-level period of the second PWM signal SU2, and the voltage V2u across the second switching element 2U becomes zero at time t43, when the second dead time period Td2 ends. Therefore, when the second PWM signal SU2 changes from a low level to a high level at time t43, the second switching element 2U is soft-switched to zero voltage. In the example shown in Figure 8, the current iL1 flowing through the resonant inductor L1 begins to flow from time t41, when the high-level period of the control signal SU7 starts, reaches the same value as the load current iU at time t42, after an additional time Tadu has elapsed from time t41, reaches the same value as the load current iU at time t43, when the second dead time period Td2 ends, and becomes zero at time t44, after a second predetermined time Tad2, which is the same length as the first predetermined time, has elapsed from time t43. In the signal generation circuit 52, the control signal SU7 changes from a low level to a high level when the first PWM signal SU1 changes from a high level to a low level. The current iL1 flowing between time t42 and time t43 is the resonant current (discharge current of the resonant capacitor 9U) flowing from the resonant capacitor 9U to the resonant inductor L1.

[0093] In Figure 8, the first period T01 is the period from time t41 to t42. During the first period T01, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in the off state, and the fourth switching element 7U is in the on state. During the first period T01, the current iL1 flows through the path from the AC terminal 41U - diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15. Also during the first period T01, the load current iU flows through the path from the AC load RA1 - AC terminal 41U - first diode 4 which is connected in antiparallel to the first switching element 1U.

[0094] In Figure 8, the second period T02 is the period from time t42 to t43. During the second period T02, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in the off state, and the fourth switching element 7U is in the on state. During the second period T02, the current iL1 flowing through the resonant inductor L1 is the combined current of the current flowing from the AC terminal 41U through the diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15 and the current flowing from the resonant capacitor 9U through the diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15 (resonant current). During the second period T02, the resonant capacitor 9U is discharged.

[0095] In Figure 8, the third period T03 is the period from time t43 to t44. During the third period T03, until the second predetermined time Tad2 has elapsed from time t43, the second switching element 2U and the fourth switching element 7U are each in the ON state, and the first switching element 1U and the third switching element 6U are each in the OFF state. After the second predetermined time Tad2 has elapsed from time t43, the second switching element 2U is turned ON, and the first switching element 1U, the third switching element 6U, and the fourth switching element 7U are each turned OFF. Therefore, during the third period T03, until the control signal SU7 changes from a high level to a low level, the current iL1 flows through the path of AC terminal 41U - connection point 3U - diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15. Furthermore, during the third period T03, after the control signal SU7 changes to a low level, the current iL1 flows through the path of the fourth diode 14 - resonant inductor L1 - regenerative capacitor 15. As a result, the absolute value of the current iL1 is reduced to zero. Also during the third period T03, the load current iU flows through the path of the AC load RA1 - AC terminal 41U - second switching element 2U - second DC terminal 32.

[0096] The above describes an example of when the control device 51 sets the second dead time period Td2 for the switching circuit 10U, but the same applies when the control device 51 sets the second dead time period Td2 for the switching circuit 10V and the switching circuit 10W.

[0097] (3.2) The current protection operation control device 51 stops the operation of the power conversion circuit 11 when the input current detected value by the current detection unit 16 exceeds the current protection threshold Ith.

[0098] The control device 51 includes, for example, a first A / D conversion unit 513 that performs A / D conversion on the input current detection value (analog value) of the current detection unit 16. By comparing the input current detection value (digital value) after A / D conversion with the digital value of the current protection threshold Ith, the control device 51 determines whether the input current detection value from the current detection unit 16 exceeds the current protection threshold Ith.

[0099] In the control device 51, the current protection threshold Ith during basic operation is set as the first current protection threshold I1 (see Figure 4). The first current protection threshold I1 is, for example, 5 [A].

[0100] The control device 51 stops the operation of the power conversion circuit 11 when it determines that the input current detection value exceeds the current protection threshold Ith. "Stopping the operation of the power conversion circuit 11" means that the control device 51 sets each of the multiple first PWM signals SU1, SV1, SW1 and the multiple second PWM signals SU2, SV2, SW2 to a low level, or stops outputting the multiple first PWM signals SU1, SV1, SW1 and the multiple second PWM signals SU2, SV2, SW2.

[0101] (3.3) In the operating power converter 100 when two-phase resonant currents flow simultaneously, the duty cycle command values ​​of two of the three-phase duty cycle command values ​​du, dv, and dw approach each other at electrical angles of 60°, and the time difference between the start of the ON period of each of the two-phase switches 8 becomes shorter during one cycle of the carrier signal CA1, and there is a possibility that the resonant currents flowing through the resonant capacitors 9 of the two switching circuits 10 corresponding to the two-phase duty cycle command values ​​may flow simultaneously in the resonant inductor L1. In region A1 of Figure 3, the duty cycle command values ​​du and dv are each 0.75 or close to 0.75. In region A2 of Figure 3, the duty cycle command values ​​dv and dw are each 0.25 or close to 0.25.

[0102] For example, in the example shown in Figure 3, if the duty cycle command values ​​du and dv are both 0.75 or close to 0.75, the time difference between the start of the high-level period of the control signal SU6 and the start of the high-level period of the control signal SV6 becomes shorter, and it is possible that the resonant current passing through the resonant capacitor 9U (hereinafter also referred to as the "U-phase resonant current") and the resonant current passing through the resonant capacitor 9V (hereinafter also referred to as the "V-phase resonant current") will flow through the resonant inductor L1 simultaneously. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the U-phase resonant current and the V-phase resonant current is positive.

[0103] Furthermore, in the example shown in Figure 3, if the duty cycle command values ​​dv and dw are both 0.75 or close to 0.75, the time difference between the start of the high-level period of the control signal SV6 and the start of the high-level period of the control signal SW6 becomes shorter, and it is possible that the resonant current of the V phase and the resonant current passing through the resonant capacitor 9W (hereinafter also referred to as the "W phase resonant current") will flow through the resonant inductor L1 simultaneously. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the V phase resonant current and the W phase resonant current is positive.

[0104] Furthermore, in the example shown in Figure 3, if the duty cycle command values ​​dw and du are both 0.75 or close to 0.75, the time difference between the start of the high-level period of the control signal SW6 and the start of the high-level period of the control signal SU6 becomes shorter, and it is possible that the W-phase resonant current and the U-phase resonant current will flow simultaneously through the resonant inductor L1. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the W-phase resonant current and the U-phase resonant current is positive.

[0105] Furthermore, in the example shown in Figure 3, if the duty cycle command values ​​du and dv are both 0.25 or close to 0.25, the time difference between the start of the high-level period of the control signal SU7 and the start of the high-level period of the control signal SV7 becomes shorter, and it is possible that the resonant current of the U-phase and the resonant current of the V-phase will flow simultaneously through the resonant inductor L1. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the resonant current of the U-phase and the resonant current of the V-phase is negative.

[0106] Furthermore, in the example shown in Figure 3, if the duty cycle command values ​​dv and dw are both 0.25 or close to 0.25, the time difference between the start of the high-level period of the control signal SV7 and the start of the high-level period of the control signal SW7 becomes shorter, and it is possible that the resonant current of the V-phase and the resonant current of the W-phase will flow simultaneously through the resonant inductor L1. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the resonant current of the V-phase and the resonant current of the W-phase is negative.

[0107] Furthermore, in the example shown in Figure 3, if the duty cycle command values ​​dw and du are both 0.25 or close to 0.25, the time difference between the start of the high-level period of the control signal SW7 and the start of the high-level period of the control signal SU7 becomes shorter, and it is possible that the resonant current passing through the resonant capacitor 9W and the resonant current passing through the resonant capacitor 9U will flow through the resonant inductor L1 simultaneously. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the resonant current passing through the resonant capacitor 9W and the resonant current passing through the resonant capacitor 9U is negative.

[0108] In the power converter 100, when two-phase current flows simultaneously through the resonant inductor L1, current flows simultaneously through each of the two resonant capacitors 9. In the power converter 100, when two-phase resonant current flows simultaneously through the resonant inductor L1, the resonant frequency of the resonant circuit including the resonant inductor L1 changes compared to when one-phase current flows through the resonant inductor L1. As a result, the resonant capacitors 9 are not sufficiently charged, and for example, as shown in Figure 4, the input current Iin may temporarily become large.

[0109] The control device 51 determines, at each control cycle, whether two-phase resonant currents corresponding to two of the multiple switching circuits 10 will flow simultaneously through the resonant inductor L1 in the next control cycle. If it determines that two-phase resonant currents will flow simultaneously, it increases the current protection threshold Ith. In this embodiment, the control cycle is the same as one cycle of the carrier signal CA1.

[0110] "When it is determined that two-phase resonant currents flow simultaneously" means when the control device 51 has previously estimated that resonant currents corresponding to each of the two switching circuits 10 will flow simultaneously through the resonant inductor L1. For the sake of explanation, below, "two-phase resonant currents corresponding to each of the two switching circuits 10 flow simultaneously through the resonant inductor L1" may also be referred to as "two-phase resonant currents flowing simultaneously through the resonant inductor L1."

[0111] The control device 51 first determines whether the resonant currents of two of the U-phase, V-phase, and W-phase overlap. If it determines in advance that the resonant currents of two phases flow simultaneously through the resonant inductor L1, it sets the current protection threshold Ith to a second current protection threshold I2 (see Figure 4), which is greater than the first current protection threshold I1 (see Figure 4). In this embodiment, the first current protection threshold I1 is set to 5 [A] and the second current protection threshold I2 is set to 8 [A], but the first current protection threshold I1 is not limited to 5 [A], and the second current protection threshold is not limited to 8 [A]. Furthermore, if the control device 51 determines that the resonant currents of two phases do not flow simultaneously after setting the current protection threshold Ith to the second current protection threshold I2, it sets the current protection threshold Ith to the first current protection threshold I1. In the example shown in Figure 4, if the control device 51 determines in the nth control period (where n is a natural number) that the resonant current of the U phase and the resonant current of the V phase flow simultaneously in the (n+1)th control period, it sets the current protection threshold Ith in the (n+1)th control period as the second current protection threshold I2. If the control device 51 determines in the (n+1)th control period that the resonant current of the U phase and the resonant current of the V phase do not flow simultaneously in the (n+2)th control period, it sets the current protection threshold Ith in the (n+2)th control period as the first current protection threshold I1.

[0112] Furthermore, if the control device 51 determines that two-phase resonant currents corresponding to two of the multiple switching circuits 10 are flowing simultaneously through the resonant inductor L1, it invalidates the detected values ​​of the two-phase load currents corresponding to the two switching circuits 10 (invalidates the detected values ​​of the two-phase load currents). The control device 51 includes a second A / D conversion unit 514 that performs A / D conversion on the detected values ​​(analog values) of each current sensor 18a, 18b, and 18c. "Invalidating the detected values ​​of the two-phase load currents" means that the second A / D conversion unit 514 does not perform A / D conversion on the detected values ​​(analog values) of the two-phase load currents, or that the second A / D conversion unit 514 performs A / D conversion on the two-phase load currents and invalidates the detected values ​​(digital values) after A / D conversion. In the example in Figure 4, if it is determined that the U-phase resonant current and the V-phase resonant current flow simultaneously in the (n+1)th control cycle during the nth (n is a natural number) control cycle, the detected values ​​of the two-phase load currents iU and iV are invalidated. If it is determined that the U-phase resonant current and the V-phase resonant current do not flow simultaneously in the (n+2)th control cycle during the (n+1)th control cycle, the detected values ​​of the two-phase load currents iU and iV are validated.

[0113] In this embodiment, the control device 51 determines that the resonant currents of two phases overlap when the difference between the duty cycle command values ​​of any two of the multiple phases (du, dv, dw) is less than a predetermined threshold Δdth. For example, the control device 51 compares the predetermined duty cycle command values ​​(du, dv, dw) of multiple phases. Here, the control device 51 calculates the difference Δd (Δduv = |du - dv|) between the duty cycle command value (du) of the U phase and the duty cycle command value (dv) of the V phase, and determines that the resonant currents of the U phase and the V phase overlap when Δduv is less than a predetermined threshold Δdth. In this embodiment, the predetermined threshold Δdth is set such that when Δduv is less than a predetermined threshold Δdth, the resonant current of the U phase and the resonant current of the V phase overlap in the resonant inductor L1, and when Δduv is greater than or equal to the predetermined threshold Δdth, the resonant current of the U phase and the resonant current of the V phase do not overlap in the resonant inductor L1. Furthermore, the control device 51 calculates the difference Δd (Δdvw = |dv - dw|) between the duty cycle command value dv of the V phase and the duty cycle command value dw of the W phase, and determines that the resonant current of the V phase and the resonant current of the W phase overlap when Δdvw is less than the predetermined threshold Δdth. In this embodiment, the predetermined threshold Δdth is set such that when Δdvw is less than a predetermined threshold Δdth, the resonant current of the V phase and the resonant current of the W phase overlap in the resonant inductor L1, and when Δdvw is greater than or equal to the predetermined threshold Δdth, the resonant current of the V phase and the resonant current of the W phase do not overlap in the resonant inductor L1. Furthermore, the control device 51 calculates the difference Δd (Δdwu = |dw - du|) between the duty cycle command value dw of the W phase and the duty cycle command value du of the U phase, and determines that the resonant current of the W phase and the resonant current of the U phase overlap when Δdwu is less than the predetermined threshold Δdth. In this embodiment, the case where the W-phase resonant current and the U-phase resonant current overlap in the resonant inductor L1 when Δdwu is less than a predetermined threshold Δdth is included, and the predetermined threshold Δdth is set so that the W-phase resonant current and the U-phase resonant current do not overlap in the resonant inductor L1 when Δdwu is equal to or greater than the predetermined threshold Δdth.

[0114] The operation example of the control device 51 will be explained below based on the flowchart shown in Figure 9. Figure 9 is a flowchart of the main function related to current control in the overall operation flowchart of the control device 51 (not shown).

[0115] The control device 51 sets the current protection threshold Ith to the first current protection threshold I1 (step S11).

[0116] After step S11, the control device 51 determines whether the resonant current of the U phase and the resonant current of the V phase overlap (flow simultaneously) (step S12).

[0117] If the control device 51 determines in step S12 that the resonant current of the U phase and the resonant current of the V phase overlap (step S12: Yes), it increases the current protection threshold Ith in the next control cycle (one cycle of the carrier signal CA1) from the first current protection threshold I1 to the second current protection threshold I2 (step S13).

[0118] In this embodiment, after step S13, the control device 51 invalidates the detected values ​​of the two-phase load current (step S14), and returns to the flowchart of the overall operation of the control device 51.

[0119] If the control device 51 determines in step S12 that the resonant current of the U phase and the resonant current of the V phase do not overlap (step S12: No), it determines whether the resonant current of the V phase and the resonant current of the W phase overlap (flow simultaneously) (step S15).

[0120] If the control device 51 determines in step S15 that the resonant current of the V phase and the resonant current of the W phase overlap (step S15: Yes), it increases the current protection threshold Ith for the next control cycle (one cycle of the carrier signal CA1) from the first current protection threshold I1 to the second current protection threshold I2 (step S13).

[0121] In this embodiment, after step S13, the control device 51 invalidates the detected values ​​of the two-phase load current (step S14), and returns to the flowchart of the overall operation of the control device 51.

[0122] If the control device 51 determines in step S15 that the resonant current of the V phase and the resonant current of the W phase do not overlap (step S15: No), it determines whether the resonant current of the W phase and the resonant current of the U phase overlap (flow simultaneously) (step S16).

[0123] If the control device 51 determines in step S16 that the resonant current of the W phase and the resonant current of the U phase overlap (step S16: Yes), it increases the current protection threshold Ith in the next control cycle (one cycle of the carrier signal CA1) from the first current protection threshold I1 to the second current protection threshold I2 (step S13).

[0124] In this embodiment, after step S13, the control device 51 invalidates the detected values ​​of the two-phase load current (step S14), and returns to the flowchart of the overall operation of the control device 51.

[0125] If the control device 51 determines in step S16 that the resonant current of the W phase and the resonant current of the U phase do not overlap (step S16: No), it returns to the flowchart of the overall operation of the control device 51.

[0126] Figure 4 illustrates the timing chart for two control cycles, showing the state of the first PWM signal SU1, the second PWM signal SU2, the first PWM signal SV1, the second PWM signal SV2, the control signals SU6, SU7, SV6, SV7, the current iL1, the current protection threshold Ith, the input current Iin, and the load current detection state. Figure 4 shows an example where, in the (n-1)th control cycle, it is determined that the two-phase resonant currents do not overlap in the nth control cycle, and an example where, in the nth control cycle, it is determined that the two-phase resonant currents overlap in the (n+1)th control cycle. In Figure 4, the U-phase resonant current and the V-phase resonant current, which partially overlap each other in the (n+1)th control cycle, are shown separately. In Figure 4, the nth control cycle is labeled "nth cycle," and the (n+1)th control cycle is labeled "(n+1)th cycle." In Figure 4, the "Normal Period" for "Overlap Judgment" means that when it is determined that the two-phase resonant currents do not overlap in the (n-1)th control cycle, it is determined that the two-phase resonant currents do not overlap in the nth control cycle. The "Overlap Judgment Period" for "Overlap Judgment" means that when it is determined that the two-phase resonant currents overlap in the nth control cycle, it is determined that the two-phase resonant currents overlap in the (n+1)th control cycle. The "Enabled" status for "Load Current Detection State" means that when it is determined in the (n-1)th control cycle that the U-phase resonant current and the V-phase resonant current do not flow simultaneously in the nth control cycle, the detected values ​​of the two-phase load currents iU and iV are enabled in the nth control cycle. The "Disabled" status means that when it is determined in the nth control cycle that the U-phase resonant current and the V-phase resonant current flow simultaneously in the (n+1)th control cycle, the detected values ​​of the two-phase load currents iU and iV are disabled in the (n+1)th control cycle.

[0127] Figure 10 shows the timing chart of the first PWM signal SU1, second PWM signal SU2, first PWM signal SV1, second PWM signal SV2, control signal SU6, control signal SV6, U-phase load current iU, V-phase load current iV, and current iL1 when the control device 51 determines that the U-phase resonant current and the V-phase resonant current overlap when the polarity of the load current iU and the V-phase load current iV are both positive. In Figure 10, the output signal from the output terminal Q of the preceding multivibrator M11 of the logic circuit 521 (see Figure 2) is shown in the third row from the top, and the output signal from the inverting output terminal (shown as Q with an overline in Figure 10) of the subsequent multivibrator M12 of the logic circuit 521 is shown in the fourth row from the top. Furthermore, in Figure 10, the output signal from the output terminal Q of the preceding multivibrator M11 of the logic circuit 523 (see Figure 2) is shown in the eighth row from the top, and the output signal from the inverting output terminal (represented as Q with an overline in Figure 10) of the subsequent multivibrator M12 of the logic circuit 523 is shown in the ninth row from the top.

[0128] In this embodiment, if the control device 51 determines in the nth control cycle that the resonant current of the U phase and the resonant current of the V phase will overlap in the next (n+1)th control cycle, it sets the current protection threshold Ith in the (n+1)th control cycle to the second current protection threshold I2.

[0129] Figure 12 shows the timing chart of the first PWM signal SU1, second PWM signal SU2, first PWM signal SV1, second PWM signal SV2, control signal SU7, control signal SV7, U-phase load current iU, V-phase load current iV, and current iL1 when the control device 51 determines that the U-phase resonant current and the V-phase resonant current overlap when the polarity of the load current iU and the V-phase load current iV are negative. In Figure 11, the output signal from the output terminal Q of the preceding multivibrator M11 of the logic circuit 522 (see Figure 2) is shown in the third row from the top, and the output signal from the inverting output terminal (represented as Q with an overline in Figure 11) of the subsequent multivibrator M12 of the logic circuit 522 is shown in the fourth row from the top. Furthermore, in Figure 11, the output signal from the output terminal Q of the preceding multivibrator M11 of the logic circuit 524 (see Figure 2) is shown in the eighth row from the top, and the output signal from the inverting output terminal (represented as Q with an overline in Figure 11) of the subsequent multivibrator M12 of the logic circuit 524 is shown in the ninth row from the top.

[0130] In this embodiment, if the control device 51 determines in the nth control cycle that the resonant current of the U phase and the resonant current of the V phase will overlap in the next (n+1)th control cycle, it sets the current protection threshold Ith in the (n+1)th control cycle to the second current protection threshold I2.

[0131] (4) Advantages In the power conversion device 100 according to Embodiment 1, the current detection unit 16 detects the input current Iin flowing to the power conversion circuit 11. The control device 51 generates a plurality of first PWM signals SU1, SV1, SW1 for controlling a plurality of first switching elements 1, and a plurality of second PWM signals SU2, SV2, SW2 for controlling a plurality of second switching elements 2, based on a plurality of duty cycle command values ​​of a plurality of phases corresponding one-to-one to a plurality of switching circuits 10. The signal generation circuit 52 provides control signals SU6, SU7, SV6, SV7, SW6, SW7 to each of the plurality of switches 8, which change potential between high level and low level. The control device 51 sets a second dead time period Td2 for each of the plurality of switching circuits 10, which is a predetermined first dead time period Td1 plus a predetermined time, so that the ON periods of the first switching element 1 and the second switching element 2 do not overlap between the high-level period of the first PWM signal to the first switching element 1 and the high-level period of the second PWM signal to the second switching element 2. The predetermined time is determined according to the current value of the load current, the inductance of the resonant inductor L1 and the voltage value of the regenerative capacitor 15. The signal generation circuit 52 generates a control signal for each of the plurality of switches 8 that has a high-level period corresponding to the second dead time period Td2 for the corresponding switching circuit 10 among the plurality of switching circuits 10. The control device 51 generates a plurality of first PWM signals SU1, SV1, SW1 and a plurality of second PWM signals SU2, SV2, SW2 in the nth control cycle, where n is a natural number. The control device 51 stops the operation of the power conversion circuit 11 if the input current detected by the current detection unit 16 exceeds the current protection threshold Ith. If the control device 51 determines during the nth control cycle that two-phase resonant currents corresponding to two of the multiple switching circuits 10 flow simultaneously through the resonant inductor L1 during the (n+1)th control cycle, it increases the current protection threshold Ith during the (n+1)th control cycle.

[0132] With the above configuration, zero-voltage soft switching can be performed without the control device 51 directly controlling the multiple switches 8 for zero-voltage soft switching, and current distortion can be reduced. More specifically, since the signal generation circuit 52 generates control signals SU6, SU7, SV6, SV7, SW6, SW7 for controlling the multiple switches 8 for zero-voltage soft switching, the control device 51 does not need to generate control signals to directly control the multiple switches 8 for zero-voltage soft switching, and zero-voltage soft switching of each of the multiple first switching elements 1 and the multiple second switching elements 2 can be realized without the control device 51 directly controlling the multiple switches 8. Furthermore, with the above configuration, since the control device 51 does not need to generate and output multiple control signals SU6, SU7, SV6, SV7, SW6, SW7, the control device 51 can be simplified, for example, an increase in the number of control ports of the microcomputer included in the control device 51 can be suppressed, and the size of the control device 51 can be suppressed. Furthermore, according to the above configuration, if the control device 51 determines during the nth control cycle that two-phase resonant currents corresponding to two of the multiple switching circuits 10 flow simultaneously through the resonant inductor L1 during the (n+1)th control cycle, it increases the current protection threshold Ith during the (n+1)th control cycle, but does not shift the on-periods of the first and second switching elements in one of the switching circuits. This makes it possible to reduce current distortion while preventing the operation of the power conversion circuit 11 from stopping. Also, according to the above configuration, since the shift control in the control device of the power conversion device disclosed in Patent Document 1 is not performed, it is possible to reduce the processing time for each control cycle in the control device 51. "Shift control" means a control in which the control device shifts the on-periods of the first and second switching elements in one of the two switching circuits.

[0133] Furthermore, in the power conversion device 100 according to Embodiment 1, if the control device 51 determines during the nth control cycle that two-phase resonant currents corresponding to two of the multiple switching circuits 10 flow simultaneously through the resonant inductor L1 during the (n+1)th control cycle, it invalidates the detected values ​​of the two-phase load currents corresponding to the two switching circuits 10 during the (n+1)th control cycle.

[0134] With the above configuration, it becomes possible to further reduce the processing time for each control cycle in the control device 51.

[0135] Furthermore, in the power conversion device 100 according to Embodiment 1, when the control device 51 sets a second dead time period Td2 for each of the plurality of switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time (additional time) to the first dead time period Td1 by shortening the high-level period of the second PWM signal to the second switching element 2. Also, when the control device 51 sets a second dead time period Td2 for each of the plurality of switching circuits 10, if the polarity of the load current is negative, it adds a predetermined time (additional time) to the first dead time period Td1 by shortening the high-level period of the first PWM signal to the first switching element 1.

[0136] With the above configuration, it becomes possible to achieve zero-voltage soft switching while further reducing dead time loss and dead time error.

[0137] (5) Modified Examples (5.1) Modified Example 1 In the power conversion device 100 according to Modified Example 1 of Embodiment 1, when the control device 51 sets a second dead time period Td2 for each of the plurality of switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time to the first dead time period Td1 by advancing the end time of the high-level period of the second PWM signal to the second switching element 2 and delaying the start time of the high-level period of the first PWM signal to the first switching element 1. If the polarity of the load current is negative, it adds a predetermined time to the first dead time period Td1 by advancing the end time of the high-level period of the first PWM signal to the first switching element 1 and delaying the start time of the high-level period of the second PWM signal to the second switching element 2.

[0138] The power converter 100 according to Modification 1 has the same advantages as the power converter 100 according to Embodiment 1.

[0139] (5.2) Modification 2 In the power conversion device 100 according to Modification 2 of Embodiment 1, when the control device 51 sets a second dead time period Td2 for each of the plurality of switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time to the first dead time period Td1 by shortening the high-level period of the first PWM signal to the first switching element 1, and if the polarity of the load current is negative, it adds a predetermined time to the first dead time period Td1 by shortening the high-level period of the second PWM signal to the second switching element 2.

[0140] The power converter 100 according to the modified example 2 has the same advantages as the power converter 100 according to embodiment 1.

[0141] (Embodiment 2) Hereinafter, the power converter 100A according to Embodiment 2 will be described with reference to Figure 12.

[0142] (1) The power converter 100A according to Embodiment 1 differs from the power converter 100 according to Embodiment 1 (see Figures 1 and 2) in that it is equipped with a signal generation circuit 52A instead of the signal generation circuit 52 of the power converter 100 according to Embodiment 1, as shown in Figure 12. With respect to the power converter 100A according to Embodiment 2, the same reference numerals are used for components that are the same as those in the power converter 100 according to Embodiment 1, and their descriptions are omitted.

[0143] In this embodiment, the signal generation circuit 52A includes a PLD (Programmable Logic Device) 520 and a plurality of gate drive circuits 531 to 536 (see Figure 2). The signal generation circuit 52A is equipped with the PLD 520 instead of the plurality of logic circuits 521 to 526 (see Figure 2) of the signal generation circuit 52.

[0144] The signal generation circuit 52A, like the signal generation circuit 52, provides each of the multiple switches 8 with a control signal whose potential changes between high and low levels. For each of the multiple switches 8, the signal generation circuit 52A generates a control signal that has a high-level period corresponding to the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10. The operation of the signal generation circuit 52A is the same as the relationship between the input and output of the signal generation circuit 52, in terms of the relationship between the input and output of the signal generation circuit 52. The signal generation circuit 52A generates control signals SU6, SU7, SV6, SV7, SW6, SW7, similar to the control signals SU6, SU7, SV6, SV7, SW6, SW7 generated by the signal generation circuit 52.

[0145] Similar to the signal generation circuit 52, the signal generation circuit 52A adjusts the start time of the high-level period of the control signal generated for each of the multiple switches 8 to coincide with the start timing of the second dead time period Td2.

[0146] In the signal generation circuit 52A, the PLD 520 generates a control signal for each of the multiple switches 8 using either the first PWM signal to the first switching element 1 of the corresponding switching circuit 10 and the second PWM signal to the second switching element 2. For each of the multiple switches 8, the PLD 520 generates a control signal having a high-level period corresponding to the second dead time period Td2 for the corresponding switching circuit 10.

[0147] In the signal generation circuit 52A, the PLD 520 causes the start time of the high-level period of the control signal generated for each of the multiple switches 8 to follow the start timing of the second dead time period Td2.

[0148] (2) Advantages The power converter 100A according to Embodiment 2, like the power converter 100 according to Embodiment 1, is capable of performing zero-voltage soft switching without the control device 51 directly controlling the multiple switches 8 for zero-voltage soft switching, and is also capable of reducing current distortion.

[0149] (Other Modifications) Embodiments 1 and 2 described above are merely one of many embodiments of the present disclosure. Embodiments 1 and 2 described above can be modified in various ways depending on the design, etc., as long as the objectives of the present disclosure are achieved.

[0150] In the power converter 100, the time difference at the start of the high-level period of the two first PWM signals corresponding to the first switching element 1 of each of the two phase switching circuits 10 may be used as a criterion for determining whether or not two-phase resonant currents flow simultaneously. For example, the control device 51 may determine (estimate) that if the time difference ΔTuv between the start of the high-level period of the first PWM signal SU1 and the start of the high-level period of the first PWM signal SV1 is greater than or equal to a threshold, the resonant current of the U phase and the resonant current of the V phase do not overlap in the resonant inductor L1, and if the time difference ΔTuv is less than the threshold, the resonant current of the U phase and the resonant current of the V phase overlap. The threshold may be set to, for example, the value of Tres / 2. The threshold is not limited to the value of Tres / 2. For example, considering errors in the value of Tres / 2, the threshold may be set to a value even larger than Tres / 2. Furthermore, the method for calculating the time difference used by the control device 51 to determine whether or not two-phase resonant currents flow simultaneously is not limited to the above example. For example, the control device 51 may use the time difference between the end of the high-level periods of the two second PWM signals as the time difference used to determine whether or not two-phase resonant currents flow simultaneously. For example, the time difference ΔTuv used to determine whether or not the U-phase resonant current and the V-phase resonant current flow simultaneously may be the time difference between the end of the high-level period of the second PWM signal SU2 and the end of the high-level period of the second PWM signal SV2.

[0151] Furthermore, the carrier signal CA1 is a carrier signal used to generate multiple first PWM signals SU1, SV1, SW1 and multiple second PWM signals SU2, SV2, SW2, but it is not limited to a triangular waveform; a sawtooth waveform carrier signal is also acceptable.

[0152] The signal generation circuits 52 and 52A may be configured to synchronize the start time of the high-level period of the control signal to each of the multiple switches 8 with the start time of the second dead time period Td2.

[0153] Furthermore, each of the multiple first switching elements 1 and the multiple second switching elements 2 is not limited to IGBTs, but may be, for example, a MOSFET. In this case, each of the multiple first diodes 4 may be replaced with a parasitic diode of the MOSFET constituting the corresponding first switching element 1 among the multiple first switching elements 1. Similarly, each of the multiple second diodes 5 may be replaced with a parasitic diode of the MOSFET constituting the corresponding second switching element 2 among the multiple second switching elements 2. The MOSFETs are, for example, Si-based MOSFETs or SiC-based MOSFETs. Each of the multiple first switching elements 1 and the multiple second switching elements 2 may be, for example, a bipolar transistor or a GaN-based GIT (Gate Injection Transistor).

[0154] Furthermore, in power converters 100 and 100A, if the capacitance of each of the multiple resonant capacitors 9 is relatively small, instead of externally mounting multiple resonant capacitors 9, the parasitic capacitance between the ends of the multiple second switching elements 2 may serve as the multiple resonant capacitors 9.

[0155] Furthermore, the length of the resonant half-period is not limited to being shorter than the length of the first dead time period Td1; it may also be set to be the same length as the resonant half-period.

[0156] Furthermore, in the power conversion devices 100 and 100A according to Embodiment 1, the diodes 61 and 71 are not limited to being externally attached to the third switching element 6 and the fourth switching element 7, respectively, but may also be elements built into a single chip.

[0157] Furthermore, the power converters 100 and 100A may also include a second regenerative capacitor connected between the sixth terminal 154 of the regenerative capacitor 15 (hereinafter also referred to as the first regenerative capacitor 15) and the first DC terminal 31. The capacitance of the second regenerative capacitor is the same as the capacitance of the first regenerative capacitor 15. The statement "the capacitance of the second regenerative capacitor is the same as the capacitance of the first regenerative capacitor 15" is not limited to the case where the capacitance of the second regenerative capacitor perfectly matches the capacitance of the first regenerative capacitor 15, but is sufficient if the capacitance of the second regenerative capacitor is within the range of 90% to 110% of the capacitance of the first regenerative capacitor 15.

[0158] In each of the multiple switches 8, the second main terminal (emitter terminal) of the third switching element 6 is connected to the second main terminal (emitter terminal) of the fourth switching element 7, the first main terminal (collector terminal) of the third switching element 6 is connected to the connection point 3 of the corresponding switching circuit 10 among the multiple switching circuits 10, and the first main terminal (collector terminal) of the fourth switching element 7 is connected to the common connection point 25. In this case, each of the multiple switches 8 further has a diode antiparallel connected to the third switching element 6 and a diode antiparallel connected to the fourth switching element 7.

[0159] Furthermore, each of the third switching element 6 and the fourth switching element 7 may be replaced with a MOSFET or a bipolar transistor.

[0160] In each of the multiple switches 8, the third switching element 6 and the fourth switching element 7 may be connected in antiparallel. Furthermore, each of the multiple switches 8 may further include a diode connected in antiparallel to the third switching element 6 and a diode connected in antiparallel to the fourth switching element 7.

[0161] Each of the multiple switches 8 may be a dual-gate type GaN-based GIT having a first source terminal, a first gate terminal, a second gate terminal, and a second source terminal. In this case, a control signal SU6 is applied between the first gate terminal and the first source terminal of the dual-gate type GaN-based GIT constituting switch 8U, and a control signal SU7 is applied between the second gate terminal and the second source terminal. Similarly, a control signal SV6 is applied between the first gate terminal and the first source terminal of the dual-gate type GaN-based GIT constituting switch 8V, and a control signal SV7 is applied between the second gate terminal and the second source terminal. Furthermore, a control signal SW6 is applied between the first gate terminal and the first source terminal of the dual-gate type GaN-based GIT constituting switch 8W, and a control signal SW7 is applied between the second gate terminal and the second source terminal.

[0162] Furthermore, the power converters 100 and 100A are not limited to a configuration that outputs three-phase AC, but may be configured to output three or more phases of multi-phase AC.

[0163] (Aspects) The following aspects are disclosed herein.

[0164] The power conversion device (100; 100A) according to the first embodiment includes a first DC terminal (31), a second DC terminal (32), a power conversion circuit (11), a plurality of AC terminals (41), a plurality of switches (8), a plurality of resonant capacitors (9), a resonant inductor (L1), a regenerative capacitor (15), a current detection unit (16), a control device (51), and a signal generation circuit (52; 52A). The power conversion circuit (11) has a plurality of first switching elements (1) and a plurality of second switching elements (2). In the power conversion circuit (11), a plurality of switching circuits (10), each in which a plurality of first switching elements (1) and a plurality of second switching elements (2) are connected in series one to one, are connected in parallel to each other. In the power conversion circuit (11), a plurality of first switching elements (1) are connected to the first DC terminal (31). In the power conversion circuit (11), multiple second switching elements (2) are connected to the second DC terminal (32). Multiple AC terminals (41) correspond one-to-one with multiple switching circuits (10). Each of the multiple AC terminals (41) is connected to the connection point (3) of the first switching element (1) and the second switching element (2) in the corresponding switching circuit (10) among the multiple switching circuits (10), and load current flows through it. Multiple switches (8) correspond one-to-one with multiple switching circuits (10). Each of the multiple switches (8) has a first terminal (81) and a second terminal (82). The first terminal (81) of each of the multiple switches (8) is connected to the connection point (3) of the first switching element (1) and the second switching element (2) in the corresponding switching circuit (10) among the multiple switching circuits (10). Multiple resonant capacitors (9) correspond one-to-one with multiple switches (8). Each of the multiple resonant capacitors (9) is connected between the first terminal (81) and the second DC terminal (32) of the corresponding switch (8) among the multiple switches (8). The resonant inductor (L1) has a third terminal and a fourth terminal. In the resonant inductor (L1), the third terminal is connected to the second terminal (82) of the multiple switches (8). The regenerative capacitor (15) has a fifth terminal (153) and a sixth terminal (154).In the regenerative capacitor (15), the fifth terminal (153) is connected to the second DC terminal (32), and the sixth terminal (154) is connected to the fourth terminal of the resonant inductor (L1). The current detection unit (16) detects the input current (Iin) flowing from the first DC terminal (31) to the power conversion circuit (11). The control device (51) generates multiple first PWM signals (SU1, SV1, SW1) to control multiple first switching elements (1) and multiple second PWM signals (SU2, SV2, SW2) to control multiple second switching elements (2), based on multiphase duty command values ​​(du, dv, dw) that correspond one-to-one to multiple switching circuits (10). The signal generation circuit (52; 52A) provides each of the multiple switches (8) with control signals (SU6, SU7, SV6, SV7, SW6, SW7) that change potential between high level and low level. The control device (51) sets a second dead time period (Td2) for each of the multiple switching circuits (10) by adding a predetermined time to a preset first dead time period (Td1) such that the on periods of the first switching element (1) and the second switching element (2) do not overlap between the high-level period of the first PWM signal to the first switching element (1) and the high-level period of the second PWM signal to the second switching element (2). The predetermined time is determined according to the current value of the load current, the inductance of the resonant inductor (L1), and the voltage value of the regenerative capacitor (15). The signal generation circuit (52; 52A) generates a control signal for each of the multiple switches (8) that has a high-level period corresponding to the second dead time period (Td2) for the corresponding switching circuit (10) among the multiple switching circuits (10). The control device (51) generates multiple first PWM signals (SU1, SV1, SW1) and multiple second PWM signals (SU2, SV2, SW2) in the nth control cycle, where n is a natural number. The control device (51) stops the operation of the power conversion circuit (11) if the input current detected value by the current detection unit (16) exceeds the current protection threshold (Ith).If the control device (51) determines during the nth control cycle that two-phase resonant currents corresponding to two of the multiple switching circuits (10) flow simultaneously through the resonant inductor (L1) during the (n+1)th control cycle, it increases the current protection threshold (Ith) during the (n+1)th control cycle.

[0165] According to this embodiment, zero-voltage soft switching can be performed without the control device (51) directly controlling the plurality of switches (8) for zero-voltage soft switching, and current distortion can be reduced.

[0166] In the power converter (100; 100A) according to the second embodiment, in the first embodiment, if the control device (51) determines during the nth control cycle that two-phase resonant currents corresponding to two of the multiple switching circuits (10) flow simultaneously through the resonant inductor (L1) during the (n+1)th control cycle, it invalidates the detected values ​​of the two-phase load currents corresponding to the two switching circuits (10) during the (n+1)th control cycle.

[0167] According to this embodiment, it is possible to further reduce the processing time for each control cycle in the control device (51).

[0168] In the power conversion device (100) according to the third embodiment, in the first or second embodiment, when the control device (51) sets a second dead time period (Td2) for each of the plurality of switching circuits (10), if the polarity of the load current is positive, it adds a predetermined time (additional time) to the first dead time period (Td1) by shortening the high-level period of the second PWM signal to the second switching element (2). Also, when the control device (51) sets a second dead time period (Td2) for each of the plurality of switching circuits (10), if the polarity of the load current is negative, it adds a predetermined time (additional time) to the first dead time period (Td1) by shortening the high-level period of the first PWM signal to the first switching element (1).

[0169] With the above configuration, it becomes possible to achieve zero-voltage soft switching while further reducing dead time loss and dead time error.

[0170] 1 First switching element 2 Second switching element 3 Connection point 4 First diode 5 Second diode 6 Third switching element 7 Fourth switching element 8 Switch 81 First terminal 82 Second terminal 9 Resonant capacitor 10 Switching circuit 13 Third diode 14 Fourth diode 11 Power conversion circuit 15 Regenerative capacitor 153 Fifth terminal 154 Sixth terminal 16 Current detection unit 31 First DC terminal 32 Second DC terminal 41 AC terminal 51 Control device 52, 52A Signal generation circuit 100, 100A Power converter iU, iv, iW Output current (load current) L1 Resonant inductor RA1 AC load SU1, SV1, SW1 First PWM signal SU2, SV2, SW2 Second PWM signal SU6, SU7, SV6, SV7, SW6, SW7 Control signals Tadu Additional time Tadv Additional time Tadw Additional time Td1 First dead time period Td2 Second dead time period

Claims

1. A power conversion circuit comprising: a first DC terminal; a second DC terminal; a plurality of switching circuits having a plurality of first switching elements and a plurality of second switching elements, wherein the plurality of first switching elements and the plurality of second switching elements are connected in series one to one, and the plurality of first switching elements are connected to the first DC terminal and the plurality of second switching elements are connected to the second DC terminal; a plurality of AC terminals corresponding one to one of the plurality of switching circuits, each connected to the connection point of the first switching element and the second switching element in the corresponding switching circuit, through which load current flows; a plurality of switches corresponding one to one of the plurality of switching circuits, each having a first end and a second end, with the first end of the first end of the first end of the first end of the first end of the switch connected to the second DC terminal; a plurality of resonant capacitors corresponding one to one of the plurality of switches, each connected between the first end of the corresponding switch and the second DC terminal; The device comprises: a resonant inductor having a third and a fourth terminal, the third terminal of which is connected to the second terminal of the plurality of switches; a regenerative capacitor having a fifth and a sixth terminal, the fifth terminal of which is connected to the second DC terminal, and the sixth terminal of which is connected to the fourth terminal of the resonant inductor; a current detection unit for detecting the input current flowing from the first DC terminal to the power conversion circuit; a control device that generates a plurality of first PWM signals for controlling the plurality of first switching elements and a plurality of second PWM signals for controlling the plurality of second switching elements based on a plurality of phase duty command values ​​corresponding one-to-one to the plurality of switching circuits; and a signal generation circuit that provides a control signal to each of the plurality of switches whose potential changes between a high level and a low level. The control device isFor each of the plurality of switching circuits, a second dead time period is set by adding a predetermined time to a first dead time period, which is set so that the ON periods of the first and second switching elements do not overlap between the high-level period of the first PWM signal to the first switching element and the high-level period of the second PWM signal to the second switching element, the predetermined time is determined according to the current value of the load current, the inductance of the resonant inductor and the voltage value of the regenerative capacitor, the signal generation circuit generates the control signal for each of the plurality of switches, which has a high-level period corresponding to the second dead time period for the corresponding switching circuit among the plurality of switching circuits, the control device generates the plurality of first PWM signals and the plurality of second PWM signals in the nth control cycle, where n is a natural number, and if the input current detection value by the current detection unit exceeds the current protection threshold, the operation of the power conversion circuit is stopped. A power converter that, when it is determined during the nth control cycle that two-phase resonant currents corresponding to two of the plurality of switching circuits flow simultaneously through the resonant inductor during the (n+1)th control cycle, increases the current protection threshold during the (n+1)th control cycle.

2. The power conversion device according to claim 1, wherein the control device determines during the nth control cycle that two-phase resonant currents corresponding to two of the plurality of switching circuits flow simultaneously through the resonant inductor during the (n+1)th control cycle, and invalidates the detected values ​​of the two-phase load currents corresponding to the two switching circuits during the (n+1)th control cycle.

3. The power conversion device according to claim 1 or 2, wherein when the control device sets the second dead time period for each of the plurality of switching circuits, if the polarity of the load current is positive, it adds the predetermined time to the first dead time period by shortening the high-level period of the second PWM signal to the second switching element, and if the polarity of the load current is negative, it adds the predetermined time to the first dead time period by shortening the high-level period of the first PWM signal to the first switching element.

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